blob: a4288f428819a3175d2e74cb2feec138ffacb4dc [file] [log] [blame]
Shawn Guofba311f2010-12-18 21:39:31 +08001/*
2 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * Based on code from Freescale,
6 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 * MA 02110-1301, USA.
21 */
22
Thierry Reding641d0342013-01-21 11:09:01 +010023#include <linux/err.h>
Shawn Guofba311f2010-12-18 21:39:31 +080024#include <linux/init.h>
25#include <linux/interrupt.h>
26#include <linux/io.h>
27#include <linux/irq.h>
Shawn Guo0b76c542012-08-20 16:43:32 +080028#include <linux/irqdomain.h>
Shawn Guofba311f2010-12-18 21:39:31 +080029#include <linux/gpio.h>
Shawn Guo4052d452012-05-04 14:29:22 +080030#include <linux/of.h>
31#include <linux/of_address.h>
32#include <linux/of_device.h>
Shawn Guo8d7cf832011-06-06 09:37:58 -060033#include <linux/platform_device.h>
34#include <linux/slab.h>
Shawn Guo06f88a82011-06-06 22:31:29 +080035#include <linux/basic_mmio_gpio.h>
Paul Gortmakerbb207ef2011-07-03 13:38:09 -040036#include <linux/module.h>
Shawn Guofba311f2010-12-18 21:39:31 +080037
Shawn Guo8d7cf832011-06-06 09:37:58 -060038#define MXS_SET 0x4
39#define MXS_CLR 0x8
Shawn Guofba311f2010-12-18 21:39:31 +080040
Shawn Guo164387d2012-05-03 23:32:52 +080041#define PINCTRL_DOUT(p) ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
42#define PINCTRL_DIN(p) ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
43#define PINCTRL_DOE(p) ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
44#define PINCTRL_PIN2IRQ(p) ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
45#define PINCTRL_IRQEN(p) ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
46#define PINCTRL_IRQLEV(p) ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
47#define PINCTRL_IRQPOL(p) ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
48#define PINCTRL_IRQSTAT(p) ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
Shawn Guofba311f2010-12-18 21:39:31 +080049
50#define GPIO_INT_FALL_EDGE 0x0
51#define GPIO_INT_LOW_LEV 0x1
52#define GPIO_INT_RISE_EDGE 0x2
53#define GPIO_INT_HIGH_LEV 0x3
54#define GPIO_INT_LEV_MASK (1 << 0)
55#define GPIO_INT_POL_MASK (1 << 1)
56
Shawn Guo164387d2012-05-03 23:32:52 +080057enum mxs_gpio_id {
58 IMX23_GPIO,
59 IMX28_GPIO,
60};
61
Grant Likely7b2fa572011-06-06 09:37:58 -060062struct mxs_gpio_port {
63 void __iomem *base;
64 int id;
65 int irq;
Shawn Guo0b76c542012-08-20 16:43:32 +080066 struct irq_domain *domain;
Shawn Guo06f88a82011-06-06 22:31:29 +080067 struct bgpio_chip bgc;
Shawn Guo164387d2012-05-03 23:32:52 +080068 enum mxs_gpio_id devid;
Gwenhael Goavec-Merou66d79902013-01-29 09:16:33 +010069 u32 both_edges;
Grant Likely7b2fa572011-06-06 09:37:58 -060070};
71
Shawn Guo164387d2012-05-03 23:32:52 +080072static inline int is_imx23_gpio(struct mxs_gpio_port *port)
73{
74 return port->devid == IMX23_GPIO;
75}
76
77static inline int is_imx28_gpio(struct mxs_gpio_port *port)
78{
79 return port->devid == IMX28_GPIO;
80}
81
Shawn Guofba311f2010-12-18 21:39:31 +080082/* Note: This driver assumes 32 GPIOs are handled in one register */
83
Uwe Kleine-Königbf0c11182011-02-18 21:31:41 +010084static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
Shawn Guofba311f2010-12-18 21:39:31 +080085{
Gwenhael Goavec-Merou66d79902013-01-29 09:16:33 +010086 u32 val;
Shawn Guo0b76c542012-08-20 16:43:32 +080087 u32 pin_mask = 1 << d->hwirq;
Shawn Guo498c17c2011-06-07 22:00:54 +080088 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
89 struct mxs_gpio_port *port = gc->private;
Shawn Guofba311f2010-12-18 21:39:31 +080090 void __iomem *pin_addr;
91 int edge;
92
Gwenhael Goavec-Merou66d79902013-01-29 09:16:33 +010093 port->both_edges &= ~pin_mask;
Shawn Guofba311f2010-12-18 21:39:31 +080094 switch (type) {
Gwenhael Goavec-Merou66d79902013-01-29 09:16:33 +010095 case IRQ_TYPE_EDGE_BOTH:
96 val = gpio_get_value(port->bgc.gc.base + d->hwirq);
97 if (val)
98 edge = GPIO_INT_FALL_EDGE;
99 else
100 edge = GPIO_INT_RISE_EDGE;
101 port->both_edges |= pin_mask;
102 break;
Shawn Guofba311f2010-12-18 21:39:31 +0800103 case IRQ_TYPE_EDGE_RISING:
104 edge = GPIO_INT_RISE_EDGE;
105 break;
106 case IRQ_TYPE_EDGE_FALLING:
107 edge = GPIO_INT_FALL_EDGE;
108 break;
109 case IRQ_TYPE_LEVEL_LOW:
110 edge = GPIO_INT_LOW_LEV;
111 break;
112 case IRQ_TYPE_LEVEL_HIGH:
113 edge = GPIO_INT_HIGH_LEV;
114 break;
115 default:
116 return -EINVAL;
117 }
118
119 /* set level or edge */
Shawn Guo164387d2012-05-03 23:32:52 +0800120 pin_addr = port->base + PINCTRL_IRQLEV(port);
Shawn Guofba311f2010-12-18 21:39:31 +0800121 if (edge & GPIO_INT_LEV_MASK)
Shawn Guo8d7cf832011-06-06 09:37:58 -0600122 writel(pin_mask, pin_addr + MXS_SET);
Shawn Guofba311f2010-12-18 21:39:31 +0800123 else
Shawn Guo8d7cf832011-06-06 09:37:58 -0600124 writel(pin_mask, pin_addr + MXS_CLR);
Shawn Guofba311f2010-12-18 21:39:31 +0800125
126 /* set polarity */
Shawn Guo164387d2012-05-03 23:32:52 +0800127 pin_addr = port->base + PINCTRL_IRQPOL(port);
Shawn Guofba311f2010-12-18 21:39:31 +0800128 if (edge & GPIO_INT_POL_MASK)
Shawn Guo8d7cf832011-06-06 09:37:58 -0600129 writel(pin_mask, pin_addr + MXS_SET);
Shawn Guofba311f2010-12-18 21:39:31 +0800130 else
Shawn Guo8d7cf832011-06-06 09:37:58 -0600131 writel(pin_mask, pin_addr + MXS_CLR);
Shawn Guofba311f2010-12-18 21:39:31 +0800132
Shawn Guo0b76c542012-08-20 16:43:32 +0800133 writel(pin_mask,
Shawn Guo164387d2012-05-03 23:32:52 +0800134 port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
Shawn Guofba311f2010-12-18 21:39:31 +0800135
136 return 0;
137}
138
Gwenhael Goavec-Merou66d79902013-01-29 09:16:33 +0100139static void mxs_flip_edge(struct mxs_gpio_port *port, u32 gpio)
140{
141 u32 bit, val, edge;
142 void __iomem *pin_addr;
143
144 bit = 1 << gpio;
145
146 pin_addr = port->base + PINCTRL_IRQPOL(port);
147 val = readl(pin_addr);
148 edge = val & bit;
149
150 if (edge)
151 writel(bit, pin_addr + MXS_CLR);
152 else
153 writel(bit, pin_addr + MXS_SET);
154}
155
Shawn Guofba311f2010-12-18 21:39:31 +0800156/* MXS has one interrupt *per* gpio port */
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200157static void mxs_gpio_irq_handler(struct irq_desc *desc)
Shawn Guofba311f2010-12-18 21:39:31 +0800158{
159 u32 irq_stat;
Jiang Liu476f8b42015-06-04 12:13:15 +0800160 struct mxs_gpio_port *port = irq_desc_get_handler_data(desc);
Shawn Guofba311f2010-12-18 21:39:31 +0800161
Uwe Kleine-König1f6b5dd2011-01-25 16:54:22 +0100162 desc->irq_data.chip->irq_ack(&desc->irq_data);
163
Shawn Guo164387d2012-05-03 23:32:52 +0800164 irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
165 readl(port->base + PINCTRL_IRQEN(port));
Shawn Guofba311f2010-12-18 21:39:31 +0800166
167 while (irq_stat != 0) {
168 int irqoffset = fls(irq_stat) - 1;
Gwenhael Goavec-Merou66d79902013-01-29 09:16:33 +0100169 if (port->both_edges & (1 << irqoffset))
170 mxs_flip_edge(port, irqoffset);
171
Shawn Guo0b76c542012-08-20 16:43:32 +0800172 generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
Shawn Guofba311f2010-12-18 21:39:31 +0800173 irq_stat &= ~(1 << irqoffset);
174 }
175}
176
177/*
178 * Set interrupt number "irq" in the GPIO as a wake-up source.
179 * While system is running, all registered GPIO interrupts need to have
180 * wake-up enabled. When system is suspended, only selected GPIO interrupts
181 * need to have wake-up enabled.
182 * @param irq interrupt source number
183 * @param enable enable as wake-up if equal to non-zero
184 * @return This function returns 0 on success.
185 */
Uwe Kleine-Königbf0c11182011-02-18 21:31:41 +0100186static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
Shawn Guofba311f2010-12-18 21:39:31 +0800187{
Shawn Guo498c17c2011-06-07 22:00:54 +0800188 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
189 struct mxs_gpio_port *port = gc->private;
Shawn Guofba311f2010-12-18 21:39:31 +0800190
Shawn Guo61617152011-06-07 22:00:53 +0800191 if (enable)
192 enable_irq_wake(port->irq);
193 else
194 disable_irq_wake(port->irq);
Shawn Guofba311f2010-12-18 21:39:31 +0800195
196 return 0;
197}
198
Peng Fan1bbc5572015-08-23 21:11:53 +0800199static int __init mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
Shawn Guo498c17c2011-06-07 22:00:54 +0800200{
201 struct irq_chip_generic *gc;
202 struct irq_chip_type *ct;
203
Shawn Guo0b76c542012-08-20 16:43:32 +0800204 gc = irq_alloc_generic_chip("gpio-mxs", 1, irq_base,
Shawn Guo498c17c2011-06-07 22:00:54 +0800205 port->base, handle_level_irq);
Peng Fan1bbc5572015-08-23 21:11:53 +0800206 if (!gc)
207 return -ENOMEM;
208
Shawn Guo498c17c2011-06-07 22:00:54 +0800209 gc->private = port;
210
211 ct = gc->chip_types;
Shawn Guo591567a2011-07-19 21:16:56 +0800212 ct->chip.irq_ack = irq_gc_ack_set_bit;
Shawn Guo498c17c2011-06-07 22:00:54 +0800213 ct->chip.irq_mask = irq_gc_mask_clr_bit;
214 ct->chip.irq_unmask = irq_gc_mask_set_bit;
215 ct->chip.irq_set_type = mxs_gpio_set_irq_type;
Shawn Guo591567a2011-07-19 21:16:56 +0800216 ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
Shawn Guo164387d2012-05-03 23:32:52 +0800217 ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
218 ct->regs.mask = PINCTRL_IRQEN(port);
Shawn Guo498c17c2011-06-07 22:00:54 +0800219
Marek Vasuta585f872014-03-24 03:38:10 +0100220 irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK,
221 IRQ_NOREQUEST, 0);
Peng Fan1bbc5572015-08-23 21:11:53 +0800222
223 return 0;
Shawn Guo498c17c2011-06-07 22:00:54 +0800224}
Shawn Guofba311f2010-12-18 21:39:31 +0800225
Shawn Guo06f88a82011-06-06 22:31:29 +0800226static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
Shawn Guofba311f2010-12-18 21:39:31 +0800227{
Shawn Guo06f88a82011-06-06 22:31:29 +0800228 struct bgpio_chip *bgc = to_bgpio_chip(gc);
Shawn Guofba311f2010-12-18 21:39:31 +0800229 struct mxs_gpio_port *port =
Shawn Guo06f88a82011-06-06 22:31:29 +0800230 container_of(bgc, struct mxs_gpio_port, bgc);
Shawn Guofba311f2010-12-18 21:39:31 +0800231
Shawn Guo0b76c542012-08-20 16:43:32 +0800232 return irq_find_mapping(port->domain, offset);
Shawn Guofba311f2010-12-18 21:39:31 +0800233}
234
Janusz Uzyckic8aaa1b2014-11-19 09:55:22 +0100235static int mxs_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
236{
237 struct bgpio_chip *bgc = to_bgpio_chip(gc);
238 struct mxs_gpio_port *port =
239 container_of(bgc, struct mxs_gpio_port, bgc);
240 u32 mask = 1 << offset;
241 u32 dir;
242
243 dir = readl(port->base + PINCTRL_DOE(port));
244 return !(dir & mask);
245}
246
Krzysztof Kozlowskif4f79d42015-05-02 00:56:47 +0900247static const struct platform_device_id mxs_gpio_ids[] = {
Shawn Guo164387d2012-05-03 23:32:52 +0800248 {
249 .name = "imx23-gpio",
250 .driver_data = IMX23_GPIO,
251 }, {
252 .name = "imx28-gpio",
253 .driver_data = IMX28_GPIO,
254 }, {
255 /* sentinel */
256 }
257};
258MODULE_DEVICE_TABLE(platform, mxs_gpio_ids);
259
Shawn Guo4052d452012-05-04 14:29:22 +0800260static const struct of_device_id mxs_gpio_dt_ids[] = {
261 { .compatible = "fsl,imx23-gpio", .data = (void *) IMX23_GPIO, },
262 { .compatible = "fsl,imx28-gpio", .data = (void *) IMX28_GPIO, },
263 { /* sentinel */ }
264};
265MODULE_DEVICE_TABLE(of, mxs_gpio_dt_ids);
266
Bill Pemberton38363092012-11-19 13:22:34 -0500267static int mxs_gpio_probe(struct platform_device *pdev)
Shawn Guofba311f2010-12-18 21:39:31 +0800268{
Shawn Guo4052d452012-05-04 14:29:22 +0800269 const struct of_device_id *of_id =
270 of_match_device(mxs_gpio_dt_ids, &pdev->dev);
271 struct device_node *np = pdev->dev.of_node;
272 struct device_node *parent;
Shawn Guo8d7cf832011-06-06 09:37:58 -0600273 static void __iomem *base;
274 struct mxs_gpio_port *port;
Shawn Guo0b76c542012-08-20 16:43:32 +0800275 int irq_base;
Shawn Guo498c17c2011-06-07 22:00:54 +0800276 int err;
Shawn Guofba311f2010-12-18 21:39:31 +0800277
Shawn Guo940a4f72012-05-04 10:30:14 +0800278 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
Shawn Guo8d7cf832011-06-06 09:37:58 -0600279 if (!port)
280 return -ENOMEM;
Shawn Guofba311f2010-12-18 21:39:31 +0800281
Fabio Estevam99357122013-11-05 17:21:22 -0200282 port->id = of_alias_get_id(np, "gpio");
283 if (port->id < 0)
284 return port->id;
285 port->devid = (enum mxs_gpio_id) of_id->data;
Shawn Guo940a4f72012-05-04 10:30:14 +0800286 port->irq = platform_get_irq(pdev, 0);
287 if (port->irq < 0)
288 return port->irq;
289
Shawn Guo8d7cf832011-06-06 09:37:58 -0600290 /*
291 * map memory region only once, as all the gpio ports
292 * share the same one
293 */
294 if (!base) {
Fabio Estevam99357122013-11-05 17:21:22 -0200295 parent = of_get_parent(np);
296 base = of_iomap(parent, 0);
297 of_node_put(parent);
298 if (!base)
299 return -EADDRNOTAVAIL;
Shawn Guofba311f2010-12-18 21:39:31 +0800300 }
Shawn Guo8d7cf832011-06-06 09:37:58 -0600301 port->base = base;
302
Shawn Guo498c17c2011-06-07 22:00:54 +0800303 /*
304 * select the pin interrupt functionality but initially
305 * disable the interrupts
306 */
Shawn Guo164387d2012-05-03 23:32:52 +0800307 writel(~0U, port->base + PINCTRL_PIN2IRQ(port));
308 writel(0, port->base + PINCTRL_IRQEN(port));
Shawn Guo8d7cf832011-06-06 09:37:58 -0600309
310 /* clear address has to be used to clear IRQSTAT bits */
Shawn Guo164387d2012-05-03 23:32:52 +0800311 writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
Shawn Guo8d7cf832011-06-06 09:37:58 -0600312
Shawn Guo0b76c542012-08-20 16:43:32 +0800313 irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
314 if (irq_base < 0)
315 return irq_base;
316
317 port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
318 &irq_domain_simple_ops, NULL);
319 if (!port->domain) {
320 err = -ENODEV;
321 goto out_irqdesc_free;
322 }
323
Shawn Guo498c17c2011-06-07 22:00:54 +0800324 /* gpio-mxs can be a generic irq chip */
Peng Fan1bbc5572015-08-23 21:11:53 +0800325 err = mxs_gpio_init_gc(port, irq_base);
326 if (err < 0)
327 goto out_irqdomain_remove;
Shawn Guo8d7cf832011-06-06 09:37:58 -0600328
329 /* setup one handler for each entry */
Russell Kinga44735f2015-06-16 23:06:45 +0100330 irq_set_chained_handler_and_data(port->irq, mxs_gpio_irq_handler,
331 port);
Shawn Guo8d7cf832011-06-06 09:37:58 -0600332
Shawn Guo06f88a82011-06-06 22:31:29 +0800333 err = bgpio_init(&port->bgc, &pdev->dev, 4,
Shawn Guo164387d2012-05-03 23:32:52 +0800334 port->base + PINCTRL_DIN(port),
Maxime Ripard90dae4e2013-04-29 16:07:18 +0200335 port->base + PINCTRL_DOUT(port) + MXS_SET,
336 port->base + PINCTRL_DOUT(port) + MXS_CLR,
Linus Torvalds84a442b2012-05-26 12:57:47 -0700337 port->base + PINCTRL_DOE(port), NULL, 0);
Shawn Guo8d7cf832011-06-06 09:37:58 -0600338 if (err)
Shawn Guo0b76c542012-08-20 16:43:32 +0800339 goto out_irqdesc_free;
Shawn Guofba311f2010-12-18 21:39:31 +0800340
Shawn Guo06f88a82011-06-06 22:31:29 +0800341 port->bgc.gc.to_irq = mxs_gpio_to_irq;
Janusz Uzyckic8aaa1b2014-11-19 09:55:22 +0100342 port->bgc.gc.get_direction = mxs_gpio_get_direction;
Shawn Guo06f88a82011-06-06 22:31:29 +0800343 port->bgc.gc.base = port->id * 32;
344
345 err = gpiochip_add(&port->bgc.gc);
Shawn Guo0b76c542012-08-20 16:43:32 +0800346 if (err)
347 goto out_bgpio_remove;
Shawn Guo06f88a82011-06-06 22:31:29 +0800348
Shawn Guofba311f2010-12-18 21:39:31 +0800349 return 0;
Shawn Guo0b76c542012-08-20 16:43:32 +0800350
351out_bgpio_remove:
352 bgpio_remove(&port->bgc);
Peng Fan1bbc5572015-08-23 21:11:53 +0800353out_irqdomain_remove:
354 irq_domain_remove(port->domain);
Shawn Guo0b76c542012-08-20 16:43:32 +0800355out_irqdesc_free:
356 irq_free_descs(irq_base, 32);
357 return err;
Shawn Guofba311f2010-12-18 21:39:31 +0800358}
359
Shawn Guo8d7cf832011-06-06 09:37:58 -0600360static struct platform_driver mxs_gpio_driver = {
361 .driver = {
362 .name = "gpio-mxs",
Shawn Guo4052d452012-05-04 14:29:22 +0800363 .of_match_table = mxs_gpio_dt_ids,
Shawn Guo8d7cf832011-06-06 09:37:58 -0600364 },
365 .probe = mxs_gpio_probe,
Shawn Guo164387d2012-05-03 23:32:52 +0800366 .id_table = mxs_gpio_ids,
Shawn Guofba311f2010-12-18 21:39:31 +0800367};
Sascha Haueref196602011-01-24 12:57:46 +0100368
Shawn Guo8d7cf832011-06-06 09:37:58 -0600369static int __init mxs_gpio_init(void)
Sascha Haueref196602011-01-24 12:57:46 +0100370{
Shawn Guo8d7cf832011-06-06 09:37:58 -0600371 return platform_driver_register(&mxs_gpio_driver);
Sascha Haueref196602011-01-24 12:57:46 +0100372}
Shawn Guo8d7cf832011-06-06 09:37:58 -0600373postcore_initcall(mxs_gpio_init);
Shawn Guofba311f2010-12-18 21:39:31 +0800374
Shawn Guo8d7cf832011-06-06 09:37:58 -0600375MODULE_AUTHOR("Freescale Semiconductor, "
376 "Daniel Mack <danielncaiaq.de>, "
377 "Juergen Beisert <kernel@pengutronix.de>");
378MODULE_DESCRIPTION("Freescale MXS GPIO");
379MODULE_LICENSE("GPL");