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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * ahci.c - AHCI SATA support
3 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04004 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04008 * Copyright 2004-2005 Red Hat, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040011 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
Linus Torvalds1da177e2005-04-16 15:20:36 -070030 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040031 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
Linus Torvalds1da177e2005-04-16 15:20:36 -070032 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
domen@coderock.org87507cf2005-04-08 09:53:06 +020042#include <linux/dma-mapping.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050043#include <linux/device.h>
Tejun Heoedc93052007-10-25 14:59:16 +090044#include <linux/dmi.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090045#include <linux/gfp.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070046#include <scsi/scsi_host.h>
Jeff Garzik193515d2005-11-07 00:59:37 -050047#include <scsi/scsi_cmnd.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070048#include <linux/libata.h>
Anton Vorontsov365cfa12010-03-28 00:22:14 -040049#include "ahci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070050
51#define DRV_NAME "ahci"
Tejun Heo7d50b602007-09-23 13:19:54 +090052#define DRV_VERSION "3.0"
Linus Torvalds1da177e2005-04-16 15:20:36 -070053
Linus Torvalds1da177e2005-04-16 15:20:36 -070054enum {
Alessandro Rubini318893e2012-01-06 13:33:39 +010055 AHCI_PCI_BAR_STA2X11 = 0,
Hugh Daschbach7f9c9f82013-01-04 14:39:09 -080056 AHCI_PCI_BAR_ENMOTUS = 2,
Alessandro Rubini318893e2012-01-06 13:33:39 +010057 AHCI_PCI_BAR_STANDARD = 5,
Tejun Heo441577e2010-03-29 10:32:39 +090058};
Linus Torvalds1da177e2005-04-16 15:20:36 -070059
Tejun Heo441577e2010-03-29 10:32:39 +090060enum board_ids {
61 /* board IDs by feature in alphabetical order */
62 board_ahci,
63 board_ahci_ign_iferr,
64 board_ahci_nosntf,
Tejun Heo5f173102010-07-24 16:53:48 +020065 board_ahci_yes_fbs,
Tejun Heo441577e2010-03-29 10:32:39 +090066
67 /* board IDs for specific chipsets in alphabetical order */
68 board_ahci_mcp65,
Tejun Heo83f2b962010-03-30 10:28:32 +090069 board_ahci_mcp77,
70 board_ahci_mcp89,
Tejun Heo441577e2010-03-29 10:32:39 +090071 board_ahci_mv,
72 board_ahci_sb600,
73 board_ahci_sb700, /* for SB700 and SB800 */
74 board_ahci_vt8251,
75
76 /* aliases */
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
Tejun Heo83f2b962010-03-30 10:28:32 +090080 board_ahci_mcp79 = board_ahci_mcp77,
Linus Torvalds1da177e2005-04-16 15:20:36 -070081};
82
Jeff Garzik2dcb4072007-10-19 06:42:56 -040083static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
Tejun Heoa1efdab2008-03-25 12:22:50 +090084static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
Tejun Heo438ac6d2007-03-02 17:31:26 +090088#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +090089static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
90static int ahci_pci_device_resume(struct pci_dev *pdev);
Tejun Heo438ac6d2007-03-02 17:31:26 +090091#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070092
Tejun Heofad16e72010-09-21 09:25:48 +020093static struct scsi_host_template ahci_sht = {
94 AHCI_SHT("ahci"),
95};
96
Tejun Heo029cfd62008-03-25 12:22:49 +090097static struct ata_port_operations ahci_vt8251_ops = {
98 .inherits = &ahci_ops,
Tejun Heoa1efdab2008-03-25 12:22:50 +090099 .hardreset = ahci_vt8251_hardreset,
Tejun Heoad616ff2006-11-01 18:00:24 +0900100};
101
Tejun Heo029cfd62008-03-25 12:22:49 +0900102static struct ata_port_operations ahci_p5wdh_ops = {
103 .inherits = &ahci_ops,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900104 .hardreset = ahci_p5wdh_hardreset,
Tejun Heoedc93052007-10-25 14:59:16 +0900105};
106
Arjan van de Ven98ac62d2005-11-28 10:06:23 +0100107static const struct ata_port_info ahci_port_info[] = {
Tejun Heo441577e2010-03-29 10:32:39 +0900108 /* by features */
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530109 [board_ahci] = {
Tejun Heo1188c0d2007-04-23 02:41:05 +0900110 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100111 .pio_mask = ATA_PIO4,
Jeff Garzik469248a2007-07-08 01:13:16 -0400112 .udma_mask = ATA_UDMA6,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700113 .port_ops = &ahci_ops,
114 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530115 [board_ahci_ign_iferr] = {
Tejun Heo417a1a62007-09-23 13:19:55 +0900116 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
117 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100118 .pio_mask = ATA_PIO4,
Jeff Garzik469248a2007-07-08 01:13:16 -0400119 .udma_mask = ATA_UDMA6,
Tejun Heo41669552006-11-29 11:33:14 +0900120 .port_ops = &ahci_ops,
121 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530122 [board_ahci_nosntf] = {
Tejun Heo441577e2010-03-29 10:32:39 +0900123 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
124 .flags = AHCI_FLAG_COMMON,
125 .pio_mask = ATA_PIO4,
126 .udma_mask = ATA_UDMA6,
127 .port_ops = &ahci_ops,
128 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530129 [board_ahci_yes_fbs] = {
Tejun Heo5f173102010-07-24 16:53:48 +0200130 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
131 .flags = AHCI_FLAG_COMMON,
132 .pio_mask = ATA_PIO4,
133 .udma_mask = ATA_UDMA6,
134 .port_ops = &ahci_ops,
135 },
Tejun Heo441577e2010-03-29 10:32:39 +0900136 /* by chipsets */
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530137 [board_ahci_mcp65] = {
Tejun Heo83f2b962010-03-30 10:28:32 +0900138 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
139 AHCI_HFLAG_YES_NCQ),
Tejun Heoae01b242011-03-16 11:14:55 +0100140 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
Tejun Heo83f2b962010-03-30 10:28:32 +0900141 .pio_mask = ATA_PIO4,
142 .udma_mask = ATA_UDMA6,
143 .port_ops = &ahci_ops,
144 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530145 [board_ahci_mcp77] = {
Tejun Heo83f2b962010-03-30 10:28:32 +0900146 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
147 .flags = AHCI_FLAG_COMMON,
148 .pio_mask = ATA_PIO4,
149 .udma_mask = ATA_UDMA6,
150 .port_ops = &ahci_ops,
151 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530152 [board_ahci_mcp89] = {
Tejun Heo83f2b962010-03-30 10:28:32 +0900153 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
Tejun Heo441577e2010-03-29 10:32:39 +0900154 .flags = AHCI_FLAG_COMMON,
155 .pio_mask = ATA_PIO4,
156 .udma_mask = ATA_UDMA6,
157 .port_ops = &ahci_ops,
158 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530159 [board_ahci_mv] = {
Tejun Heo441577e2010-03-29 10:32:39 +0900160 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
161 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
Sergei Shtylyov9cbe0562011-02-04 22:05:48 +0300162 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
Tejun Heo441577e2010-03-29 10:32:39 +0900163 .pio_mask = ATA_PIO4,
164 .udma_mask = ATA_UDMA6,
165 .port_ops = &ahci_ops,
166 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530167 [board_ahci_sb600] = {
Tejun Heo417a1a62007-09-23 13:19:55 +0900168 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900169 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
170 AHCI_HFLAG_32BIT_ONLY),
Tejun Heo417a1a62007-09-23 13:19:55 +0900171 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100172 .pio_mask = ATA_PIO4,
Jeff Garzik469248a2007-07-08 01:13:16 -0400173 .udma_mask = ATA_UDMA6,
Yuan-Hsin Chen345347c2011-06-21 17:17:38 +0800174 .port_ops = &ahci_pmp_retry_srst_ops,
Conke Hu55a61602007-03-27 18:33:05 +0800175 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530176 [board_ahci_sb700] = { /* for SB700 and SB800 */
Shane Huangbd172432008-06-10 15:52:04 +0800177 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
Shane Huange39fc8c2008-02-22 05:00:31 -0800178 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100179 .pio_mask = ATA_PIO4,
Shane Huange39fc8c2008-02-22 05:00:31 -0800180 .udma_mask = ATA_UDMA6,
Yuan-Hsin Chen345347c2011-06-21 17:17:38 +0800181 .port_ops = &ahci_pmp_retry_srst_ops,
Shane Huange39fc8c2008-02-22 05:00:31 -0800182 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530183 [board_ahci_vt8251] = {
Tejun Heo441577e2010-03-29 10:32:39 +0900184 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
Tejun Heoe297d992008-06-10 00:13:04 +0900185 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100186 .pio_mask = ATA_PIO4,
Tejun Heoe297d992008-06-10 00:13:04 +0900187 .udma_mask = ATA_UDMA6,
Tejun Heo441577e2010-03-29 10:32:39 +0900188 .port_ops = &ahci_vt8251_ops,
Shaohua Li1b677af2009-11-16 09:56:05 +0800189 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700190};
191
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500192static const struct pci_device_id ahci_pci_tbl[] = {
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400193 /* Intel */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400194 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
195 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
196 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
197 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
198 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
Tejun Heo82490c02007-01-23 15:13:39 +0900199 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400200 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
201 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
202 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
203 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
Tejun Heo7a234af2007-09-03 12:44:57 +0900204 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
Shaohua Li1b677af2009-11-16 09:56:05 +0800205 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
Tejun Heo7a234af2007-09-03 12:44:57 +0900206 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
207 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
208 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
209 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
210 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
211 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
212 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
213 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
214 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
215 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
216 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
217 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
218 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
219 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
220 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
Jason Gastond4155e62007-09-20 17:35:00 -0400221 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
222 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
Jason Gaston16ad1ad2008-01-28 17:34:14 -0800223 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
Mark Goodwinb2dde6a2009-06-26 10:44:11 -0500224 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
Jason Gaston16ad1ad2008-01-28 17:34:14 -0800225 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
David Milburnc1f57d92009-07-22 15:15:56 -0500226 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
227 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
Seth Heasleyadcb5302008-08-11 17:03:09 -0700228 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
Seth Heasley8e48b6b2008-08-27 16:47:22 -0700229 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
David Milburnc1f57d92009-07-22 15:15:56 -0500230 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
Seth Heasleyadcb5302008-08-11 17:03:09 -0700231 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
Seth Heasley8e48b6b2008-08-27 16:47:22 -0700232 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
David Milburnc1f57d92009-07-22 15:15:56 -0500233 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
Seth Heasley5623cab2010-01-12 17:00:18 -0800234 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
235 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
236 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
237 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
238 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
239 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
Seth Heasley992b3fb2010-09-09 09:44:56 -0700240 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
241 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
242 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
Seth Heasley64a39032011-03-11 11:57:42 -0800243 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
Seth Heasleya4a461a2011-01-10 12:57:17 -0800244 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
Seth Heasley181e3ce2011-04-20 08:45:20 -0700245 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
246 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
247 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
248 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
249 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
250 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
Seth Heasley2cab7a42011-07-14 16:50:49 -0700251 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
Seth Heasleyea4ace62012-01-23 16:27:30 -0800252 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
253 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
254 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
255 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
256 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
257 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
258 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
259 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
James Ralston77b12bc92012-08-09 09:02:31 -0700260 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
261 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
262 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
263 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
264 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
265 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
266 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
267 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
Seth Heasley29e674d2013-01-25 12:01:05 -0800268 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
269 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
270 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
271 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
272 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
273 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
274 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
275 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
276 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
277 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
278 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
279 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
280 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
281 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
282 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
283 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
James Ralstonefda3322013-02-21 11:08:51 -0800284 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
285 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
James Ralston151743f2013-02-08 17:34:47 -0800286 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
287 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
288 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
289 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
290 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
291 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
292 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
293 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400294
Tejun Heoe34bb372007-02-26 20:24:03 +0900295 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
296 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
297 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
Ben Hutchings1fefb8f2012-09-10 01:09:04 +0100298 /* JMicron 362B and 362C have an AHCI function with IDE class code */
299 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
300 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400301
302 /* ATI */
Conke Huc65ec1c2007-04-11 18:23:14 +0800303 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
Shane Huange39fc8c2008-02-22 05:00:31 -0800304 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
305 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
306 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
307 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
308 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
309 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400310
Shane Huange2dd90b2009-07-29 11:34:49 +0800311 /* AMD */
Shane Huang5deab532009-10-13 11:14:00 +0800312 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
Shane Huange2dd90b2009-07-29 11:34:49 +0800313 /* AMD is using RAID class only for ahci controllers */
314 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
315 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
316
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400317 /* VIA */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400318 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
Tejun Heobf335542007-04-11 17:27:14 +0900319 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400320
321 /* NVIDIA */
Tejun Heoe297d992008-06-10 00:13:04 +0900322 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
323 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
324 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
325 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
326 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
327 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
328 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
329 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
Tejun Heo441577e2010-03-29 10:32:39 +0900330 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
331 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
332 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
333 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
334 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
335 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
336 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
337 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
338 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
339 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
340 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
341 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
342 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
343 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
344 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
345 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
346 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
347 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
348 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
349 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
350 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
351 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
352 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
353 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
354 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
355 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
356 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
357 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
358 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
359 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
360 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
361 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
362 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
363 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
364 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
365 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
366 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
367 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
368 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
369 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
370 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
371 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
372 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
373 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
374 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
375 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
376 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
377 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
378 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
379 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
380 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
381 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
382 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
383 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
384 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
385 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
386 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
387 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
388 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
389 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
390 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
391 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
392 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
393 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
394 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
395 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
396 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
397 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
398 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
399 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
400 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
401 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
402 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
403 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
404 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
405 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400406
Jeff Garzik95916ed2006-07-29 04:10:14 -0400407 /* SiS */
Tejun Heo20e2de42008-08-01 12:51:43 +0900408 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
409 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
410 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
Jeff Garzik95916ed2006-07-29 04:10:14 -0400411
Alessandro Rubini318893e2012-01-06 13:33:39 +0100412 /* ST Microelectronics */
413 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
414
Jeff Garzikcd70c262007-07-08 02:29:42 -0400415 /* Marvell */
416 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100417 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
Myron Stowe69fd3152013-04-08 11:32:49 -0600418 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
Anssi Hannula10aca062011-01-18 20:03:26 -0500419 .class = PCI_CLASS_STORAGE_SATA_AHCI,
420 .class_mask = 0xffffff,
Tejun Heo5f173102010-07-24 16:53:48 +0200421 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
Myron Stowe69fd3152013-04-08 11:32:49 -0600422 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
Per Jessen467b41c2011-02-08 13:54:32 +0100423 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
Myron Stowe69fd3152013-04-08 11:32:49 -0600424 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
Matt Johnson642d8922012-04-27 01:42:30 -0500425 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
Myron Stowe69fd3152013-04-08 11:32:49 -0600426 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
Alan Cox17c60c62012-09-04 16:07:18 +0100427 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
Myron Stowe69fd3152013-04-08 11:32:49 -0600428 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
Tejun Heo50be5e32010-11-29 15:57:14 +0100429 .driver_data = board_ahci_yes_fbs },
Jeff Garzikcd70c262007-07-08 02:29:42 -0400430
Mark Nelsonc77a0362008-10-23 14:08:16 +1100431 /* Promise */
432 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
433
Keng-Yu Linc9703762011-11-09 01:47:36 -0500434 /* Asmedia */
Alan Cox7b4f6ec2012-09-04 16:25:25 +0100435 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
436 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
437 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
438 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
Keng-Yu Linc9703762011-11-09 01:47:36 -0500439
Hugh Daschbach7f9c9f82013-01-04 14:39:09 -0800440 /* Enmotus */
441 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
442
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500443 /* Generic, PCI class code for AHCI */
444 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
Conke Huc9f89472007-01-09 05:32:51 -0500445 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500446
Linus Torvalds1da177e2005-04-16 15:20:36 -0700447 { } /* terminate list */
448};
449
450
451static struct pci_driver ahci_pci_driver = {
452 .name = DRV_NAME,
453 .id_table = ahci_pci_tbl,
454 .probe = ahci_init_one,
Tejun Heo24dc5f32007-01-20 16:00:28 +0900455 .remove = ata_pci_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900456#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900457 .suspend = ahci_pci_device_suspend,
458 .resume = ahci_pci_device_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900459#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700460};
461
Alan Cox5b66c822008-09-03 14:48:34 +0100462#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
463static int marvell_enable;
464#else
465static int marvell_enable = 1;
466#endif
467module_param(marvell_enable, int, 0644);
468MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
469
470
Anton Vorontsov394d6e52010-03-03 20:17:36 +0300471static void ahci_pci_save_initial_config(struct pci_dev *pdev,
472 struct ahci_host_priv *hpriv)
473{
474 unsigned int force_port_map = 0;
475 unsigned int mask_port_map = 0;
476
477 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
478 dev_info(&pdev->dev, "JMB361 has only one port\n");
479 force_port_map = 1;
480 }
481
482 /*
483 * Temporary Marvell 6145 hack: PATA port presence
484 * is asserted through the standard AHCI port
485 * presence register, as bit 4 (counting from 0)
486 */
487 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
488 if (pdev->device == 0x6121)
489 mask_port_map = 0x3;
490 else
491 mask_port_map = 0xf;
492 dev_info(&pdev->dev,
493 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
494 }
495
Anton Vorontsov1d513352010-03-03 20:17:37 +0300496 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
497 mask_port_map);
Anton Vorontsov394d6e52010-03-03 20:17:36 +0300498}
499
Anton Vorontsov33030402010-03-03 20:17:39 +0300500static int ahci_pci_reset_controller(struct ata_host *host)
501{
502 struct pci_dev *pdev = to_pci_dev(host->dev);
503
504 ahci_reset_controller(host);
505
Tejun Heod91542c2006-07-26 15:59:26 +0900506 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
Anton Vorontsov33030402010-03-03 20:17:39 +0300507 struct ahci_host_priv *hpriv = host->private_data;
Tejun Heod91542c2006-07-26 15:59:26 +0900508 u16 tmp16;
509
510 /* configure PCS */
511 pci_read_config_word(pdev, 0x92, &tmp16);
Tejun Heo49f29092007-11-19 16:03:44 +0900512 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
513 tmp16 |= hpriv->port_map;
514 pci_write_config_word(pdev, 0x92, tmp16);
515 }
Tejun Heod91542c2006-07-26 15:59:26 +0900516 }
517
518 return 0;
519}
520
Anton Vorontsov781d6552010-03-03 20:17:42 +0300521static void ahci_pci_init_controller(struct ata_host *host)
522{
523 struct ahci_host_priv *hpriv = host->private_data;
524 struct pci_dev *pdev = to_pci_dev(host->dev);
525 void __iomem *port_mmio;
526 u32 tmp;
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100527 int mv;
Tejun Heod91542c2006-07-26 15:59:26 +0900528
Tejun Heo417a1a62007-09-23 13:19:55 +0900529 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100530 if (pdev->device == 0x6121)
531 mv = 2;
532 else
533 mv = 4;
534 port_mmio = __ahci_port_base(host, mv);
Jeff Garzikcd70c262007-07-08 02:29:42 -0400535
536 writel(0, port_mmio + PORT_IRQ_MASK);
537
538 /* clear port IRQ */
539 tmp = readl(port_mmio + PORT_IRQ_STAT);
540 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
541 if (tmp)
542 writel(tmp, port_mmio + PORT_IRQ_STAT);
543 }
544
Anton Vorontsov781d6552010-03-03 20:17:42 +0300545 ahci_init_controller(host);
Tejun Heod91542c2006-07-26 15:59:26 +0900546}
547
Tejun Heocc0680a2007-08-06 18:36:23 +0900548static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
Tejun Heod4b2bab2007-02-02 16:50:52 +0900549 unsigned long deadline)
Tejun Heoad616ff2006-11-01 18:00:24 +0900550{
Tejun Heocc0680a2007-08-06 18:36:23 +0900551 struct ata_port *ap = link->ap;
Tejun Heo9dadd452008-04-07 22:47:19 +0900552 bool online;
Tejun Heoad616ff2006-11-01 18:00:24 +0900553 int rc;
554
555 DPRINTK("ENTER\n");
556
Tejun Heo4447d352007-04-17 23:44:08 +0900557 ahci_stop_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +0900558
Tejun Heocc0680a2007-08-06 18:36:23 +0900559 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
Tejun Heo9dadd452008-04-07 22:47:19 +0900560 deadline, &online, NULL);
Tejun Heoad616ff2006-11-01 18:00:24 +0900561
Tejun Heo4447d352007-04-17 23:44:08 +0900562 ahci_start_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +0900563
564 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
565
566 /* vt8251 doesn't clear BSY on signature FIS reception,
567 * request follow-up softreset.
568 */
Tejun Heo9dadd452008-04-07 22:47:19 +0900569 return online ? -EAGAIN : rc;
Tejun Heoad616ff2006-11-01 18:00:24 +0900570}
571
Tejun Heoedc93052007-10-25 14:59:16 +0900572static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
573 unsigned long deadline)
574{
575 struct ata_port *ap = link->ap;
576 struct ahci_port_priv *pp = ap->private_data;
577 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
578 struct ata_taskfile tf;
Tejun Heo9dadd452008-04-07 22:47:19 +0900579 bool online;
Tejun Heoedc93052007-10-25 14:59:16 +0900580 int rc;
581
582 ahci_stop_engine(ap);
583
584 /* clear D2H reception area to properly wait for D2H FIS */
585 ata_tf_init(link->device, &tf);
586 tf.command = 0x80;
587 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
588
589 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
Tejun Heo9dadd452008-04-07 22:47:19 +0900590 deadline, &online, NULL);
Tejun Heoedc93052007-10-25 14:59:16 +0900591
592 ahci_start_engine(ap);
593
Tejun Heoedc93052007-10-25 14:59:16 +0900594 /* The pseudo configuration device on SIMG4726 attached to
595 * ASUS P5W-DH Deluxe doesn't send signature FIS after
596 * hardreset if no device is attached to the first downstream
597 * port && the pseudo device locks up on SRST w/ PMP==0. To
598 * work around this, wait for !BSY only briefly. If BSY isn't
599 * cleared, perform CLO and proceed to IDENTIFY (achieved by
600 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
601 *
602 * Wait for two seconds. Devices attached to downstream port
603 * which can't process the following IDENTIFY after this will
604 * have to be reset again. For most cases, this should
605 * suffice while making probing snappish enough.
606 */
Tejun Heo9dadd452008-04-07 22:47:19 +0900607 if (online) {
608 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
609 ahci_check_ready);
610 if (rc)
Shane Huang78d5ae32009-08-07 15:05:52 +0800611 ahci_kick_engine(ap);
Tejun Heo9dadd452008-04-07 22:47:19 +0900612 }
Tejun Heo9dadd452008-04-07 22:47:19 +0900613 return rc;
Tejun Heoedc93052007-10-25 14:59:16 +0900614}
615
Tejun Heo438ac6d2007-03-02 17:31:26 +0900616#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900617static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
618{
Jingoo Han0a86e1c2013-06-03 14:05:36 +0900619 struct ata_host *host = pci_get_drvdata(pdev);
Tejun Heo9b10ae82009-05-30 20:50:12 +0900620 struct ahci_host_priv *hpriv = host->private_data;
Anton Vorontsovd8993342010-03-03 20:17:34 +0300621 void __iomem *mmio = hpriv->mmio;
Tejun Heoc1332872006-07-26 15:59:26 +0900622 u32 ctl;
623
Tejun Heo9b10ae82009-05-30 20:50:12 +0900624 if (mesg.event & PM_EVENT_SUSPEND &&
625 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
Joe Perchesa44fec12011-04-15 15:51:58 -0700626 dev_err(&pdev->dev,
627 "BIOS update required for suspend/resume\n");
Tejun Heo9b10ae82009-05-30 20:50:12 +0900628 return -EIO;
629 }
630
Rafael J. Wysocki3a2d5b72008-02-23 19:13:25 +0100631 if (mesg.event & PM_EVENT_SLEEP) {
Tejun Heoc1332872006-07-26 15:59:26 +0900632 /* AHCI spec rev1.1 section 8.3.3:
633 * Software must disable interrupts prior to requesting a
634 * transition of the HBA to D3 state.
635 */
636 ctl = readl(mmio + HOST_CTL);
637 ctl &= ~HOST_IRQ_EN;
638 writel(ctl, mmio + HOST_CTL);
639 readl(mmio + HOST_CTL); /* flush */
640 }
641
642 return ata_pci_device_suspend(pdev, mesg);
643}
644
645static int ahci_pci_device_resume(struct pci_dev *pdev)
646{
Jingoo Han0a86e1c2013-06-03 14:05:36 +0900647 struct ata_host *host = pci_get_drvdata(pdev);
Tejun Heoc1332872006-07-26 15:59:26 +0900648 int rc;
649
Tejun Heo553c4aa2006-12-26 19:39:50 +0900650 rc = ata_pci_device_do_resume(pdev);
651 if (rc)
652 return rc;
Tejun Heoc1332872006-07-26 15:59:26 +0900653
654 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
Anton Vorontsov33030402010-03-03 20:17:39 +0300655 rc = ahci_pci_reset_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +0900656 if (rc)
657 return rc;
658
Anton Vorontsov781d6552010-03-03 20:17:42 +0300659 ahci_pci_init_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +0900660 }
661
Jeff Garzikcca39742006-08-24 03:19:22 -0400662 ata_host_resume(host);
Tejun Heoc1332872006-07-26 15:59:26 +0900663
664 return 0;
665}
Tejun Heo438ac6d2007-03-02 17:31:26 +0900666#endif
Tejun Heoc1332872006-07-26 15:59:26 +0900667
Tejun Heo4447d352007-04-17 23:44:08 +0900668static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700669{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700670 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700671
Alessandro Rubini318893e2012-01-06 13:33:39 +0100672 /*
673 * If the device fixup already set the dma_mask to some non-standard
674 * value, don't extend it here. This happens on STA2X11, for example.
675 */
676 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
677 return 0;
678
Linus Torvalds1da177e2005-04-16 15:20:36 -0700679 if (using_dac &&
Yang Hongyang6a355282009-04-06 19:01:13 -0700680 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
681 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700682 if (rc) {
Yang Hongyang284901a2009-04-06 19:01:15 -0700683 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700684 if (rc) {
Joe Perchesa44fec12011-04-15 15:51:58 -0700685 dev_err(&pdev->dev,
686 "64-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700687 return rc;
688 }
689 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700690 } else {
Yang Hongyang284901a2009-04-06 19:01:15 -0700691 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700692 if (rc) {
Joe Perchesa44fec12011-04-15 15:51:58 -0700693 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700694 return rc;
695 }
Yang Hongyang284901a2009-04-06 19:01:15 -0700696 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700697 if (rc) {
Joe Perchesa44fec12011-04-15 15:51:58 -0700698 dev_err(&pdev->dev,
699 "32-bit consistent DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700700 return rc;
701 }
702 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700703 return 0;
704}
705
Anton Vorontsov439fcae2010-03-03 20:17:43 +0300706static void ahci_pci_print_info(struct ata_host *host)
707{
708 struct pci_dev *pdev = to_pci_dev(host->dev);
709 u16 cc;
710 const char *scc_s;
711
712 pci_read_config_word(pdev, 0x0a, &cc);
713 if (cc == PCI_CLASS_STORAGE_IDE)
714 scc_s = "IDE";
715 else if (cc == PCI_CLASS_STORAGE_SATA)
716 scc_s = "SATA";
717 else if (cc == PCI_CLASS_STORAGE_RAID)
718 scc_s = "RAID";
719 else
720 scc_s = "unknown";
721
722 ahci_print_info(host, scc_s);
723}
724
Tejun Heoedc93052007-10-25 14:59:16 +0900725/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
726 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
727 * support PMP and the 4726 either directly exports the device
728 * attached to the first downstream port or acts as a hardware storage
729 * controller and emulate a single ATA device (can be RAID 0/1 or some
730 * other configuration).
731 *
732 * When there's no device attached to the first downstream port of the
733 * 4726, "Config Disk" appears, which is a pseudo ATA device to
734 * configure the 4726. However, ATA emulation of the device is very
735 * lame. It doesn't send signature D2H Reg FIS after the initial
736 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
737 *
738 * The following function works around the problem by always using
739 * hardreset on the port and not depending on receiving signature FIS
740 * afterward. If signature FIS isn't received soon, ATA class is
741 * assumed without follow-up softreset.
742 */
743static void ahci_p5wdh_workaround(struct ata_host *host)
744{
745 static struct dmi_system_id sysids[] = {
746 {
747 .ident = "P5W DH Deluxe",
748 .matches = {
749 DMI_MATCH(DMI_SYS_VENDOR,
750 "ASUSTEK COMPUTER INC"),
751 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
752 },
753 },
754 { }
755 };
756 struct pci_dev *pdev = to_pci_dev(host->dev);
757
758 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
759 dmi_check_system(sysids)) {
760 struct ata_port *ap = host->ports[1];
761
Joe Perchesa44fec12011-04-15 15:51:58 -0700762 dev_info(&pdev->dev,
763 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
Tejun Heoedc93052007-10-25 14:59:16 +0900764
765 ap->ops = &ahci_p5wdh_ops;
766 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
767 }
768}
769
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900770/* only some SB600 ahci controllers can do 64bit DMA */
771static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
Shane Huang58a09b32009-05-27 15:04:43 +0800772{
773 static const struct dmi_system_id sysids[] = {
Tejun Heo03d783b2009-08-16 21:04:02 +0900774 /*
775 * The oldest version known to be broken is 0901 and
776 * working is 1501 which was released on 2007-10-26.
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900777 * Enable 64bit DMA on 1501 and anything newer.
778 *
Tejun Heo03d783b2009-08-16 21:04:02 +0900779 * Please read bko#9412 for more info.
780 */
Shane Huang58a09b32009-05-27 15:04:43 +0800781 {
782 .ident = "ASUS M2A-VM",
783 .matches = {
784 DMI_MATCH(DMI_BOARD_VENDOR,
785 "ASUSTeK Computer INC."),
786 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
787 },
Tejun Heo03d783b2009-08-16 21:04:02 +0900788 .driver_data = "20071026", /* yyyymmdd */
Shane Huang58a09b32009-05-27 15:04:43 +0800789 },
Mark Nelsone65cc192009-11-03 20:06:48 +1100790 /*
791 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
792 * support 64bit DMA.
793 *
794 * BIOS versions earlier than 1.5 had the Manufacturer DMI
795 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
796 * This spelling mistake was fixed in BIOS version 1.5, so
797 * 1.5 and later have the Manufacturer as
798 * "MICRO-STAR INTERNATIONAL CO.,LTD".
799 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
800 *
801 * BIOS versions earlier than 1.9 had a Board Product Name
802 * DMI field of "MS-7376". This was changed to be
803 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
804 * match on DMI_BOARD_NAME of "MS-7376".
805 */
806 {
807 .ident = "MSI K9A2 Platinum",
808 .matches = {
809 DMI_MATCH(DMI_BOARD_VENDOR,
810 "MICRO-STAR INTER"),
811 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
812 },
813 },
Mark Nelson3c4aa912011-06-27 16:33:44 +1000814 /*
Mark Nelsonff0173c2012-06-28 12:32:14 +1000815 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
816 * 64bit DMA.
817 *
818 * This board also had the typo mentioned above in the
819 * Manufacturer DMI field (fixed in BIOS version 1.5), so
820 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
821 */
822 {
823 .ident = "MSI K9AGM2",
824 .matches = {
825 DMI_MATCH(DMI_BOARD_VENDOR,
826 "MICRO-STAR INTER"),
827 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
828 },
829 },
830 /*
Mark Nelson3c4aa912011-06-27 16:33:44 +1000831 * All BIOS versions for the Asus M3A support 64bit DMA.
832 * (all release versions from 0301 to 1206 were tested)
833 */
834 {
835 .ident = "ASUS M3A",
836 .matches = {
837 DMI_MATCH(DMI_BOARD_VENDOR,
838 "ASUSTeK Computer INC."),
839 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
840 },
841 },
Shane Huang58a09b32009-05-27 15:04:43 +0800842 { }
843 };
Tejun Heo03d783b2009-08-16 21:04:02 +0900844 const struct dmi_system_id *match;
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900845 int year, month, date;
846 char buf[9];
Shane Huang58a09b32009-05-27 15:04:43 +0800847
Tejun Heo03d783b2009-08-16 21:04:02 +0900848 match = dmi_first_match(sysids);
Shane Huang58a09b32009-05-27 15:04:43 +0800849 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
Tejun Heo03d783b2009-08-16 21:04:02 +0900850 !match)
Shane Huang58a09b32009-05-27 15:04:43 +0800851 return false;
852
Mark Nelsone65cc192009-11-03 20:06:48 +1100853 if (!match->driver_data)
854 goto enable_64bit;
855
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900856 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
857 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
Shane Huang58a09b32009-05-27 15:04:43 +0800858
Mark Nelsone65cc192009-11-03 20:06:48 +1100859 if (strcmp(buf, match->driver_data) >= 0)
860 goto enable_64bit;
861 else {
Joe Perchesa44fec12011-04-15 15:51:58 -0700862 dev_warn(&pdev->dev,
863 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
864 match->ident);
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900865 return false;
866 }
Mark Nelsone65cc192009-11-03 20:06:48 +1100867
868enable_64bit:
Joe Perchesa44fec12011-04-15 15:51:58 -0700869 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
Mark Nelsone65cc192009-11-03 20:06:48 +1100870 return true;
Shane Huang58a09b32009-05-27 15:04:43 +0800871}
872
Rafael J. Wysocki1fd68432009-01-19 20:57:36 +0100873static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
874{
875 static const struct dmi_system_id broken_systems[] = {
876 {
877 .ident = "HP Compaq nx6310",
878 .matches = {
879 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
880 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
881 },
882 /* PCI slot number of the controller */
883 .driver_data = (void *)0x1FUL,
884 },
Maciej Ruteckid2f9c062009-03-20 00:06:46 +0100885 {
886 .ident = "HP Compaq 6720s",
887 .matches = {
888 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
889 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
890 },
891 /* PCI slot number of the controller */
892 .driver_data = (void *)0x1FUL,
893 },
Rafael J. Wysocki1fd68432009-01-19 20:57:36 +0100894
895 { } /* terminate list */
896 };
897 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
898
899 if (dmi) {
900 unsigned long slot = (unsigned long)dmi->driver_data;
901 /* apply the quirk only to on-board controllers */
902 return slot == PCI_SLOT(pdev->devfn);
903 }
904
905 return false;
906}
907
Tejun Heo9b10ae82009-05-30 20:50:12 +0900908static bool ahci_broken_suspend(struct pci_dev *pdev)
909{
910 static const struct dmi_system_id sysids[] = {
911 /*
912 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
913 * to the harddisk doesn't become online after
914 * resuming from STR. Warn and fail suspend.
Tejun Heo9deb3432010-03-16 09:50:26 +0900915 *
916 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
917 *
918 * Use dates instead of versions to match as HP is
919 * apparently recycling both product and version
920 * strings.
921 *
922 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
Tejun Heo9b10ae82009-05-30 20:50:12 +0900923 */
924 {
925 .ident = "dv4",
926 .matches = {
927 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
928 DMI_MATCH(DMI_PRODUCT_NAME,
929 "HP Pavilion dv4 Notebook PC"),
930 },
Tejun Heo9deb3432010-03-16 09:50:26 +0900931 .driver_data = "20090105", /* F.30 */
Tejun Heo9b10ae82009-05-30 20:50:12 +0900932 },
933 {
934 .ident = "dv5",
935 .matches = {
936 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
937 DMI_MATCH(DMI_PRODUCT_NAME,
938 "HP Pavilion dv5 Notebook PC"),
939 },
Tejun Heo9deb3432010-03-16 09:50:26 +0900940 .driver_data = "20090506", /* F.16 */
Tejun Heo9b10ae82009-05-30 20:50:12 +0900941 },
942 {
943 .ident = "dv6",
944 .matches = {
945 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
946 DMI_MATCH(DMI_PRODUCT_NAME,
947 "HP Pavilion dv6 Notebook PC"),
948 },
Tejun Heo9deb3432010-03-16 09:50:26 +0900949 .driver_data = "20090423", /* F.21 */
Tejun Heo9b10ae82009-05-30 20:50:12 +0900950 },
951 {
952 .ident = "HDX18",
953 .matches = {
954 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
955 DMI_MATCH(DMI_PRODUCT_NAME,
956 "HP HDX18 Notebook PC"),
957 },
Tejun Heo9deb3432010-03-16 09:50:26 +0900958 .driver_data = "20090430", /* F.23 */
Tejun Heo9b10ae82009-05-30 20:50:12 +0900959 },
Tejun Heocedc9bf2010-01-28 16:04:15 +0900960 /*
961 * Acer eMachines G725 has the same problem. BIOS
962 * V1.03 is known to be broken. V3.04 is known to
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300963 * work. Between, there are V1.06, V2.06 and V3.03
Tejun Heocedc9bf2010-01-28 16:04:15 +0900964 * that we don't have much idea about. For now,
965 * blacklist anything older than V3.04.
Tejun Heo9deb3432010-03-16 09:50:26 +0900966 *
967 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
Tejun Heocedc9bf2010-01-28 16:04:15 +0900968 */
969 {
970 .ident = "G725",
971 .matches = {
972 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
973 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
974 },
Tejun Heo9deb3432010-03-16 09:50:26 +0900975 .driver_data = "20091216", /* V3.04 */
Tejun Heocedc9bf2010-01-28 16:04:15 +0900976 },
Tejun Heo9b10ae82009-05-30 20:50:12 +0900977 { } /* terminate list */
978 };
979 const struct dmi_system_id *dmi = dmi_first_match(sysids);
Tejun Heo9deb3432010-03-16 09:50:26 +0900980 int year, month, date;
981 char buf[9];
Tejun Heo9b10ae82009-05-30 20:50:12 +0900982
983 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
984 return false;
985
Tejun Heo9deb3432010-03-16 09:50:26 +0900986 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
987 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
Tejun Heo9b10ae82009-05-30 20:50:12 +0900988
Tejun Heo9deb3432010-03-16 09:50:26 +0900989 return strcmp(buf, dmi->driver_data) < 0;
Tejun Heo9b10ae82009-05-30 20:50:12 +0900990}
991
Tejun Heo55946392009-08-04 14:30:08 +0900992static bool ahci_broken_online(struct pci_dev *pdev)
993{
994#define ENCODE_BUSDEVFN(bus, slot, func) \
995 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
996 static const struct dmi_system_id sysids[] = {
997 /*
998 * There are several gigabyte boards which use
999 * SIMG5723s configured as hardware RAID. Certain
1000 * 5723 firmware revisions shipped there keep the link
1001 * online but fail to answer properly to SRST or
1002 * IDENTIFY when no device is attached downstream
1003 * causing libata to retry quite a few times leading
1004 * to excessive detection delay.
1005 *
1006 * As these firmwares respond to the second reset try
1007 * with invalid device signature, considering unknown
1008 * sig as offline works around the problem acceptably.
1009 */
1010 {
1011 .ident = "EP45-DQ6",
1012 .matches = {
1013 DMI_MATCH(DMI_BOARD_VENDOR,
1014 "Gigabyte Technology Co., Ltd."),
1015 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1016 },
1017 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1018 },
1019 {
1020 .ident = "EP45-DS5",
1021 .matches = {
1022 DMI_MATCH(DMI_BOARD_VENDOR,
1023 "Gigabyte Technology Co., Ltd."),
1024 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1025 },
1026 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1027 },
1028 { } /* terminate list */
1029 };
1030#undef ENCODE_BUSDEVFN
1031 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1032 unsigned int val;
1033
1034 if (!dmi)
1035 return false;
1036
1037 val = (unsigned long)dmi->driver_data;
1038
1039 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1040}
1041
Markus Trippelsdorf8e513212009-10-09 05:41:47 +02001042#ifdef CONFIG_ATA_ACPI
Tejun Heof80ae7e2009-09-16 04:18:03 +09001043static void ahci_gtf_filter_workaround(struct ata_host *host)
1044{
1045 static const struct dmi_system_id sysids[] = {
1046 /*
1047 * Aspire 3810T issues a bunch of SATA enable commands
1048 * via _GTF including an invalid one and one which is
1049 * rejected by the device. Among the successful ones
1050 * is FPDMA non-zero offset enable which when enabled
1051 * only on the drive side leads to NCQ command
1052 * failures. Filter it out.
1053 */
1054 {
1055 .ident = "Aspire 3810T",
1056 .matches = {
1057 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1058 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1059 },
1060 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1061 },
1062 { }
1063 };
1064 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1065 unsigned int filter;
1066 int i;
1067
1068 if (!dmi)
1069 return;
1070
1071 filter = (unsigned long)dmi->driver_data;
Joe Perchesa44fec12011-04-15 15:51:58 -07001072 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1073 filter, dmi->ident);
Tejun Heof80ae7e2009-09-16 04:18:03 +09001074
1075 for (i = 0; i < host->n_ports; i++) {
1076 struct ata_port *ap = host->ports[i];
1077 struct ata_link *link;
1078 struct ata_device *dev;
1079
1080 ata_for_each_link(link, ap, EDGE)
1081 ata_for_each_dev(dev, link, ALL)
1082 dev->gtf_filter |= filter;
1083 }
1084}
Markus Trippelsdorf8e513212009-10-09 05:41:47 +02001085#else
1086static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1087{}
1088#endif
Tejun Heof80ae7e2009-09-16 04:18:03 +09001089
Alexander Gordeev5ca72c42012-11-19 16:02:48 +01001090int ahci_init_interrupts(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1091{
1092 int rc;
1093 unsigned int maxvec;
1094
1095 if (!(hpriv->flags & AHCI_HFLAG_NO_MSI)) {
1096 rc = pci_enable_msi_block_auto(pdev, &maxvec);
1097 if (rc > 0) {
1098 if ((rc == maxvec) || (rc == 1))
1099 return rc;
1100 /*
1101 * Assume that advantage of multipe MSIs is negated,
1102 * so fallback to single MSI mode to save resources
1103 */
1104 pci_disable_msi(pdev);
1105 if (!pci_enable_msi(pdev))
1106 return 1;
1107 }
1108 }
1109
1110 pci_intx(pdev, 1);
1111 return 0;
1112}
1113
1114/**
1115 * ahci_host_activate - start AHCI host, request IRQs and register it
1116 * @host: target ATA host
1117 * @irq: base IRQ number to request
1118 * @n_msis: number of MSIs allocated for this host
1119 * @irq_handler: irq_handler used when requesting IRQs
1120 * @irq_flags: irq_flags used when requesting IRQs
1121 *
1122 * Similar to ata_host_activate, but requests IRQs according to AHCI-1.1
1123 * when multiple MSIs were allocated. That is one MSI per port, starting
1124 * from @irq.
1125 *
1126 * LOCKING:
1127 * Inherited from calling layer (may sleep).
1128 *
1129 * RETURNS:
1130 * 0 on success, -errno otherwise.
1131 */
1132int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis)
1133{
1134 int i, rc;
1135
1136 /* Sharing Last Message among several ports is not supported */
1137 if (n_msis < host->n_ports)
1138 return -EINVAL;
1139
1140 rc = ata_host_start(host);
1141 if (rc)
1142 return rc;
1143
1144 for (i = 0; i < host->n_ports; i++) {
Alexander Gordeevb29900e2013-05-22 08:53:48 +09001145 struct ahci_port_priv *pp = host->ports[i]->private_data;
1146
Alexander Gordeev5ca72c42012-11-19 16:02:48 +01001147 rc = devm_request_threaded_irq(host->dev,
1148 irq + i, ahci_hw_interrupt, ahci_thread_fn, IRQF_SHARED,
Alexander Gordeevb29900e2013-05-22 08:53:48 +09001149 pp->irq_desc, host->ports[i]);
Alexander Gordeev5ca72c42012-11-19 16:02:48 +01001150 if (rc)
1151 goto out_free_irqs;
1152 }
1153
1154 for (i = 0; i < host->n_ports; i++)
1155 ata_port_desc(host->ports[i], "irq %d", irq + i);
1156
1157 rc = ata_host_register(host, &ahci_sht);
1158 if (rc)
1159 goto out_free_all_irqs;
1160
1161 return 0;
1162
1163out_free_all_irqs:
1164 i = host->n_ports;
1165out_free_irqs:
1166 for (i--; i >= 0; i--)
1167 devm_free_irq(host->dev, irq + i, host->ports[i]);
1168
1169 return rc;
1170}
1171
Tejun Heo24dc5f32007-01-20 16:00:28 +09001172static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001173{
Tejun Heoe297d992008-06-10 00:13:04 +09001174 unsigned int board_id = ent->driver_data;
1175 struct ata_port_info pi = ahci_port_info[board_id];
Tejun Heo4447d352007-04-17 23:44:08 +09001176 const struct ata_port_info *ppi[] = { &pi, NULL };
Tejun Heo24dc5f32007-01-20 16:00:28 +09001177 struct device *dev = &pdev->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001178 struct ahci_host_priv *hpriv;
Tejun Heo4447d352007-04-17 23:44:08 +09001179 struct ata_host *host;
Alexander Gordeev5ca72c42012-11-19 16:02:48 +01001180 int n_ports, n_msis, i, rc;
Alessandro Rubini318893e2012-01-06 13:33:39 +01001181 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001182
1183 VPRINTK("ENTER\n");
1184
Justin P. Mattockb429dd52010-07-03 07:29:25 -07001185 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
Tejun Heo12fad3f2006-05-15 21:03:55 +09001186
Joe Perches06296a12011-04-15 15:52:00 -07001187 ata_print_version_once(&pdev->dev, DRV_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001188
Alan Cox5b66c822008-09-03 14:48:34 +01001189 /* The AHCI driver can only drive the SATA ports, the PATA driver
1190 can drive them all so if both drivers are selected make sure
1191 AHCI stays out of the way */
1192 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1193 return -ENODEV;
1194
Tejun Heoc6353b42010-06-17 11:42:22 +02001195 /*
1196 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1197 * ahci, use ata_generic instead.
1198 */
1199 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1200 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1201 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1202 pdev->subsystem_device == 0xcb89)
1203 return -ENODEV;
1204
Mark Nelson7a022672009-11-22 12:07:41 +11001205 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1206 * At the moment, we can only use the AHCI mode. Let the users know
1207 * that for SAS drives they're out of luck.
1208 */
1209 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
Joe Perchesa44fec12011-04-15 15:51:58 -07001210 dev_info(&pdev->dev,
1211 "PDC42819 can only drive SATA devices with this driver\n");
Mark Nelson7a022672009-11-22 12:07:41 +11001212
Hugh Daschbach7f9c9f82013-01-04 14:39:09 -08001213 /* Both Connext and Enmotus devices use non-standard BARs */
Alessandro Rubini318893e2012-01-06 13:33:39 +01001214 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1215 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
Hugh Daschbach7f9c9f82013-01-04 14:39:09 -08001216 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1217 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
Alessandro Rubini318893e2012-01-06 13:33:39 +01001218
Tejun Heo4447d352007-04-17 23:44:08 +09001219 /* acquire resources */
Tejun Heo24dc5f32007-01-20 16:00:28 +09001220 rc = pcim_enable_device(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001221 if (rc)
1222 return rc;
1223
Tejun Heodea55132008-03-11 19:52:31 +09001224 /* AHCI controllers often implement SFF compatible interface.
1225 * Grab all PCI BARs just in case.
1226 */
Alessandro Rubini318893e2012-01-06 13:33:39 +01001227 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001228 if (rc == -EBUSY)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001229 pcim_pin_device(pdev);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001230 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001231 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001232
Tejun Heoc4f77922007-12-06 15:09:43 +09001233 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1234 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1235 u8 map;
1236
1237 /* ICH6s share the same PCI ID for both piix and ahci
1238 * modes. Enabling ahci mode while MAP indicates
1239 * combined mode is a bad idea. Yield to ata_piix.
1240 */
1241 pci_read_config_byte(pdev, ICH_MAP, &map);
1242 if (map & 0x3) {
Joe Perchesa44fec12011-04-15 15:51:58 -07001243 dev_info(&pdev->dev,
1244 "controller is in combined mode, can't enable AHCI mode\n");
Tejun Heoc4f77922007-12-06 15:09:43 +09001245 return -ENODEV;
1246 }
1247 }
1248
Tejun Heo24dc5f32007-01-20 16:00:28 +09001249 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1250 if (!hpriv)
1251 return -ENOMEM;
Tejun Heo417a1a62007-09-23 13:19:55 +09001252 hpriv->flags |= (unsigned long)pi.private_data;
1253
Tejun Heoe297d992008-06-10 00:13:04 +09001254 /* MCP65 revision A1 and A2 can't do MSI */
1255 if (board_id == board_ahci_mcp65 &&
1256 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1257 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1258
Shane Huange427fe02008-12-30 10:53:41 +08001259 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1260 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1261 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1262
Tejun Heo2fcad9d2009-10-03 18:27:29 +09001263 /* only some SB600s can do 64bit DMA */
1264 if (ahci_sb600_enable_64bit(pdev))
1265 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
Shane Huang58a09b32009-05-27 15:04:43 +08001266
Alessandro Rubini318893e2012-01-06 13:33:39 +01001267 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
Anton Vorontsovd8993342010-03-03 20:17:34 +03001268
Alexander Gordeev5ca72c42012-11-19 16:02:48 +01001269 n_msis = ahci_init_interrupts(pdev, hpriv);
1270 if (n_msis > 1)
1271 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1272
Tejun Heo4447d352007-04-17 23:44:08 +09001273 /* save initial config */
Anton Vorontsov394d6e52010-03-03 20:17:36 +03001274 ahci_pci_save_initial_config(pdev, hpriv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001275
Tejun Heo4447d352007-04-17 23:44:08 +09001276 /* prepare host */
Robert Hancock453d3132010-01-26 22:33:23 -06001277 if (hpriv->cap & HOST_CAP_NCQ) {
1278 pi.flags |= ATA_FLAG_NCQ;
Tejun Heo83f2b962010-03-30 10:28:32 +09001279 /*
1280 * Auto-activate optimization is supposed to be
1281 * supported on all AHCI controllers indicating NCQ
1282 * capability, but it seems to be broken on some
1283 * chipsets including NVIDIAs.
1284 */
1285 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
Robert Hancock453d3132010-01-26 22:33:23 -06001286 pi.flags |= ATA_FLAG_FPDMA_AA;
1287 }
Tejun Heo4447d352007-04-17 23:44:08 +09001288
Tejun Heo7d50b602007-09-23 13:19:54 +09001289 if (hpriv->cap & HOST_CAP_PMP)
1290 pi.flags |= ATA_FLAG_PMP;
1291
Anton Vorontsov0cbb0e72010-03-03 20:17:45 +03001292 ahci_set_em_messages(hpriv, &pi);
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001293
Rafael J. Wysocki1fd68432009-01-19 20:57:36 +01001294 if (ahci_broken_system_poweroff(pdev)) {
1295 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1296 dev_info(&pdev->dev,
1297 "quirky BIOS, skipping spindown on poweroff\n");
1298 }
1299
Tejun Heo9b10ae82009-05-30 20:50:12 +09001300 if (ahci_broken_suspend(pdev)) {
1301 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
Joe Perchesa44fec12011-04-15 15:51:58 -07001302 dev_warn(&pdev->dev,
1303 "BIOS update required for suspend/resume\n");
Tejun Heo9b10ae82009-05-30 20:50:12 +09001304 }
1305
Tejun Heo55946392009-08-04 14:30:08 +09001306 if (ahci_broken_online(pdev)) {
1307 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1308 dev_info(&pdev->dev,
1309 "online status unreliable, applying workaround\n");
1310 }
1311
Tejun Heo837f5f82008-02-06 15:13:51 +09001312 /* CAP.NP sometimes indicate the index of the last enabled
1313 * port, at other times, that of the last possible port, so
1314 * determining the maximum port number requires looking at
1315 * both CAP.NP and port_map.
1316 */
1317 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1318
1319 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
Tejun Heo4447d352007-04-17 23:44:08 +09001320 if (!host)
1321 return -ENOMEM;
Tejun Heo4447d352007-04-17 23:44:08 +09001322 host->private_data = hpriv;
1323
Arjan van de Venf3d7f232009-01-26 02:05:44 -08001324 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
Arjan van de Ven886ad092009-01-09 15:54:07 -08001325 host->flags |= ATA_HOST_PARALLEL_SCAN;
Arjan van de Venf3d7f232009-01-26 02:05:44 -08001326 else
1327 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
Arjan van de Ven886ad092009-01-09 15:54:07 -08001328
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001329 if (pi.flags & ATA_FLAG_EM)
1330 ahci_reset_em(host);
1331
Tejun Heo4447d352007-04-17 23:44:08 +09001332 for (i = 0; i < host->n_ports; i++) {
Jeff Garzikdab632e2007-05-28 08:33:01 -04001333 struct ata_port *ap = host->ports[i];
Tejun Heo4447d352007-04-17 23:44:08 +09001334
Alessandro Rubini318893e2012-01-06 13:33:39 +01001335 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1336 ata_port_pbar_desc(ap, ahci_pci_bar,
Tejun Heocbcdd872007-08-18 13:14:55 +09001337 0x100 + ap->port_no * 0x80, "port");
1338
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001339 /* set enclosure management message type */
1340 if (ap->flags & ATA_FLAG_EM)
Harry Zhang008dbd62010-04-23 17:27:19 +08001341 ap->em_message_type = hpriv->em_msg_type;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001342
1343
Jeff Garzikdab632e2007-05-28 08:33:01 -04001344 /* disabled/not-implemented port */
Tejun Heo350756f2008-04-07 22:47:21 +09001345 if (!(hpriv->port_map & (1 << i)))
Jeff Garzikdab632e2007-05-28 08:33:01 -04001346 ap->ops = &ata_dummy_port_ops;
Tejun Heo4447d352007-04-17 23:44:08 +09001347 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001348
Tejun Heoedc93052007-10-25 14:59:16 +09001349 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1350 ahci_p5wdh_workaround(host);
1351
Tejun Heof80ae7e2009-09-16 04:18:03 +09001352 /* apply gtf filter quirk */
1353 ahci_gtf_filter_workaround(host);
1354
Linus Torvalds1da177e2005-04-16 15:20:36 -07001355 /* initialize adapter */
Tejun Heo4447d352007-04-17 23:44:08 +09001356 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001357 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001358 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001359
Anton Vorontsov33030402010-03-03 20:17:39 +03001360 rc = ahci_pci_reset_controller(host);
Tejun Heo4447d352007-04-17 23:44:08 +09001361 if (rc)
1362 return rc;
Tejun Heo12fad3f2006-05-15 21:03:55 +09001363
Anton Vorontsov781d6552010-03-03 20:17:42 +03001364 ahci_pci_init_controller(host);
Anton Vorontsov439fcae2010-03-03 20:17:43 +03001365 ahci_pci_print_info(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001366
Tejun Heo4447d352007-04-17 23:44:08 +09001367 pci_set_master(pdev);
Alexander Gordeev5ca72c42012-11-19 16:02:48 +01001368
1369 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
1370 return ahci_host_activate(host, pdev->irq, n_msis);
1371
Tejun Heo4447d352007-04-17 23:44:08 +09001372 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1373 &ahci_sht);
Jeff Garzik907f4672005-05-12 15:03:42 -04001374}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001375
Axel Lin2fc75da2012-04-19 13:43:05 +08001376module_pci_driver(ahci_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001377
1378MODULE_AUTHOR("Jeff Garzik");
1379MODULE_DESCRIPTION("AHCI SATA low-level driver");
1380MODULE_LICENSE("GPL");
1381MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
Jeff Garzik68854332005-08-23 02:53:51 -04001382MODULE_VERSION(DRV_VERSION);