Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1 | /**************************************************************************** |
| 2 | * Driver for Solarflare Solarstorm network controllers and boards |
| 3 | * Copyright 2005 Fen Systems Ltd. |
| 4 | * Copyright 2006 Solarflare Communications Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License version 2 as published |
| 8 | * by the Free Software Foundation, incorporated herein by reference. |
| 9 | */ |
| 10 | |
| 11 | #ifndef EFX_SPI_H |
| 12 | #define EFX_SPI_H |
| 13 | |
| 14 | #include "net_driver.h" |
| 15 | |
| 16 | /************************************************************************** |
| 17 | * |
| 18 | * Basic SPI command set and bit definitions |
| 19 | * |
| 20 | *************************************************************************/ |
| 21 | |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 22 | #define SPI_WRSR 0x01 /* Write status register */ |
| 23 | #define SPI_WRITE 0x02 /* Write data to memory array */ |
| 24 | #define SPI_READ 0x03 /* Read data from memory array */ |
| 25 | #define SPI_WRDI 0x04 /* Reset write enable latch */ |
| 26 | #define SPI_RDSR 0x05 /* Read status register */ |
| 27 | #define SPI_WREN 0x06 /* Set write enable latch */ |
| 28 | |
| 29 | #define SPI_STATUS_WPEN 0x80 /* Write-protect pin enabled */ |
| 30 | #define SPI_STATUS_BP2 0x10 /* Block protection bit 2 */ |
| 31 | #define SPI_STATUS_BP1 0x08 /* Block protection bit 1 */ |
| 32 | #define SPI_STATUS_BP0 0x04 /* Block protection bit 0 */ |
| 33 | #define SPI_STATUS_WEN 0x02 /* State of the write enable latch */ |
| 34 | #define SPI_STATUS_NRDY 0x01 /* Device busy flag */ |
| 35 | |
| 36 | /** |
| 37 | * struct efx_spi_device - an Efx SPI (Serial Peripheral Interface) device |
| 38 | * @efx: The Efx controller that owns this device |
| 39 | * @device_id: Controller's id for the device |
| 40 | * @size: Size (in bytes) |
| 41 | * @addr_len: Number of address bytes in read/write commands |
| 42 | * @munge_address: Flag whether addresses should be munged. |
| 43 | * Some devices with 9-bit addresses (e.g. AT25040A EEPROM) |
| 44 | * use bit 3 of the command byte as address bit A8, rather |
| 45 | * than having a two-byte address. If this flag is set, then |
| 46 | * commands should be munged in this way. |
| 47 | * @block_size: Write block size (in bytes). |
| 48 | * Write commands are limited to blocks with this size and alignment. |
| 49 | * @read: Read function for the device |
| 50 | * @write: Write function for the device |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 51 | */ |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 52 | struct efx_spi_device { |
| 53 | struct efx_nic *efx; |
| 54 | int device_id; |
| 55 | unsigned int size; |
| 56 | unsigned int addr_len; |
| 57 | unsigned int munge_address:1; |
| 58 | unsigned int block_size; |
| 59 | }; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 60 | |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 61 | int falcon_spi_read(const struct efx_spi_device *spi, loff_t start, |
| 62 | size_t len, size_t *retlen, u8 *buffer); |
| 63 | int falcon_spi_write(const struct efx_spi_device *spi, loff_t start, |
| 64 | size_t len, size_t *retlen, const u8 *buffer); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 65 | |
Ben Hutchings | 0a95f56 | 2008-11-04 20:33:11 +0000 | [diff] [blame^] | 66 | /* |
| 67 | * SFC4000 flash is partitioned into: |
| 68 | * 0-0x400 chip and board config (see falcon_hwdefs.h) |
| 69 | * 0x400-0x8000 unused (or may contain VPD if EEPROM not present) |
| 70 | * 0x8000-end boot code (mapped to PCI expansion ROM) |
| 71 | * SFC4000 small EEPROM (size < 0x400) is used for VPD only. |
| 72 | * SFC4000 large EEPROM (size >= 0x400) is partitioned into: |
| 73 | * 0-0x400 chip and board config |
| 74 | * configurable VPD |
| 75 | * 0x800-0x1800 boot config |
| 76 | * Aside from the chip and board config, all of these are optional and may |
| 77 | * be absent or truncated depending on the devices used. |
| 78 | */ |
| 79 | #define FALCON_NVCONFIG_END 0x400U |
| 80 | #define EFX_EEPROM_BOOTCONFIG_START 0x800U |
| 81 | #define EFX_EEPROM_BOOTCONFIG_END 0x1800U |
| 82 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 83 | #endif /* EFX_SPI_H */ |