Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
| 2 | */ |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 3 | /* |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 4 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 6 | * All Rights Reserved. |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 7 | * |
| 8 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 9 | * copy of this software and associated documentation files (the |
| 10 | * "Software"), to deal in the Software without restriction, including |
| 11 | * without limitation the rights to use, copy, modify, merge, publish, |
| 12 | * distribute, sub license, and/or sell copies of the Software, and to |
| 13 | * permit persons to whom the Software is furnished to do so, subject to |
| 14 | * the following conditions: |
| 15 | * |
| 16 | * The above copyright notice and this permission notice (including the |
| 17 | * next paragraph) shall be included in all copies or substantial portions |
| 18 | * of the Software. |
| 19 | * |
| 20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 27 | * |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 28 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | |
| 30 | #ifndef _I915_DRV_H_ |
| 31 | #define _I915_DRV_H_ |
| 32 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 33 | #include "i915_reg.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 34 | #include "intel_bios.h" |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 35 | #include "intel_ringbuffer.h" |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 36 | #include <linux/io-mapping.h> |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 37 | #include <linux/i2c.h> |
Daniel Vetter | c167a6f | 2012-02-28 00:43:09 +0100 | [diff] [blame] | 38 | #include <linux/i2c-algo-bit.h> |
Daniel Vetter | 0ade638 | 2010-08-24 22:18:41 +0200 | [diff] [blame] | 39 | #include <drm/intel-gtt.h> |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 40 | #include <linux/backlight.h> |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 41 | #include <linux/intel-iommu.h> |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 42 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 43 | /* General customization: |
| 44 | */ |
| 45 | |
| 46 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." |
| 47 | |
| 48 | #define DRIVER_NAME "i915" |
| 49 | #define DRIVER_DESC "Intel Graphics" |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 50 | #define DRIVER_DATE "20080730" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 51 | |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 52 | enum pipe { |
| 53 | PIPE_A = 0, |
| 54 | PIPE_B, |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 55 | PIPE_C, |
| 56 | I915_MAX_PIPES |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 57 | }; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 58 | #define pipe_name(p) ((p) + 'A') |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 59 | |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 60 | enum plane { |
| 61 | PLANE_A = 0, |
| 62 | PLANE_B, |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 63 | PLANE_C, |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 64 | }; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 65 | #define plane_name(p) ((p) + 'A') |
Keith Packard | 5244021 | 2008-11-18 09:30:25 -0800 | [diff] [blame] | 66 | |
Eugeni Dodonov | 2b13952 | 2012-03-29 12:32:22 -0300 | [diff] [blame] | 67 | enum port { |
| 68 | PORT_A = 0, |
| 69 | PORT_B, |
| 70 | PORT_C, |
| 71 | PORT_D, |
| 72 | PORT_E, |
| 73 | I915_MAX_PORTS |
| 74 | }; |
| 75 | #define port_name(p) ((p) + 'A') |
| 76 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 77 | #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) |
| 78 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 79 | #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) |
| 80 | |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 81 | struct intel_pch_pll { |
| 82 | int refcount; /* count of number of CRTCs sharing this PLL */ |
| 83 | int active; /* count of number of active CRTCs (i.e. DPMS on) */ |
| 84 | bool on; /* is the PLL actually active? Disabled during modeset */ |
| 85 | int pll_reg; |
| 86 | int fp0_reg; |
| 87 | int fp1_reg; |
| 88 | }; |
| 89 | #define I915_NUM_PLLS 2 |
| 90 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 91 | /* Interface history: |
| 92 | * |
| 93 | * 1.1: Original. |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 94 | * 1.2: Add Power Management |
| 95 | * 1.3: Add vblank support |
Dave Airlie | de227f5 | 2006-01-25 15:31:43 +1100 | [diff] [blame] | 96 | * 1.4: Fix cmdbuffer path, add heap destroy |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 97 | * 1.5: Add vblank pipe configuration |
=?utf-8?q?Michel_D=C3=A4nzer?= | 2228ed6 | 2006-10-25 01:05:09 +1000 | [diff] [blame] | 98 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
| 99 | * - Support vertical blank on secondary display pipe |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 100 | */ |
| 101 | #define DRIVER_MAJOR 1 |
=?utf-8?q?Michel_D=C3=A4nzer?= | 2228ed6 | 2006-10-25 01:05:09 +1000 | [diff] [blame] | 102 | #define DRIVER_MINOR 6 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 103 | #define DRIVER_PATCHLEVEL 0 |
| 104 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 105 | #define WATCH_COHERENCY 0 |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 106 | #define WATCH_LISTS 0 |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 107 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 108 | #define I915_GEM_PHYS_CURSOR_0 1 |
| 109 | #define I915_GEM_PHYS_CURSOR_1 2 |
| 110 | #define I915_GEM_PHYS_OVERLAY_REGS 3 |
| 111 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) |
| 112 | |
| 113 | struct drm_i915_gem_phys_object { |
| 114 | int id; |
| 115 | struct page **page_list; |
| 116 | drm_dma_handle_t *handle; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 117 | struct drm_i915_gem_object *cur_obj; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 118 | }; |
| 119 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 120 | struct mem_block { |
| 121 | struct mem_block *next; |
| 122 | struct mem_block *prev; |
| 123 | int start; |
| 124 | int size; |
Eric Anholt | 6c340ea | 2007-08-25 20:23:09 +1000 | [diff] [blame] | 125 | struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 126 | }; |
| 127 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 128 | struct opregion_header; |
| 129 | struct opregion_acpi; |
| 130 | struct opregion_swsci; |
| 131 | struct opregion_asle; |
Keith Packard | 8d715f0 | 2011-11-18 20:39:01 -0800 | [diff] [blame] | 132 | struct drm_i915_private; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 133 | |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 134 | struct intel_opregion { |
Ben Widawsky | 5bc4418 | 2012-04-16 14:07:42 -0700 | [diff] [blame] | 135 | struct opregion_header __iomem *header; |
| 136 | struct opregion_acpi __iomem *acpi; |
| 137 | struct opregion_swsci __iomem *swsci; |
| 138 | struct opregion_asle __iomem *asle; |
| 139 | void __iomem *vbt; |
Chris Wilson | 01fe9db | 2011-01-16 19:37:30 +0000 | [diff] [blame] | 140 | u32 __iomem *lid_state; |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 141 | }; |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 142 | #define OPREGION_SIZE (8*1024) |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 143 | |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 144 | struct intel_overlay; |
| 145 | struct intel_overlay_error_state; |
| 146 | |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 147 | struct drm_i915_master_private { |
| 148 | drm_local_map_t *sarea; |
| 149 | struct _drm_i915_sarea *sarea_priv; |
| 150 | }; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 151 | #define I915_FENCE_REG_NONE -1 |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 152 | #define I915_MAX_NUM_FENCES 16 |
| 153 | /* 16 fences + sign bit for FENCE_REG_NONE */ |
| 154 | #define I915_MAX_NUM_FENCE_BITS 5 |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 155 | |
| 156 | struct drm_i915_fence_reg { |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 157 | struct list_head lru_list; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 158 | struct drm_i915_gem_object *obj; |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 159 | int pin_count; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 160 | }; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 161 | |
yakui_zhao | 9b9d172 | 2009-05-31 17:17:17 +0800 | [diff] [blame] | 162 | struct sdvo_device_mapping { |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 163 | u8 initialized; |
yakui_zhao | 9b9d172 | 2009-05-31 17:17:17 +0800 | [diff] [blame] | 164 | u8 dvo_port; |
| 165 | u8 slave_addr; |
| 166 | u8 dvo_wiring; |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 167 | u8 i2c_pin; |
Adam Jackson | b108333 | 2010-04-23 16:07:40 -0400 | [diff] [blame] | 168 | u8 ddc_pin; |
yakui_zhao | 9b9d172 | 2009-05-31 17:17:17 +0800 | [diff] [blame] | 169 | }; |
| 170 | |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 171 | struct intel_display_error_state; |
| 172 | |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 173 | struct drm_i915_error_state { |
| 174 | u32 eir; |
| 175 | u32 pgtbl_er; |
Ben Widawsky | be998e2 | 2012-04-26 16:03:00 -0700 | [diff] [blame] | 176 | u32 ier; |
Ben Widawsky | 9574b3f | 2012-04-26 16:03:01 -0700 | [diff] [blame] | 177 | bool waiting[I915_NUM_RINGS]; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 178 | u32 pipestat[I915_MAX_PIPES]; |
Daniel Vetter | c1cd90e | 2011-12-14 13:57:02 +0100 | [diff] [blame] | 179 | u32 tail[I915_NUM_RINGS]; |
| 180 | u32 head[I915_NUM_RINGS]; |
Daniel Vetter | d27b1e0 | 2011-12-14 13:57:01 +0100 | [diff] [blame] | 181 | u32 ipeir[I915_NUM_RINGS]; |
| 182 | u32 ipehr[I915_NUM_RINGS]; |
| 183 | u32 instdone[I915_NUM_RINGS]; |
| 184 | u32 acthd[I915_NUM_RINGS]; |
Daniel Vetter | 7e3b873 | 2012-02-01 22:26:45 +0100 | [diff] [blame] | 185 | u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; |
| 186 | /* our own tracking of ring head and tail */ |
| 187 | u32 cpu_ring_head[I915_NUM_RINGS]; |
| 188 | u32 cpu_ring_tail[I915_NUM_RINGS]; |
Chris Wilson | 1d8f38f | 2010-10-29 19:00:51 +0100 | [diff] [blame] | 189 | u32 error; /* gen6+ */ |
Daniel Vetter | c1cd90e | 2011-12-14 13:57:02 +0100 | [diff] [blame] | 190 | u32 instpm[I915_NUM_RINGS]; |
| 191 | u32 instps[I915_NUM_RINGS]; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 192 | u32 instdone1; |
Daniel Vetter | d27b1e0 | 2011-12-14 13:57:01 +0100 | [diff] [blame] | 193 | u32 seqno[I915_NUM_RINGS]; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 194 | u64 bbaddr; |
Daniel Vetter | 33f3f51 | 2011-12-14 13:57:39 +0100 | [diff] [blame] | 195 | u32 fault_reg[I915_NUM_RINGS]; |
| 196 | u32 done_reg; |
Daniel Vetter | c1cd90e | 2011-12-14 13:57:02 +0100 | [diff] [blame] | 197 | u32 faddr[I915_NUM_RINGS]; |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 198 | u64 fence[I915_MAX_NUM_FENCES]; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 199 | struct timeval time; |
Chris Wilson | 52d39a2 | 2012-02-15 11:25:37 +0000 | [diff] [blame] | 200 | struct drm_i915_error_ring { |
| 201 | struct drm_i915_error_object { |
| 202 | int page_count; |
| 203 | u32 gtt_offset; |
| 204 | u32 *pages[0]; |
| 205 | } *ringbuffer, *batchbuffer; |
| 206 | struct drm_i915_error_request { |
| 207 | long jiffies; |
| 208 | u32 seqno; |
Chris Wilson | ee4f42b | 2012-02-15 11:25:38 +0000 | [diff] [blame] | 209 | u32 tail; |
Chris Wilson | 52d39a2 | 2012-02-15 11:25:37 +0000 | [diff] [blame] | 210 | } *requests; |
| 211 | int num_requests; |
| 212 | } ring[I915_NUM_RINGS]; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 213 | struct drm_i915_error_buffer { |
Chris Wilson | a779e5a | 2011-01-09 21:07:49 +0000 | [diff] [blame] | 214 | u32 size; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 215 | u32 name; |
| 216 | u32 seqno; |
| 217 | u32 gtt_offset; |
| 218 | u32 read_domains; |
| 219 | u32 write_domain; |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 220 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 221 | s32 pinned:2; |
| 222 | u32 tiling:2; |
| 223 | u32 dirty:1; |
| 224 | u32 purgeable:1; |
Daniel Vetter | 5d1333f | 2012-02-16 11:03:29 +0100 | [diff] [blame] | 225 | s32 ring:4; |
Chris Wilson | 93dfb40 | 2011-03-29 16:59:50 -0700 | [diff] [blame] | 226 | u32 cache_level:2; |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 227 | } *active_bo, *pinned_bo; |
| 228 | u32 active_bo_count, pinned_bo_count; |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 229 | struct intel_overlay_error_state *overlay; |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 230 | struct intel_display_error_state *display; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 231 | }; |
| 232 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 233 | struct drm_i915_display_funcs { |
| 234 | void (*dpms)(struct drm_crtc *crtc, int mode); |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 235 | bool (*fbc_enabled)(struct drm_device *dev); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 236 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
| 237 | void (*disable_fbc)(struct drm_device *dev); |
| 238 | int (*get_display_clock_speed)(struct drm_device *dev); |
| 239 | int (*get_fifo_size)(struct drm_device *dev, int plane); |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 240 | void (*update_wm)(struct drm_device *dev); |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 241 | void (*update_sprite_wm)(struct drm_device *dev, int pipe, |
| 242 | uint32_t sprite_width, int pixel_size); |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 243 | int (*crtc_mode_set)(struct drm_crtc *crtc, |
| 244 | struct drm_display_mode *mode, |
| 245 | struct drm_display_mode *adjusted_mode, |
| 246 | int x, int y, |
| 247 | struct drm_framebuffer *old_fb); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 248 | void (*off)(struct drm_crtc *crtc); |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 249 | void (*write_eld)(struct drm_connector *connector, |
| 250 | struct drm_crtc *crtc); |
Jesse Barnes | 674cf96 | 2011-04-28 14:27:04 -0700 | [diff] [blame] | 251 | void (*fdi_link_train)(struct drm_crtc *crtc); |
Jesse Barnes | 6067aae | 2011-04-28 15:04:31 -0700 | [diff] [blame] | 252 | void (*init_clock_gating)(struct drm_device *dev); |
Jesse Barnes | 645c62a | 2011-05-11 09:49:31 -0700 | [diff] [blame] | 253 | void (*init_pch_clock_gating)(struct drm_device *dev); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 254 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
| 255 | struct drm_framebuffer *fb, |
| 256 | struct drm_i915_gem_object *obj); |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 257 | int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
| 258 | int x, int y); |
Keith Packard | 8d715f0 | 2011-11-18 20:39:01 -0800 | [diff] [blame] | 259 | void (*force_wake_get)(struct drm_i915_private *dev_priv); |
| 260 | void (*force_wake_put)(struct drm_i915_private *dev_priv); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 261 | /* clock updates for mode set */ |
| 262 | /* cursor updates */ |
| 263 | /* render clock increase/decrease */ |
| 264 | /* display clock increase/decrease */ |
| 265 | /* pll clock increase/decrease */ |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 266 | }; |
| 267 | |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 268 | struct intel_device_info { |
Chris Wilson | c96c3a8c | 2010-08-11 09:59:24 +0100 | [diff] [blame] | 269 | u8 gen; |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 270 | u8 is_mobile:1; |
| 271 | u8 is_i85x:1; |
| 272 | u8 is_i915g:1; |
| 273 | u8 is_i945gm:1; |
| 274 | u8 is_g33:1; |
| 275 | u8 need_gfx_hws:1; |
| 276 | u8 is_g4x:1; |
| 277 | u8 is_pineview:1; |
| 278 | u8 is_broadwater:1; |
| 279 | u8 is_crestline:1; |
| 280 | u8 is_ivybridge:1; |
Jesse Barnes | 70a3eb7 | 2012-03-28 13:39:21 -0700 | [diff] [blame] | 281 | u8 is_valleyview:1; |
Eugeni Dodonov | 7e508a2 | 2012-03-29 12:32:17 -0300 | [diff] [blame] | 282 | u8 has_pch_split:1; |
Eugeni Dodonov | 4cae9ae | 2012-03-29 12:32:18 -0300 | [diff] [blame] | 283 | u8 is_haswell:1; |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 284 | u8 has_fbc:1; |
| 285 | u8 has_pipe_cxsr:1; |
| 286 | u8 has_hotplug:1; |
| 287 | u8 cursor_needs_physical:1; |
| 288 | u8 has_overlay:1; |
| 289 | u8 overlay_needs_physical:1; |
| 290 | u8 supports_tv:1; |
| 291 | u8 has_bsd_ring:1; |
| 292 | u8 has_blt_ring:1; |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 293 | u8 has_llc:1; |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 294 | }; |
| 295 | |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 296 | #define I915_PPGTT_PD_ENTRIES 512 |
| 297 | #define I915_PPGTT_PT_ENTRIES 1024 |
| 298 | struct i915_hw_ppgtt { |
| 299 | unsigned num_pd_entries; |
| 300 | struct page **pt_pages; |
| 301 | uint32_t pd_offset; |
| 302 | dma_addr_t *pt_dma_addr; |
| 303 | dma_addr_t scratch_page_dma_addr; |
| 304 | }; |
| 305 | |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 306 | enum no_fbc_reason { |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 307 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 308 | FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ |
| 309 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ |
| 310 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ |
| 311 | FBC_BAD_PLANE, /* fbc not supported on plane */ |
| 312 | FBC_NOT_TILED, /* buffer not tiled */ |
Jesse Barnes | 9c928d1 | 2010-07-23 15:20:00 -0700 | [diff] [blame] | 313 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ |
Jesse Barnes | c1a9f04 | 2011-05-05 15:24:21 -0700 | [diff] [blame] | 314 | FBC_MODULE_PARAM, |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 315 | }; |
| 316 | |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 317 | enum intel_pch { |
| 318 | PCH_IBX, /* Ibexpeak PCH */ |
| 319 | PCH_CPT, /* Cougarpoint PCH */ |
Eugeni Dodonov | eb877eb | 2012-03-29 12:32:20 -0300 | [diff] [blame] | 320 | PCH_LPT, /* Lynxpoint PCH */ |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 321 | }; |
| 322 | |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 323 | #define QUIRK_PIPEA_FORCE (1<<0) |
Keith Packard | 435793d | 2011-07-12 14:56:22 -0700 | [diff] [blame] | 324 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
Carsten Emde | 4dca20e | 2012-03-15 15:56:26 +0100 | [diff] [blame] | 325 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 326 | |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 327 | struct intel_fbdev; |
Chris Wilson | 1630fe7 | 2011-07-08 12:22:42 +0100 | [diff] [blame] | 328 | struct intel_fbc_work; |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 329 | |
Daniel Vetter | c2b9152 | 2012-02-14 22:37:19 +0100 | [diff] [blame] | 330 | struct intel_gmbus { |
| 331 | struct i2c_adapter adapter; |
Daniel Vetter | f6f808c | 2012-02-14 18:58:49 +0100 | [diff] [blame] | 332 | bool force_bit; |
Daniel Vetter | c2b9152 | 2012-02-14 22:37:19 +0100 | [diff] [blame] | 333 | u32 reg0; |
Daniel Vetter | 36c785f | 2012-02-14 22:37:22 +0100 | [diff] [blame] | 334 | u32 gpio_reg; |
Daniel Vetter | c167a6f | 2012-02-28 00:43:09 +0100 | [diff] [blame] | 335 | struct i2c_algo_bit_data bit_algo; |
Daniel Vetter | c2b9152 | 2012-02-14 22:37:19 +0100 | [diff] [blame] | 336 | struct drm_i915_private *dev_priv; |
| 337 | }; |
| 338 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 339 | typedef struct drm_i915_private { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 340 | struct drm_device *dev; |
| 341 | |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 342 | const struct intel_device_info *info; |
| 343 | |
Chris Wilson | 72bfa19 | 2010-12-19 11:42:05 +0000 | [diff] [blame] | 344 | int relative_constants_mode; |
Dave Airlie | ac5c4e7 | 2008-12-19 15:38:34 +1000 | [diff] [blame] | 345 | |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 346 | void __iomem *regs; |
Daniel Vetter | 9f1f46a | 2011-12-14 13:57:03 +0100 | [diff] [blame] | 347 | /** gt_fifo_count and the subsequent register write are synchronized |
| 348 | * with dev->struct_mutex. */ |
| 349 | unsigned gt_fifo_count; |
| 350 | /** forcewake_count is protected by gt_lock */ |
| 351 | unsigned forcewake_count; |
| 352 | /** gt_lock is also taken in irq contexts. */ |
| 353 | struct spinlock gt_lock; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 354 | |
Daniel Kurtz | f2c9677 | 2012-03-28 02:36:16 +0800 | [diff] [blame] | 355 | struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 356 | |
Yufeng Shen | 8a8ed1f | 2012-02-13 17:36:54 -0500 | [diff] [blame] | 357 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
| 358 | * controller on different i2c buses. */ |
| 359 | struct mutex gmbus_mutex; |
| 360 | |
Daniel Vetter | 110447fc | 2012-03-23 23:43:36 +0100 | [diff] [blame] | 361 | /** |
| 362 | * Base address of the gmbus and gpio block. |
| 363 | */ |
| 364 | uint32_t gpio_mmio_base; |
| 365 | |
Dave Airlie | ec2a4c3 | 2009-08-04 11:43:41 +1000 | [diff] [blame] | 366 | struct pci_dev *bridge_dev; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 367 | struct intel_ring_buffer ring[I915_NUM_RINGS]; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 368 | uint32_t next_seqno; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 369 | |
Dave Airlie | 9c8da5e | 2005-07-10 15:38:56 +1000 | [diff] [blame] | 370 | drm_dma_handle_t *status_page_dmah; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 371 | uint32_t counter; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 372 | struct drm_i915_gem_object *pwrctx; |
| 373 | struct drm_i915_gem_object *renderctx; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 374 | |
Jesse Barnes | d765898 | 2009-06-05 14:41:29 +0000 | [diff] [blame] | 375 | struct resource mch_res; |
| 376 | |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 377 | unsigned int cpp; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 378 | int back_offset; |
| 379 | int front_offset; |
| 380 | int current_page; |
| 381 | int page_flipping; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 382 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 383 | atomic_t irq_received; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 384 | |
| 385 | /* protects the irq masks */ |
| 386 | spinlock_t irq_lock; |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 387 | |
| 388 | /* DPIO indirect register protection */ |
| 389 | spinlock_t dpio_lock; |
| 390 | |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 391 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 392 | u32 pipestat[2]; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 393 | u32 irq_mask; |
| 394 | u32 gt_irq_mask; |
| 395 | u32 pch_irq_mask; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 396 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 397 | u32 hotplug_supported_mask; |
| 398 | struct work_struct hotplug_work; |
| 399 | |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 400 | unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; |
Dave Airlie | a3524f1 | 2010-06-06 18:59:41 +1000 | [diff] [blame] | 401 | int num_pipe; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 402 | int num_pch_pll; |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 403 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 404 | /* For hangcheck timer */ |
Chris Wilson | 576ae4b | 2010-11-12 13:36:26 +0000 | [diff] [blame] | 405 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 406 | struct timer_list hangcheck_timer; |
| 407 | int hangcheck_count; |
| 408 | uint32_t last_acthd; |
Daniel Vetter | 097354e | 2011-11-27 18:58:17 +0100 | [diff] [blame] | 409 | uint32_t last_acthd_bsd; |
| 410 | uint32_t last_acthd_blt; |
Chris Wilson | cbb465e | 2010-06-06 12:16:24 +0100 | [diff] [blame] | 411 | uint32_t last_instdone; |
| 412 | uint32_t last_instdone1; |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 413 | |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 414 | unsigned long cfb_size; |
Chris Wilson | 016b9b6 | 2011-07-08 12:22:43 +0100 | [diff] [blame] | 415 | unsigned int cfb_fb; |
| 416 | enum plane cfb_plane; |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 417 | int cfb_y; |
Chris Wilson | 1630fe7 | 2011-07-08 12:22:42 +0100 | [diff] [blame] | 418 | struct intel_fbc_work *fbc_work; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 419 | |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 420 | struct intel_opregion opregion; |
| 421 | |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 422 | /* overlay */ |
| 423 | struct intel_overlay *overlay; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 424 | bool sprite_scaling_enabled; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 425 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 426 | /* LVDS info */ |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 427 | int backlight_level; /* restore backlight to this value */ |
Chris Wilson | 47356eb | 2011-01-11 17:06:04 +0000 | [diff] [blame] | 428 | bool backlight_enabled; |
Ma Ling | 8863170 | 2009-05-13 11:19:55 +0800 | [diff] [blame] | 429 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
| 430 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 431 | |
| 432 | /* Feature bits from the VBIOS */ |
Hannes Eder | 95281e3 | 2008-12-18 15:09:00 +0100 | [diff] [blame] | 433 | unsigned int int_tv_support:1; |
| 434 | unsigned int lvds_dither:1; |
| 435 | unsigned int lvds_vbt:1; |
| 436 | unsigned int int_crt_support:1; |
Kristian Høgsberg | 43565a0 | 2009-02-13 20:56:52 -0500 | [diff] [blame] | 437 | unsigned int lvds_use_ssc:1; |
Keith Packard | abd0686 | 2011-09-26 14:24:14 -0700 | [diff] [blame] | 438 | unsigned int display_clock_mode:1; |
Kristian Høgsberg | 43565a0 | 2009-02-13 20:56:52 -0500 | [diff] [blame] | 439 | int lvds_ssc_freq; |
Takashi Iwai | b035438 | 2012-03-20 13:07:05 +0100 | [diff] [blame] | 440 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ |
| 441 | unsigned int lvds_val; /* used for checking LVDS channel mode */ |
Chris Wilson | 5ceb0f9 | 2010-09-24 10:24:28 +0100 | [diff] [blame] | 442 | struct { |
Jesse Barnes | 9f0e7ff | 2010-10-07 16:01:14 -0700 | [diff] [blame] | 443 | int rate; |
| 444 | int lanes; |
| 445 | int preemphasis; |
| 446 | int vswing; |
Chris Wilson | 5ceb0f9 | 2010-09-24 10:24:28 +0100 | [diff] [blame] | 447 | |
Jesse Barnes | 9f0e7ff | 2010-10-07 16:01:14 -0700 | [diff] [blame] | 448 | bool initialized; |
| 449 | bool support; |
| 450 | int bpp; |
| 451 | struct edp_power_seq pps; |
Chris Wilson | 5ceb0f9 | 2010-09-24 10:24:28 +0100 | [diff] [blame] | 452 | } edp; |
Jesse Barnes | 8966738 | 2010-10-07 16:01:21 -0700 | [diff] [blame] | 453 | bool no_aux_handshake; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 454 | |
Jesse Barnes | c1c7af6 | 2009-09-10 15:28:03 -0700 | [diff] [blame] | 455 | struct notifier_block lid_notifier; |
| 456 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 457 | int crt_ddc_pin; |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 458 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 459 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ |
| 460 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ |
| 461 | |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 462 | unsigned int fsb_freq, mem_freq, is_ddr3; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 463 | |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 464 | spinlock_t error_lock; |
| 465 | struct drm_i915_error_state *first_error; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 466 | struct work_struct error_work; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 467 | struct completion error_completion; |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 468 | struct workqueue_struct *wq; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 469 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 470 | /* Display functions */ |
| 471 | struct drm_i915_display_funcs display; |
| 472 | |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 473 | /* PCH chipset type */ |
| 474 | enum intel_pch pch_type; |
| 475 | |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 476 | unsigned long quirks; |
| 477 | |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 478 | /* Register state */ |
Linus Torvalds | c9354c8 | 2009-11-02 09:29:55 -0800 | [diff] [blame] | 479 | bool modeset_on_lid; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 480 | u8 saveLBB; |
| 481 | u32 saveDSPACNTR; |
| 482 | u32 saveDSPBCNTR; |
Keith Packard | e948e99 | 2008-05-07 12:27:53 +1000 | [diff] [blame] | 483 | u32 saveDSPARB; |
Chris Wilson | 968b503 | 2011-03-23 18:16:55 +0000 | [diff] [blame] | 484 | u32 saveHWS; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 485 | u32 savePIPEACONF; |
| 486 | u32 savePIPEBCONF; |
| 487 | u32 savePIPEASRC; |
| 488 | u32 savePIPEBSRC; |
| 489 | u32 saveFPA0; |
| 490 | u32 saveFPA1; |
| 491 | u32 saveDPLL_A; |
| 492 | u32 saveDPLL_A_MD; |
| 493 | u32 saveHTOTAL_A; |
| 494 | u32 saveHBLANK_A; |
| 495 | u32 saveHSYNC_A; |
| 496 | u32 saveVTOTAL_A; |
| 497 | u32 saveVBLANK_A; |
| 498 | u32 saveVSYNC_A; |
| 499 | u32 saveBCLRPAT_A; |
Zhenyu Wang | 5586c8b | 2009-11-06 02:13:02 +0000 | [diff] [blame] | 500 | u32 saveTRANSACONF; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 501 | u32 saveTRANS_HTOTAL_A; |
| 502 | u32 saveTRANS_HBLANK_A; |
| 503 | u32 saveTRANS_HSYNC_A; |
| 504 | u32 saveTRANS_VTOTAL_A; |
| 505 | u32 saveTRANS_VBLANK_A; |
| 506 | u32 saveTRANS_VSYNC_A; |
Jesse Barnes | 0da3ea1 | 2008-02-20 09:39:58 +1000 | [diff] [blame] | 507 | u32 savePIPEASTAT; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 508 | u32 saveDSPASTRIDE; |
| 509 | u32 saveDSPASIZE; |
| 510 | u32 saveDSPAPOS; |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 511 | u32 saveDSPAADDR; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 512 | u32 saveDSPASURF; |
| 513 | u32 saveDSPATILEOFF; |
| 514 | u32 savePFIT_PGM_RATIOS; |
Jesse Barnes | 0eb96d6 | 2009-10-14 12:33:41 -0700 | [diff] [blame] | 515 | u32 saveBLC_HIST_CTL; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 516 | u32 saveBLC_PWM_CTL; |
| 517 | u32 saveBLC_PWM_CTL2; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 518 | u32 saveBLC_CPU_PWM_CTL; |
| 519 | u32 saveBLC_CPU_PWM_CTL2; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 520 | u32 saveFPB0; |
| 521 | u32 saveFPB1; |
| 522 | u32 saveDPLL_B; |
| 523 | u32 saveDPLL_B_MD; |
| 524 | u32 saveHTOTAL_B; |
| 525 | u32 saveHBLANK_B; |
| 526 | u32 saveHSYNC_B; |
| 527 | u32 saveVTOTAL_B; |
| 528 | u32 saveVBLANK_B; |
| 529 | u32 saveVSYNC_B; |
| 530 | u32 saveBCLRPAT_B; |
Zhenyu Wang | 5586c8b | 2009-11-06 02:13:02 +0000 | [diff] [blame] | 531 | u32 saveTRANSBCONF; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 532 | u32 saveTRANS_HTOTAL_B; |
| 533 | u32 saveTRANS_HBLANK_B; |
| 534 | u32 saveTRANS_HSYNC_B; |
| 535 | u32 saveTRANS_VTOTAL_B; |
| 536 | u32 saveTRANS_VBLANK_B; |
| 537 | u32 saveTRANS_VSYNC_B; |
Jesse Barnes | 0da3ea1 | 2008-02-20 09:39:58 +1000 | [diff] [blame] | 538 | u32 savePIPEBSTAT; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 539 | u32 saveDSPBSTRIDE; |
| 540 | u32 saveDSPBSIZE; |
| 541 | u32 saveDSPBPOS; |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 542 | u32 saveDSPBADDR; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 543 | u32 saveDSPBSURF; |
| 544 | u32 saveDSPBTILEOFF; |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 545 | u32 saveVGA0; |
| 546 | u32 saveVGA1; |
| 547 | u32 saveVGA_PD; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 548 | u32 saveVGACNTRL; |
| 549 | u32 saveADPA; |
| 550 | u32 saveLVDS; |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 551 | u32 savePP_ON_DELAYS; |
| 552 | u32 savePP_OFF_DELAYS; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 553 | u32 saveDVOA; |
| 554 | u32 saveDVOB; |
| 555 | u32 saveDVOC; |
| 556 | u32 savePP_ON; |
| 557 | u32 savePP_OFF; |
| 558 | u32 savePP_CONTROL; |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 559 | u32 savePP_DIVISOR; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 560 | u32 savePFIT_CONTROL; |
| 561 | u32 save_palette_a[256]; |
| 562 | u32 save_palette_b[256]; |
Jesse Barnes | 06027f9 | 2009-10-05 13:47:26 -0700 | [diff] [blame] | 563 | u32 saveDPFC_CB_BASE; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 564 | u32 saveFBC_CFB_BASE; |
| 565 | u32 saveFBC_LL_BASE; |
| 566 | u32 saveFBC_CONTROL; |
| 567 | u32 saveFBC_CONTROL2; |
Jesse Barnes | 0da3ea1 | 2008-02-20 09:39:58 +1000 | [diff] [blame] | 568 | u32 saveIER; |
| 569 | u32 saveIIR; |
| 570 | u32 saveIMR; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 571 | u32 saveDEIER; |
| 572 | u32 saveDEIMR; |
| 573 | u32 saveGTIER; |
| 574 | u32 saveGTIMR; |
| 575 | u32 saveFDI_RXA_IMR; |
| 576 | u32 saveFDI_RXB_IMR; |
Keith Packard | 1f84e55 | 2008-02-16 19:19:29 -0800 | [diff] [blame] | 577 | u32 saveCACHE_MODE_0; |
Keith Packard | 1f84e55 | 2008-02-16 19:19:29 -0800 | [diff] [blame] | 578 | u32 saveMI_ARB_STATE; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 579 | u32 saveSWF0[16]; |
| 580 | u32 saveSWF1[16]; |
| 581 | u32 saveSWF2[3]; |
| 582 | u8 saveMSR; |
| 583 | u8 saveSR[8]; |
Jesse Barnes | 123f794 | 2008-02-07 11:15:20 -0800 | [diff] [blame] | 584 | u8 saveGR[25]; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 585 | u8 saveAR_INDEX; |
Jesse Barnes | a59e122 | 2008-05-07 12:25:46 +1000 | [diff] [blame] | 586 | u8 saveAR[21]; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 587 | u8 saveDACMASK; |
Jesse Barnes | a59e122 | 2008-05-07 12:25:46 +1000 | [diff] [blame] | 588 | u8 saveCR[37]; |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 589 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
Eric Anholt | 1fd1c62 | 2009-06-03 07:26:58 +0000 | [diff] [blame] | 590 | u32 saveCURACNTR; |
| 591 | u32 saveCURAPOS; |
| 592 | u32 saveCURABASE; |
| 593 | u32 saveCURBCNTR; |
| 594 | u32 saveCURBPOS; |
| 595 | u32 saveCURBBASE; |
| 596 | u32 saveCURSIZE; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 597 | u32 saveDP_B; |
| 598 | u32 saveDP_C; |
| 599 | u32 saveDP_D; |
| 600 | u32 savePIPEA_GMCH_DATA_M; |
| 601 | u32 savePIPEB_GMCH_DATA_M; |
| 602 | u32 savePIPEA_GMCH_DATA_N; |
| 603 | u32 savePIPEB_GMCH_DATA_N; |
| 604 | u32 savePIPEA_DP_LINK_M; |
| 605 | u32 savePIPEB_DP_LINK_M; |
| 606 | u32 savePIPEA_DP_LINK_N; |
| 607 | u32 savePIPEB_DP_LINK_N; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 608 | u32 saveFDI_RXA_CTL; |
| 609 | u32 saveFDI_TXA_CTL; |
| 610 | u32 saveFDI_RXB_CTL; |
| 611 | u32 saveFDI_TXB_CTL; |
| 612 | u32 savePFA_CTL_1; |
| 613 | u32 savePFB_CTL_1; |
| 614 | u32 savePFA_WIN_SZ; |
| 615 | u32 savePFB_WIN_SZ; |
| 616 | u32 savePFA_WIN_POS; |
| 617 | u32 savePFB_WIN_POS; |
Zhenyu Wang | 5586c8b | 2009-11-06 02:13:02 +0000 | [diff] [blame] | 618 | u32 savePCH_DREF_CONTROL; |
| 619 | u32 saveDISP_ARB_CTL; |
| 620 | u32 savePIPEA_DATA_M1; |
| 621 | u32 savePIPEA_DATA_N1; |
| 622 | u32 savePIPEA_LINK_M1; |
| 623 | u32 savePIPEA_LINK_N1; |
| 624 | u32 savePIPEB_DATA_M1; |
| 625 | u32 savePIPEB_DATA_N1; |
| 626 | u32 savePIPEB_LINK_M1; |
| 627 | u32 savePIPEB_LINK_N1; |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 628 | u32 saveMCHBAR_RENDER_STANDBY; |
Adam Jackson | cda2bb7 | 2011-07-26 16:53:06 -0400 | [diff] [blame] | 629 | u32 savePCH_PORT_HOTPLUG; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 630 | |
| 631 | struct { |
Daniel Vetter | 1996675 | 2010-09-06 20:08:44 +0200 | [diff] [blame] | 632 | /** Bridge to intel-gtt-ko */ |
Chris Wilson | c64f7ba | 2010-11-23 14:24:24 +0000 | [diff] [blame] | 633 | const struct intel_gtt *gtt; |
Daniel Vetter | 1996675 | 2010-09-06 20:08:44 +0200 | [diff] [blame] | 634 | /** Memory allocator for GTT stolen memory */ |
Chris Wilson | fe669bf | 2010-11-23 12:09:30 +0000 | [diff] [blame] | 635 | struct drm_mm stolen; |
Daniel Vetter | 1996675 | 2010-09-06 20:08:44 +0200 | [diff] [blame] | 636 | /** Memory allocator for GTT */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 637 | struct drm_mm gtt_space; |
Daniel Vetter | 93a37f2 | 2010-11-05 20:24:53 +0100 | [diff] [blame] | 638 | /** List of all objects in gtt_space. Used to restore gtt |
| 639 | * mappings on resume */ |
| 640 | struct list_head gtt_list; |
Chris Wilson | bee4a18 | 2011-01-21 10:54:32 +0000 | [diff] [blame] | 641 | |
| 642 | /** Usable portion of the GTT for GEM */ |
| 643 | unsigned long gtt_start; |
Daniel Vetter | a6e0aa4 | 2010-09-16 15:45:15 +0200 | [diff] [blame] | 644 | unsigned long gtt_mappable_end; |
Chris Wilson | bee4a18 | 2011-01-21 10:54:32 +0000 | [diff] [blame] | 645 | unsigned long gtt_end; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 646 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 647 | struct io_mapping *gtt_mapping; |
Eric Anholt | ab657db1 | 2009-01-23 12:57:47 -0800 | [diff] [blame] | 648 | int gtt_mtrr; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 649 | |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 650 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
| 651 | struct i915_hw_ppgtt *aliasing_ppgtt; |
| 652 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 653 | struct shrinker inactive_shrinker; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 654 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 655 | /** |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 656 | * List of objects currently involved in rendering. |
| 657 | * |
| 658 | * Includes buffers having the contents of their GPU caches |
| 659 | * flushed, not necessarily primitives. last_rendering_seqno |
| 660 | * represents when the rendering involved will be completed. |
| 661 | * |
| 662 | * A reference is held on the buffer while on this list. |
| 663 | */ |
| 664 | struct list_head active_list; |
| 665 | |
| 666 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 667 | * List of objects which are not in the ringbuffer but which |
| 668 | * still have a write_domain which needs to be flushed before |
| 669 | * unbinding. |
| 670 | * |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 671 | * last_rendering_seqno is 0 while an object is in this list. |
| 672 | * |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 673 | * A reference is held on the buffer while on this list. |
| 674 | */ |
| 675 | struct list_head flushing_list; |
| 676 | |
| 677 | /** |
| 678 | * LRU list of objects which are not in the ringbuffer and |
| 679 | * are ready to unbind, but are still in the GTT. |
| 680 | * |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 681 | * last_rendering_seqno is 0 while an object is in this list. |
| 682 | * |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 683 | * A reference is not held on the buffer while on this list, |
| 684 | * as merely being GTT-bound shouldn't prevent its being |
| 685 | * freed, and we'll pull it off the list in the free path. |
| 686 | */ |
| 687 | struct list_head inactive_list; |
| 688 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 689 | /** LRU list of objects with fence regs on them. */ |
| 690 | struct list_head fence_list; |
| 691 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 692 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 693 | * We leave the user IRQ off as much as possible, |
| 694 | * but this means that requests will finish and never |
| 695 | * be retired once the system goes idle. Set a timer to |
| 696 | * fire periodically while the ring is running. When it |
| 697 | * fires, go retire requests. |
| 698 | */ |
| 699 | struct delayed_work retire_work; |
| 700 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 701 | /** |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 702 | * Are we in a non-interruptible section of code like |
| 703 | * modesetting? |
| 704 | */ |
| 705 | bool interruptible; |
| 706 | |
| 707 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 708 | * Flag if the X Server, and thus DRM, is not currently in |
| 709 | * control of the device. |
| 710 | * |
| 711 | * This is set between LeaveVT and EnterVT. It needs to be |
| 712 | * replaced with a semaphore. It also needs to be |
| 713 | * transitioned away from for kernel modesetting. |
| 714 | */ |
| 715 | int suspended; |
| 716 | |
| 717 | /** |
| 718 | * Flag if the hardware appears to be wedged. |
| 719 | * |
| 720 | * This is set when attempts to idle the device timeout. |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 721 | * It prevents command submission from occurring and makes |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 722 | * every pending request fail |
| 723 | */ |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 724 | atomic_t wedged; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 725 | |
| 726 | /** Bit 6 swizzling required for X tiling */ |
| 727 | uint32_t bit_6_swizzle_x; |
| 728 | /** Bit 6 swizzling required for Y tiling */ |
| 729 | uint32_t bit_6_swizzle_y; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 730 | |
| 731 | /* storage for physical objects */ |
| 732 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 733 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 734 | /* accounting, useful for userland debugging */ |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 735 | size_t gtt_total; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 736 | size_t mappable_gtt_total; |
| 737 | size_t object_memory; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 738 | u32 object_count; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 739 | } mm; |
Daniel Vetter | 8781342 | 2012-05-02 11:49:32 +0200 | [diff] [blame] | 740 | |
| 741 | /* Old dri1 support infrastructure, beware the dragons ya fools entering |
| 742 | * here! */ |
| 743 | struct { |
| 744 | unsigned allow_batchbuffer : 1; |
Daniel Vetter | 316d388 | 2012-04-26 23:28:15 +0200 | [diff] [blame] | 745 | u32 __iomem *gfx_hws_cpu_addr; |
Daniel Vetter | 8781342 | 2012-05-02 11:49:32 +0200 | [diff] [blame] | 746 | } dri1; |
| 747 | |
| 748 | /* Kernel Modesetting */ |
| 749 | |
yakui_zhao | 9b9d172 | 2009-05-31 17:17:17 +0800 | [diff] [blame] | 750 | struct sdvo_device_mapping sdvo_mappings[2]; |
Zhao Yakui | a3e17eb | 2009-10-10 10:42:37 +0800 | [diff] [blame] | 751 | /* indicate whether the LVDS_BORDER should be enabled or not */ |
| 752 | unsigned int lvds_border_bits; |
Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 753 | /* Panel fitter placement and size for Ironlake+ */ |
| 754 | u32 pch_pf_pos, pch_pf_size; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 755 | |
Jesse Barnes | 27f8227 | 2011-09-02 12:54:37 -0700 | [diff] [blame] | 756 | struct drm_crtc *plane_to_crtc_mapping[3]; |
| 757 | struct drm_crtc *pipe_to_crtc_mapping[3]; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 758 | wait_queue_head_t pending_flip_queue; |
| 759 | |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 760 | struct intel_pch_pll pch_plls[I915_NUM_PLLS]; |
| 761 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 762 | /* Reclocking support */ |
| 763 | bool render_reclock_avail; |
| 764 | bool lvds_downclock_avail; |
Zhao Yakui | 18f9ed1 | 2009-11-20 03:24:16 +0000 | [diff] [blame] | 765 | /* indicates the reduced downclock for LVDS*/ |
| 766 | int lvds_downclock; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 767 | struct work_struct idle_work; |
| 768 | struct timer_list idle_timer; |
| 769 | bool busy; |
| 770 | u16 orig_clock; |
Zhao Yakui | 6363ee6 | 2009-11-24 09:48:44 +0800 | [diff] [blame] | 771 | int child_dev_num; |
| 772 | struct child_device_config *child_dev; |
Zhao Yakui | a256537 | 2009-12-11 09:26:11 +0800 | [diff] [blame] | 773 | struct drm_connector *int_lvds_connector; |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 774 | struct drm_connector *int_edp_connector; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 775 | |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 776 | bool mchbar_need_disable; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 777 | |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 778 | struct work_struct rps_work; |
| 779 | spinlock_t rps_lock; |
| 780 | u32 pm_iir; |
| 781 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 782 | u8 cur_delay; |
| 783 | u8 min_delay; |
| 784 | u8 max_delay; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 785 | u8 fmax; |
| 786 | u8 fstart; |
| 787 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 788 | u64 last_count1; |
| 789 | unsigned long last_time1; |
Eugeni Dodonov | 4ed0b57 | 2011-11-10 13:55:15 -0200 | [diff] [blame] | 790 | unsigned long chipset_power; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 791 | u64 last_count2; |
| 792 | struct timespec last_time2; |
| 793 | unsigned long gfx_power; |
| 794 | int c_m; |
| 795 | int r_t; |
| 796 | u8 corr; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 797 | spinlock_t *mchdev_lock; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 798 | |
| 799 | enum no_fbc_reason no_fbc_reason; |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 800 | |
Jesse Barnes | 20bf377 | 2010-04-21 11:39:22 -0700 | [diff] [blame] | 801 | struct drm_mm_node *compressed_fb; |
| 802 | struct drm_mm_node *compressed_llb; |
Eric Anholt | 34dc4d4 | 2010-05-07 14:30:03 -0700 | [diff] [blame] | 803 | |
Chris Wilson | ae681d9 | 2010-10-01 14:57:56 +0100 | [diff] [blame] | 804 | unsigned long last_gpu_reset; |
| 805 | |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 806 | /* list of fbdev register on this device */ |
| 807 | struct intel_fbdev *fbdev; |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 808 | |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 809 | struct backlight_device *backlight; |
| 810 | |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 811 | struct drm_property *broadcast_rgb_property; |
Chris Wilson | 3f43c48 | 2011-05-12 22:17:24 +0100 | [diff] [blame] | 812 | struct drm_property *force_audio_property; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 813 | } drm_i915_private_t; |
| 814 | |
Wu Fengguang | b1d7e4b | 2012-02-14 11:45:36 +0800 | [diff] [blame] | 815 | enum hdmi_force_audio { |
| 816 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ |
| 817 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ |
| 818 | HDMI_AUDIO_AUTO, /* trust EDID */ |
| 819 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ |
| 820 | }; |
| 821 | |
Chris Wilson | 93dfb40 | 2011-03-29 16:59:50 -0700 | [diff] [blame] | 822 | enum i915_cache_level { |
| 823 | I915_CACHE_NONE, |
| 824 | I915_CACHE_LLC, |
| 825 | I915_CACHE_LLC_MLC, /* gen6+ */ |
| 826 | }; |
| 827 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 828 | struct drm_i915_gem_object { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 829 | struct drm_gem_object base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 830 | |
| 831 | /** Current space allocated to this object in the GTT, if any. */ |
| 832 | struct drm_mm_node *gtt_space; |
Daniel Vetter | 93a37f2 | 2010-11-05 20:24:53 +0100 | [diff] [blame] | 833 | struct list_head gtt_list; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 834 | |
| 835 | /** This object's place on the active/flushing/inactive lists */ |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 836 | struct list_head ring_list; |
| 837 | struct list_head mm_list; |
Daniel Vetter | 99fcb76 | 2010-02-07 16:20:18 +0100 | [diff] [blame] | 838 | /** This object's place on GPU write list */ |
| 839 | struct list_head gpu_write_list; |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 840 | /** This object's place in the batchbuffer or on the eviction list */ |
| 841 | struct list_head exec_list; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 842 | |
| 843 | /** |
| 844 | * This is set if the object is on the active or flushing lists |
| 845 | * (has pending rendering), and is not set if it's on inactive (ready |
| 846 | * to be unbound). |
| 847 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 848 | unsigned int active:1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 849 | |
| 850 | /** |
| 851 | * This is set if the object has been written to since last bound |
| 852 | * to the GTT |
| 853 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 854 | unsigned int dirty:1; |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 855 | |
| 856 | /** |
Chris Wilson | 87ca9c8 | 2010-12-02 09:42:56 +0000 | [diff] [blame] | 857 | * This is set if the object has been written to since the last |
| 858 | * GPU flush. |
| 859 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 860 | unsigned int pending_gpu_write:1; |
Chris Wilson | 87ca9c8 | 2010-12-02 09:42:56 +0000 | [diff] [blame] | 861 | |
| 862 | /** |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 863 | * Fence register bits (if any) for this object. Will be set |
| 864 | * as needed when mapped into the GTT. |
| 865 | * Protected by dev->struct_mutex. |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 866 | */ |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 867 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 868 | |
| 869 | /** |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 870 | * Advice: are the backing pages purgeable? |
| 871 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 872 | unsigned int madv:2; |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 873 | |
| 874 | /** |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 875 | * Current tiling mode for the object. |
| 876 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 877 | unsigned int tiling_mode:2; |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 878 | /** |
| 879 | * Whether the tiling parameters for the currently associated fence |
| 880 | * register have changed. Note that for the purposes of tracking |
| 881 | * tiling changes we also treat the unfenced register, the register |
| 882 | * slot that the object occupies whilst it executes a fenced |
| 883 | * command (such as BLT on gen2/3), as a "fence". |
| 884 | */ |
| 885 | unsigned int fence_dirty:1; |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 886 | |
| 887 | /** How many users have pinned this object in GTT space. The following |
| 888 | * users can each hold at most one reference: pwrite/pread, pin_ioctl |
| 889 | * (via user_pin_count), execbuffer (objects are not allowed multiple |
| 890 | * times for the same batchbuffer), and the framebuffer code. When |
| 891 | * switching/pageflipping, the framebuffer code has at most two buffers |
| 892 | * pinned per crtc. |
| 893 | * |
| 894 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 |
| 895 | * bits with absolutely no headroom. So use 4 bits. */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 896 | unsigned int pin_count:4; |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 897 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 898 | |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 899 | /** |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 900 | * Is the object at the current location in the gtt mappable and |
| 901 | * fenceable? Used to avoid costly recalculations. |
| 902 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 903 | unsigned int map_and_fenceable:1; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 904 | |
| 905 | /** |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 906 | * Whether the current gtt mapping needs to be mappable (and isn't just |
| 907 | * mappable by accident). Track pin and fault separate for a more |
| 908 | * accurate mappable working set. |
| 909 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 910 | unsigned int fault_mappable:1; |
| 911 | unsigned int pin_mappable:1; |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 912 | |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 913 | /* |
| 914 | * Is the GPU currently using a fence to access this buffer, |
| 915 | */ |
| 916 | unsigned int pending_fenced_gpu_access:1; |
| 917 | unsigned int fenced_gpu_access:1; |
| 918 | |
Chris Wilson | 93dfb40 | 2011-03-29 16:59:50 -0700 | [diff] [blame] | 919 | unsigned int cache_level:2; |
| 920 | |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 921 | unsigned int has_aliasing_ppgtt_mapping:1; |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 922 | unsigned int has_global_gtt_mapping:1; |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 923 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 924 | struct page **pages; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 925 | |
| 926 | /** |
Daniel Vetter | 185cbcb | 2010-11-06 12:12:35 +0100 | [diff] [blame] | 927 | * DMAR support |
| 928 | */ |
| 929 | struct scatterlist *sg_list; |
| 930 | int num_sg; |
| 931 | |
| 932 | /** |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 933 | * Used for performing relocations during execbuffer insertion. |
| 934 | */ |
| 935 | struct hlist_node exec_node; |
| 936 | unsigned long exec_handle; |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 937 | struct drm_i915_gem_exec_object2 *exec_entry; |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 938 | |
| 939 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 940 | * Current offset of the object in GTT space. |
| 941 | * |
| 942 | * This is the same as gtt_space->start |
| 943 | */ |
| 944 | uint32_t gtt_offset; |
Chris Wilson | e67b8ce | 2009-09-14 16:50:26 +0100 | [diff] [blame] | 945 | |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 946 | struct intel_ring_buffer *ring; |
| 947 | |
Chris Wilson | 1c293ea | 2012-04-17 15:31:27 +0100 | [diff] [blame] | 948 | /** Breadcrumb of last rendering to the buffer. */ |
| 949 | uint32_t last_rendering_seqno; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 950 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
| 951 | uint32_t last_fenced_seqno; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 952 | |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 953 | /** Current tiling stride for the object, if it's tiled. */ |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 954 | uint32_t stride; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 955 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 956 | /** Record of address bit 17 of each page at last unbind. */ |
Chris Wilson | d312ec2 | 2010-06-06 15:40:22 +0100 | [diff] [blame] | 957 | unsigned long *bit_17; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 958 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 959 | /** User space pin count and filp owning the pin */ |
| 960 | uint32_t user_pin_count; |
| 961 | struct drm_file *pin_filp; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 962 | |
| 963 | /** for phy allocated objects */ |
| 964 | struct drm_i915_gem_phys_object *phys_obj; |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 965 | |
| 966 | /** |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 967 | * Number of crtcs where this object is currently the fb, but |
| 968 | * will be page flipped away on the next vblank. When it |
| 969 | * reaches 0, dev_priv->pending_flip_queue will be woken up. |
| 970 | */ |
| 971 | atomic_t pending_flip; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 972 | }; |
| 973 | |
Daniel Vetter | 62b8b21 | 2010-04-09 19:05:08 +0000 | [diff] [blame] | 974 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 975 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 976 | /** |
| 977 | * Request queue structure. |
| 978 | * |
| 979 | * The request queue allows us to note sequence numbers that have been emitted |
| 980 | * and may be associated with active buffers to be retired. |
| 981 | * |
| 982 | * By keeping this list, we can avoid having to do questionable |
| 983 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate |
| 984 | * an emission time with seqnos for tracking how far ahead of the GPU we are. |
| 985 | */ |
| 986 | struct drm_i915_gem_request { |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 987 | /** On Which ring this request was generated */ |
| 988 | struct intel_ring_buffer *ring; |
| 989 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 990 | /** GEM sequence number associated with this request. */ |
| 991 | uint32_t seqno; |
| 992 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 993 | /** Postion in the ringbuffer of the end of the request */ |
| 994 | u32 tail; |
| 995 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 996 | /** Time at which this request was emitted, in jiffies. */ |
| 997 | unsigned long emitted_jiffies; |
| 998 | |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 999 | /** global list entry for this request */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1000 | struct list_head list; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1001 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1002 | struct drm_i915_file_private *file_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1003 | /** file_priv list entry for this request */ |
| 1004 | struct list_head client_list; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1005 | }; |
| 1006 | |
| 1007 | struct drm_i915_file_private { |
| 1008 | struct { |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1009 | struct spinlock lock; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1010 | struct list_head request_list; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1011 | } mm; |
| 1012 | }; |
| 1013 | |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1014 | #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) |
| 1015 | |
| 1016 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) |
| 1017 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) |
| 1018 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
| 1019 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) |
| 1020 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
| 1021 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) |
| 1022 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) |
| 1023 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
| 1024 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) |
| 1025 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) |
| 1026 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) |
| 1027 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
| 1028 | #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) |
| 1029 | #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) |
| 1030 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
| 1031 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) |
| 1032 | #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) |
| 1033 | #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) |
Jesse Barnes | 4b65177 | 2011-04-28 14:33:09 -0700 | [diff] [blame] | 1034 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
Jesse Barnes | 70a3eb7 | 2012-03-28 13:39:21 -0700 | [diff] [blame] | 1035 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
Eugeni Dodonov | 4cae9ae | 2012-03-29 12:32:18 -0300 | [diff] [blame] | 1036 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1037 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
| 1038 | |
Jesse Barnes | 8543669 | 2011-04-06 12:11:14 -0700 | [diff] [blame] | 1039 | /* |
| 1040 | * The genX designation typically refers to the render engine, so render |
| 1041 | * capability related checks should use IS_GEN, while display and other checks |
| 1042 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular |
| 1043 | * chips, etc.). |
| 1044 | */ |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1045 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
| 1046 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) |
| 1047 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) |
| 1048 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) |
| 1049 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) |
Jesse Barnes | 8543669 | 2011-04-06 12:11:14 -0700 | [diff] [blame] | 1050 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1051 | |
| 1052 | #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) |
| 1053 | #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 1054 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1055 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
| 1056 | |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1057 | #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6) |
| 1058 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1059 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1060 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
| 1061 | |
| 1062 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
| 1063 | * rows, which changed the alignment requirements and fence programming. |
| 1064 | */ |
| 1065 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ |
| 1066 | IS_I915GM(dev))) |
| 1067 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) |
| 1068 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) |
| 1069 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) |
| 1070 | #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) |
| 1071 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) |
| 1072 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) |
| 1073 | /* dsparb controlled by hw only */ |
| 1074 | #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) |
| 1075 | |
| 1076 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) |
| 1077 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) |
| 1078 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1079 | |
Eugeni Dodonov | 7e508a2 | 2012-03-29 12:32:17 -0300 | [diff] [blame] | 1080 | #define HAS_PCH_SPLIT(dev) (INTEL_INFO(dev)->has_pch_split) |
Jesse Barnes | eceae48 | 2011-04-06 12:15:08 -0700 | [diff] [blame] | 1081 | #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1082 | |
| 1083 | #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) |
Eugeni Dodonov | eb877eb | 2012-03-29 12:32:20 -0300 | [diff] [blame] | 1084 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1085 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
| 1086 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) |
| 1087 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1088 | #include "i915_trace.h" |
| 1089 | |
Eugeni Dodonov | 83b7f9a | 2012-03-23 11:57:18 -0300 | [diff] [blame] | 1090 | /** |
| 1091 | * RC6 is a special power stage which allows the GPU to enter an very |
| 1092 | * low-voltage mode when idle, using down to 0V while at this stage. This |
| 1093 | * stage is entered automatically when the GPU is idle when RC6 support is |
| 1094 | * enabled, and as soon as new workload arises GPU wakes up automatically as well. |
| 1095 | * |
| 1096 | * There are different RC6 modes available in Intel GPU, which differentiate |
| 1097 | * among each other with the latency required to enter and leave RC6 and |
| 1098 | * voltage consumed by the GPU in different states. |
| 1099 | * |
| 1100 | * The combination of the following flags define which states GPU is allowed |
| 1101 | * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and |
| 1102 | * RC6pp is deepest RC6. Their support by hardware varies according to the |
| 1103 | * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one |
| 1104 | * which brings the most power savings; deeper states save more power, but |
| 1105 | * require higher latency to switch to and wake up. |
| 1106 | */ |
| 1107 | #define INTEL_RC6_ENABLE (1<<0) |
| 1108 | #define INTEL_RC6p_ENABLE (1<<1) |
| 1109 | #define INTEL_RC6pp_ENABLE (1<<2) |
| 1110 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1111 | extern struct drm_ioctl_desc i915_ioctls[]; |
Dave Airlie | b3a8363 | 2005-09-30 18:37:36 +1000 | [diff] [blame] | 1112 | extern int i915_max_ioctl; |
Ben Widawsky | a35d9d3 | 2011-07-13 14:38:17 -0700 | [diff] [blame] | 1113 | extern unsigned int i915_fbpercrtc __always_unused; |
| 1114 | extern int i915_panel_ignore_lid __read_mostly; |
| 1115 | extern unsigned int i915_powersave __read_mostly; |
Eugeni Dodonov | f45b555 | 2011-12-09 17:16:37 -0800 | [diff] [blame] | 1116 | extern int i915_semaphores __read_mostly; |
Ben Widawsky | a35d9d3 | 2011-07-13 14:38:17 -0700 | [diff] [blame] | 1117 | extern unsigned int i915_lvds_downclock __read_mostly; |
Takashi Iwai | 121d527 | 2012-03-20 13:07:06 +0100 | [diff] [blame] | 1118 | extern int i915_lvds_channel_mode __read_mostly; |
Keith Packard | 4415e63 | 2011-11-09 09:57:50 -0800 | [diff] [blame] | 1119 | extern int i915_panel_use_ssc __read_mostly; |
Ben Widawsky | a35d9d3 | 2011-07-13 14:38:17 -0700 | [diff] [blame] | 1120 | extern int i915_vbt_sdvo_panel_type __read_mostly; |
Keith Packard | c0f372b3 | 2011-11-16 22:24:52 -0800 | [diff] [blame] | 1121 | extern int i915_enable_rc6 __read_mostly; |
Keith Packard | 4415e63 | 2011-11-09 09:57:50 -0800 | [diff] [blame] | 1122 | extern int i915_enable_fbc __read_mostly; |
Ben Widawsky | a35d9d3 | 2011-07-13 14:38:17 -0700 | [diff] [blame] | 1123 | extern bool i915_enable_hangcheck __read_mostly; |
Daniel Vetter | 650dc07 | 2012-04-02 10:08:35 +0200 | [diff] [blame] | 1124 | extern int i915_enable_ppgtt __read_mostly; |
Dave Airlie | b3a8363 | 2005-09-30 18:37:36 +1000 | [diff] [blame] | 1125 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1126 | extern int i915_suspend(struct drm_device *dev, pm_message_t state); |
| 1127 | extern int i915_resume(struct drm_device *dev); |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1128 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
| 1129 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); |
| 1130 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1131 | /* i915_dma.c */ |
Daniel Vetter | d05c617 | 2012-04-26 23:28:09 +0200 | [diff] [blame] | 1132 | void i915_update_dri1_breadcrumb(struct drm_device *dev); |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1133 | extern void i915_kernel_lost_context(struct drm_device * dev); |
Dave Airlie | 22eae94 | 2005-11-10 22:16:34 +1100 | [diff] [blame] | 1134 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 1135 | extern int i915_driver_unload(struct drm_device *); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1136 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1137 | extern void i915_driver_lastclose(struct drm_device * dev); |
Eric Anholt | 6c340ea | 2007-08-25 20:23:09 +1000 | [diff] [blame] | 1138 | extern void i915_driver_preclose(struct drm_device *dev, |
| 1139 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1140 | extern void i915_driver_postclose(struct drm_device *dev, |
| 1141 | struct drm_file *file_priv); |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1142 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 1143 | #ifdef CONFIG_COMPAT |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 1144 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
| 1145 | unsigned long arg); |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 1146 | #endif |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1147 | extern int i915_emit_box(struct drm_device *dev, |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1148 | struct drm_clip_rect *box, |
| 1149 | int DR1, int DR4); |
Chris Wilson | f803aa5 | 2010-09-19 12:38:26 +0100 | [diff] [blame] | 1150 | extern int i915_reset(struct drm_device *dev, u8 flags); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1151 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
| 1152 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); |
| 1153 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); |
| 1154 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); |
| 1155 | |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 1156 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1157 | /* i915_irq.c */ |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1158 | void i915_hangcheck_elapsed(unsigned long data); |
Chris Wilson | 527f9e9 | 2010-11-11 01:16:58 +0000 | [diff] [blame] | 1159 | void i915_handle_error(struct drm_device *dev, bool wedged); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1160 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 1161 | extern void intel_irq_init(struct drm_device *dev); |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 1162 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1163 | void |
| 1164 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); |
| 1165 | |
| 1166 | void |
| 1167 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); |
| 1168 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1169 | void intel_enable_asle(struct drm_device *dev); |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 1170 | |
Chris Wilson | 3bd3c93 | 2010-08-19 08:19:30 +0100 | [diff] [blame] | 1171 | #ifdef CONFIG_DEBUG_FS |
| 1172 | extern void i915_destroy_error_state(struct drm_device *dev); |
| 1173 | #else |
| 1174 | #define i915_destroy_error_state(x) |
| 1175 | #endif |
| 1176 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1177 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1178 | /* i915_gem.c */ |
| 1179 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, |
| 1180 | struct drm_file *file_priv); |
| 1181 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 1182 | struct drm_file *file_priv); |
| 1183 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
| 1184 | struct drm_file *file_priv); |
| 1185 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
| 1186 | struct drm_file *file_priv); |
| 1187 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
| 1188 | struct drm_file *file_priv); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1189 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 1190 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1191 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
| 1192 | struct drm_file *file_priv); |
| 1193 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
| 1194 | struct drm_file *file_priv); |
| 1195 | int i915_gem_execbuffer(struct drm_device *dev, void *data, |
| 1196 | struct drm_file *file_priv); |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 1197 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
| 1198 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1199 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
| 1200 | struct drm_file *file_priv); |
| 1201 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
| 1202 | struct drm_file *file_priv); |
| 1203 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
| 1204 | struct drm_file *file_priv); |
| 1205 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 1206 | struct drm_file *file_priv); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1207 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 1208 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1209 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
| 1210 | struct drm_file *file_priv); |
| 1211 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
| 1212 | struct drm_file *file_priv); |
| 1213 | int i915_gem_set_tiling(struct drm_device *dev, void *data, |
| 1214 | struct drm_file *file_priv); |
| 1215 | int i915_gem_get_tiling(struct drm_device *dev, void *data, |
| 1216 | struct drm_file *file_priv); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 1217 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
| 1218 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1219 | void i915_gem_load(struct drm_device *dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1220 | int i915_gem_init_object(struct drm_gem_object *obj); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1221 | int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring, |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 1222 | uint32_t invalidate_domains, |
| 1223 | uint32_t flush_domains); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1224 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
| 1225 | size_t size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1226 | void i915_gem_free_object(struct drm_gem_object *obj); |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 1227 | int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, |
| 1228 | uint32_t alignment, |
| 1229 | bool map_and_fenceable); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1230 | void i915_gem_object_unpin(struct drm_i915_gem_object *obj); |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 1231 | int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1232 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1233 | void i915_gem_lastclose(struct drm_device *dev); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1234 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1235 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 1236 | int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj); |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 1237 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
| 1238 | struct intel_ring_buffer *to); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1239 | void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1240 | struct intel_ring_buffer *ring, |
| 1241 | u32 seqno); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1242 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1243 | int i915_gem_dumb_create(struct drm_file *file_priv, |
| 1244 | struct drm_device *dev, |
| 1245 | struct drm_mode_create_dumb *args); |
| 1246 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, |
| 1247 | uint32_t handle, uint64_t *offset); |
| 1248 | int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1249 | uint32_t handle); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1250 | /** |
| 1251 | * Returns true if seq1 is later than seq2. |
| 1252 | */ |
| 1253 | static inline bool |
| 1254 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) |
| 1255 | { |
| 1256 | return (int32_t)(seq1 - seq2) >= 0; |
| 1257 | } |
| 1258 | |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 1259 | u32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1260 | |
Chris Wilson | 06d9813 | 2012-04-17 15:31:24 +0100 | [diff] [blame] | 1261 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 1262 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 1263 | |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 1264 | static inline bool |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 1265 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) |
| 1266 | { |
| 1267 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 1268 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 1269 | dev_priv->fence_regs[obj->fence_reg].pin_count++; |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 1270 | return true; |
| 1271 | } else |
| 1272 | return false; |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 1273 | } |
| 1274 | |
| 1275 | static inline void |
| 1276 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) |
| 1277 | { |
| 1278 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 1279 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 1280 | dev_priv->fence_regs[obj->fence_reg].pin_count--; |
| 1281 | } |
| 1282 | } |
| 1283 | |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1284 | void i915_gem_retire_requests(struct drm_device *dev); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1285 | void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); |
| 1286 | |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 1287 | void i915_gem_reset(struct drm_device *dev); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1288 | void i915_gem_clflush_object(struct drm_i915_gem_object *obj); |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 1289 | int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj, |
| 1290 | uint32_t read_domains, |
| 1291 | uint32_t write_domain); |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 1292 | int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 1293 | int __must_check i915_gem_init(struct drm_device *dev); |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 1294 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
| 1295 | void i915_gem_init_swizzling(struct drm_device *dev); |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 1296 | void i915_gem_init_ppgtt(struct drm_device *dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1297 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 1298 | int __must_check i915_gpu_idle(struct drm_device *dev); |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 1299 | int __must_check i915_gem_idle(struct drm_device *dev); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1300 | int __must_check i915_add_request(struct intel_ring_buffer *ring, |
| 1301 | struct drm_file *file, |
| 1302 | struct drm_i915_gem_request *request); |
| 1303 | int __must_check i915_wait_request(struct intel_ring_buffer *ring, |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 1304 | uint32_t seqno); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1305 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 1306 | int __must_check |
| 1307 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, |
| 1308 | bool write); |
| 1309 | int __must_check |
Chris Wilson | dabdfe0 | 2012-03-26 10:10:27 +0200 | [diff] [blame] | 1310 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
| 1311 | int __must_check |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 1312 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
| 1313 | u32 alignment, |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 1314 | struct intel_ring_buffer *pipelined); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 1315 | int i915_gem_attach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1316 | struct drm_i915_gem_object *obj, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 1317 | int id, |
| 1318 | int align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 1319 | void i915_gem_detach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1320 | struct drm_i915_gem_object *obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 1321 | void i915_gem_free_all_phys_object(struct drm_device *dev); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1322 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1323 | |
Chris Wilson | 467cffb | 2011-03-07 10:42:03 +0000 | [diff] [blame] | 1324 | uint32_t |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1325 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
| 1326 | uint32_t size, |
| 1327 | int tiling_mode); |
Chris Wilson | 467cffb | 2011-03-07 10:42:03 +0000 | [diff] [blame] | 1328 | |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 1329 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
| 1330 | enum i915_cache_level cache_level); |
| 1331 | |
Daniel Vetter | 76aaf22 | 2010-11-05 22:23:30 +0100 | [diff] [blame] | 1332 | /* i915_gem_gtt.c */ |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1333 | int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev); |
| 1334 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 1335 | void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, |
| 1336 | struct drm_i915_gem_object *obj, |
| 1337 | enum i915_cache_level cache_level); |
| 1338 | void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, |
| 1339 | struct drm_i915_gem_object *obj); |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1340 | |
Daniel Vetter | 76aaf22 | 2010-11-05 22:23:30 +0100 | [diff] [blame] | 1341 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 1342 | int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); |
| 1343 | void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 1344 | enum i915_cache_level cache_level); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1345 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 1346 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); |
Daniel Vetter | 644ec02 | 2012-03-26 09:45:40 +0200 | [diff] [blame] | 1347 | void i915_gem_init_global_gtt(struct drm_device *dev, |
| 1348 | unsigned long start, |
| 1349 | unsigned long mappable_end, |
| 1350 | unsigned long end); |
Daniel Vetter | 76aaf22 | 2010-11-05 22:23:30 +0100 | [diff] [blame] | 1351 | |
Chris Wilson | b47eb4a | 2010-08-07 11:01:23 +0100 | [diff] [blame] | 1352 | /* i915_gem_evict.c */ |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 1353 | int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size, |
| 1354 | unsigned alignment, bool mappable); |
Chris Wilson | a39d7ef | 2012-04-24 18:22:52 +0100 | [diff] [blame] | 1355 | int i915_gem_evict_everything(struct drm_device *dev, bool purgeable_only); |
Chris Wilson | b47eb4a | 2010-08-07 11:01:23 +0100 | [diff] [blame] | 1356 | |
Chris Wilson | 9797fbf | 2012-04-24 15:47:39 +0100 | [diff] [blame] | 1357 | /* i915_gem_stolen.c */ |
| 1358 | int i915_gem_init_stolen(struct drm_device *dev); |
| 1359 | void i915_gem_cleanup_stolen(struct drm_device *dev); |
| 1360 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1361 | /* i915_gem_tiling.c */ |
| 1362 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1363 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
| 1364 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1365 | |
| 1366 | /* i915_gem_debug.c */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1367 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1368 | const char *where, uint32_t mark); |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1369 | #if WATCH_LISTS |
| 1370 | int i915_verify_lists(struct drm_device *dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1371 | #else |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1372 | #define i915_verify_lists(dev) 0 |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1373 | #endif |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1374 | void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj, |
| 1375 | int handle); |
| 1376 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1377 | const char *where, uint32_t mark); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1378 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 1379 | /* i915_debugfs.c */ |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 1380 | int i915_debugfs_init(struct drm_minor *minor); |
| 1381 | void i915_debugfs_cleanup(struct drm_minor *minor); |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 1382 | |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 1383 | /* i915_suspend.c */ |
| 1384 | extern int i915_save_state(struct drm_device *dev); |
| 1385 | extern int i915_restore_state(struct drm_device *dev); |
| 1386 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1387 | /* i915_suspend.c */ |
| 1388 | extern int i915_save_state(struct drm_device *dev); |
| 1389 | extern int i915_restore_state(struct drm_device *dev); |
| 1390 | |
Ben Widawsky | 0136db58 | 2012-04-10 21:17:01 -0700 | [diff] [blame] | 1391 | /* i915_sysfs.c */ |
| 1392 | void i915_setup_sysfs(struct drm_device *dev_priv); |
| 1393 | void i915_teardown_sysfs(struct drm_device *dev_priv); |
| 1394 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1395 | /* intel_i2c.c */ |
| 1396 | extern int intel_setup_gmbus(struct drm_device *dev); |
| 1397 | extern void intel_teardown_gmbus(struct drm_device *dev); |
Daniel Kurtz | 3bd7d90 | 2012-03-28 02:36:14 +0800 | [diff] [blame] | 1398 | extern inline bool intel_gmbus_is_port_valid(unsigned port) |
| 1399 | { |
Daniel Kurtz | 2ed06c9 | 2012-03-28 02:36:15 +0800 | [diff] [blame] | 1400 | return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); |
Daniel Kurtz | 3bd7d90 | 2012-03-28 02:36:14 +0800 | [diff] [blame] | 1401 | } |
| 1402 | |
| 1403 | extern struct i2c_adapter *intel_gmbus_get_adapter( |
| 1404 | struct drm_i915_private *dev_priv, unsigned port); |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1405 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
| 1406 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); |
Chris Wilson | b8232e9 | 2010-09-28 16:41:32 +0100 | [diff] [blame] | 1407 | extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
| 1408 | { |
| 1409 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; |
| 1410 | } |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1411 | extern void intel_i2c_reset(struct drm_device *dev); |
| 1412 | |
Chris Wilson | 3b61796 | 2010-08-24 09:02:58 +0100 | [diff] [blame] | 1413 | /* intel_opregion.c */ |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1414 | extern int intel_opregion_setup(struct drm_device *dev); |
| 1415 | #ifdef CONFIG_ACPI |
| 1416 | extern void intel_opregion_init(struct drm_device *dev); |
| 1417 | extern void intel_opregion_fini(struct drm_device *dev); |
Chris Wilson | 3b61796 | 2010-08-24 09:02:58 +0100 | [diff] [blame] | 1418 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
| 1419 | extern void intel_opregion_gse_intr(struct drm_device *dev); |
| 1420 | extern void intel_opregion_enable_asle(struct drm_device *dev); |
Len Brown | 65e082c | 2008-10-24 17:18:10 -0400 | [diff] [blame] | 1421 | #else |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1422 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
| 1423 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } |
Chris Wilson | 3b61796 | 2010-08-24 09:02:58 +0100 | [diff] [blame] | 1424 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
| 1425 | static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; } |
| 1426 | static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; } |
Len Brown | 65e082c | 2008-10-24 17:18:10 -0400 | [diff] [blame] | 1427 | #endif |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 1428 | |
Jesse Barnes | 723bfd7 | 2010-10-07 16:01:13 -0700 | [diff] [blame] | 1429 | /* intel_acpi.c */ |
| 1430 | #ifdef CONFIG_ACPI |
| 1431 | extern void intel_register_dsm_handler(void); |
| 1432 | extern void intel_unregister_dsm_handler(void); |
| 1433 | #else |
| 1434 | static inline void intel_register_dsm_handler(void) { return; } |
| 1435 | static inline void intel_unregister_dsm_handler(void) { return; } |
| 1436 | #endif /* CONFIG_ACPI */ |
| 1437 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1438 | /* modesetting */ |
Daniel Vetter | f817586 | 2012-04-10 15:50:11 +0200 | [diff] [blame] | 1439 | extern void intel_modeset_init_hw(struct drm_device *dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1440 | extern void intel_modeset_init(struct drm_device *dev); |
Chris Wilson | 2c7111d | 2011-03-29 10:40:27 +0100 | [diff] [blame] | 1441 | extern void intel_modeset_gem_init(struct drm_device *dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1442 | extern void intel_modeset_cleanup(struct drm_device *dev); |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 1443 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1444 | extern bool intel_fbc_enabled(struct drm_device *dev); |
Chris Wilson | 43a9539 | 2011-07-08 12:22:36 +0100 | [diff] [blame] | 1445 | extern void intel_disable_fbc(struct drm_device *dev); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1446 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
Keith Packard | 9fb526d | 2011-09-26 22:24:57 -0700 | [diff] [blame] | 1447 | extern void ironlake_init_pch_refclk(struct drm_device *dev); |
Jesse Barnes | d5bb081 | 2011-01-05 12:01:26 -0800 | [diff] [blame] | 1448 | extern void ironlake_enable_rc6(struct drm_device *dev); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1449 | extern void gen6_set_rps(struct drm_device *dev, u8 val); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1450 | extern void intel_detect_pch(struct drm_device *dev); |
| 1451 | extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); |
Ben Widawsky | 0136db58 | 2012-04-10 21:17:01 -0700 | [diff] [blame] | 1452 | extern int intel_enable_rc6(const struct drm_device *dev); |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 1453 | |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 1454 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
Keith Packard | 8d715f0 | 2011-11-18 20:39:01 -0800 | [diff] [blame] | 1455 | extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); |
| 1456 | extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv); |
| 1457 | extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); |
| 1458 | extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv); |
| 1459 | |
Jesse Barnes | 575155a | 2012-03-28 13:39:37 -0700 | [diff] [blame] | 1460 | extern void vlv_force_wake_get(struct drm_i915_private *dev_priv); |
| 1461 | extern void vlv_force_wake_put(struct drm_i915_private *dev_priv); |
| 1462 | |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 1463 | /* overlay */ |
Chris Wilson | 3bd3c93 | 2010-08-19 08:19:30 +0100 | [diff] [blame] | 1464 | #ifdef CONFIG_DEBUG_FS |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 1465 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); |
| 1466 | extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 1467 | |
| 1468 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); |
| 1469 | extern void intel_display_print_error_state(struct seq_file *m, |
| 1470 | struct drm_device *dev, |
| 1471 | struct intel_display_error_state *error); |
Chris Wilson | 3bd3c93 | 2010-08-19 08:19:30 +0100 | [diff] [blame] | 1472 | #endif |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 1473 | |
Ben Widawsky | b7287d8 | 2011-04-25 11:22:22 -0700 | [diff] [blame] | 1474 | /* On SNB platform, before reading ring registers forcewake bit |
| 1475 | * must be set to prevent GT core from power down and stale values being |
| 1476 | * returned. |
| 1477 | */ |
Ben Widawsky | fcca792 | 2011-04-25 11:23:07 -0700 | [diff] [blame] | 1478 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); |
| 1479 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); |
Ben Widawsky | 67a3744 | 2012-02-09 10:15:20 +0100 | [diff] [blame] | 1480 | int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); |
Ben Widawsky | b7287d8 | 2011-04-25 11:22:22 -0700 | [diff] [blame] | 1481 | |
Keith Packard | 5f75377 | 2010-11-22 09:24:22 +0000 | [diff] [blame] | 1482 | #define __i915_read(x, y) \ |
Andi Kleen | f700088 | 2011-10-13 16:08:51 -0700 | [diff] [blame] | 1483 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); |
Ben Widawsky | fcca792 | 2011-04-25 11:23:07 -0700 | [diff] [blame] | 1484 | |
Keith Packard | 5f75377 | 2010-11-22 09:24:22 +0000 | [diff] [blame] | 1485 | __i915_read(8, b) |
| 1486 | __i915_read(16, w) |
| 1487 | __i915_read(32, l) |
| 1488 | __i915_read(64, q) |
| 1489 | #undef __i915_read |
| 1490 | |
| 1491 | #define __i915_write(x, y) \ |
Andi Kleen | f700088 | 2011-10-13 16:08:51 -0700 | [diff] [blame] | 1492 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val); |
| 1493 | |
Keith Packard | 5f75377 | 2010-11-22 09:24:22 +0000 | [diff] [blame] | 1494 | __i915_write(8, b) |
| 1495 | __i915_write(16, w) |
| 1496 | __i915_write(32, l) |
| 1497 | __i915_write(64, q) |
| 1498 | #undef __i915_write |
| 1499 | |
| 1500 | #define I915_READ8(reg) i915_read8(dev_priv, (reg)) |
| 1501 | #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) |
| 1502 | |
| 1503 | #define I915_READ16(reg) i915_read16(dev_priv, (reg)) |
| 1504 | #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) |
| 1505 | #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg)) |
| 1506 | #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg)) |
| 1507 | |
| 1508 | #define I915_READ(reg) i915_read32(dev_priv, (reg)) |
| 1509 | #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1510 | #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg)) |
| 1511 | #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg)) |
Keith Packard | 5f75377 | 2010-11-22 09:24:22 +0000 | [diff] [blame] | 1512 | |
| 1513 | #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) |
| 1514 | #define I915_READ64(reg) i915_read64(dev_priv, (reg)) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1515 | |
| 1516 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
| 1517 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) |
| 1518 | |
Yuanhan Liu | ba4f01a | 2010-11-08 17:09:41 +0800 | [diff] [blame] | 1519 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1520 | #endif |