Ben Skeggs | a11c319 | 2010-08-27 10:00:25 +1000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2010 Red Hat Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Ben Skeggs |
| 23 | */ |
| 24 | |
| 25 | #include "drmP.h" |
| 26 | |
| 27 | #include "nouveau_drv.h" |
| 28 | #include "nouveau_vm.h" |
| 29 | |
| 30 | void |
Ben Skeggs | 3ee0128 | 2010-12-15 11:04:39 +1000 | [diff] [blame] | 31 | nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde, |
| 32 | struct nouveau_gpuobj *pgt[2]) |
Ben Skeggs | a11c319 | 2010-08-27 10:00:25 +1000 | [diff] [blame] | 33 | { |
Ben Skeggs | 3ee0128 | 2010-12-15 11:04:39 +1000 | [diff] [blame] | 34 | u64 phys = 0xdeadcafe00000000ULL; |
| 35 | u32 coverage = 0; |
Ben Skeggs | a11c319 | 2010-08-27 10:00:25 +1000 | [diff] [blame] | 36 | |
Ben Skeggs | 3ee0128 | 2010-12-15 11:04:39 +1000 | [diff] [blame] | 37 | if (pgt[0]) { |
| 38 | phys = 0x00000003 | pgt[0]->vinst; /* present, 4KiB pages */ |
| 39 | coverage = (pgt[0]->size >> 3) << 12; |
| 40 | } else |
| 41 | if (pgt[1]) { |
| 42 | phys = 0x00000001 | pgt[1]->vinst; /* present */ |
| 43 | coverage = (pgt[1]->size >> 3) << 16; |
Ben Skeggs | a11c319 | 2010-08-27 10:00:25 +1000 | [diff] [blame] | 44 | } |
| 45 | |
Ben Skeggs | 3ee0128 | 2010-12-15 11:04:39 +1000 | [diff] [blame] | 46 | if (phys & 1) { |
Ben Skeggs | 3ee0128 | 2010-12-15 11:04:39 +1000 | [diff] [blame] | 47 | if (coverage <= 32 * 1024 * 1024) |
| 48 | phys |= 0x60; |
| 49 | else if (coverage <= 64 * 1024 * 1024) |
| 50 | phys |= 0x40; |
Marcin Slusarz | 9e7f96a | 2011-11-06 20:32:06 +0100 | [diff] [blame] | 51 | else if (coverage <= 128 * 1024 * 1024) |
Ben Skeggs | 3ee0128 | 2010-12-15 11:04:39 +1000 | [diff] [blame] | 52 | phys |= 0x20; |
| 53 | } |
Ben Skeggs | a11c319 | 2010-08-27 10:00:25 +1000 | [diff] [blame] | 54 | |
| 55 | nv_wo32(pgd, (pde * 8) + 0, lower_32_bits(phys)); |
| 56 | nv_wo32(pgd, (pde * 8) + 4, upper_32_bits(phys)); |
| 57 | } |
| 58 | |
Ben Skeggs | a11c319 | 2010-08-27 10:00:25 +1000 | [diff] [blame] | 59 | static inline u64 |
Ben Skeggs | 990449c | 2012-01-12 15:34:54 +1000 | [diff] [blame] | 60 | vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target) |
Ben Skeggs | a11c319 | 2010-08-27 10:00:25 +1000 | [diff] [blame] | 61 | { |
Ben Skeggs | a11c319 | 2010-08-27 10:00:25 +1000 | [diff] [blame] | 62 | phys |= 1; /* present */ |
| 63 | phys |= (u64)memtype << 40; |
Ben Skeggs | a11c319 | 2010-08-27 10:00:25 +1000 | [diff] [blame] | 64 | phys |= target << 4; |
Ben Skeggs | a11c319 | 2010-08-27 10:00:25 +1000 | [diff] [blame] | 65 | if (vma->access & NV_MEM_ACCESS_SYS) |
| 66 | phys |= (1 << 6); |
Ben Skeggs | a11c319 | 2010-08-27 10:00:25 +1000 | [diff] [blame] | 67 | if (!(vma->access & NV_MEM_ACCESS_WO)) |
| 68 | phys |= (1 << 3); |
Ben Skeggs | a11c319 | 2010-08-27 10:00:25 +1000 | [diff] [blame] | 69 | return phys; |
| 70 | } |
| 71 | |
| 72 | void |
| 73 | nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, |
Ben Skeggs | 8f7286f | 2011-02-14 09:57:35 +1000 | [diff] [blame] | 74 | struct nouveau_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta) |
Ben Skeggs | a11c319 | 2010-08-27 10:00:25 +1000 | [diff] [blame] | 75 | { |
Ben Skeggs | 990449c | 2012-01-12 15:34:54 +1000 | [diff] [blame] | 76 | struct drm_nouveau_private *dev_priv = vma->vm->dev->dev_private; |
Ben Skeggs | 8f7286f | 2011-02-14 09:57:35 +1000 | [diff] [blame] | 77 | u32 comp = (mem->memtype & 0x180) >> 7; |
Ben Skeggs | 990449c | 2012-01-12 15:34:54 +1000 | [diff] [blame] | 78 | u32 block, target; |
Ben Skeggs | 910d1b3 | 2010-12-21 11:15:44 +1000 | [diff] [blame] | 79 | int i; |
Ben Skeggs | a11c319 | 2010-08-27 10:00:25 +1000 | [diff] [blame] | 80 | |
Ben Skeggs | 990449c | 2012-01-12 15:34:54 +1000 | [diff] [blame] | 81 | /* IGPs don't have real VRAM, re-target to stolen system memory */ |
| 82 | target = 0; |
| 83 | if (dev_priv->vram_sys_base) { |
| 84 | phys += dev_priv->vram_sys_base; |
| 85 | target = 3; |
| 86 | } |
| 87 | |
| 88 | phys = vm_addr(vma, phys, mem->memtype, target); |
Ben Skeggs | a11c319 | 2010-08-27 10:00:25 +1000 | [diff] [blame] | 89 | pte <<= 3; |
| 90 | cnt <<= 3; |
| 91 | |
| 92 | while (cnt) { |
| 93 | u32 offset_h = upper_32_bits(phys); |
| 94 | u32 offset_l = lower_32_bits(phys); |
| 95 | |
| 96 | for (i = 7; i >= 0; i--) { |
| 97 | block = 1 << (i + 3); |
| 98 | if (cnt >= block && !(pte & (block - 1))) |
| 99 | break; |
| 100 | } |
| 101 | offset_l |= (i << 7); |
| 102 | |
| 103 | phys += block << (vma->node->type - 3); |
| 104 | cnt -= block; |
Ben Skeggs | 8f7286f | 2011-02-14 09:57:35 +1000 | [diff] [blame] | 105 | if (comp) { |
| 106 | u32 tag = mem->tag->start + ((delta >> 16) * comp); |
| 107 | offset_h |= (tag << 17); |
| 108 | delta += block << (vma->node->type - 3); |
| 109 | } |
Ben Skeggs | a11c319 | 2010-08-27 10:00:25 +1000 | [diff] [blame] | 110 | |
| 111 | while (block) { |
| 112 | nv_wo32(pgt, pte + 0, offset_l); |
| 113 | nv_wo32(pgt, pte + 4, offset_h); |
| 114 | pte += 8; |
| 115 | block -= 8; |
| 116 | } |
| 117 | } |
| 118 | } |
| 119 | |
| 120 | void |
| 121 | nv50_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, |
Ben Skeggs | 26c0c9e | 2011-02-10 12:59:51 +1000 | [diff] [blame] | 122 | struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) |
Ben Skeggs | a11c319 | 2010-08-27 10:00:25 +1000 | [diff] [blame] | 123 | { |
Ben Skeggs | 990449c | 2012-01-12 15:34:54 +1000 | [diff] [blame] | 124 | u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 3 : 2; |
Ben Skeggs | a11c319 | 2010-08-27 10:00:25 +1000 | [diff] [blame] | 125 | pte <<= 3; |
| 126 | while (cnt--) { |
Ben Skeggs | 990449c | 2012-01-12 15:34:54 +1000 | [diff] [blame] | 127 | u64 phys = vm_addr(vma, (u64)*list++, mem->memtype, target); |
Ben Skeggs | a11c319 | 2010-08-27 10:00:25 +1000 | [diff] [blame] | 128 | nv_wo32(pgt, pte + 0, lower_32_bits(phys)); |
| 129 | nv_wo32(pgt, pte + 4, upper_32_bits(phys)); |
| 130 | pte += 8; |
| 131 | } |
| 132 | } |
| 133 | |
| 134 | void |
| 135 | nv50_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) |
| 136 | { |
| 137 | pte <<= 3; |
| 138 | while (cnt--) { |
| 139 | nv_wo32(pgt, pte + 0, 0x00000000); |
| 140 | nv_wo32(pgt, pte + 4, 0x00000000); |
| 141 | pte += 8; |
| 142 | } |
| 143 | } |
| 144 | |
| 145 | void |
| 146 | nv50_vm_flush(struct nouveau_vm *vm) |
| 147 | { |
| 148 | struct drm_nouveau_private *dev_priv = vm->dev->dev_private; |
| 149 | struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem; |
Ben Skeggs | 4c136142 | 2010-11-15 11:54:21 +1000 | [diff] [blame] | 150 | struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; |
Ben Skeggs | 6dfdd7a | 2011-03-31 15:40:43 +1000 | [diff] [blame] | 151 | int i; |
Ben Skeggs | a11c319 | 2010-08-27 10:00:25 +1000 | [diff] [blame] | 152 | |
| 153 | pinstmem->flush(vm->dev); |
Ben Skeggs | 4c136142 | 2010-11-15 11:54:21 +1000 | [diff] [blame] | 154 | |
| 155 | /* BAR */ |
Ben Skeggs | b79181c | 2011-06-03 09:57:27 +1000 | [diff] [blame] | 156 | if (vm == dev_priv->bar1_vm || vm == dev_priv->bar3_vm) { |
Ben Skeggs | 4c136142 | 2010-11-15 11:54:21 +1000 | [diff] [blame] | 157 | nv50_vm_flush_engine(vm->dev, 6); |
| 158 | return; |
| 159 | } |
| 160 | |
| 161 | pfifo->tlb_flush(vm->dev); |
Ben Skeggs | 6dfdd7a | 2011-03-31 15:40:43 +1000 | [diff] [blame] | 162 | for (i = 0; i < NVOBJ_ENGINE_NR; i++) { |
| 163 | if (atomic_read(&vm->engref[i])) |
| 164 | dev_priv->eng[i]->tlb_flush(vm->dev, i); |
| 165 | } |
Ben Skeggs | a11c319 | 2010-08-27 10:00:25 +1000 | [diff] [blame] | 166 | } |
| 167 | |
| 168 | void |
| 169 | nv50_vm_flush_engine(struct drm_device *dev, int engine) |
| 170 | { |
Ben Skeggs | 6f70a4c | 2011-03-07 17:18:04 +1000 | [diff] [blame] | 171 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
Ben Skeggs | 04eb34a | 2011-04-06 13:28:35 +1000 | [diff] [blame] | 172 | unsigned long flags; |
Ben Skeggs | 6f70a4c | 2011-03-07 17:18:04 +1000 | [diff] [blame] | 173 | |
Ben Skeggs | 04eb34a | 2011-04-06 13:28:35 +1000 | [diff] [blame] | 174 | spin_lock_irqsave(&dev_priv->vm_lock, flags); |
Ben Skeggs | a11c319 | 2010-08-27 10:00:25 +1000 | [diff] [blame] | 175 | nv_wr32(dev, 0x100c80, (engine << 16) | 1); |
| 176 | if (!nv_wait(dev, 0x100c80, 0x00000001, 0x00000000)) |
| 177 | NV_ERROR(dev, "vm flush timeout: engine %d\n", engine); |
Ben Skeggs | 04eb34a | 2011-04-06 13:28:35 +1000 | [diff] [blame] | 178 | spin_unlock_irqrestore(&dev_priv->vm_lock, flags); |
Ben Skeggs | a11c319 | 2010-08-27 10:00:25 +1000 | [diff] [blame] | 179 | } |