Ben Skeggs | fade7ad | 2010-09-27 11:18:14 +1000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2010 Red Hat Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Ben Skeggs |
| 23 | */ |
| 24 | |
| 25 | #include "drmP.h" |
| 26 | #include "nouveau_drv.h" |
| 27 | #include "nouveau_bios.h" |
| 28 | #include "nouveau_pm.h" |
| 29 | |
Ben Skeggs | ca94a71 | 2011-06-17 15:38:48 +1000 | [diff] [blame] | 30 | static u32 read_clk(struct drm_device *, int, bool); |
Ben Skeggs | cec2a27 | 2011-06-17 16:33:13 +1000 | [diff] [blame] | 31 | static u32 read_pll(struct drm_device *, int, u32); |
Ben Skeggs | 3b0582d | 2011-06-17 11:09:40 +1000 | [diff] [blame] | 32 | |
| 33 | static u32 |
Ben Skeggs | ca94a71 | 2011-06-17 15:38:48 +1000 | [diff] [blame] | 34 | read_vco(struct drm_device *dev, int clk) |
| 35 | { |
| 36 | u32 sctl = nv_rd32(dev, 0x4120 + (clk * 4)); |
| 37 | if ((sctl & 0x00000030) != 0x00000030) |
Ben Skeggs | cec2a27 | 2011-06-17 16:33:13 +1000 | [diff] [blame] | 38 | return read_pll(dev, 0x41, 0x00e820); |
| 39 | return read_pll(dev, 0x42, 0x00e8a0); |
Ben Skeggs | ca94a71 | 2011-06-17 15:38:48 +1000 | [diff] [blame] | 40 | } |
| 41 | |
| 42 | static u32 |
| 43 | read_clk(struct drm_device *dev, int clk, bool ignore_en) |
Ben Skeggs | 3b0582d | 2011-06-17 11:09:40 +1000 | [diff] [blame] | 44 | { |
Ben Skeggs | 64e740b | 2011-07-21 15:52:52 +1000 | [diff] [blame] | 45 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
Ben Skeggs | 3b0582d | 2011-06-17 11:09:40 +1000 | [diff] [blame] | 46 | u32 sctl, sdiv, sclk; |
| 47 | |
Ben Skeggs | 64e740b | 2011-07-21 15:52:52 +1000 | [diff] [blame] | 48 | /* refclk for the 0xe8xx plls is a fixed frequency */ |
Ben Skeggs | 378f85e | 2011-07-21 15:54:48 +1000 | [diff] [blame] | 49 | if (clk >= 0x40) { |
| 50 | if (dev_priv->chipset == 0xaf) { |
| 51 | /* no joke.. seriously.. sigh.. */ |
| 52 | return nv_rd32(dev, 0x00471c) * 1000; |
| 53 | } |
| 54 | |
Ben Skeggs | 64e740b | 2011-07-21 15:52:52 +1000 | [diff] [blame] | 55 | return dev_priv->crystal; |
Ben Skeggs | 378f85e | 2011-07-21 15:54:48 +1000 | [diff] [blame] | 56 | } |
Ben Skeggs | 3b0582d | 2011-06-17 11:09:40 +1000 | [diff] [blame] | 57 | |
| 58 | sctl = nv_rd32(dev, 0x4120 + (clk * 4)); |
Ben Skeggs | ca94a71 | 2011-06-17 15:38:48 +1000 | [diff] [blame] | 59 | if (!ignore_en && !(sctl & 0x00000100)) |
| 60 | return 0; |
| 61 | |
| 62 | switch (sctl & 0x00003000) { |
| 63 | case 0x00000000: |
Ben Skeggs | 64e740b | 2011-07-21 15:52:52 +1000 | [diff] [blame] | 64 | return dev_priv->crystal; |
Ben Skeggs | ca94a71 | 2011-06-17 15:38:48 +1000 | [diff] [blame] | 65 | case 0x00002000: |
Ben Skeggs | 3b0582d | 2011-06-17 11:09:40 +1000 | [diff] [blame] | 66 | if (sctl & 0x00000040) |
| 67 | return 108000; |
| 68 | return 100000; |
Ben Skeggs | ca94a71 | 2011-06-17 15:38:48 +1000 | [diff] [blame] | 69 | case 0x00003000: |
| 70 | sclk = read_vco(dev, clk); |
Ben Skeggs | 3b0582d | 2011-06-17 11:09:40 +1000 | [diff] [blame] | 71 | sdiv = ((sctl & 0x003f0000) >> 16) + 2; |
Ben Skeggs | 3b0582d | 2011-06-17 11:09:40 +1000 | [diff] [blame] | 72 | return (sclk * 2) / sdiv; |
| 73 | default: |
| 74 | return 0; |
| 75 | } |
| 76 | } |
| 77 | |
| 78 | static u32 |
Ben Skeggs | cec2a27 | 2011-06-17 16:33:13 +1000 | [diff] [blame] | 79 | read_pll(struct drm_device *dev, int clk, u32 pll) |
Ben Skeggs | 3b0582d | 2011-06-17 11:09:40 +1000 | [diff] [blame] | 80 | { |
| 81 | u32 ctrl = nv_rd32(dev, pll + 0); |
Ben Skeggs | 93e692d | 2011-07-20 09:59:05 +1000 | [diff] [blame] | 82 | u32 sclk = 0, P = 1, N = 1, M = 1; |
Ben Skeggs | 3b0582d | 2011-06-17 11:09:40 +1000 | [diff] [blame] | 83 | |
| 84 | if (!(ctrl & 0x00000008)) { |
Ben Skeggs | 93e692d | 2011-07-20 09:59:05 +1000 | [diff] [blame] | 85 | if (ctrl & 0x00000001) { |
| 86 | u32 coef = nv_rd32(dev, pll + 4); |
| 87 | M = (coef & 0x000000ff) >> 0; |
| 88 | N = (coef & 0x0000ff00) >> 8; |
| 89 | P = (coef & 0x003f0000) >> 16; |
Ben Skeggs | cec2a27 | 2011-06-17 16:33:13 +1000 | [diff] [blame] | 90 | |
Ben Skeggs | 93e692d | 2011-07-20 09:59:05 +1000 | [diff] [blame] | 91 | /* no post-divider on these.. */ |
| 92 | if ((pll & 0x00ff00) == 0x00e800) |
| 93 | P = 1; |
Ben Skeggs | 3b0582d | 2011-06-17 11:09:40 +1000 | [diff] [blame] | 94 | |
Ben Skeggs | 93e692d | 2011-07-20 09:59:05 +1000 | [diff] [blame] | 95 | sclk = read_clk(dev, 0x00 + clk, false); |
| 96 | } |
Ben Skeggs | 3b0582d | 2011-06-17 11:09:40 +1000 | [diff] [blame] | 97 | } else { |
Ben Skeggs | ca94a71 | 2011-06-17 15:38:48 +1000 | [diff] [blame] | 98 | sclk = read_clk(dev, 0x10 + clk, false); |
Ben Skeggs | 3b0582d | 2011-06-17 11:09:40 +1000 | [diff] [blame] | 99 | } |
| 100 | |
| 101 | return sclk * N / (M * P); |
| 102 | } |
Ben Skeggs | fade7ad | 2010-09-27 11:18:14 +1000 | [diff] [blame] | 103 | |
Ben Skeggs | ca94a71 | 2011-06-17 15:38:48 +1000 | [diff] [blame] | 104 | struct creg { |
| 105 | u32 clk; |
| 106 | u32 pll; |
Ben Skeggs | fade7ad | 2010-09-27 11:18:14 +1000 | [diff] [blame] | 107 | }; |
| 108 | |
Ben Skeggs | 215f902 | 2011-04-14 15:02:03 +1000 | [diff] [blame] | 109 | static int |
Ben Skeggs | cec2a27 | 2011-06-17 16:33:13 +1000 | [diff] [blame] | 110 | calc_clk(struct drm_device *dev, int clk, u32 pll, u32 khz, struct creg *reg) |
Ben Skeggs | 215f902 | 2011-04-14 15:02:03 +1000 | [diff] [blame] | 111 | { |
Ben Skeggs | ca94a71 | 2011-06-17 15:38:48 +1000 | [diff] [blame] | 112 | struct pll_lims limits; |
| 113 | u32 oclk, sclk, sdiv; |
| 114 | int P, N, M, diff; |
| 115 | int ret; |
Ben Skeggs | 215f902 | 2011-04-14 15:02:03 +1000 | [diff] [blame] | 116 | |
Ben Skeggs | ca94a71 | 2011-06-17 15:38:48 +1000 | [diff] [blame] | 117 | reg->pll = 0; |
| 118 | reg->clk = 0; |
Ben Skeggs | cec2a27 | 2011-06-17 16:33:13 +1000 | [diff] [blame] | 119 | if (!khz) { |
| 120 | NV_DEBUG(dev, "no clock for 0x%04x/0x%02x\n", pll, clk); |
| 121 | return 0; |
| 122 | } |
Ben Skeggs | ca94a71 | 2011-06-17 15:38:48 +1000 | [diff] [blame] | 123 | |
| 124 | switch (khz) { |
| 125 | case 27000: |
| 126 | reg->clk = 0x00000100; |
| 127 | return khz; |
| 128 | case 100000: |
| 129 | reg->clk = 0x00002100; |
| 130 | return khz; |
| 131 | case 108000: |
| 132 | reg->clk = 0x00002140; |
| 133 | return khz; |
| 134 | default: |
| 135 | sclk = read_vco(dev, clk); |
| 136 | sdiv = min((sclk * 2) / (khz - 2999), (u32)65); |
Ben Skeggs | cec2a27 | 2011-06-17 16:33:13 +1000 | [diff] [blame] | 137 | /* if the clock has a PLL attached, and we can get a within |
| 138 | * [-2, 3) MHz of a divider, we'll disable the PLL and use |
| 139 | * the divider instead. |
| 140 | * |
| 141 | * divider can go as low as 2, limited here because NVIDIA |
| 142 | * and the VBIOS on my NVA8 seem to prefer using the PLL |
| 143 | * for 810MHz - is there a good reason? |
| 144 | */ |
Ben Skeggs | ca94a71 | 2011-06-17 15:38:48 +1000 | [diff] [blame] | 145 | if (sdiv > 4) { |
| 146 | oclk = (sclk * 2) / sdiv; |
| 147 | diff = khz - oclk; |
| 148 | if (!pll || (diff >= -2000 && diff < 3000)) { |
| 149 | reg->clk = (((sdiv - 2) << 16) | 0x00003100); |
| 150 | return oclk; |
| 151 | } |
| 152 | } |
Ben Skeggs | cec2a27 | 2011-06-17 16:33:13 +1000 | [diff] [blame] | 153 | |
| 154 | if (!pll) { |
| 155 | NV_ERROR(dev, "bad freq %02x: %d %d\n", clk, khz, sclk); |
| 156 | return -ERANGE; |
| 157 | } |
| 158 | |
Ben Skeggs | ca94a71 | 2011-06-17 15:38:48 +1000 | [diff] [blame] | 159 | break; |
Ben Skeggs | 215f902 | 2011-04-14 15:02:03 +1000 | [diff] [blame] | 160 | } |
| 161 | |
Ben Skeggs | ca94a71 | 2011-06-17 15:38:48 +1000 | [diff] [blame] | 162 | ret = get_pll_limits(dev, pll, &limits); |
| 163 | if (ret) |
| 164 | return ret; |
| 165 | |
| 166 | limits.refclk = read_clk(dev, clk - 0x10, true); |
| 167 | if (!limits.refclk) |
| 168 | return -EINVAL; |
| 169 | |
| 170 | ret = nva3_calc_pll(dev, &limits, khz, &N, NULL, &M, &P); |
| 171 | if (ret >= 0) { |
| 172 | reg->clk = nv_rd32(dev, 0x4120 + (clk * 4)); |
| 173 | reg->pll = (P << 16) | (N << 8) | M; |
| 174 | } |
| 175 | return ret; |
Ben Skeggs | 215f902 | 2011-04-14 15:02:03 +1000 | [diff] [blame] | 176 | } |
| 177 | |
Ben Skeggs | cec2a27 | 2011-06-17 16:33:13 +1000 | [diff] [blame] | 178 | static void |
| 179 | prog_pll(struct drm_device *dev, int clk, u32 pll, struct creg *reg) |
| 180 | { |
| 181 | const u32 src0 = 0x004120 + (clk * 4); |
| 182 | const u32 src1 = 0x004160 + (clk * 4); |
| 183 | const u32 ctrl = pll + 0; |
| 184 | const u32 coef = pll + 4; |
| 185 | u32 cntl; |
| 186 | |
| 187 | if (!reg->clk && !reg->pll) { |
| 188 | NV_DEBUG(dev, "no clock for %02x\n", clk); |
| 189 | return; |
| 190 | } |
| 191 | |
| 192 | cntl = nv_rd32(dev, ctrl) & 0xfffffff2; |
| 193 | if (reg->pll) { |
| 194 | nv_mask(dev, src0, 0x00000101, 0x00000101); |
| 195 | nv_wr32(dev, coef, reg->pll); |
| 196 | nv_wr32(dev, ctrl, cntl | 0x00000015); |
| 197 | nv_mask(dev, src1, 0x00000100, 0x00000000); |
| 198 | nv_mask(dev, src1, 0x00000001, 0x00000000); |
| 199 | } else { |
| 200 | nv_mask(dev, src1, 0x003f3141, 0x00000101 | reg->clk); |
| 201 | nv_wr32(dev, ctrl, cntl | 0x0000001d); |
| 202 | nv_mask(dev, ctrl, 0x00000001, 0x00000000); |
| 203 | nv_mask(dev, src0, 0x00000100, 0x00000000); |
| 204 | nv_mask(dev, src0, 0x00000001, 0x00000000); |
| 205 | } |
| 206 | } |
| 207 | |
| 208 | static void |
| 209 | prog_clk(struct drm_device *dev, int clk, struct creg *reg) |
| 210 | { |
| 211 | if (!reg->clk) { |
| 212 | NV_DEBUG(dev, "no clock for %02x\n", clk); |
| 213 | return; |
| 214 | } |
| 215 | |
| 216 | nv_mask(dev, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 | reg->clk); |
| 217 | } |
| 218 | |
Ben Skeggs | fade7ad | 2010-09-27 11:18:14 +1000 | [diff] [blame] | 219 | int |
Ben Skeggs | ca94a71 | 2011-06-17 15:38:48 +1000 | [diff] [blame] | 220 | nva3_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl) |
Ben Skeggs | fade7ad | 2010-09-27 11:18:14 +1000 | [diff] [blame] | 221 | { |
Ben Skeggs | cec2a27 | 2011-06-17 16:33:13 +1000 | [diff] [blame] | 222 | perflvl->core = read_pll(dev, 0x00, 0x4200); |
| 223 | perflvl->shader = read_pll(dev, 0x01, 0x4220); |
| 224 | perflvl->memory = read_pll(dev, 0x02, 0x4000); |
Ben Skeggs | 4fd2847 | 2011-06-17 16:11:31 +1000 | [diff] [blame] | 225 | perflvl->unka0 = read_clk(dev, 0x20, false); |
| 226 | perflvl->vdec = read_clk(dev, 0x21, false); |
Ben Skeggs | 9698b9a | 2011-06-21 15:12:26 +1000 | [diff] [blame] | 227 | perflvl->daemon = read_clk(dev, 0x25, false); |
| 228 | perflvl->copy = perflvl->core; |
Ben Skeggs | ca94a71 | 2011-06-17 15:38:48 +1000 | [diff] [blame] | 229 | return 0; |
Ben Skeggs | fade7ad | 2010-09-27 11:18:14 +1000 | [diff] [blame] | 230 | } |
| 231 | |
Ben Skeggs | ca94a71 | 2011-06-17 15:38:48 +1000 | [diff] [blame] | 232 | struct nva3_pm_state { |
| 233 | struct creg nclk; |
| 234 | struct creg sclk; |
| 235 | struct creg mclk; |
Ben Skeggs | 4fd2847 | 2011-06-17 16:11:31 +1000 | [diff] [blame] | 236 | struct creg vdec; |
| 237 | struct creg unka0; |
Ben Skeggs | ca94a71 | 2011-06-17 15:38:48 +1000 | [diff] [blame] | 238 | }; |
| 239 | |
Ben Skeggs | fade7ad | 2010-09-27 11:18:14 +1000 | [diff] [blame] | 240 | void * |
Ben Skeggs | ca94a71 | 2011-06-17 15:38:48 +1000 | [diff] [blame] | 241 | nva3_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl) |
Ben Skeggs | fade7ad | 2010-09-27 11:18:14 +1000 | [diff] [blame] | 242 | { |
Ben Skeggs | ca94a71 | 2011-06-17 15:38:48 +1000 | [diff] [blame] | 243 | struct nva3_pm_state *info; |
| 244 | int ret; |
Ben Skeggs | fade7ad | 2010-09-27 11:18:14 +1000 | [diff] [blame] | 245 | |
Ben Skeggs | ca94a71 | 2011-06-17 15:38:48 +1000 | [diff] [blame] | 246 | info = kzalloc(sizeof(*info), GFP_KERNEL); |
| 247 | if (!info) |
Ben Skeggs | dac55b5 | 2011-04-15 11:16:55 +1000 | [diff] [blame] | 248 | return ERR_PTR(-ENOMEM); |
Ben Skeggs | dac55b5 | 2011-04-15 11:16:55 +1000 | [diff] [blame] | 249 | |
Ben Skeggs | cec2a27 | 2011-06-17 16:33:13 +1000 | [diff] [blame] | 250 | ret = calc_clk(dev, 0x10, 0x4200, perflvl->core, &info->nclk); |
Ben Skeggs | ca94a71 | 2011-06-17 15:38:48 +1000 | [diff] [blame] | 251 | if (ret < 0) |
| 252 | goto out; |
| 253 | |
Ben Skeggs | cec2a27 | 2011-06-17 16:33:13 +1000 | [diff] [blame] | 254 | ret = calc_clk(dev, 0x11, 0x4220, perflvl->shader, &info->sclk); |
Ben Skeggs | ca94a71 | 2011-06-17 15:38:48 +1000 | [diff] [blame] | 255 | if (ret < 0) |
| 256 | goto out; |
| 257 | |
Ben Skeggs | cec2a27 | 2011-06-17 16:33:13 +1000 | [diff] [blame] | 258 | ret = calc_clk(dev, 0x12, 0x4000, perflvl->memory, &info->mclk); |
Ben Skeggs | ca94a71 | 2011-06-17 15:38:48 +1000 | [diff] [blame] | 259 | if (ret < 0) |
| 260 | goto out; |
| 261 | |
Ben Skeggs | cec2a27 | 2011-06-17 16:33:13 +1000 | [diff] [blame] | 262 | ret = calc_clk(dev, 0x20, 0x0000, perflvl->unka0, &info->unka0); |
Ben Skeggs | 4fd2847 | 2011-06-17 16:11:31 +1000 | [diff] [blame] | 263 | if (ret < 0) |
| 264 | goto out; |
| 265 | |
Ben Skeggs | cec2a27 | 2011-06-17 16:33:13 +1000 | [diff] [blame] | 266 | ret = calc_clk(dev, 0x21, 0x0000, perflvl->vdec, &info->vdec); |
Ben Skeggs | 4fd2847 | 2011-06-17 16:11:31 +1000 | [diff] [blame] | 267 | if (ret < 0) |
| 268 | goto out; |
| 269 | |
Ben Skeggs | ca94a71 | 2011-06-17 15:38:48 +1000 | [diff] [blame] | 270 | out: |
| 271 | if (ret < 0) { |
| 272 | kfree(info); |
| 273 | info = ERR_PTR(ret); |
Ben Skeggs | fade7ad | 2010-09-27 11:18:14 +1000 | [diff] [blame] | 274 | } |
Ben Skeggs | ca94a71 | 2011-06-17 15:38:48 +1000 | [diff] [blame] | 275 | return info; |
| 276 | } |
Ben Skeggs | fade7ad | 2010-09-27 11:18:14 +1000 | [diff] [blame] | 277 | |
Ben Skeggs | d0f67a4 | 2011-06-18 16:28:00 +1000 | [diff] [blame] | 278 | static bool |
| 279 | nva3_pm_grcp_idle(void *data) |
| 280 | { |
| 281 | struct drm_device *dev = data; |
| 282 | |
| 283 | if (!(nv_rd32(dev, 0x400304) & 0x00000001)) |
| 284 | return true; |
| 285 | if (nv_rd32(dev, 0x400308) == 0x0050001c) |
| 286 | return true; |
| 287 | return false; |
| 288 | } |
| 289 | |
Martin Peres | dd1da8d | 2011-07-10 00:08:41 +0200 | [diff] [blame] | 290 | int |
Ben Skeggs | ca94a71 | 2011-06-17 15:38:48 +1000 | [diff] [blame] | 291 | nva3_pm_clocks_set(struct drm_device *dev, void *pre_state) |
Ben Skeggs | fade7ad | 2010-09-27 11:18:14 +1000 | [diff] [blame] | 292 | { |
Ben Skeggs | d0f67a4 | 2011-06-18 16:28:00 +1000 | [diff] [blame] | 293 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
Ben Skeggs | ca94a71 | 2011-06-17 15:38:48 +1000 | [diff] [blame] | 294 | struct nva3_pm_state *info = pre_state; |
Ben Skeggs | d0f67a4 | 2011-06-18 16:28:00 +1000 | [diff] [blame] | 295 | unsigned long flags; |
Martin Peres | dd1da8d | 2011-07-10 00:08:41 +0200 | [diff] [blame] | 296 | int ret = -EAGAIN; |
Ben Skeggs | d0f67a4 | 2011-06-18 16:28:00 +1000 | [diff] [blame] | 297 | |
| 298 | /* prevent any new grctx switches from starting */ |
| 299 | spin_lock_irqsave(&dev_priv->context_switch_lock, flags); |
| 300 | nv_wr32(dev, 0x400324, 0x00000000); |
| 301 | nv_wr32(dev, 0x400328, 0x0050001c); /* wait flag 0x1c */ |
| 302 | /* wait for any pending grctx switches to complete */ |
| 303 | if (!nv_wait_cb(dev, nva3_pm_grcp_idle, dev)) { |
| 304 | NV_ERROR(dev, "pm: ctxprog didn't go idle\n"); |
| 305 | goto cleanup; |
| 306 | } |
| 307 | /* freeze PFIFO */ |
| 308 | nv_mask(dev, 0x002504, 0x00000001, 0x00000001); |
| 309 | if (!nv_wait(dev, 0x002504, 0x00000010, 0x00000010)) { |
| 310 | NV_ERROR(dev, "pm: fifo didn't go idle\n"); |
| 311 | goto cleanup; |
| 312 | } |
Ben Skeggs | fade7ad | 2010-09-27 11:18:14 +1000 | [diff] [blame] | 313 | |
Ben Skeggs | cec2a27 | 2011-06-17 16:33:13 +1000 | [diff] [blame] | 314 | prog_pll(dev, 0x00, 0x004200, &info->nclk); |
| 315 | prog_pll(dev, 0x01, 0x004220, &info->sclk); |
Ben Skeggs | 4fd2847 | 2011-06-17 16:11:31 +1000 | [diff] [blame] | 316 | prog_clk(dev, 0x20, &info->unka0); |
| 317 | prog_clk(dev, 0x21, &info->vdec); |
Ben Skeggs | dac55b5 | 2011-04-15 11:16:55 +1000 | [diff] [blame] | 318 | |
Ben Skeggs | 93e692d | 2011-07-20 09:59:05 +1000 | [diff] [blame] | 319 | if (info->mclk.clk || info->mclk.pll) { |
| 320 | nv_wr32(dev, 0x100210, 0); |
| 321 | nv_wr32(dev, 0x1002dc, 1); |
| 322 | nv_wr32(dev, 0x004018, 0x00001000); |
| 323 | prog_pll(dev, 0x02, 0x004000, &info->mclk); |
| 324 | if (nv_rd32(dev, 0x4000) & 0x00000008) |
| 325 | nv_wr32(dev, 0x004018, 0x1000d000); |
| 326 | else |
| 327 | nv_wr32(dev, 0x004018, 0x10005000); |
| 328 | nv_wr32(dev, 0x1002dc, 0); |
| 329 | nv_wr32(dev, 0x100210, 0x80000000); |
| 330 | } |
Ben Skeggs | dac55b5 | 2011-04-15 11:16:55 +1000 | [diff] [blame] | 331 | |
Martin Peres | dd1da8d | 2011-07-10 00:08:41 +0200 | [diff] [blame] | 332 | ret = 0; |
| 333 | |
Ben Skeggs | d0f67a4 | 2011-06-18 16:28:00 +1000 | [diff] [blame] | 334 | cleanup: |
| 335 | /* unfreeze PFIFO */ |
| 336 | nv_mask(dev, 0x002504, 0x00000001, 0x00000000); |
| 337 | /* restore ctxprog to normal */ |
| 338 | nv_wr32(dev, 0x400324, 0x00000000); |
| 339 | nv_wr32(dev, 0x400328, 0x0070009c); /* set flag 0x1c */ |
| 340 | /* unblock it if necessary */ |
| 341 | if (nv_rd32(dev, 0x400308) == 0x0050001c) |
| 342 | nv_mask(dev, 0x400824, 0x10000000, 0x10000000); |
| 343 | spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); |
Ben Skeggs | ca94a71 | 2011-06-17 15:38:48 +1000 | [diff] [blame] | 344 | kfree(info); |
Martin Peres | dd1da8d | 2011-07-10 00:08:41 +0200 | [diff] [blame] | 345 | return ret; |
Ben Skeggs | fade7ad | 2010-09-27 11:18:14 +1000 | [diff] [blame] | 346 | } |