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H. Peter Anvin1965aae2008-10-22 22:26:29 -07001#ifndef _ASM_X86_MSR_INDEX_H
2#define _ASM_X86_MSR_INDEX_H
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +02003
4/* CPU model specific register (MSR) numbers */
5
6/* x86-64 specific MSRs */
7#define MSR_EFER 0xc0000080 /* extended feature register */
8#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
9#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
10#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
11#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
12#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
13#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
14#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
Sheng Yang5df97402009-12-16 13:48:04 +080015#define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +020016
17/* EFER bits: */
18#define _EFER_SCE 0 /* SYSCALL/SYSRET */
19#define _EFER_LME 8 /* Long mode enable */
20#define _EFER_LMA 10 /* Long mode active (read-only) */
21#define _EFER_NX 11 /* No execute enable */
Alexander Graf9962d032008-11-25 20:17:02 +010022#define _EFER_SVME 12 /* Enable virtualization */
Joerg Roedeleec4b142010-05-05 16:04:44 +020023#define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */
Alexander Grafd2062692009-02-02 16:23:50 +010024#define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +020025
26#define EFER_SCE (1<<_EFER_SCE)
27#define EFER_LME (1<<_EFER_LME)
28#define EFER_LMA (1<<_EFER_LMA)
29#define EFER_NX (1<<_EFER_NX)
Alexander Graf9962d032008-11-25 20:17:02 +010030#define EFER_SVME (1<<_EFER_SVME)
Joerg Roedeleec4b142010-05-05 16:04:44 +020031#define EFER_LMSLE (1<<_EFER_LMSLE)
Alexander Grafd2062692009-02-02 16:23:50 +010032#define EFER_FFXSR (1<<_EFER_FFXSR)
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +020033
34/* Intel MSRs. Some also available on other CPUs */
35#define MSR_IA32_PERFCTR0 0x000000c1
36#define MSR_IA32_PERFCTR1 0x000000c2
37#define MSR_FSB_FREQ 0x000000cd
Linus Torvalds6842d982012-12-18 12:34:29 -080038#define MSR_NHM_PLATFORM_INFO 0x000000ce
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +020039
Len Brown14796fc2011-01-18 20:48:27 -050040#define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2
41#define NHM_C3_AUTO_DEMOTE (1UL << 25)
42#define NHM_C1_AUTO_DEMOTE (1UL << 26)
Len Brownbfb53cc2011-02-16 01:32:48 -050043#define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25)
Linus Torvalds6842d982012-12-18 12:34:29 -080044#define SNB_C1_AUTO_UNDEMOTE (1UL << 27)
45#define SNB_C3_AUTO_UNDEMOTE (1UL << 28)
Len Brown14796fc2011-01-18 20:48:27 -050046
Konrad Rzeszutek Wilk05e99c8cf2013-03-20 14:21:10 +000047#define MSR_PLATFORM_INFO 0x000000ce
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +020048#define MSR_MTRRcap 0x000000fe
49#define MSR_IA32_BBL_CR_CTL 0x00000119
john cooper91c9c3e2011-01-21 00:21:00 -050050#define MSR_IA32_BBL_CR_CTL3 0x0000011e
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +020051
52#define MSR_IA32_SYSENTER_CS 0x00000174
53#define MSR_IA32_SYSENTER_ESP 0x00000175
54#define MSR_IA32_SYSENTER_EIP 0x00000176
55
56#define MSR_IA32_MCG_CAP 0x00000179
57#define MSR_IA32_MCG_STATUS 0x0000017a
58#define MSR_IA32_MCG_CTL 0x0000017b
59
Andi Kleena7e3ed12011-03-03 10:34:47 +080060#define MSR_OFFCORE_RSP_0 0x000001a6
61#define MSR_OFFCORE_RSP_1 0x000001a7
Linus Torvalds6842d982012-12-18 12:34:29 -080062#define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad
63#define MSR_IVT_TURBO_RATIO_LIMIT 0x000001ae
Andi Kleena7e3ed12011-03-03 10:34:47 +080064
Stephane Eranian225ce532012-02-09 23:20:52 +010065#define MSR_LBR_SELECT 0x000001c8
66#define MSR_LBR_TOS 0x000001c9
67#define MSR_LBR_NHM_FROM 0x00000680
68#define MSR_LBR_NHM_TO 0x000006c0
69#define MSR_LBR_CORE_FROM 0x00000040
70#define MSR_LBR_CORE_TO 0x00000060
71
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +020072#define MSR_IA32_PEBS_ENABLE 0x000003f1
73#define MSR_IA32_DS_AREA 0x00000600
74#define MSR_IA32_PERF_CAPABILITIES 0x00000345
Stephane Eranianf20093e2013-01-24 16:10:32 +010075#define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +020076
77#define MSR_MTRRfix64K_00000 0x00000250
78#define MSR_MTRRfix16K_80000 0x00000258
79#define MSR_MTRRfix16K_A0000 0x00000259
80#define MSR_MTRRfix4K_C0000 0x00000268
81#define MSR_MTRRfix4K_C8000 0x00000269
82#define MSR_MTRRfix4K_D0000 0x0000026a
83#define MSR_MTRRfix4K_D8000 0x0000026b
84#define MSR_MTRRfix4K_E0000 0x0000026c
85#define MSR_MTRRfix4K_E8000 0x0000026d
86#define MSR_MTRRfix4K_F0000 0x0000026e
87#define MSR_MTRRfix4K_F8000 0x0000026f
88#define MSR_MTRRdefType 0x000002ff
89
venkatesh.pallipadi@intel.com2e5d9c82008-03-18 17:00:14 -070090#define MSR_IA32_CR_PAT 0x00000277
91
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +020092#define MSR_IA32_DEBUGCTLMSR 0x000001d9
93#define MSR_IA32_LASTBRANCHFROMIP 0x000001db
94#define MSR_IA32_LASTBRANCHTOIP 0x000001dc
95#define MSR_IA32_LASTINTFROMIP 0x000001dd
96#define MSR_IA32_LASTINTTOIP 0x000001de
97
Roland McGrathd2499d82008-01-30 13:30:54 +010098/* DEBUGCTLMSR bits (others vary by model): */
Peter Zijlstra7c5ecaf2010-03-25 14:51:49 +010099#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */
100#define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */
101#define DEBUGCTLMSR_TR (1UL << 6)
102#define DEBUGCTLMSR_BTS (1UL << 7)
103#define DEBUGCTLMSR_BTINT (1UL << 8)
104#define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9)
105#define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10)
106#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11)
Roland McGrathd2499d82008-01-30 13:30:54 +0100107
Len Brown67920412013-01-31 15:22:15 -0500108#define MSR_IA32_POWER_CTL 0x000001fc
109
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200110#define MSR_IA32_MC0_CTL 0x00000400
111#define MSR_IA32_MC0_STATUS 0x00000401
112#define MSR_IA32_MC0_ADDR 0x00000402
113#define MSR_IA32_MC0_MISC 0x00000403
114
Linus Torvalds6842d982012-12-18 12:34:29 -0800115/* C-state Residency Counters */
116#define MSR_PKG_C3_RESIDENCY 0x000003f8
117#define MSR_PKG_C6_RESIDENCY 0x000003f9
118#define MSR_PKG_C7_RESIDENCY 0x000003fa
119#define MSR_CORE_C3_RESIDENCY 0x000003fc
120#define MSR_CORE_C6_RESIDENCY 0x000003fd
121#define MSR_CORE_C7_RESIDENCY 0x000003fe
122#define MSR_PKG_C2_RESIDENCY 0x0000060d
Kristen Carlson Accardica587102012-11-21 05:22:43 -0800123#define MSR_PKG_C8_RESIDENCY 0x00000630
124#define MSR_PKG_C9_RESIDENCY 0x00000631
125#define MSR_PKG_C10_RESIDENCY 0x00000632
Linus Torvalds6842d982012-12-18 12:34:29 -0800126
127/* Run Time Average Power Limiting (RAPL) Interface */
128
129#define MSR_RAPL_POWER_UNIT 0x00000606
130
131#define MSR_PKG_POWER_LIMIT 0x00000610
132#define MSR_PKG_ENERGY_STATUS 0x00000611
133#define MSR_PKG_PERF_STATUS 0x00000613
134#define MSR_PKG_POWER_INFO 0x00000614
135
136#define MSR_DRAM_POWER_LIMIT 0x00000618
137#define MSR_DRAM_ENERGY_STATUS 0x00000619
138#define MSR_DRAM_PERF_STATUS 0x0000061b
139#define MSR_DRAM_POWER_INFO 0x0000061c
140
141#define MSR_PP0_POWER_LIMIT 0x00000638
142#define MSR_PP0_ENERGY_STATUS 0x00000639
143#define MSR_PP0_POLICY 0x0000063a
144#define MSR_PP0_PERF_STATUS 0x0000063b
145
146#define MSR_PP1_POWER_LIMIT 0x00000640
147#define MSR_PP1_ENERGY_STATUS 0x00000641
148#define MSR_PP1_POLICY 0x00000642
149
Len Brown144b44b2013-11-09 00:30:16 -0500150#define MSR_CORE_C1_RES 0x00000660
151
Joerg Roedel5bbc0972011-04-15 14:47:40 +0200152#define MSR_AMD64_MC0_MASK 0xc0010044
153
Andi Kleena2d32bc2009-07-09 00:31:44 +0200154#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
155#define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x))
156#define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x))
157#define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x))
158
Joerg Roedel5bbc0972011-04-15 14:47:40 +0200159#define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x))
160
Andi Kleen03195c62009-02-12 13:49:35 +0100161/* These are consecutive and not in the normal 4er MCE bank block */
162#define MSR_IA32_MC0_CTL2 0x00000280
Andi Kleena2d32bc2009-07-09 00:31:44 +0200163#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))
164
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200165#define MSR_P6_PERFCTR0 0x000000c1
166#define MSR_P6_PERFCTR1 0x000000c2
167#define MSR_P6_EVNTSEL0 0x00000186
168#define MSR_P6_EVNTSEL1 0x00000187
169
Vince Weavere717bf42012-09-26 14:12:52 -0400170#define MSR_KNC_PERFCTR0 0x00000020
171#define MSR_KNC_PERFCTR1 0x00000021
172#define MSR_KNC_EVNTSEL0 0x00000028
173#define MSR_KNC_EVNTSEL1 0x00000029
174
Andi Kleen069e0c32013-06-25 08:12:33 -0700175/* Alternative perfctr range with full access. */
176#define MSR_IA32_PMC0 0x000004c1
177
Stephane Eranian4f8a6b12007-10-19 20:35:03 +0200178/* AMD64 MSRs. Not complete. See the architecture manual for a more
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200179 complete list. */
Stephane Eranian4f8a6b12007-10-19 20:35:03 +0200180
Andreas Herrmann29d08872008-12-16 19:16:34 +0100181#define MSR_AMD64_PATCH_LEVEL 0x0000008b
Joerg Roedelfbc0db72011-03-25 09:44:46 +0100182#define MSR_AMD64_TSC_RATIO 0xc0000104
stephane eranian12db6482008-03-07 13:05:39 -0800183#define MSR_AMD64_NB_CFG 0xc001001f
Andreas Herrmann29d08872008-12-16 19:16:34 +0100184#define MSR_AMD64_PATCH_LOADER 0xc0010020
Andreas Herrmann035a02c2010-03-19 12:09:22 +0100185#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
186#define MSR_AMD64_OSVW_STATUS 0xc0010141
Borislav Petkov3b564962014-01-15 00:07:11 +0100187#define MSR_AMD64_LS_CFG 0xc0011020
Joerg Roedel67ec6602010-05-17 14:43:35 +0200188#define MSR_AMD64_DC_CFG 0xc0011022
Boris Ostrovskyf0322bd2013-01-29 16:32:49 -0500189#define MSR_AMD64_BU_CFG2 0xc001102a
Stephane Eranian4f8a6b12007-10-19 20:35:03 +0200190#define MSR_AMD64_IBSFETCHCTL 0xc0011030
191#define MSR_AMD64_IBSFETCHLINAD 0xc0011031
192#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
Robert Richterb7074f12011-12-15 17:56:37 +0100193#define MSR_AMD64_IBSFETCH_REG_COUNT 3
194#define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
Stephane Eranian4f8a6b12007-10-19 20:35:03 +0200195#define MSR_AMD64_IBSOPCTL 0xc0011033
196#define MSR_AMD64_IBSOPRIP 0xc0011034
197#define MSR_AMD64_IBSOPDATA 0xc0011035
198#define MSR_AMD64_IBSOPDATA2 0xc0011036
199#define MSR_AMD64_IBSOPDATA3 0xc0011037
200#define MSR_AMD64_IBSDCLINAD 0xc0011038
201#define MSR_AMD64_IBSDCPHYSAD 0xc0011039
Robert Richterb7074f12011-12-15 17:56:37 +0100202#define MSR_AMD64_IBSOP_REG_COUNT 7
203#define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
Stephane Eranian4f8a6b12007-10-19 20:35:03 +0200204#define MSR_AMD64_IBSCTL 0xc001103a
Robert Richter25da6952010-09-21 15:49:31 +0200205#define MSR_AMD64_IBSBRTARGET 0xc001103b
Robert Richterb7074f12011-12-15 17:56:37 +0100206#define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */
Stephane Eranian4f8a6b12007-10-19 20:35:03 +0200207
Jacob Shinc43ca502013-04-19 16:34:28 -0500208/* Fam 16h MSRs */
209#define MSR_F16H_L2I_PERF_CTL 0xc0010230
210#define MSR_F16H_L2I_PERF_CTR 0xc0010231
211
Robert Richterda169f52010-09-24 15:54:43 +0200212/* Fam 15h MSRs */
213#define MSR_F15H_PERF_CTL 0xc0010200
214#define MSR_F15H_PERF_CTR 0xc0010201
Jacob Shine2595142013-02-06 11:26:29 -0600215#define MSR_F15H_NB_PERF_CTL 0xc0010240
216#define MSR_F15H_NB_PERF_CTR 0xc0010241
Robert Richterda169f52010-09-24 15:54:43 +0200217
Yinghai Lu2274c332008-01-30 13:33:18 +0100218/* Fam 10h MSRs */
219#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
220#define FAM10H_MMIO_CONF_ENABLE (1<<0)
221#define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
222#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
Jan Beulich37db6c82010-11-16 08:25:08 +0000223#define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL
Yinghai Lu2274c332008-01-30 13:33:18 +0100224#define FAM10H_MMIO_CONF_BASE_SHIFT 20
Andreas Herrmann9d260eb2009-12-16 15:43:55 +0100225#define MSR_FAM10H_NODE_ID 0xc001100c
Yinghai Lu2274c332008-01-30 13:33:18 +0100226
Stephane Eranian4f8a6b12007-10-19 20:35:03 +0200227/* K8 MSRs */
228#define MSR_K8_TOP_MEM1 0xc001001a
229#define MSR_K8_TOP_MEM2 0xc001001d
230#define MSR_K8_SYSCFG 0xc0010010
Thomas Gleixneraa83f3f2008-06-09 17:11:13 +0200231#define MSR_K8_INT_PENDING_MSG 0xc0010055
232/* C1E active bits in int pending message */
233#define K8_INTP_C1E_ACTIVE_MASK 0x18000000
Andi Kleen8346ea12008-03-12 03:53:32 +0100234#define MSR_K8_TSEG_ADDR 0xc0010112
Stephane Eranian4f8a6b12007-10-19 20:35:03 +0200235#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
236#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
237#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */
238
239/* K7 MSRs */
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200240#define MSR_K7_EVNTSEL0 0xc0010000
241#define MSR_K7_PERFCTR0 0xc0010004
242#define MSR_K7_EVNTSEL1 0xc0010001
243#define MSR_K7_PERFCTR1 0xc0010005
244#define MSR_K7_EVNTSEL2 0xc0010002
245#define MSR_K7_PERFCTR2 0xc0010006
246#define MSR_K7_EVNTSEL3 0xc0010003
247#define MSR_K7_PERFCTR3 0xc0010007
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200248#define MSR_K7_CLK_CTL 0xc001001b
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200249#define MSR_K7_HWCR 0xc0010015
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200250#define MSR_K7_FID_VID_CTL 0xc0010041
251#define MSR_K7_FID_VID_STATUS 0xc0010042
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200252
253/* K6 MSRs */
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200254#define MSR_K6_WHCR 0xc0000082
255#define MSR_K6_UWCCR 0xc0000085
256#define MSR_K6_EPMR 0xc0000086
257#define MSR_K6_PSOR 0xc0000087
258#define MSR_K6_PFIR 0xc0000088
259
260/* Centaur-Hauls/IDT defined MSRs. */
261#define MSR_IDT_FCR1 0x00000107
262#define MSR_IDT_FCR2 0x00000108
263#define MSR_IDT_FCR3 0x00000109
264#define MSR_IDT_FCR4 0x0000010a
265
266#define MSR_IDT_MCR0 0x00000110
267#define MSR_IDT_MCR1 0x00000111
268#define MSR_IDT_MCR2 0x00000112
269#define MSR_IDT_MCR3 0x00000113
270#define MSR_IDT_MCR4 0x00000114
271#define MSR_IDT_MCR5 0x00000115
272#define MSR_IDT_MCR6 0x00000116
273#define MSR_IDT_MCR7 0x00000117
274#define MSR_IDT_MCR_CTRL 0x00000120
275
276/* VIA Cyrix defined MSRs*/
277#define MSR_VIA_FCR 0x00001107
278#define MSR_VIA_LONGHAUL 0x0000110a
279#define MSR_VIA_RNG 0x0000110b
280#define MSR_VIA_BCR2 0x00001147
281
282/* Transmeta defined MSRs */
283#define MSR_TMTA_LONGRUN_CTRL 0x80868010
284#define MSR_TMTA_LONGRUN_FLAGS 0x80868011
285#define MSR_TMTA_LRTI_READOUT 0x80868018
286#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
287
288/* Intel defined MSRs. */
289#define MSR_IA32_P5_MC_ADDR 0x00000000
290#define MSR_IA32_P5_MC_TYPE 0x00000001
291#define MSR_IA32_TSC 0x00000010
292#define MSR_IA32_PLATFORM_ID 0x00000017
293#define MSR_IA32_EBL_CR_POWERON 0x0000002a
Jes Sorensenb9a52c42010-09-09 12:06:45 +0200294#define MSR_EBC_FREQUENCY_ID 0x0000002c
Len Brown1ed51012013-02-10 17:19:24 -0500295#define MSR_SMI_COUNT 0x00000034
Sheng Yang315a6552008-09-09 14:54:53 +0800296#define MSR_IA32_FEATURE_CONTROL 0x0000003a
Will Auldba904632012-11-29 12:42:50 -0800297#define MSR_IA32_TSC_ADJUST 0x0000003b
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200298
Shane Wangcafd6652010-04-29 12:09:01 -0400299#define FEATURE_CONTROL_LOCKED (1<<0)
300#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1)
301#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
Sheng Yangdefed7e2008-09-11 15:27:50 +0800302
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200303#define MSR_IA32_APICBASE 0x0000001b
304#define MSR_IA32_APICBASE_BSP (1<<8)
305#define MSR_IA32_APICBASE_ENABLE (1<<11)
306#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
307
Liu, Jinsongb90dfb02011-09-22 16:53:58 +0800308#define MSR_IA32_TSCDEADLINE 0x000006e0
309
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200310#define MSR_IA32_UCODE_WRITE 0x00000079
311#define MSR_IA32_UCODE_REV 0x0000008b
312
313#define MSR_IA32_PERF_STATUS 0x00000198
314#define MSR_IA32_PERF_CTL 0x00000199
Matthew Garrettf5940652012-09-04 08:28:06 +0000315#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
Matthew Garrett3dc9a632012-09-04 08:28:02 +0000316#define MSR_AMD_PERF_STATUS 0xc0010063
317#define MSR_AMD_PERF_CTL 0xc0010062
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200318
319#define MSR_IA32_MPERF 0x000000e7
320#define MSR_IA32_APERF 0x000000e8
321
322#define MSR_IA32_THERM_CONTROL 0x0000019a
323#define MSR_IA32_THERM_INTERRUPT 0x0000019b
Thomas Gleixnerba2d0f22009-04-08 12:31:24 +0200324
Fenghua Yu9792db62010-07-29 17:13:42 -0700325#define THERM_INT_HIGH_ENABLE (1 << 0)
326#define THERM_INT_LOW_ENABLE (1 << 1)
327#define THERM_INT_PLN_ENABLE (1 << 24)
Thomas Gleixnerba2d0f22009-04-08 12:31:24 +0200328
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200329#define MSR_IA32_THERM_STATUS 0x0000019c
Thomas Gleixnerba2d0f22009-04-08 12:31:24 +0200330
331#define THERM_STATUS_PROCHOT (1 << 0)
Fenghua Yu9792db62010-07-29 17:13:42 -0700332#define THERM_STATUS_POWER_LIMIT (1 << 10)
Thomas Gleixnerba2d0f22009-04-08 12:31:24 +0200333
Bartlomiej Zolnierkiewiczf3a08672009-07-29 00:04:59 +0200334#define MSR_THERM2_CTL 0x0000019d
335
336#define MSR_THERM2_CTL_TM_SELECT (1ULL << 16)
337
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200338#define MSR_IA32_MISC_ENABLE 0x000001a0
339
Carsten Emdea321ced2010-05-24 14:33:41 -0700340#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
341
Venkatesh Pallipadi23016bf2010-06-03 23:22:28 -0400342#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
Len Brownabe48b12011-07-14 00:53:24 -0400343#define ENERGY_PERF_BIAS_PERFORMANCE 0
344#define ENERGY_PERF_BIAS_NORMAL 6
H. Peter Anvin4bb82172011-07-14 14:58:44 -0700345#define ENERGY_PERF_BIAS_POWERSAVE 15
Venkatesh Pallipadi23016bf2010-06-03 23:22:28 -0400346
Fenghua Yu9792db62010-07-29 17:13:42 -0700347#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
348
349#define PACKAGE_THERM_STATUS_PROCHOT (1 << 0)
350#define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10)
351
352#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2
353
354#define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0)
355#define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1)
356#define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24)
357
R, Durgadoss9e76a972011-01-03 17:22:04 +0530358/* Thermal Thresholds Support */
359#define THERM_INT_THRESHOLD0_ENABLE (1 << 15)
360#define THERM_SHIFT_THRESHOLD0 8
361#define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0)
362#define THERM_INT_THRESHOLD1_ENABLE (1 << 23)
363#define THERM_SHIFT_THRESHOLD1 16
364#define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1)
365#define THERM_STATUS_THRESHOLD0 (1 << 6)
366#define THERM_LOG_THRESHOLD0 (1 << 7)
367#define THERM_STATUS_THRESHOLD1 (1 << 8)
368#define THERM_LOG_THRESHOLD1 (1 << 9)
369
H. Peter Anvinbdf21a42009-01-21 15:01:56 -0800370/* MISC_ENABLE bits: architectural */
H. Peter Anvin0b131be2014-03-13 15:40:52 -0700371#define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0
372#define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT)
373#define MSR_IA32_MISC_ENABLE_TCC_BIT 1
374#define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT)
375#define MSR_IA32_MISC_ENABLE_EMON_BIT 7
376#define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT)
377#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11
378#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT)
379#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12
380#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT)
381#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16
382#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT)
383#define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18
384#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT)
385#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22
386#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT);
387#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23
388#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT)
389#define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34
390#define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT)
H. Peter Anvinbdf21a42009-01-21 15:01:56 -0800391
392/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
H. Peter Anvin0b131be2014-03-13 15:40:52 -0700393#define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2
394#define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT)
395#define MSR_IA32_MISC_ENABLE_TM1_BIT 3
396#define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT)
397#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4
398#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT)
399#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6
400#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT)
401#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8
402#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT)
403#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9
404#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
405#define MSR_IA32_MISC_ENABLE_FERR_BIT 10
406#define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT)
407#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10
408#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT)
409#define MSR_IA32_MISC_ENABLE_TM2_BIT 13
410#define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT)
411#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19
412#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT)
413#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20
414#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT)
415#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24
416#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT)
417#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37
418#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT)
419#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38
420#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT)
421#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39
422#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
H. Peter Anvinbdf21a42009-01-21 15:01:56 -0800423
Suresh Siddha279f1462012-10-22 14:37:58 -0700424#define MSR_IA32_TSC_DEADLINE 0x000006E0
425
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200426/* P4/Xeon+ specific */
427#define MSR_IA32_MCG_EAX 0x00000180
428#define MSR_IA32_MCG_EBX 0x00000181
429#define MSR_IA32_MCG_ECX 0x00000182
430#define MSR_IA32_MCG_EDX 0x00000183
431#define MSR_IA32_MCG_ESI 0x00000184
432#define MSR_IA32_MCG_EDI 0x00000185
433#define MSR_IA32_MCG_EBP 0x00000186
434#define MSR_IA32_MCG_ESP 0x00000187
435#define MSR_IA32_MCG_EFLAGS 0x00000188
436#define MSR_IA32_MCG_EIP 0x00000189
437#define MSR_IA32_MCG_RESERVED 0x0000018a
438
439/* Pentium IV performance counter MSRs */
440#define MSR_P4_BPU_PERFCTR0 0x00000300
441#define MSR_P4_BPU_PERFCTR1 0x00000301
442#define MSR_P4_BPU_PERFCTR2 0x00000302
443#define MSR_P4_BPU_PERFCTR3 0x00000303
444#define MSR_P4_MS_PERFCTR0 0x00000304
445#define MSR_P4_MS_PERFCTR1 0x00000305
446#define MSR_P4_MS_PERFCTR2 0x00000306
447#define MSR_P4_MS_PERFCTR3 0x00000307
448#define MSR_P4_FLAME_PERFCTR0 0x00000308
449#define MSR_P4_FLAME_PERFCTR1 0x00000309
450#define MSR_P4_FLAME_PERFCTR2 0x0000030a
451#define MSR_P4_FLAME_PERFCTR3 0x0000030b
452#define MSR_P4_IQ_PERFCTR0 0x0000030c
453#define MSR_P4_IQ_PERFCTR1 0x0000030d
454#define MSR_P4_IQ_PERFCTR2 0x0000030e
455#define MSR_P4_IQ_PERFCTR3 0x0000030f
456#define MSR_P4_IQ_PERFCTR4 0x00000310
457#define MSR_P4_IQ_PERFCTR5 0x00000311
458#define MSR_P4_BPU_CCCR0 0x00000360
459#define MSR_P4_BPU_CCCR1 0x00000361
460#define MSR_P4_BPU_CCCR2 0x00000362
461#define MSR_P4_BPU_CCCR3 0x00000363
462#define MSR_P4_MS_CCCR0 0x00000364
463#define MSR_P4_MS_CCCR1 0x00000365
464#define MSR_P4_MS_CCCR2 0x00000366
465#define MSR_P4_MS_CCCR3 0x00000367
466#define MSR_P4_FLAME_CCCR0 0x00000368
467#define MSR_P4_FLAME_CCCR1 0x00000369
468#define MSR_P4_FLAME_CCCR2 0x0000036a
469#define MSR_P4_FLAME_CCCR3 0x0000036b
470#define MSR_P4_IQ_CCCR0 0x0000036c
471#define MSR_P4_IQ_CCCR1 0x0000036d
472#define MSR_P4_IQ_CCCR2 0x0000036e
473#define MSR_P4_IQ_CCCR3 0x0000036f
474#define MSR_P4_IQ_CCCR4 0x00000370
475#define MSR_P4_IQ_CCCR5 0x00000371
476#define MSR_P4_ALF_ESCR0 0x000003ca
477#define MSR_P4_ALF_ESCR1 0x000003cb
478#define MSR_P4_BPU_ESCR0 0x000003b2
479#define MSR_P4_BPU_ESCR1 0x000003b3
480#define MSR_P4_BSU_ESCR0 0x000003a0
481#define MSR_P4_BSU_ESCR1 0x000003a1
482#define MSR_P4_CRU_ESCR0 0x000003b8
483#define MSR_P4_CRU_ESCR1 0x000003b9
484#define MSR_P4_CRU_ESCR2 0x000003cc
485#define MSR_P4_CRU_ESCR3 0x000003cd
486#define MSR_P4_CRU_ESCR4 0x000003e0
487#define MSR_P4_CRU_ESCR5 0x000003e1
488#define MSR_P4_DAC_ESCR0 0x000003a8
489#define MSR_P4_DAC_ESCR1 0x000003a9
490#define MSR_P4_FIRM_ESCR0 0x000003a4
491#define MSR_P4_FIRM_ESCR1 0x000003a5
492#define MSR_P4_FLAME_ESCR0 0x000003a6
493#define MSR_P4_FLAME_ESCR1 0x000003a7
494#define MSR_P4_FSB_ESCR0 0x000003a2
495#define MSR_P4_FSB_ESCR1 0x000003a3
496#define MSR_P4_IQ_ESCR0 0x000003ba
497#define MSR_P4_IQ_ESCR1 0x000003bb
498#define MSR_P4_IS_ESCR0 0x000003b4
499#define MSR_P4_IS_ESCR1 0x000003b5
500#define MSR_P4_ITLB_ESCR0 0x000003b6
501#define MSR_P4_ITLB_ESCR1 0x000003b7
502#define MSR_P4_IX_ESCR0 0x000003c8
503#define MSR_P4_IX_ESCR1 0x000003c9
504#define MSR_P4_MOB_ESCR0 0x000003aa
505#define MSR_P4_MOB_ESCR1 0x000003ab
506#define MSR_P4_MS_ESCR0 0x000003c0
507#define MSR_P4_MS_ESCR1 0x000003c1
508#define MSR_P4_PMH_ESCR0 0x000003ac
509#define MSR_P4_PMH_ESCR1 0x000003ad
510#define MSR_P4_RAT_ESCR0 0x000003bc
511#define MSR_P4_RAT_ESCR1 0x000003bd
512#define MSR_P4_SAAT_ESCR0 0x000003ae
513#define MSR_P4_SAAT_ESCR1 0x000003af
514#define MSR_P4_SSU_ESCR0 0x000003be
515#define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */
516
517#define MSR_P4_TBPU_ESCR0 0x000003c2
518#define MSR_P4_TBPU_ESCR1 0x000003c3
519#define MSR_P4_TC_ESCR0 0x000003c4
520#define MSR_P4_TC_ESCR1 0x000003c5
521#define MSR_P4_U2L_ESCR0 0x000003b0
522#define MSR_P4_U2L_ESCR1 0x000003b1
523
Lin Mingcb7d6b52010-03-18 18:33:12 +0800524#define MSR_P4_PEBS_MATRIX_VERT 0x000003f2
525
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200526/* Intel Core-based CPU performance counters */
527#define MSR_CORE_PERF_FIXED_CTR0 0x00000309
528#define MSR_CORE_PERF_FIXED_CTR1 0x0000030a
529#define MSR_CORE_PERF_FIXED_CTR2 0x0000030b
530#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d
531#define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e
532#define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f
533#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390
534
535/* Geode defined MSRs */
536#define MSR_GEODE_BUSCONT_CONF0 0x00001900
537
Sheng Yang315a6552008-09-09 14:54:53 +0800538/* Intel VT MSRs */
539#define MSR_IA32_VMX_BASIC 0x00000480
540#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
541#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
542#define MSR_IA32_VMX_EXIT_CTLS 0x00000483
543#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
544#define MSR_IA32_VMX_MISC 0x00000485
545#define MSR_IA32_VMX_CR0_FIXED0 0x00000486
546#define MSR_IA32_VMX_CR0_FIXED1 0x00000487
547#define MSR_IA32_VMX_CR4_FIXED0 0x00000488
548#define MSR_IA32_VMX_CR4_FIXED1 0x00000489
549#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
550#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
551#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
Nadav Har'Elb87a51a2011-05-25 23:04:25 +0300552#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
553#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
554#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
555#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
Jan Kiszkacae50132014-01-04 18:47:22 +0100556#define MSR_IA32_VMX_VMFUNC 0x00000491
Nadav Har'Elb87a51a2011-05-25 23:04:25 +0300557
558/* VMX_BASIC bits and bitmasks */
559#define VMX_BASIC_VMCS_SIZE_SHIFT 32
560#define VMX_BASIC_64 0x0001000000000000LLU
561#define VMX_BASIC_MEM_TYPE_SHIFT 50
562#define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU
563#define VMX_BASIC_MEM_TYPE_WB 6LLU
564#define VMX_BASIC_INOUT 0x0040000000000000LLU
Sheng Yang315a6552008-09-09 14:54:53 +0800565
Abel Gordon89662e52013-04-18 14:34:55 +0300566/* MSR_IA32_VMX_MISC bits */
567#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
Arthur Chunqi Li7854cbc2013-09-16 16:11:44 +0800568#define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F
Alexander Graf9962d032008-11-25 20:17:02 +0100569/* AMD-V MSRs */
570
571#define MSR_VM_CR 0xc0010114
Alexander Graf0367b432009-06-15 15:21:22 +0200572#define MSR_VM_IGNNE 0xc0010115
Alexander Graf9962d032008-11-25 20:17:02 +0100573#define MSR_VM_HSAVE_PA 0xc0010117
574
H. Peter Anvin1965aae2008-10-22 22:26:29 -0700575#endif /* _ASM_X86_MSR_INDEX_H */