blob: 536632f6479c6966029022614f2bf863974256b4 [file] [log] [blame]
Boojin Kimb7d861d2011-12-26 18:49:52 +09001/*
2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
Jassi Brarb3040e42010-05-23 20:28:19 -07004 *
5 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
6 * Jaswinder Singh <jassi.brar@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
Boojin Kimb7d861d2011-12-26 18:49:52 +090014#include <linux/kernel.h>
Jassi Brarb3040e42010-05-23 20:28:19 -070015#include <linux/io.h>
16#include <linux/init.h>
17#include <linux/slab.h>
18#include <linux/module.h>
Boojin Kimb7d861d2011-12-26 18:49:52 +090019#include <linux/string.h>
20#include <linux/delay.h>
21#include <linux/interrupt.h>
22#include <linux/dma-mapping.h>
Jassi Brarb3040e42010-05-23 20:28:19 -070023#include <linux/dmaengine.h>
Jassi Brarb3040e42010-05-23 20:28:19 -070024#include <linux/amba/bus.h>
25#include <linux/amba/pl330.h>
Boojin Kim1b9bb712011-09-02 09:44:30 +090026#include <linux/scatterlist.h>
Thomas Abraham93ed5542011-10-24 11:43:31 +020027#include <linux/of.h>
Padmavathi Vennaa80258f2013-02-14 09:10:06 +053028#include <linux/of_dma.h>
Sachin Kamatbcc7fa92013-03-04 14:36:27 +053029#include <linux/err.h>
Jassi Brarb3040e42010-05-23 20:28:19 -070030
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +000031#include "dmaengine.h"
Boojin Kimb7d861d2011-12-26 18:49:52 +090032#define PL330_MAX_CHAN 8
33#define PL330_MAX_IRQS 32
34#define PL330_MAX_PERI 32
35
36enum pl330_srccachectrl {
37 SCCTRL0, /* Noncacheable and nonbufferable */
38 SCCTRL1, /* Bufferable only */
39 SCCTRL2, /* Cacheable, but do not allocate */
40 SCCTRL3, /* Cacheable and bufferable, but do not allocate */
41 SINVALID1,
42 SINVALID2,
43 SCCTRL6, /* Cacheable write-through, allocate on reads only */
44 SCCTRL7, /* Cacheable write-back, allocate on reads only */
45};
46
47enum pl330_dstcachectrl {
48 DCCTRL0, /* Noncacheable and nonbufferable */
49 DCCTRL1, /* Bufferable only */
50 DCCTRL2, /* Cacheable, but do not allocate */
51 DCCTRL3, /* Cacheable and bufferable, but do not allocate */
Linus Torvaldsef08e782012-03-29 15:34:57 -070052 DINVALID1, /* AWCACHE = 0x1000 */
Boojin Kimb7d861d2011-12-26 18:49:52 +090053 DINVALID2,
54 DCCTRL6, /* Cacheable write-through, allocate on writes only */
55 DCCTRL7, /* Cacheable write-back, allocate on writes only */
56};
57
58enum pl330_byteswap {
59 SWAP_NO,
60 SWAP_2,
61 SWAP_4,
62 SWAP_8,
63 SWAP_16,
64};
65
66enum pl330_reqtype {
67 MEMTOMEM,
68 MEMTODEV,
69 DEVTOMEM,
70 DEVTODEV,
71};
72
73/* Register and Bit field Definitions */
74#define DS 0x0
75#define DS_ST_STOP 0x0
76#define DS_ST_EXEC 0x1
77#define DS_ST_CMISS 0x2
78#define DS_ST_UPDTPC 0x3
79#define DS_ST_WFE 0x4
80#define DS_ST_ATBRR 0x5
81#define DS_ST_QBUSY 0x6
82#define DS_ST_WFP 0x7
83#define DS_ST_KILL 0x8
84#define DS_ST_CMPLT 0x9
85#define DS_ST_FLTCMP 0xe
86#define DS_ST_FAULT 0xf
87
88#define DPC 0x4
89#define INTEN 0x20
90#define ES 0x24
91#define INTSTATUS 0x28
92#define INTCLR 0x2c
93#define FSM 0x30
94#define FSC 0x34
95#define FTM 0x38
96
97#define _FTC 0x40
98#define FTC(n) (_FTC + (n)*0x4)
99
100#define _CS 0x100
101#define CS(n) (_CS + (n)*0x8)
102#define CS_CNS (1 << 21)
103
104#define _CPC 0x104
105#define CPC(n) (_CPC + (n)*0x8)
106
107#define _SA 0x400
108#define SA(n) (_SA + (n)*0x20)
109
110#define _DA 0x404
111#define DA(n) (_DA + (n)*0x20)
112
113#define _CC 0x408
114#define CC(n) (_CC + (n)*0x20)
115
116#define CC_SRCINC (1 << 0)
117#define CC_DSTINC (1 << 14)
118#define CC_SRCPRI (1 << 8)
119#define CC_DSTPRI (1 << 22)
120#define CC_SRCNS (1 << 9)
121#define CC_DSTNS (1 << 23)
122#define CC_SRCIA (1 << 10)
123#define CC_DSTIA (1 << 24)
124#define CC_SRCBRSTLEN_SHFT 4
125#define CC_DSTBRSTLEN_SHFT 18
126#define CC_SRCBRSTSIZE_SHFT 1
127#define CC_DSTBRSTSIZE_SHFT 15
128#define CC_SRCCCTRL_SHFT 11
129#define CC_SRCCCTRL_MASK 0x7
130#define CC_DSTCCTRL_SHFT 25
131#define CC_DRCCCTRL_MASK 0x7
132#define CC_SWAP_SHFT 28
133
134#define _LC0 0x40c
135#define LC0(n) (_LC0 + (n)*0x20)
136
137#define _LC1 0x410
138#define LC1(n) (_LC1 + (n)*0x20)
139
140#define DBGSTATUS 0xd00
141#define DBG_BUSY (1 << 0)
142
143#define DBGCMD 0xd04
144#define DBGINST0 0xd08
145#define DBGINST1 0xd0c
146
147#define CR0 0xe00
148#define CR1 0xe04
149#define CR2 0xe08
150#define CR3 0xe0c
151#define CR4 0xe10
152#define CRD 0xe14
153
154#define PERIPH_ID 0xfe0
Boojin Kim3ecf51a2011-12-26 18:55:47 +0900155#define PERIPH_REV_SHIFT 20
156#define PERIPH_REV_MASK 0xf
157#define PERIPH_REV_R0P0 0
158#define PERIPH_REV_R1P0 1
159#define PERIPH_REV_R1P1 2
Boojin Kimb7d861d2011-12-26 18:49:52 +0900160
161#define CR0_PERIPH_REQ_SET (1 << 0)
162#define CR0_BOOT_EN_SET (1 << 1)
163#define CR0_BOOT_MAN_NS (1 << 2)
164#define CR0_NUM_CHANS_SHIFT 4
165#define CR0_NUM_CHANS_MASK 0x7
166#define CR0_NUM_PERIPH_SHIFT 12
167#define CR0_NUM_PERIPH_MASK 0x1f
168#define CR0_NUM_EVENTS_SHIFT 17
169#define CR0_NUM_EVENTS_MASK 0x1f
170
171#define CR1_ICACHE_LEN_SHIFT 0
172#define CR1_ICACHE_LEN_MASK 0x7
173#define CR1_NUM_ICACHELINES_SHIFT 4
174#define CR1_NUM_ICACHELINES_MASK 0xf
175
176#define CRD_DATA_WIDTH_SHIFT 0
177#define CRD_DATA_WIDTH_MASK 0x7
178#define CRD_WR_CAP_SHIFT 4
179#define CRD_WR_CAP_MASK 0x7
180#define CRD_WR_Q_DEP_SHIFT 8
181#define CRD_WR_Q_DEP_MASK 0xf
182#define CRD_RD_CAP_SHIFT 12
183#define CRD_RD_CAP_MASK 0x7
184#define CRD_RD_Q_DEP_SHIFT 16
185#define CRD_RD_Q_DEP_MASK 0xf
186#define CRD_DATA_BUFF_SHIFT 20
187#define CRD_DATA_BUFF_MASK 0x3ff
188
189#define PART 0x330
190#define DESIGNER 0x41
191#define REVISION 0x0
192#define INTEG_CFG 0x0
193#define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
194
Boojin Kimb7d861d2011-12-26 18:49:52 +0900195#define PL330_STATE_STOPPED (1 << 0)
196#define PL330_STATE_EXECUTING (1 << 1)
197#define PL330_STATE_WFE (1 << 2)
198#define PL330_STATE_FAULTING (1 << 3)
199#define PL330_STATE_COMPLETING (1 << 4)
200#define PL330_STATE_WFP (1 << 5)
201#define PL330_STATE_KILLING (1 << 6)
202#define PL330_STATE_FAULT_COMPLETING (1 << 7)
203#define PL330_STATE_CACHEMISS (1 << 8)
204#define PL330_STATE_UPDTPC (1 << 9)
205#define PL330_STATE_ATBARRIER (1 << 10)
206#define PL330_STATE_QUEUEBUSY (1 << 11)
207#define PL330_STATE_INVALID (1 << 15)
208
209#define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
210 | PL330_STATE_WFE | PL330_STATE_FAULTING)
211
212#define CMD_DMAADDH 0x54
213#define CMD_DMAEND 0x00
214#define CMD_DMAFLUSHP 0x35
215#define CMD_DMAGO 0xa0
216#define CMD_DMALD 0x04
217#define CMD_DMALDP 0x25
218#define CMD_DMALP 0x20
219#define CMD_DMALPEND 0x28
220#define CMD_DMAKILL 0x01
221#define CMD_DMAMOV 0xbc
222#define CMD_DMANOP 0x18
223#define CMD_DMARMB 0x12
224#define CMD_DMASEV 0x34
225#define CMD_DMAST 0x08
226#define CMD_DMASTP 0x29
227#define CMD_DMASTZ 0x0c
228#define CMD_DMAWFE 0x36
229#define CMD_DMAWFP 0x30
230#define CMD_DMAWMB 0x13
231
232#define SZ_DMAADDH 3
233#define SZ_DMAEND 1
234#define SZ_DMAFLUSHP 2
235#define SZ_DMALD 1
236#define SZ_DMALDP 2
237#define SZ_DMALP 2
238#define SZ_DMALPEND 2
239#define SZ_DMAKILL 1
240#define SZ_DMAMOV 6
241#define SZ_DMANOP 1
242#define SZ_DMARMB 1
243#define SZ_DMASEV 2
244#define SZ_DMAST 1
245#define SZ_DMASTP 2
246#define SZ_DMASTZ 1
247#define SZ_DMAWFE 2
248#define SZ_DMAWFP 2
249#define SZ_DMAWMB 1
250#define SZ_DMAGO 6
251
252#define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
253#define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
254
255#define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
256#define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
257
258/*
259 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
260 * at 1byte/burst for P<->M and M<->M respectively.
261 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
262 * should be enough for P<->M and M<->M respectively.
263 */
264#define MCODE_BUFF_PER_REQ 256
265
266/* If the _pl330_req is available to the client */
267#define IS_FREE(req) (*((u8 *)((req)->mc_cpu)) == CMD_DMAEND)
268
269/* Use this _only_ to wait on transient states */
270#define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
271
272#ifdef PL330_DEBUG_MCGEN
273static unsigned cmd_line;
274#define PL330_DBGCMD_DUMP(off, x...) do { \
275 printk("%x:", cmd_line); \
276 printk(x); \
277 cmd_line += off; \
278 } while (0)
279#define PL330_DBGMC_START(addr) (cmd_line = addr)
280#else
281#define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
282#define PL330_DBGMC_START(addr) do {} while (0)
283#endif
284
285/* The number of default descriptors */
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +0000286
Jassi Brarb3040e42010-05-23 20:28:19 -0700287#define NR_DEFAULT_DESC 16
288
Boojin Kimb7d861d2011-12-26 18:49:52 +0900289/* Populated by the PL330 core driver for DMA API driver's info */
290struct pl330_config {
291 u32 periph_id;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900292#define DMAC_MODE_NS (1 << 0)
293 unsigned int mode;
294 unsigned int data_bus_width:10; /* In number of bits */
295 unsigned int data_buf_dep:10;
296 unsigned int num_chan:4;
297 unsigned int num_peri:6;
298 u32 peri_ns;
299 unsigned int num_events:6;
300 u32 irq_ns;
301};
302
303/* Handle to the DMAC provided to the PL330 core */
304struct pl330_info {
305 /* Owning device */
306 struct device *dev;
307 /* Size of MicroCode buffers for each channel. */
308 unsigned mcbufsz;
309 /* ioremap'ed address of PL330 registers. */
310 void __iomem *base;
311 /* Client can freely use it. */
312 void *client_data;
313 /* PL330 core data, Client must not touch it. */
314 void *pl330_data;
315 /* Populated by the PL330 core driver during pl330_add */
316 struct pl330_config pcfg;
317 /*
318 * If the DMAC has some reset mechanism, then the
319 * client may want to provide pointer to the method.
320 */
321 void (*dmac_reset)(struct pl330_info *pi);
322};
323
324/**
325 * Request Configuration.
326 * The PL330 core does not modify this and uses the last
327 * working configuration if the request doesn't provide any.
328 *
329 * The Client may want to provide this info only for the
330 * first request and a request with new settings.
331 */
332struct pl330_reqcfg {
333 /* Address Incrementing */
334 unsigned dst_inc:1;
335 unsigned src_inc:1;
336
337 /*
338 * For now, the SRC & DST protection levels
339 * and burst size/length are assumed same.
340 */
341 bool nonsecure;
342 bool privileged;
343 bool insnaccess;
344 unsigned brst_len:5;
345 unsigned brst_size:3; /* in power of 2 */
346
347 enum pl330_dstcachectrl dcctl;
348 enum pl330_srccachectrl scctl;
349 enum pl330_byteswap swap;
Boojin Kim3ecf51a2011-12-26 18:55:47 +0900350 struct pl330_config *pcfg;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900351};
352
353/*
354 * One cycle of DMAC operation.
355 * There may be more than one xfer in a request.
356 */
357struct pl330_xfer {
358 u32 src_addr;
359 u32 dst_addr;
360 /* Size to xfer */
361 u32 bytes;
362 /*
363 * Pointer to next xfer in the list.
364 * The last xfer in the req must point to NULL.
365 */
366 struct pl330_xfer *next;
367};
368
369/* The xfer callbacks are made with one of these arguments. */
370enum pl330_op_err {
371 /* The all xfers in the request were success. */
372 PL330_ERR_NONE,
373 /* If req aborted due to global error. */
374 PL330_ERR_ABORT,
375 /* If req failed due to problem with Channel. */
376 PL330_ERR_FAIL,
377};
378
379/* A request defining Scatter-Gather List ending with NULL xfer. */
380struct pl330_req {
381 enum pl330_reqtype rqtype;
382 /* Index of peripheral for the xfer. */
383 unsigned peri:5;
384 /* Unique token for this xfer, set by the client. */
385 void *token;
386 /* Callback to be called after xfer. */
387 void (*xfer_cb)(void *token, enum pl330_op_err err);
388 /* If NULL, req will be done at last set parameters. */
389 struct pl330_reqcfg *cfg;
390 /* Pointer to first xfer in the request. */
391 struct pl330_xfer *x;
Javi Merinofdec53d2012-06-13 15:07:00 +0100392 /* Hook to attach to DMAC's list of reqs with due callback */
393 struct list_head rqd;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900394};
395
396/*
397 * To know the status of the channel and DMAC, the client
398 * provides a pointer to this structure. The PL330 core
399 * fills it with current information.
400 */
401struct pl330_chanstatus {
402 /*
403 * If the DMAC engine halted due to some error,
404 * the client should remove-add DMAC.
405 */
406 bool dmac_halted;
407 /*
408 * If channel is halted due to some error,
409 * the client should ABORT/FLUSH and START the channel.
410 */
411 bool faulting;
412 /* Location of last load */
413 u32 src_addr;
414 /* Location of last store */
415 u32 dst_addr;
416 /*
417 * Pointer to the currently active req, NULL if channel is
418 * inactive, even though the requests may be present.
419 */
420 struct pl330_req *top_req;
421 /* Pointer to req waiting second in the queue if any. */
422 struct pl330_req *wait_req;
423};
424
425enum pl330_chan_op {
426 /* Start the channel */
427 PL330_OP_START,
428 /* Abort the active xfer */
429 PL330_OP_ABORT,
430 /* Stop xfer and flush queue */
431 PL330_OP_FLUSH,
432};
433
434struct _xfer_spec {
435 u32 ccr;
436 struct pl330_req *r;
437 struct pl330_xfer *x;
438};
439
440enum dmamov_dst {
441 SAR = 0,
442 CCR,
443 DAR,
444};
445
446enum pl330_dst {
447 SRC = 0,
448 DST,
449};
450
451enum pl330_cond {
452 SINGLE,
453 BURST,
454 ALWAYS,
455};
456
457struct _pl330_req {
458 u32 mc_bus;
459 void *mc_cpu;
460 /* Number of bytes taken to setup MC for the req */
461 u32 mc_len;
462 struct pl330_req *r;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900463};
464
465/* ToBeDone for tasklet */
466struct _pl330_tbd {
467 bool reset_dmac;
468 bool reset_mngr;
469 u8 reset_chan;
470};
471
472/* A DMAC Thread */
473struct pl330_thread {
474 u8 id;
475 int ev;
476 /* If the channel is not yet acquired by any client */
477 bool free;
478 /* Parent DMAC */
479 struct pl330_dmac *dmac;
480 /* Only two at a time */
481 struct _pl330_req req[2];
482 /* Index of the last enqueued request */
483 unsigned lstenq;
484 /* Index of the last submitted request or -1 if the DMA is stopped */
485 int req_running;
486};
487
488enum pl330_dmac_state {
489 UNINIT,
490 INIT,
491 DYING,
492};
493
494/* A DMAC */
495struct pl330_dmac {
496 spinlock_t lock;
497 /* Holds list of reqs with due callbacks */
498 struct list_head req_done;
499 /* Pointer to platform specific stuff */
500 struct pl330_info *pinfo;
501 /* Maximum possible events/irqs */
502 int events[32];
503 /* BUS address of MicroCode buffer */
Will Deaconfed8c452013-06-10 19:34:38 +0100504 dma_addr_t mcode_bus;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900505 /* CPU address of MicroCode buffer */
506 void *mcode_cpu;
507 /* List of all Channel threads */
508 struct pl330_thread *channels;
509 /* Pointer to the MANAGER thread */
510 struct pl330_thread *manager;
511 /* To handle bad news in interrupt */
512 struct tasklet_struct tasks;
513 struct _pl330_tbd dmac_tbd;
514 /* State of DMAC operation */
515 enum pl330_dmac_state state;
516};
517
Jassi Brarb3040e42010-05-23 20:28:19 -0700518enum desc_status {
519 /* In the DMAC pool */
520 FREE,
521 /*
Masanari Iidad73111c2012-08-04 23:37:53 +0900522 * Allocated to some channel during prep_xxx
Jassi Brarb3040e42010-05-23 20:28:19 -0700523 * Also may be sitting on the work_list.
524 */
525 PREP,
526 /*
527 * Sitting on the work_list and already submitted
528 * to the PL330 core. Not more than two descriptors
529 * of a channel can be BUSY at any time.
530 */
531 BUSY,
532 /*
533 * Sitting on the channel work_list but xfer done
534 * by PL330 core
535 */
536 DONE,
537};
538
539struct dma_pl330_chan {
540 /* Schedule desc completion */
541 struct tasklet_struct task;
542
543 /* DMA-Engine Channel */
544 struct dma_chan chan;
545
Jassi Brarb3040e42010-05-23 20:28:19 -0700546 /* List of to be xfered descriptors */
547 struct list_head work_list;
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +0200548 /* List of completed descriptors */
549 struct list_head completed_list;
Jassi Brarb3040e42010-05-23 20:28:19 -0700550
551 /* Pointer to the DMAC that manages this channel,
552 * NULL if the channel is available to be acquired.
553 * As the parent, this DMAC also provides descriptors
554 * to the channel.
555 */
556 struct dma_pl330_dmac *dmac;
557
558 /* To protect channel manipulation */
559 spinlock_t lock;
560
561 /* Token of a hardware channel thread of PL330 DMAC
562 * NULL if the channel is available to be acquired.
563 */
564 void *pl330_chid;
Boojin Kim1b9bb712011-09-02 09:44:30 +0900565
566 /* For D-to-M and M-to-D channels */
567 int burst_sz; /* the peripheral fifo width */
Boojin Kim1d0c1d62011-09-02 09:44:31 +0900568 int burst_len; /* the number of burst */
Boojin Kim1b9bb712011-09-02 09:44:30 +0900569 dma_addr_t fifo_addr;
Boojin Kim42bc9cf2011-09-02 09:44:33 +0900570
571 /* for cyclic capability */
572 bool cyclic;
Jassi Brarb3040e42010-05-23 20:28:19 -0700573};
574
575struct dma_pl330_dmac {
576 struct pl330_info pif;
577
578 /* DMA-Engine Device */
579 struct dma_device ddma;
580
581 /* Pool of descriptors available for the DMAC's channels */
582 struct list_head desc_pool;
583 /* To protect desc_pool manipulation */
584 spinlock_t pool_lock;
585
586 /* Peripheral channels connected to this DMAC */
Rob Herring4e0e6102011-07-25 16:05:04 -0500587 struct dma_pl330_chan *peripherals; /* keep at end */
Jassi Brarb3040e42010-05-23 20:28:19 -0700588};
589
590struct dma_pl330_desc {
591 /* To attach to a queue as child */
592 struct list_head node;
593
594 /* Descriptor for the DMA Engine API */
595 struct dma_async_tx_descriptor txd;
596
597 /* Xfer for PL330 core */
598 struct pl330_xfer px;
599
600 struct pl330_reqcfg rqcfg;
601 struct pl330_req req;
602
603 enum desc_status status;
604
605 /* The channel which currently holds this desc */
606 struct dma_pl330_chan *pchan;
607};
608
Padmavathi Venna34d19352013-02-14 09:10:05 +0530609struct dma_pl330_filter_args {
610 struct dma_pl330_dmac *pdmac;
611 unsigned int chan_id;
612};
613
Boojin Kimb7d861d2011-12-26 18:49:52 +0900614static inline void _callback(struct pl330_req *r, enum pl330_op_err err)
615{
616 if (r && r->xfer_cb)
617 r->xfer_cb(r->token, err);
618}
619
620static inline bool _queue_empty(struct pl330_thread *thrd)
621{
622 return (IS_FREE(&thrd->req[0]) && IS_FREE(&thrd->req[1]))
623 ? true : false;
624}
625
626static inline bool _queue_full(struct pl330_thread *thrd)
627{
628 return (IS_FREE(&thrd->req[0]) || IS_FREE(&thrd->req[1]))
629 ? false : true;
630}
631
632static inline bool is_manager(struct pl330_thread *thrd)
633{
634 struct pl330_dmac *pl330 = thrd->dmac;
635
636 /* MANAGER is indexed at the end */
637 if (thrd->id == pl330->pinfo->pcfg.num_chan)
638 return true;
639 else
640 return false;
641}
642
643/* If manager of the thread is in Non-Secure mode */
644static inline bool _manager_ns(struct pl330_thread *thrd)
645{
646 struct pl330_dmac *pl330 = thrd->dmac;
647
648 return (pl330->pinfo->pcfg.mode & DMAC_MODE_NS) ? true : false;
649}
650
Boojin Kim3ecf51a2011-12-26 18:55:47 +0900651static inline u32 get_revision(u32 periph_id)
652{
653 return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
654}
655
Boojin Kimb7d861d2011-12-26 18:49:52 +0900656static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[],
657 enum pl330_dst da, u16 val)
658{
659 if (dry_run)
660 return SZ_DMAADDH;
661
662 buf[0] = CMD_DMAADDH;
663 buf[0] |= (da << 1);
664 *((u16 *)&buf[1]) = val;
665
666 PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n",
667 da == 1 ? "DA" : "SA", val);
668
669 return SZ_DMAADDH;
670}
671
672static inline u32 _emit_END(unsigned dry_run, u8 buf[])
673{
674 if (dry_run)
675 return SZ_DMAEND;
676
677 buf[0] = CMD_DMAEND;
678
679 PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n");
680
681 return SZ_DMAEND;
682}
683
684static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri)
685{
686 if (dry_run)
687 return SZ_DMAFLUSHP;
688
689 buf[0] = CMD_DMAFLUSHP;
690
691 peri &= 0x1f;
692 peri <<= 3;
693 buf[1] = peri;
694
695 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3);
696
697 return SZ_DMAFLUSHP;
698}
699
700static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond)
701{
702 if (dry_run)
703 return SZ_DMALD;
704
705 buf[0] = CMD_DMALD;
706
707 if (cond == SINGLE)
708 buf[0] |= (0 << 1) | (1 << 0);
709 else if (cond == BURST)
710 buf[0] |= (1 << 1) | (1 << 0);
711
712 PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n",
713 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
714
715 return SZ_DMALD;
716}
717
718static inline u32 _emit_LDP(unsigned dry_run, u8 buf[],
719 enum pl330_cond cond, u8 peri)
720{
721 if (dry_run)
722 return SZ_DMALDP;
723
724 buf[0] = CMD_DMALDP;
725
726 if (cond == BURST)
727 buf[0] |= (1 << 1);
728
729 peri &= 0x1f;
730 peri <<= 3;
731 buf[1] = peri;
732
733 PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n",
734 cond == SINGLE ? 'S' : 'B', peri >> 3);
735
736 return SZ_DMALDP;
737}
738
739static inline u32 _emit_LP(unsigned dry_run, u8 buf[],
740 unsigned loop, u8 cnt)
741{
742 if (dry_run)
743 return SZ_DMALP;
744
745 buf[0] = CMD_DMALP;
746
747 if (loop)
748 buf[0] |= (1 << 1);
749
750 cnt--; /* DMAC increments by 1 internally */
751 buf[1] = cnt;
752
753 PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt);
754
755 return SZ_DMALP;
756}
757
758struct _arg_LPEND {
759 enum pl330_cond cond;
760 bool forever;
761 unsigned loop;
762 u8 bjump;
763};
764
765static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[],
766 const struct _arg_LPEND *arg)
767{
768 enum pl330_cond cond = arg->cond;
769 bool forever = arg->forever;
770 unsigned loop = arg->loop;
771 u8 bjump = arg->bjump;
772
773 if (dry_run)
774 return SZ_DMALPEND;
775
776 buf[0] = CMD_DMALPEND;
777
778 if (loop)
779 buf[0] |= (1 << 2);
780
781 if (!forever)
782 buf[0] |= (1 << 4);
783
784 if (cond == SINGLE)
785 buf[0] |= (0 << 1) | (1 << 0);
786 else if (cond == BURST)
787 buf[0] |= (1 << 1) | (1 << 0);
788
789 buf[1] = bjump;
790
791 PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n",
792 forever ? "FE" : "END",
793 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'),
794 loop ? '1' : '0',
795 bjump);
796
797 return SZ_DMALPEND;
798}
799
800static inline u32 _emit_KILL(unsigned dry_run, u8 buf[])
801{
802 if (dry_run)
803 return SZ_DMAKILL;
804
805 buf[0] = CMD_DMAKILL;
806
807 return SZ_DMAKILL;
808}
809
810static inline u32 _emit_MOV(unsigned dry_run, u8 buf[],
811 enum dmamov_dst dst, u32 val)
812{
813 if (dry_run)
814 return SZ_DMAMOV;
815
816 buf[0] = CMD_DMAMOV;
817 buf[1] = dst;
818 *((u32 *)&buf[2]) = val;
819
820 PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n",
821 dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
822
823 return SZ_DMAMOV;
824}
825
826static inline u32 _emit_NOP(unsigned dry_run, u8 buf[])
827{
828 if (dry_run)
829 return SZ_DMANOP;
830
831 buf[0] = CMD_DMANOP;
832
833 PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n");
834
835 return SZ_DMANOP;
836}
837
838static inline u32 _emit_RMB(unsigned dry_run, u8 buf[])
839{
840 if (dry_run)
841 return SZ_DMARMB;
842
843 buf[0] = CMD_DMARMB;
844
845 PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n");
846
847 return SZ_DMARMB;
848}
849
850static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev)
851{
852 if (dry_run)
853 return SZ_DMASEV;
854
855 buf[0] = CMD_DMASEV;
856
857 ev &= 0x1f;
858 ev <<= 3;
859 buf[1] = ev;
860
861 PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3);
862
863 return SZ_DMASEV;
864}
865
866static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond)
867{
868 if (dry_run)
869 return SZ_DMAST;
870
871 buf[0] = CMD_DMAST;
872
873 if (cond == SINGLE)
874 buf[0] |= (0 << 1) | (1 << 0);
875 else if (cond == BURST)
876 buf[0] |= (1 << 1) | (1 << 0);
877
878 PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n",
879 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
880
881 return SZ_DMAST;
882}
883
884static inline u32 _emit_STP(unsigned dry_run, u8 buf[],
885 enum pl330_cond cond, u8 peri)
886{
887 if (dry_run)
888 return SZ_DMASTP;
889
890 buf[0] = CMD_DMASTP;
891
892 if (cond == BURST)
893 buf[0] |= (1 << 1);
894
895 peri &= 0x1f;
896 peri <<= 3;
897 buf[1] = peri;
898
899 PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n",
900 cond == SINGLE ? 'S' : 'B', peri >> 3);
901
902 return SZ_DMASTP;
903}
904
905static inline u32 _emit_STZ(unsigned dry_run, u8 buf[])
906{
907 if (dry_run)
908 return SZ_DMASTZ;
909
910 buf[0] = CMD_DMASTZ;
911
912 PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n");
913
914 return SZ_DMASTZ;
915}
916
917static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev,
918 unsigned invalidate)
919{
920 if (dry_run)
921 return SZ_DMAWFE;
922
923 buf[0] = CMD_DMAWFE;
924
925 ev &= 0x1f;
926 ev <<= 3;
927 buf[1] = ev;
928
929 if (invalidate)
930 buf[1] |= (1 << 1);
931
932 PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n",
933 ev >> 3, invalidate ? ", I" : "");
934
935 return SZ_DMAWFE;
936}
937
938static inline u32 _emit_WFP(unsigned dry_run, u8 buf[],
939 enum pl330_cond cond, u8 peri)
940{
941 if (dry_run)
942 return SZ_DMAWFP;
943
944 buf[0] = CMD_DMAWFP;
945
946 if (cond == SINGLE)
947 buf[0] |= (0 << 1) | (0 << 0);
948 else if (cond == BURST)
949 buf[0] |= (1 << 1) | (0 << 0);
950 else
951 buf[0] |= (0 << 1) | (1 << 0);
952
953 peri &= 0x1f;
954 peri <<= 3;
955 buf[1] = peri;
956
957 PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n",
958 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3);
959
960 return SZ_DMAWFP;
961}
962
963static inline u32 _emit_WMB(unsigned dry_run, u8 buf[])
964{
965 if (dry_run)
966 return SZ_DMAWMB;
967
968 buf[0] = CMD_DMAWMB;
969
970 PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n");
971
972 return SZ_DMAWMB;
973}
974
975struct _arg_GO {
976 u8 chan;
977 u32 addr;
978 unsigned ns;
979};
980
981static inline u32 _emit_GO(unsigned dry_run, u8 buf[],
982 const struct _arg_GO *arg)
983{
984 u8 chan = arg->chan;
985 u32 addr = arg->addr;
986 unsigned ns = arg->ns;
987
988 if (dry_run)
989 return SZ_DMAGO;
990
991 buf[0] = CMD_DMAGO;
992 buf[0] |= (ns << 1);
993
994 buf[1] = chan & 0x7;
995
996 *((u32 *)&buf[2]) = addr;
997
998 return SZ_DMAGO;
999}
1000
1001#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
1002
1003/* Returns Time-Out */
1004static bool _until_dmac_idle(struct pl330_thread *thrd)
1005{
1006 void __iomem *regs = thrd->dmac->pinfo->base;
1007 unsigned long loops = msecs_to_loops(5);
1008
1009 do {
1010 /* Until Manager is Idle */
1011 if (!(readl(regs + DBGSTATUS) & DBG_BUSY))
1012 break;
1013
1014 cpu_relax();
1015 } while (--loops);
1016
1017 if (!loops)
1018 return true;
1019
1020 return false;
1021}
1022
1023static inline void _execute_DBGINSN(struct pl330_thread *thrd,
1024 u8 insn[], bool as_manager)
1025{
1026 void __iomem *regs = thrd->dmac->pinfo->base;
1027 u32 val;
1028
1029 val = (insn[0] << 16) | (insn[1] << 24);
1030 if (!as_manager) {
1031 val |= (1 << 0);
1032 val |= (thrd->id << 8); /* Channel Number */
1033 }
1034 writel(val, regs + DBGINST0);
1035
1036 val = *((u32 *)&insn[2]);
1037 writel(val, regs + DBGINST1);
1038
1039 /* If timed out due to halted state-machine */
1040 if (_until_dmac_idle(thrd)) {
1041 dev_err(thrd->dmac->pinfo->dev, "DMAC halted!\n");
1042 return;
1043 }
1044
1045 /* Get going */
1046 writel(0, regs + DBGCMD);
1047}
1048
1049/*
1050 * Mark a _pl330_req as free.
1051 * We do it by writing DMAEND as the first instruction
1052 * because no valid request is going to have DMAEND as
1053 * its first instruction to execute.
1054 */
1055static void mark_free(struct pl330_thread *thrd, int idx)
1056{
1057 struct _pl330_req *req = &thrd->req[idx];
1058
1059 _emit_END(0, req->mc_cpu);
1060 req->mc_len = 0;
1061
1062 thrd->req_running = -1;
1063}
1064
1065static inline u32 _state(struct pl330_thread *thrd)
1066{
1067 void __iomem *regs = thrd->dmac->pinfo->base;
1068 u32 val;
1069
1070 if (is_manager(thrd))
1071 val = readl(regs + DS) & 0xf;
1072 else
1073 val = readl(regs + CS(thrd->id)) & 0xf;
1074
1075 switch (val) {
1076 case DS_ST_STOP:
1077 return PL330_STATE_STOPPED;
1078 case DS_ST_EXEC:
1079 return PL330_STATE_EXECUTING;
1080 case DS_ST_CMISS:
1081 return PL330_STATE_CACHEMISS;
1082 case DS_ST_UPDTPC:
1083 return PL330_STATE_UPDTPC;
1084 case DS_ST_WFE:
1085 return PL330_STATE_WFE;
1086 case DS_ST_FAULT:
1087 return PL330_STATE_FAULTING;
1088 case DS_ST_ATBRR:
1089 if (is_manager(thrd))
1090 return PL330_STATE_INVALID;
1091 else
1092 return PL330_STATE_ATBARRIER;
1093 case DS_ST_QBUSY:
1094 if (is_manager(thrd))
1095 return PL330_STATE_INVALID;
1096 else
1097 return PL330_STATE_QUEUEBUSY;
1098 case DS_ST_WFP:
1099 if (is_manager(thrd))
1100 return PL330_STATE_INVALID;
1101 else
1102 return PL330_STATE_WFP;
1103 case DS_ST_KILL:
1104 if (is_manager(thrd))
1105 return PL330_STATE_INVALID;
1106 else
1107 return PL330_STATE_KILLING;
1108 case DS_ST_CMPLT:
1109 if (is_manager(thrd))
1110 return PL330_STATE_INVALID;
1111 else
1112 return PL330_STATE_COMPLETING;
1113 case DS_ST_FLTCMP:
1114 if (is_manager(thrd))
1115 return PL330_STATE_INVALID;
1116 else
1117 return PL330_STATE_FAULT_COMPLETING;
1118 default:
1119 return PL330_STATE_INVALID;
1120 }
1121}
1122
1123static void _stop(struct pl330_thread *thrd)
1124{
1125 void __iomem *regs = thrd->dmac->pinfo->base;
1126 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1127
1128 if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
1129 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1130
1131 /* Return if nothing needs to be done */
1132 if (_state(thrd) == PL330_STATE_COMPLETING
1133 || _state(thrd) == PL330_STATE_KILLING
1134 || _state(thrd) == PL330_STATE_STOPPED)
1135 return;
1136
1137 _emit_KILL(0, insn);
1138
1139 /* Stop generating interrupts for SEV */
1140 writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN);
1141
1142 _execute_DBGINSN(thrd, insn, is_manager(thrd));
1143}
1144
1145/* Start doing req 'idx' of thread 'thrd' */
1146static bool _trigger(struct pl330_thread *thrd)
1147{
1148 void __iomem *regs = thrd->dmac->pinfo->base;
1149 struct _pl330_req *req;
1150 struct pl330_req *r;
1151 struct _arg_GO go;
1152 unsigned ns;
1153 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1154 int idx;
1155
1156 /* Return if already ACTIVE */
1157 if (_state(thrd) != PL330_STATE_STOPPED)
1158 return true;
1159
1160 idx = 1 - thrd->lstenq;
1161 if (!IS_FREE(&thrd->req[idx]))
1162 req = &thrd->req[idx];
1163 else {
1164 idx = thrd->lstenq;
1165 if (!IS_FREE(&thrd->req[idx]))
1166 req = &thrd->req[idx];
1167 else
1168 req = NULL;
1169 }
1170
1171 /* Return if no request */
1172 if (!req || !req->r)
1173 return true;
1174
1175 r = req->r;
1176
1177 if (r->cfg)
1178 ns = r->cfg->nonsecure ? 1 : 0;
1179 else if (readl(regs + CS(thrd->id)) & CS_CNS)
1180 ns = 1;
1181 else
1182 ns = 0;
1183
1184 /* See 'Abort Sources' point-4 at Page 2-25 */
1185 if (_manager_ns(thrd) && !ns)
1186 dev_info(thrd->dmac->pinfo->dev, "%s:%d Recipe for ABORT!\n",
1187 __func__, __LINE__);
1188
1189 go.chan = thrd->id;
1190 go.addr = req->mc_bus;
1191 go.ns = ns;
1192 _emit_GO(0, insn, &go);
1193
1194 /* Set to generate interrupts for SEV */
1195 writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN);
1196
1197 /* Only manager can execute GO */
1198 _execute_DBGINSN(thrd, insn, true);
1199
1200 thrd->req_running = idx;
1201
1202 return true;
1203}
1204
1205static bool _start(struct pl330_thread *thrd)
1206{
1207 switch (_state(thrd)) {
1208 case PL330_STATE_FAULT_COMPLETING:
1209 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1210
1211 if (_state(thrd) == PL330_STATE_KILLING)
1212 UNTIL(thrd, PL330_STATE_STOPPED)
1213
1214 case PL330_STATE_FAULTING:
1215 _stop(thrd);
1216
1217 case PL330_STATE_KILLING:
1218 case PL330_STATE_COMPLETING:
1219 UNTIL(thrd, PL330_STATE_STOPPED)
1220
1221 case PL330_STATE_STOPPED:
1222 return _trigger(thrd);
1223
1224 case PL330_STATE_WFP:
1225 case PL330_STATE_QUEUEBUSY:
1226 case PL330_STATE_ATBARRIER:
1227 case PL330_STATE_UPDTPC:
1228 case PL330_STATE_CACHEMISS:
1229 case PL330_STATE_EXECUTING:
1230 return true;
1231
1232 case PL330_STATE_WFE: /* For RESUME, nothing yet */
1233 default:
1234 return false;
1235 }
1236}
1237
1238static inline int _ldst_memtomem(unsigned dry_run, u8 buf[],
1239 const struct _xfer_spec *pxs, int cyc)
1240{
1241 int off = 0;
Boojin Kim3ecf51a2011-12-26 18:55:47 +09001242 struct pl330_config *pcfg = pxs->r->cfg->pcfg;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001243
Boojin Kim3ecf51a2011-12-26 18:55:47 +09001244 /* check lock-up free version */
1245 if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) {
1246 while (cyc--) {
1247 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1248 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1249 }
1250 } else {
1251 while (cyc--) {
1252 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1253 off += _emit_RMB(dry_run, &buf[off]);
1254 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1255 off += _emit_WMB(dry_run, &buf[off]);
1256 }
Boojin Kimb7d861d2011-12-26 18:49:52 +09001257 }
1258
1259 return off;
1260}
1261
1262static inline int _ldst_devtomem(unsigned dry_run, u8 buf[],
1263 const struct _xfer_spec *pxs, int cyc)
1264{
1265 int off = 0;
1266
1267 while (cyc--) {
1268 off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->r->peri);
1269 off += _emit_LDP(dry_run, &buf[off], SINGLE, pxs->r->peri);
1270 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1271 off += _emit_FLUSHP(dry_run, &buf[off], pxs->r->peri);
1272 }
1273
1274 return off;
1275}
1276
1277static inline int _ldst_memtodev(unsigned dry_run, u8 buf[],
1278 const struct _xfer_spec *pxs, int cyc)
1279{
1280 int off = 0;
1281
1282 while (cyc--) {
1283 off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->r->peri);
1284 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1285 off += _emit_STP(dry_run, &buf[off], SINGLE, pxs->r->peri);
1286 off += _emit_FLUSHP(dry_run, &buf[off], pxs->r->peri);
1287 }
1288
1289 return off;
1290}
1291
1292static int _bursts(unsigned dry_run, u8 buf[],
1293 const struct _xfer_spec *pxs, int cyc)
1294{
1295 int off = 0;
1296
1297 switch (pxs->r->rqtype) {
1298 case MEMTODEV:
1299 off += _ldst_memtodev(dry_run, &buf[off], pxs, cyc);
1300 break;
1301 case DEVTOMEM:
1302 off += _ldst_devtomem(dry_run, &buf[off], pxs, cyc);
1303 break;
1304 case MEMTOMEM:
1305 off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
1306 break;
1307 default:
1308 off += 0x40000000; /* Scare off the Client */
1309 break;
1310 }
1311
1312 return off;
1313}
1314
1315/* Returns bytes consumed and updates bursts */
1316static inline int _loop(unsigned dry_run, u8 buf[],
1317 unsigned long *bursts, const struct _xfer_spec *pxs)
1318{
1319 int cyc, cycmax, szlp, szlpend, szbrst, off;
1320 unsigned lcnt0, lcnt1, ljmp0, ljmp1;
1321 struct _arg_LPEND lpend;
1322
1323 /* Max iterations possible in DMALP is 256 */
1324 if (*bursts >= 256*256) {
1325 lcnt1 = 256;
1326 lcnt0 = 256;
1327 cyc = *bursts / lcnt1 / lcnt0;
1328 } else if (*bursts > 256) {
1329 lcnt1 = 256;
1330 lcnt0 = *bursts / lcnt1;
1331 cyc = 1;
1332 } else {
1333 lcnt1 = *bursts;
1334 lcnt0 = 0;
1335 cyc = 1;
1336 }
1337
1338 szlp = _emit_LP(1, buf, 0, 0);
1339 szbrst = _bursts(1, buf, pxs, 1);
1340
1341 lpend.cond = ALWAYS;
1342 lpend.forever = false;
1343 lpend.loop = 0;
1344 lpend.bjump = 0;
1345 szlpend = _emit_LPEND(1, buf, &lpend);
1346
1347 if (lcnt0) {
1348 szlp *= 2;
1349 szlpend *= 2;
1350 }
1351
1352 /*
1353 * Max bursts that we can unroll due to limit on the
1354 * size of backward jump that can be encoded in DMALPEND
1355 * which is 8-bits and hence 255
1356 */
1357 cycmax = (255 - (szlp + szlpend)) / szbrst;
1358
1359 cyc = (cycmax < cyc) ? cycmax : cyc;
1360
1361 off = 0;
1362
1363 if (lcnt0) {
1364 off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
1365 ljmp0 = off;
1366 }
1367
1368 off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
1369 ljmp1 = off;
1370
1371 off += _bursts(dry_run, &buf[off], pxs, cyc);
1372
1373 lpend.cond = ALWAYS;
1374 lpend.forever = false;
1375 lpend.loop = 1;
1376 lpend.bjump = off - ljmp1;
1377 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1378
1379 if (lcnt0) {
1380 lpend.cond = ALWAYS;
1381 lpend.forever = false;
1382 lpend.loop = 0;
1383 lpend.bjump = off - ljmp0;
1384 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1385 }
1386
1387 *bursts = lcnt1 * cyc;
1388 if (lcnt0)
1389 *bursts *= lcnt0;
1390
1391 return off;
1392}
1393
1394static inline int _setup_loops(unsigned dry_run, u8 buf[],
1395 const struct _xfer_spec *pxs)
1396{
1397 struct pl330_xfer *x = pxs->x;
1398 u32 ccr = pxs->ccr;
1399 unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr);
1400 int off = 0;
1401
1402 while (bursts) {
1403 c = bursts;
1404 off += _loop(dry_run, &buf[off], &c, pxs);
1405 bursts -= c;
1406 }
1407
1408 return off;
1409}
1410
1411static inline int _setup_xfer(unsigned dry_run, u8 buf[],
1412 const struct _xfer_spec *pxs)
1413{
1414 struct pl330_xfer *x = pxs->x;
1415 int off = 0;
1416
1417 /* DMAMOV SAR, x->src_addr */
1418 off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
1419 /* DMAMOV DAR, x->dst_addr */
1420 off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
1421
1422 /* Setup Loop(s) */
1423 off += _setup_loops(dry_run, &buf[off], pxs);
1424
1425 return off;
1426}
1427
1428/*
1429 * A req is a sequence of one or more xfer units.
1430 * Returns the number of bytes taken to setup the MC for the req.
1431 */
1432static int _setup_req(unsigned dry_run, struct pl330_thread *thrd,
1433 unsigned index, struct _xfer_spec *pxs)
1434{
1435 struct _pl330_req *req = &thrd->req[index];
1436 struct pl330_xfer *x;
1437 u8 *buf = req->mc_cpu;
1438 int off = 0;
1439
1440 PL330_DBGMC_START(req->mc_bus);
1441
1442 /* DMAMOV CCR, ccr */
1443 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
1444
1445 x = pxs->r->x;
1446 do {
1447 /* Error if xfer length is not aligned at burst size */
1448 if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr)))
1449 return -EINVAL;
1450
1451 pxs->x = x;
1452 off += _setup_xfer(dry_run, &buf[off], pxs);
1453
1454 x = x->next;
1455 } while (x);
1456
1457 /* DMASEV peripheral/event */
1458 off += _emit_SEV(dry_run, &buf[off], thrd->ev);
1459 /* DMAEND */
1460 off += _emit_END(dry_run, &buf[off]);
1461
1462 return off;
1463}
1464
1465static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
1466{
1467 u32 ccr = 0;
1468
1469 if (rqc->src_inc)
1470 ccr |= CC_SRCINC;
1471
1472 if (rqc->dst_inc)
1473 ccr |= CC_DSTINC;
1474
1475 /* We set same protection levels for Src and DST for now */
1476 if (rqc->privileged)
1477 ccr |= CC_SRCPRI | CC_DSTPRI;
1478 if (rqc->nonsecure)
1479 ccr |= CC_SRCNS | CC_DSTNS;
1480 if (rqc->insnaccess)
1481 ccr |= CC_SRCIA | CC_DSTIA;
1482
1483 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT);
1484 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT);
1485
1486 ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
1487 ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
1488
1489 ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
1490 ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
1491
1492 ccr |= (rqc->swap << CC_SWAP_SHFT);
1493
1494 return ccr;
1495}
1496
1497static inline bool _is_valid(u32 ccr)
1498{
1499 enum pl330_dstcachectrl dcctl;
1500 enum pl330_srccachectrl scctl;
1501
1502 dcctl = (ccr >> CC_DSTCCTRL_SHFT) & CC_DRCCCTRL_MASK;
1503 scctl = (ccr >> CC_SRCCCTRL_SHFT) & CC_SRCCCTRL_MASK;
1504
1505 if (dcctl == DINVALID1 || dcctl == DINVALID2
1506 || scctl == SINVALID1 || scctl == SINVALID2)
1507 return false;
1508 else
1509 return true;
1510}
1511
1512/*
1513 * Submit a list of xfers after which the client wants notification.
1514 * Client is not notified after each xfer unit, just once after all
1515 * xfer units are done or some error occurs.
1516 */
1517static int pl330_submit_req(void *ch_id, struct pl330_req *r)
1518{
1519 struct pl330_thread *thrd = ch_id;
1520 struct pl330_dmac *pl330;
1521 struct pl330_info *pi;
1522 struct _xfer_spec xs;
1523 unsigned long flags;
1524 void __iomem *regs;
1525 unsigned idx;
1526 u32 ccr;
1527 int ret = 0;
1528
1529 /* No Req or Unacquired Channel or DMAC */
1530 if (!r || !thrd || thrd->free)
1531 return -EINVAL;
1532
1533 pl330 = thrd->dmac;
1534 pi = pl330->pinfo;
1535 regs = pi->base;
1536
1537 if (pl330->state == DYING
1538 || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) {
1539 dev_info(thrd->dmac->pinfo->dev, "%s:%d\n",
1540 __func__, __LINE__);
1541 return -EAGAIN;
1542 }
1543
1544 /* If request for non-existing peripheral */
1545 if (r->rqtype != MEMTOMEM && r->peri >= pi->pcfg.num_peri) {
1546 dev_info(thrd->dmac->pinfo->dev,
1547 "%s:%d Invalid peripheral(%u)!\n",
1548 __func__, __LINE__, r->peri);
1549 return -EINVAL;
1550 }
1551
1552 spin_lock_irqsave(&pl330->lock, flags);
1553
1554 if (_queue_full(thrd)) {
1555 ret = -EAGAIN;
1556 goto xfer_exit;
1557 }
1558
Boojin Kimb7d861d2011-12-26 18:49:52 +09001559
1560 /* Use last settings, if not provided */
Sachin Kamat2e2c6822012-09-17 15:20:22 +05301561 if (r->cfg) {
1562 /* Prefer Secure Channel */
1563 if (!_manager_ns(thrd))
1564 r->cfg->nonsecure = 0;
1565 else
1566 r->cfg->nonsecure = 1;
1567
Boojin Kimb7d861d2011-12-26 18:49:52 +09001568 ccr = _prepare_ccr(r->cfg);
Sachin Kamat2e2c6822012-09-17 15:20:22 +05301569 } else {
Boojin Kimb7d861d2011-12-26 18:49:52 +09001570 ccr = readl(regs + CC(thrd->id));
Sachin Kamat2e2c6822012-09-17 15:20:22 +05301571 }
Boojin Kimb7d861d2011-12-26 18:49:52 +09001572
1573 /* If this req doesn't have valid xfer settings */
1574 if (!_is_valid(ccr)) {
1575 ret = -EINVAL;
1576 dev_info(thrd->dmac->pinfo->dev, "%s:%d Invalid CCR(%x)!\n",
1577 __func__, __LINE__, ccr);
1578 goto xfer_exit;
1579 }
1580
1581 idx = IS_FREE(&thrd->req[0]) ? 0 : 1;
1582
1583 xs.ccr = ccr;
1584 xs.r = r;
1585
1586 /* First dry run to check if req is acceptable */
1587 ret = _setup_req(1, thrd, idx, &xs);
1588 if (ret < 0)
1589 goto xfer_exit;
1590
1591 if (ret > pi->mcbufsz / 2) {
1592 dev_info(thrd->dmac->pinfo->dev,
1593 "%s:%d Trying increasing mcbufsz\n",
1594 __func__, __LINE__);
1595 ret = -ENOMEM;
1596 goto xfer_exit;
1597 }
1598
1599 /* Hook the request */
1600 thrd->lstenq = idx;
1601 thrd->req[idx].mc_len = _setup_req(0, thrd, idx, &xs);
1602 thrd->req[idx].r = r;
1603
1604 ret = 0;
1605
1606xfer_exit:
1607 spin_unlock_irqrestore(&pl330->lock, flags);
1608
1609 return ret;
1610}
1611
1612static void pl330_dotask(unsigned long data)
1613{
1614 struct pl330_dmac *pl330 = (struct pl330_dmac *) data;
1615 struct pl330_info *pi = pl330->pinfo;
1616 unsigned long flags;
1617 int i;
1618
1619 spin_lock_irqsave(&pl330->lock, flags);
1620
1621 /* The DMAC itself gone nuts */
1622 if (pl330->dmac_tbd.reset_dmac) {
1623 pl330->state = DYING;
1624 /* Reset the manager too */
1625 pl330->dmac_tbd.reset_mngr = true;
1626 /* Clear the reset flag */
1627 pl330->dmac_tbd.reset_dmac = false;
1628 }
1629
1630 if (pl330->dmac_tbd.reset_mngr) {
1631 _stop(pl330->manager);
1632 /* Reset all channels */
1633 pl330->dmac_tbd.reset_chan = (1 << pi->pcfg.num_chan) - 1;
1634 /* Clear the reset flag */
1635 pl330->dmac_tbd.reset_mngr = false;
1636 }
1637
1638 for (i = 0; i < pi->pcfg.num_chan; i++) {
1639
1640 if (pl330->dmac_tbd.reset_chan & (1 << i)) {
1641 struct pl330_thread *thrd = &pl330->channels[i];
1642 void __iomem *regs = pi->base;
1643 enum pl330_op_err err;
1644
1645 _stop(thrd);
1646
1647 if (readl(regs + FSC) & (1 << thrd->id))
1648 err = PL330_ERR_FAIL;
1649 else
1650 err = PL330_ERR_ABORT;
1651
1652 spin_unlock_irqrestore(&pl330->lock, flags);
1653
1654 _callback(thrd->req[1 - thrd->lstenq].r, err);
1655 _callback(thrd->req[thrd->lstenq].r, err);
1656
1657 spin_lock_irqsave(&pl330->lock, flags);
1658
1659 thrd->req[0].r = NULL;
1660 thrd->req[1].r = NULL;
1661 mark_free(thrd, 0);
1662 mark_free(thrd, 1);
1663
1664 /* Clear the reset flag */
1665 pl330->dmac_tbd.reset_chan &= ~(1 << i);
1666 }
1667 }
1668
1669 spin_unlock_irqrestore(&pl330->lock, flags);
1670
1671 return;
1672}
1673
1674/* Returns 1 if state was updated, 0 otherwise */
1675static int pl330_update(const struct pl330_info *pi)
1676{
Javi Merinofdec53d2012-06-13 15:07:00 +01001677 struct pl330_req *rqdone, *tmp;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001678 struct pl330_dmac *pl330;
1679 unsigned long flags;
1680 void __iomem *regs;
1681 u32 val;
1682 int id, ev, ret = 0;
1683
1684 if (!pi || !pi->pl330_data)
1685 return 0;
1686
1687 regs = pi->base;
1688 pl330 = pi->pl330_data;
1689
1690 spin_lock_irqsave(&pl330->lock, flags);
1691
1692 val = readl(regs + FSM) & 0x1;
1693 if (val)
1694 pl330->dmac_tbd.reset_mngr = true;
1695 else
1696 pl330->dmac_tbd.reset_mngr = false;
1697
1698 val = readl(regs + FSC) & ((1 << pi->pcfg.num_chan) - 1);
1699 pl330->dmac_tbd.reset_chan |= val;
1700 if (val) {
1701 int i = 0;
1702 while (i < pi->pcfg.num_chan) {
1703 if (val & (1 << i)) {
1704 dev_info(pi->dev,
1705 "Reset Channel-%d\t CS-%x FTC-%x\n",
1706 i, readl(regs + CS(i)),
1707 readl(regs + FTC(i)));
1708 _stop(&pl330->channels[i]);
1709 }
1710 i++;
1711 }
1712 }
1713
1714 /* Check which event happened i.e, thread notified */
1715 val = readl(regs + ES);
1716 if (pi->pcfg.num_events < 32
1717 && val & ~((1 << pi->pcfg.num_events) - 1)) {
1718 pl330->dmac_tbd.reset_dmac = true;
1719 dev_err(pi->dev, "%s:%d Unexpected!\n", __func__, __LINE__);
1720 ret = 1;
1721 goto updt_exit;
1722 }
1723
1724 for (ev = 0; ev < pi->pcfg.num_events; ev++) {
1725 if (val & (1 << ev)) { /* Event occurred */
1726 struct pl330_thread *thrd;
1727 u32 inten = readl(regs + INTEN);
1728 int active;
1729
1730 /* Clear the event */
1731 if (inten & (1 << ev))
1732 writel(1 << ev, regs + INTCLR);
1733
1734 ret = 1;
1735
1736 id = pl330->events[ev];
1737
1738 thrd = &pl330->channels[id];
1739
1740 active = thrd->req_running;
1741 if (active == -1) /* Aborted */
1742 continue;
1743
Javi Merinofdec53d2012-06-13 15:07:00 +01001744 /* Detach the req */
1745 rqdone = thrd->req[active].r;
1746 thrd->req[active].r = NULL;
1747
Boojin Kimb7d861d2011-12-26 18:49:52 +09001748 mark_free(thrd, active);
1749
1750 /* Get going again ASAP */
1751 _start(thrd);
1752
1753 /* For now, just make a list of callbacks to be done */
1754 list_add_tail(&rqdone->rqd, &pl330->req_done);
1755 }
1756 }
1757
1758 /* Now that we are in no hurry, do the callbacks */
Javi Merinofdec53d2012-06-13 15:07:00 +01001759 list_for_each_entry_safe(rqdone, tmp, &pl330->req_done, rqd) {
1760 list_del(&rqdone->rqd);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001761
1762 spin_unlock_irqrestore(&pl330->lock, flags);
Javi Merinofdec53d2012-06-13 15:07:00 +01001763 _callback(rqdone, PL330_ERR_NONE);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001764 spin_lock_irqsave(&pl330->lock, flags);
1765 }
1766
1767updt_exit:
1768 spin_unlock_irqrestore(&pl330->lock, flags);
1769
1770 if (pl330->dmac_tbd.reset_dmac
1771 || pl330->dmac_tbd.reset_mngr
1772 || pl330->dmac_tbd.reset_chan) {
1773 ret = 1;
1774 tasklet_schedule(&pl330->tasks);
1775 }
1776
1777 return ret;
1778}
1779
1780static int pl330_chan_ctrl(void *ch_id, enum pl330_chan_op op)
1781{
1782 struct pl330_thread *thrd = ch_id;
1783 struct pl330_dmac *pl330;
1784 unsigned long flags;
Linus Torvaldsef08e782012-03-29 15:34:57 -07001785 int ret = 0, active;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001786
1787 if (!thrd || thrd->free || thrd->dmac->state == DYING)
1788 return -EINVAL;
1789
1790 pl330 = thrd->dmac;
Linus Torvaldsef08e782012-03-29 15:34:57 -07001791 active = thrd->req_running;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001792
1793 spin_lock_irqsave(&pl330->lock, flags);
1794
1795 switch (op) {
1796 case PL330_OP_FLUSH:
1797 /* Make sure the channel is stopped */
1798 _stop(thrd);
1799
1800 thrd->req[0].r = NULL;
1801 thrd->req[1].r = NULL;
1802 mark_free(thrd, 0);
1803 mark_free(thrd, 1);
1804 break;
1805
1806 case PL330_OP_ABORT:
1807 /* Make sure the channel is stopped */
1808 _stop(thrd);
1809
1810 /* ABORT is only for the active req */
1811 if (active == -1)
1812 break;
1813
1814 thrd->req[active].r = NULL;
1815 mark_free(thrd, active);
1816
1817 /* Start the next */
1818 case PL330_OP_START:
1819 if ((active == -1) && !_start(thrd))
1820 ret = -EIO;
1821 break;
1822
1823 default:
1824 ret = -EINVAL;
1825 }
1826
1827 spin_unlock_irqrestore(&pl330->lock, flags);
1828 return ret;
1829}
1830
Boojin Kimb7d861d2011-12-26 18:49:52 +09001831/* Reserve an event */
1832static inline int _alloc_event(struct pl330_thread *thrd)
1833{
1834 struct pl330_dmac *pl330 = thrd->dmac;
1835 struct pl330_info *pi = pl330->pinfo;
1836 int ev;
1837
1838 for (ev = 0; ev < pi->pcfg.num_events; ev++)
1839 if (pl330->events[ev] == -1) {
1840 pl330->events[ev] = thrd->id;
1841 return ev;
1842 }
1843
1844 return -1;
1845}
1846
1847static bool _chan_ns(const struct pl330_info *pi, int i)
1848{
1849 return pi->pcfg.irq_ns & (1 << i);
1850}
1851
1852/* Upon success, returns IdentityToken for the
1853 * allocated channel, NULL otherwise.
1854 */
1855static void *pl330_request_channel(const struct pl330_info *pi)
1856{
1857 struct pl330_thread *thrd = NULL;
1858 struct pl330_dmac *pl330;
1859 unsigned long flags;
1860 int chans, i;
1861
1862 if (!pi || !pi->pl330_data)
1863 return NULL;
1864
1865 pl330 = pi->pl330_data;
1866
1867 if (pl330->state == DYING)
1868 return NULL;
1869
1870 chans = pi->pcfg.num_chan;
1871
1872 spin_lock_irqsave(&pl330->lock, flags);
1873
1874 for (i = 0; i < chans; i++) {
1875 thrd = &pl330->channels[i];
1876 if ((thrd->free) && (!_manager_ns(thrd) ||
1877 _chan_ns(pi, i))) {
1878 thrd->ev = _alloc_event(thrd);
1879 if (thrd->ev >= 0) {
1880 thrd->free = false;
1881 thrd->lstenq = 1;
1882 thrd->req[0].r = NULL;
1883 mark_free(thrd, 0);
1884 thrd->req[1].r = NULL;
1885 mark_free(thrd, 1);
1886 break;
1887 }
1888 }
1889 thrd = NULL;
1890 }
1891
1892 spin_unlock_irqrestore(&pl330->lock, flags);
1893
1894 return thrd;
1895}
1896
1897/* Release an event */
1898static inline void _free_event(struct pl330_thread *thrd, int ev)
1899{
1900 struct pl330_dmac *pl330 = thrd->dmac;
1901 struct pl330_info *pi = pl330->pinfo;
1902
1903 /* If the event is valid and was held by the thread */
1904 if (ev >= 0 && ev < pi->pcfg.num_events
1905 && pl330->events[ev] == thrd->id)
1906 pl330->events[ev] = -1;
1907}
1908
1909static void pl330_release_channel(void *ch_id)
1910{
1911 struct pl330_thread *thrd = ch_id;
1912 struct pl330_dmac *pl330;
1913 unsigned long flags;
1914
1915 if (!thrd || thrd->free)
1916 return;
1917
1918 _stop(thrd);
1919
1920 _callback(thrd->req[1 - thrd->lstenq].r, PL330_ERR_ABORT);
1921 _callback(thrd->req[thrd->lstenq].r, PL330_ERR_ABORT);
1922
1923 pl330 = thrd->dmac;
1924
1925 spin_lock_irqsave(&pl330->lock, flags);
1926 _free_event(thrd, thrd->ev);
1927 thrd->free = true;
1928 spin_unlock_irqrestore(&pl330->lock, flags);
1929}
1930
1931/* Initialize the structure for PL330 configuration, that can be used
1932 * by the client driver the make best use of the DMAC
1933 */
1934static void read_dmac_config(struct pl330_info *pi)
1935{
1936 void __iomem *regs = pi->base;
1937 u32 val;
1938
1939 val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
1940 val &= CRD_DATA_WIDTH_MASK;
1941 pi->pcfg.data_bus_width = 8 * (1 << val);
1942
1943 val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
1944 val &= CRD_DATA_BUFF_MASK;
1945 pi->pcfg.data_buf_dep = val + 1;
1946
1947 val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
1948 val &= CR0_NUM_CHANS_MASK;
1949 val += 1;
1950 pi->pcfg.num_chan = val;
1951
1952 val = readl(regs + CR0);
1953 if (val & CR0_PERIPH_REQ_SET) {
1954 val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
1955 val += 1;
1956 pi->pcfg.num_peri = val;
1957 pi->pcfg.peri_ns = readl(regs + CR4);
1958 } else {
1959 pi->pcfg.num_peri = 0;
1960 }
1961
1962 val = readl(regs + CR0);
1963 if (val & CR0_BOOT_MAN_NS)
1964 pi->pcfg.mode |= DMAC_MODE_NS;
1965 else
1966 pi->pcfg.mode &= ~DMAC_MODE_NS;
1967
1968 val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
1969 val &= CR0_NUM_EVENTS_MASK;
1970 val += 1;
1971 pi->pcfg.num_events = val;
1972
1973 pi->pcfg.irq_ns = readl(regs + CR3);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001974}
1975
1976static inline void _reset_thread(struct pl330_thread *thrd)
1977{
1978 struct pl330_dmac *pl330 = thrd->dmac;
1979 struct pl330_info *pi = pl330->pinfo;
1980
1981 thrd->req[0].mc_cpu = pl330->mcode_cpu
1982 + (thrd->id * pi->mcbufsz);
1983 thrd->req[0].mc_bus = pl330->mcode_bus
1984 + (thrd->id * pi->mcbufsz);
1985 thrd->req[0].r = NULL;
1986 mark_free(thrd, 0);
1987
1988 thrd->req[1].mc_cpu = thrd->req[0].mc_cpu
1989 + pi->mcbufsz / 2;
1990 thrd->req[1].mc_bus = thrd->req[0].mc_bus
1991 + pi->mcbufsz / 2;
1992 thrd->req[1].r = NULL;
1993 mark_free(thrd, 1);
1994}
1995
1996static int dmac_alloc_threads(struct pl330_dmac *pl330)
1997{
1998 struct pl330_info *pi = pl330->pinfo;
1999 int chans = pi->pcfg.num_chan;
2000 struct pl330_thread *thrd;
2001 int i;
2002
2003 /* Allocate 1 Manager and 'chans' Channel threads */
2004 pl330->channels = kzalloc((1 + chans) * sizeof(*thrd),
2005 GFP_KERNEL);
2006 if (!pl330->channels)
2007 return -ENOMEM;
2008
2009 /* Init Channel threads */
2010 for (i = 0; i < chans; i++) {
2011 thrd = &pl330->channels[i];
2012 thrd->id = i;
2013 thrd->dmac = pl330;
2014 _reset_thread(thrd);
2015 thrd->free = true;
2016 }
2017
2018 /* MANAGER is indexed at the end */
2019 thrd = &pl330->channels[chans];
2020 thrd->id = chans;
2021 thrd->dmac = pl330;
2022 thrd->free = false;
2023 pl330->manager = thrd;
2024
2025 return 0;
2026}
2027
2028static int dmac_alloc_resources(struct pl330_dmac *pl330)
2029{
2030 struct pl330_info *pi = pl330->pinfo;
2031 int chans = pi->pcfg.num_chan;
2032 int ret;
2033
2034 /*
2035 * Alloc MicroCode buffer for 'chans' Channel threads.
2036 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
2037 */
2038 pl330->mcode_cpu = dma_alloc_coherent(pi->dev,
2039 chans * pi->mcbufsz,
2040 &pl330->mcode_bus, GFP_KERNEL);
2041 if (!pl330->mcode_cpu) {
2042 dev_err(pi->dev, "%s:%d Can't allocate memory!\n",
2043 __func__, __LINE__);
2044 return -ENOMEM;
2045 }
2046
2047 ret = dmac_alloc_threads(pl330);
2048 if (ret) {
2049 dev_err(pi->dev, "%s:%d Can't to create channels for DMAC!\n",
2050 __func__, __LINE__);
2051 dma_free_coherent(pi->dev,
2052 chans * pi->mcbufsz,
2053 pl330->mcode_cpu, pl330->mcode_bus);
2054 return ret;
2055 }
2056
2057 return 0;
2058}
2059
2060static int pl330_add(struct pl330_info *pi)
2061{
2062 struct pl330_dmac *pl330;
2063 void __iomem *regs;
2064 int i, ret;
2065
2066 if (!pi || !pi->dev)
2067 return -EINVAL;
2068
2069 /* If already added */
2070 if (pi->pl330_data)
2071 return -EINVAL;
2072
2073 /*
2074 * If the SoC can perform reset on the DMAC, then do it
2075 * before reading its configuration.
2076 */
2077 if (pi->dmac_reset)
2078 pi->dmac_reset(pi);
2079
2080 regs = pi->base;
2081
2082 /* Check if we can handle this DMAC */
Will Deacon09677172013-06-10 19:34:37 +01002083 if ((pi->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) {
2084 dev_err(pi->dev, "PERIPH_ID 0x%x !\n", pi->pcfg.periph_id);
Boojin Kimb7d861d2011-12-26 18:49:52 +09002085 return -EINVAL;
2086 }
2087
2088 /* Read the configuration of the DMAC */
2089 read_dmac_config(pi);
2090
2091 if (pi->pcfg.num_events == 0) {
2092 dev_err(pi->dev, "%s:%d Can't work without events!\n",
2093 __func__, __LINE__);
2094 return -EINVAL;
2095 }
2096
2097 pl330 = kzalloc(sizeof(*pl330), GFP_KERNEL);
2098 if (!pl330) {
2099 dev_err(pi->dev, "%s:%d Can't allocate memory!\n",
2100 __func__, __LINE__);
2101 return -ENOMEM;
2102 }
2103
2104 /* Assign the info structure and private data */
2105 pl330->pinfo = pi;
2106 pi->pl330_data = pl330;
2107
2108 spin_lock_init(&pl330->lock);
2109
2110 INIT_LIST_HEAD(&pl330->req_done);
2111
2112 /* Use default MC buffer size if not provided */
2113 if (!pi->mcbufsz)
2114 pi->mcbufsz = MCODE_BUFF_PER_REQ * 2;
2115
2116 /* Mark all events as free */
2117 for (i = 0; i < pi->pcfg.num_events; i++)
2118 pl330->events[i] = -1;
2119
2120 /* Allocate resources needed by the DMAC */
2121 ret = dmac_alloc_resources(pl330);
2122 if (ret) {
2123 dev_err(pi->dev, "Unable to create channels for DMAC\n");
2124 kfree(pl330);
2125 return ret;
2126 }
2127
2128 tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330);
2129
2130 pl330->state = INIT;
2131
2132 return 0;
2133}
2134
2135static int dmac_free_threads(struct pl330_dmac *pl330)
2136{
2137 struct pl330_info *pi = pl330->pinfo;
2138 int chans = pi->pcfg.num_chan;
2139 struct pl330_thread *thrd;
2140 int i;
2141
2142 /* Release Channel threads */
2143 for (i = 0; i < chans; i++) {
2144 thrd = &pl330->channels[i];
2145 pl330_release_channel((void *)thrd);
2146 }
2147
2148 /* Free memory */
2149 kfree(pl330->channels);
2150
2151 return 0;
2152}
2153
2154static void dmac_free_resources(struct pl330_dmac *pl330)
2155{
2156 struct pl330_info *pi = pl330->pinfo;
2157 int chans = pi->pcfg.num_chan;
2158
2159 dmac_free_threads(pl330);
2160
2161 dma_free_coherent(pi->dev, chans * pi->mcbufsz,
2162 pl330->mcode_cpu, pl330->mcode_bus);
2163}
2164
2165static void pl330_del(struct pl330_info *pi)
2166{
2167 struct pl330_dmac *pl330;
2168
2169 if (!pi || !pi->pl330_data)
2170 return;
2171
2172 pl330 = pi->pl330_data;
2173
2174 pl330->state = UNINIT;
2175
2176 tasklet_kill(&pl330->tasks);
2177
2178 /* Free DMAC resources */
2179 dmac_free_resources(pl330);
2180
2181 kfree(pl330);
2182 pi->pl330_data = NULL;
2183}
2184
Thomas Abraham3e2ec132011-10-24 11:43:02 +02002185/* forward declaration */
2186static struct amba_driver pl330_driver;
2187
Jassi Brarb3040e42010-05-23 20:28:19 -07002188static inline struct dma_pl330_chan *
2189to_pchan(struct dma_chan *ch)
2190{
2191 if (!ch)
2192 return NULL;
2193
2194 return container_of(ch, struct dma_pl330_chan, chan);
2195}
2196
2197static inline struct dma_pl330_desc *
2198to_desc(struct dma_async_tx_descriptor *tx)
2199{
2200 return container_of(tx, struct dma_pl330_desc, txd);
2201}
2202
Jassi Brarb3040e42010-05-23 20:28:19 -07002203static inline void fill_queue(struct dma_pl330_chan *pch)
2204{
2205 struct dma_pl330_desc *desc;
2206 int ret;
2207
2208 list_for_each_entry(desc, &pch->work_list, node) {
2209
2210 /* If already submitted */
2211 if (desc->status == BUSY)
Jassi Brar30fb9802013-02-13 16:13:14 +05302212 continue;
Jassi Brarb3040e42010-05-23 20:28:19 -07002213
2214 ret = pl330_submit_req(pch->pl330_chid,
2215 &desc->req);
2216 if (!ret) {
2217 desc->status = BUSY;
Jassi Brarb3040e42010-05-23 20:28:19 -07002218 } else if (ret == -EAGAIN) {
2219 /* QFull or DMAC Dying */
2220 break;
2221 } else {
2222 /* Unacceptable request */
2223 desc->status = DONE;
2224 dev_err(pch->dmac->pif.dev, "%s:%d Bad Desc(%d)\n",
2225 __func__, __LINE__, desc->txd.cookie);
2226 tasklet_schedule(&pch->task);
2227 }
2228 }
2229}
2230
2231static void pl330_tasklet(unsigned long data)
2232{
2233 struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data;
2234 struct dma_pl330_desc *desc, *_dt;
2235 unsigned long flags;
Jassi Brarb3040e42010-05-23 20:28:19 -07002236
2237 spin_lock_irqsave(&pch->lock, flags);
2238
2239 /* Pick up ripe tomatoes */
2240 list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
2241 if (desc->status == DONE) {
Tushar Behera30c1dc02012-05-23 16:47:31 +05302242 if (!pch->cyclic)
Vinod Kouleab21582012-05-11 11:24:41 +05302243 dma_cookie_complete(&desc->txd);
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02002244 list_move_tail(&desc->node, &pch->completed_list);
Jassi Brarb3040e42010-05-23 20:28:19 -07002245 }
2246
2247 /* Try to submit a req imm. next to the last completed cookie */
2248 fill_queue(pch);
2249
2250 /* Make sure the PL330 Channel thread is active */
2251 pl330_chan_ctrl(pch->pl330_chid, PL330_OP_START);
2252
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02002253 while (!list_empty(&pch->completed_list)) {
2254 dma_async_tx_callback callback;
2255 void *callback_param;
Jassi Brarb3040e42010-05-23 20:28:19 -07002256
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02002257 desc = list_first_entry(&pch->completed_list,
2258 struct dma_pl330_desc, node);
2259
2260 callback = desc->txd.callback;
2261 callback_param = desc->txd.callback_param;
2262
2263 if (pch->cyclic) {
2264 desc->status = PREP;
2265 list_move_tail(&desc->node, &pch->work_list);
2266 } else {
2267 desc->status = FREE;
2268 list_move_tail(&desc->node, &pch->dmac->desc_pool);
2269 }
2270
Dan Williamsd38a8c62013-10-18 19:35:23 +02002271 dma_descriptor_unmap(&desc->txd);
2272
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02002273 if (callback) {
2274 spin_unlock_irqrestore(&pch->lock, flags);
2275 callback(callback_param);
2276 spin_lock_irqsave(&pch->lock, flags);
2277 }
2278 }
2279 spin_unlock_irqrestore(&pch->lock, flags);
Jassi Brarb3040e42010-05-23 20:28:19 -07002280}
2281
2282static void dma_pl330_rqcb(void *token, enum pl330_op_err err)
2283{
2284 struct dma_pl330_desc *desc = token;
2285 struct dma_pl330_chan *pch = desc->pchan;
2286 unsigned long flags;
2287
2288 /* If desc aborted */
2289 if (!pch)
2290 return;
2291
2292 spin_lock_irqsave(&pch->lock, flags);
2293
2294 desc->status = DONE;
2295
2296 spin_unlock_irqrestore(&pch->lock, flags);
2297
2298 tasklet_schedule(&pch->task);
2299}
2300
Padmavathi Venna34d19352013-02-14 09:10:05 +05302301static bool pl330_dt_filter(struct dma_chan *chan, void *param)
2302{
2303 struct dma_pl330_filter_args *fargs = param;
2304
2305 if (chan->device != &fargs->pdmac->ddma)
2306 return false;
2307
2308 return (chan->chan_id == fargs->chan_id);
2309}
2310
Thomas Abraham3e2ec132011-10-24 11:43:02 +02002311bool pl330_filter(struct dma_chan *chan, void *param)
2312{
Thomas Abrahamcd072512011-10-24 11:43:11 +02002313 u8 *peri_id;
Thomas Abraham3e2ec132011-10-24 11:43:02 +02002314
2315 if (chan->device->dev->driver != &pl330_driver.drv)
2316 return false;
2317
Thomas Abrahamcd072512011-10-24 11:43:11 +02002318 peri_id = chan->private;
Dan Carpenter2f986ec2013-11-08 12:51:16 +03002319 return *peri_id == (unsigned long)param;
Thomas Abraham3e2ec132011-10-24 11:43:02 +02002320}
2321EXPORT_SYMBOL(pl330_filter);
2322
Padmavathi Vennaa80258f2013-02-14 09:10:06 +05302323static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec,
2324 struct of_dma *ofdma)
2325{
2326 int count = dma_spec->args_count;
2327 struct dma_pl330_dmac *pdmac = ofdma->of_dma_data;
2328 struct dma_pl330_filter_args fargs;
2329 dma_cap_mask_t cap;
2330
2331 if (!pdmac)
2332 return NULL;
2333
2334 if (count != 1)
2335 return NULL;
2336
2337 fargs.pdmac = pdmac;
2338 fargs.chan_id = dma_spec->args[0];
2339
2340 dma_cap_zero(cap);
2341 dma_cap_set(DMA_SLAVE, cap);
2342 dma_cap_set(DMA_CYCLIC, cap);
2343
2344 return dma_request_channel(cap, pl330_dt_filter, &fargs);
2345}
2346
Jassi Brarb3040e42010-05-23 20:28:19 -07002347static int pl330_alloc_chan_resources(struct dma_chan *chan)
2348{
2349 struct dma_pl330_chan *pch = to_pchan(chan);
2350 struct dma_pl330_dmac *pdmac = pch->dmac;
2351 unsigned long flags;
2352
2353 spin_lock_irqsave(&pch->lock, flags);
2354
Russell King - ARM Linuxd3ee98cdc2012-03-06 22:35:47 +00002355 dma_cookie_init(chan);
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002356 pch->cyclic = false;
Jassi Brarb3040e42010-05-23 20:28:19 -07002357
2358 pch->pl330_chid = pl330_request_channel(&pdmac->pif);
2359 if (!pch->pl330_chid) {
2360 spin_unlock_irqrestore(&pch->lock, flags);
Inderpal Singh02747882012-09-17 09:57:45 +05302361 return -ENOMEM;
Jassi Brarb3040e42010-05-23 20:28:19 -07002362 }
2363
2364 tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch);
2365
2366 spin_unlock_irqrestore(&pch->lock, flags);
2367
2368 return 1;
2369}
2370
2371static int pl330_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, unsigned long arg)
2372{
2373 struct dma_pl330_chan *pch = to_pchan(chan);
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02002374 struct dma_pl330_desc *desc;
Jassi Brarb3040e42010-05-23 20:28:19 -07002375 unsigned long flags;
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002376 struct dma_pl330_dmac *pdmac = pch->dmac;
2377 struct dma_slave_config *slave_config;
Boojin Kimae43b882011-09-02 09:44:32 +09002378 LIST_HEAD(list);
Jassi Brarb3040e42010-05-23 20:28:19 -07002379
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002380 switch (cmd) {
2381 case DMA_TERMINATE_ALL:
2382 spin_lock_irqsave(&pch->lock, flags);
2383
2384 /* FLUSH the PL330 Channel thread */
2385 pl330_chan_ctrl(pch->pl330_chid, PL330_OP_FLUSH);
2386
2387 /* Mark all desc done */
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02002388 list_for_each_entry(desc, &pch->work_list , node) {
2389 desc->status = FREE;
2390 dma_cookie_complete(&desc->txd);
Boojin Kimae43b882011-09-02 09:44:32 +09002391 }
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002392
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02002393 list_for_each_entry(desc, &pch->completed_list , node) {
2394 desc->status = FREE;
2395 dma_cookie_complete(&desc->txd);
2396 }
2397
2398 list_splice_tail_init(&pch->work_list, &pdmac->desc_pool);
2399 list_splice_tail_init(&pch->completed_list, &pdmac->desc_pool);
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002400 spin_unlock_irqrestore(&pch->lock, flags);
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002401 break;
2402 case DMA_SLAVE_CONFIG:
2403 slave_config = (struct dma_slave_config *)arg;
2404
Vinod Kouldb8196d2011-10-13 22:34:23 +05302405 if (slave_config->direction == DMA_MEM_TO_DEV) {
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002406 if (slave_config->dst_addr)
2407 pch->fifo_addr = slave_config->dst_addr;
2408 if (slave_config->dst_addr_width)
2409 pch->burst_sz = __ffs(slave_config->dst_addr_width);
2410 if (slave_config->dst_maxburst)
2411 pch->burst_len = slave_config->dst_maxburst;
Vinod Kouldb8196d2011-10-13 22:34:23 +05302412 } else if (slave_config->direction == DMA_DEV_TO_MEM) {
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002413 if (slave_config->src_addr)
2414 pch->fifo_addr = slave_config->src_addr;
2415 if (slave_config->src_addr_width)
2416 pch->burst_sz = __ffs(slave_config->src_addr_width);
2417 if (slave_config->src_maxburst)
2418 pch->burst_len = slave_config->src_maxburst;
2419 }
2420 break;
2421 default:
2422 dev_err(pch->dmac->pif.dev, "Not supported command.\n");
Jassi Brarb3040e42010-05-23 20:28:19 -07002423 return -ENXIO;
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002424 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002425
2426 return 0;
2427}
2428
2429static void pl330_free_chan_resources(struct dma_chan *chan)
2430{
2431 struct dma_pl330_chan *pch = to_pchan(chan);
2432 unsigned long flags;
2433
Jassi Brarb3040e42010-05-23 20:28:19 -07002434 tasklet_kill(&pch->task);
2435
Bartlomiej Zolnierkiewiczda331ba2013-07-03 15:00:43 -07002436 spin_lock_irqsave(&pch->lock, flags);
2437
Jassi Brarb3040e42010-05-23 20:28:19 -07002438 pl330_release_channel(pch->pl330_chid);
2439 pch->pl330_chid = NULL;
2440
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002441 if (pch->cyclic)
2442 list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
2443
Jassi Brarb3040e42010-05-23 20:28:19 -07002444 spin_unlock_irqrestore(&pch->lock, flags);
2445}
2446
2447static enum dma_status
2448pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2449 struct dma_tx_state *txstate)
2450{
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +00002451 return dma_cookie_status(chan, cookie, txstate);
Jassi Brarb3040e42010-05-23 20:28:19 -07002452}
2453
2454static void pl330_issue_pending(struct dma_chan *chan)
2455{
2456 pl330_tasklet((unsigned long) to_pchan(chan));
2457}
2458
2459/*
2460 * We returned the last one of the circular list of descriptor(s)
2461 * from prep_xxx, so the argument to submit corresponds to the last
2462 * descriptor of the list.
2463 */
2464static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
2465{
2466 struct dma_pl330_desc *desc, *last = to_desc(tx);
2467 struct dma_pl330_chan *pch = to_pchan(tx->chan);
2468 dma_cookie_t cookie;
2469 unsigned long flags;
2470
2471 spin_lock_irqsave(&pch->lock, flags);
2472
2473 /* Assign cookies to all nodes */
Jassi Brarb3040e42010-05-23 20:28:19 -07002474 while (!list_empty(&last->node)) {
2475 desc = list_entry(last->node.next, struct dma_pl330_desc, node);
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002476 if (pch->cyclic) {
2477 desc->txd.callback = last->txd.callback;
2478 desc->txd.callback_param = last->txd.callback_param;
2479 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002480
Russell King - ARM Linux884485e2012-03-06 22:34:46 +00002481 dma_cookie_assign(&desc->txd);
Jassi Brarb3040e42010-05-23 20:28:19 -07002482
2483 list_move_tail(&desc->node, &pch->work_list);
2484 }
2485
Russell King - ARM Linux884485e2012-03-06 22:34:46 +00002486 cookie = dma_cookie_assign(&last->txd);
Jassi Brarb3040e42010-05-23 20:28:19 -07002487 list_add_tail(&last->node, &pch->work_list);
Jassi Brarb3040e42010-05-23 20:28:19 -07002488 spin_unlock_irqrestore(&pch->lock, flags);
2489
2490 return cookie;
2491}
2492
2493static inline void _init_desc(struct dma_pl330_desc *desc)
2494{
Jassi Brarb3040e42010-05-23 20:28:19 -07002495 desc->req.x = &desc->px;
2496 desc->req.token = desc;
2497 desc->rqcfg.swap = SWAP_NO;
Jassi Brarb3040e42010-05-23 20:28:19 -07002498 desc->rqcfg.scctl = SCCTRL0;
2499 desc->rqcfg.dcctl = DCCTRL0;
2500 desc->req.cfg = &desc->rqcfg;
2501 desc->req.xfer_cb = dma_pl330_rqcb;
2502 desc->txd.tx_submit = pl330_tx_submit;
2503
2504 INIT_LIST_HEAD(&desc->node);
2505}
2506
2507/* Returns the number of descriptors added to the DMAC pool */
Sachin Kamat5a67ac52012-06-04 17:09:45 +05302508static int add_desc(struct dma_pl330_dmac *pdmac, gfp_t flg, int count)
Jassi Brarb3040e42010-05-23 20:28:19 -07002509{
2510 struct dma_pl330_desc *desc;
2511 unsigned long flags;
2512 int i;
2513
2514 if (!pdmac)
2515 return 0;
2516
Will Deacon0baf8f62013-12-02 18:01:30 +00002517 desc = kcalloc(count, sizeof(*desc), flg);
Jassi Brarb3040e42010-05-23 20:28:19 -07002518 if (!desc)
2519 return 0;
2520
2521 spin_lock_irqsave(&pdmac->pool_lock, flags);
2522
2523 for (i = 0; i < count; i++) {
2524 _init_desc(&desc[i]);
2525 list_add_tail(&desc[i].node, &pdmac->desc_pool);
2526 }
2527
2528 spin_unlock_irqrestore(&pdmac->pool_lock, flags);
2529
2530 return count;
2531}
2532
2533static struct dma_pl330_desc *
2534pluck_desc(struct dma_pl330_dmac *pdmac)
2535{
2536 struct dma_pl330_desc *desc = NULL;
2537 unsigned long flags;
2538
2539 if (!pdmac)
2540 return NULL;
2541
2542 spin_lock_irqsave(&pdmac->pool_lock, flags);
2543
2544 if (!list_empty(&pdmac->desc_pool)) {
2545 desc = list_entry(pdmac->desc_pool.next,
2546 struct dma_pl330_desc, node);
2547
2548 list_del_init(&desc->node);
2549
2550 desc->status = PREP;
2551 desc->txd.callback = NULL;
2552 }
2553
2554 spin_unlock_irqrestore(&pdmac->pool_lock, flags);
2555
2556 return desc;
2557}
2558
2559static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
2560{
2561 struct dma_pl330_dmac *pdmac = pch->dmac;
Thomas Abrahamcd072512011-10-24 11:43:11 +02002562 u8 *peri_id = pch->chan.private;
Jassi Brarb3040e42010-05-23 20:28:19 -07002563 struct dma_pl330_desc *desc;
2564
2565 /* Pluck one desc from the pool of DMAC */
2566 desc = pluck_desc(pdmac);
2567
2568 /* If the DMAC pool is empty, alloc new */
2569 if (!desc) {
2570 if (!add_desc(pdmac, GFP_ATOMIC, 1))
2571 return NULL;
2572
2573 /* Try again */
2574 desc = pluck_desc(pdmac);
2575 if (!desc) {
2576 dev_err(pch->dmac->pif.dev,
2577 "%s:%d ALERT!\n", __func__, __LINE__);
2578 return NULL;
2579 }
2580 }
2581
2582 /* Initialize the descriptor */
2583 desc->pchan = pch;
2584 desc->txd.cookie = 0;
2585 async_tx_ack(&desc->txd);
2586
Thomas Abrahamcd072512011-10-24 11:43:11 +02002587 desc->req.peri = peri_id ? pch->chan.chan_id : 0;
Boojin Kim3ecf51a2011-12-26 18:55:47 +09002588 desc->rqcfg.pcfg = &pch->dmac->pif.pcfg;
Jassi Brarb3040e42010-05-23 20:28:19 -07002589
2590 dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
2591
2592 return desc;
2593}
2594
2595static inline void fill_px(struct pl330_xfer *px,
2596 dma_addr_t dst, dma_addr_t src, size_t len)
2597{
2598 px->next = NULL;
2599 px->bytes = len;
2600 px->dst_addr = dst;
2601 px->src_addr = src;
2602}
2603
2604static struct dma_pl330_desc *
2605__pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst,
2606 dma_addr_t src, size_t len)
2607{
2608 struct dma_pl330_desc *desc = pl330_get_desc(pch);
2609
2610 if (!desc) {
2611 dev_err(pch->dmac->pif.dev, "%s:%d Unable to fetch desc\n",
2612 __func__, __LINE__);
2613 return NULL;
2614 }
2615
2616 /*
2617 * Ideally we should lookout for reqs bigger than
2618 * those that can be programmed with 256 bytes of
2619 * MC buffer, but considering a req size is seldom
2620 * going to be word-unaligned and more than 200MB,
2621 * we take it easy.
2622 * Also, should the limit is reached we'd rather
2623 * have the platform increase MC buffer size than
2624 * complicating this API driver.
2625 */
2626 fill_px(&desc->px, dst, src, len);
2627
2628 return desc;
2629}
2630
2631/* Call after fixing burst size */
2632static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
2633{
2634 struct dma_pl330_chan *pch = desc->pchan;
2635 struct pl330_info *pi = &pch->dmac->pif;
2636 int burst_len;
2637
2638 burst_len = pi->pcfg.data_bus_width / 8;
2639 burst_len *= pi->pcfg.data_buf_dep;
2640 burst_len >>= desc->rqcfg.brst_size;
2641
2642 /* src/dst_burst_len can't be more than 16 */
2643 if (burst_len > 16)
2644 burst_len = 16;
2645
2646 while (burst_len > 1) {
2647 if (!(len % (burst_len << desc->rqcfg.brst_size)))
2648 break;
2649 burst_len--;
2650 }
2651
2652 return burst_len;
2653}
2654
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002655static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
2656 struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
Alexandre Bounine185ecb52012-03-08 15:35:13 -05002657 size_t period_len, enum dma_transfer_direction direction,
Peter Ujfalusiec8b5e42012-09-14 15:05:47 +03002658 unsigned long flags, void *context)
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002659{
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002660 struct dma_pl330_desc *desc = NULL, *first = NULL;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002661 struct dma_pl330_chan *pch = to_pchan(chan);
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002662 struct dma_pl330_dmac *pdmac = pch->dmac;
2663 unsigned int i;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002664 dma_addr_t dst;
2665 dma_addr_t src;
2666
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002667 if (len % period_len != 0)
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002668 return NULL;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002669
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002670 if (!is_slave_direction(direction)) {
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002671 dev_err(pch->dmac->pif.dev, "%s:%d Invalid dma direction\n",
2672 __func__, __LINE__);
2673 return NULL;
2674 }
2675
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002676 for (i = 0; i < len / period_len; i++) {
2677 desc = pl330_get_desc(pch);
2678 if (!desc) {
2679 dev_err(pch->dmac->pif.dev, "%s:%d Unable to fetch desc\n",
2680 __func__, __LINE__);
2681
2682 if (!first)
2683 return NULL;
2684
2685 spin_lock_irqsave(&pdmac->pool_lock, flags);
2686
2687 while (!list_empty(&first->node)) {
2688 desc = list_entry(first->node.next,
2689 struct dma_pl330_desc, node);
2690 list_move_tail(&desc->node, &pdmac->desc_pool);
2691 }
2692
2693 list_move_tail(&first->node, &pdmac->desc_pool);
2694
2695 spin_unlock_irqrestore(&pdmac->pool_lock, flags);
2696
2697 return NULL;
2698 }
2699
2700 switch (direction) {
2701 case DMA_MEM_TO_DEV:
2702 desc->rqcfg.src_inc = 1;
2703 desc->rqcfg.dst_inc = 0;
2704 desc->req.rqtype = MEMTODEV;
2705 src = dma_addr;
2706 dst = pch->fifo_addr;
2707 break;
2708 case DMA_DEV_TO_MEM:
2709 desc->rqcfg.src_inc = 0;
2710 desc->rqcfg.dst_inc = 1;
2711 desc->req.rqtype = DEVTOMEM;
2712 src = pch->fifo_addr;
2713 dst = dma_addr;
2714 break;
2715 default:
2716 break;
2717 }
2718
2719 desc->rqcfg.brst_size = pch->burst_sz;
2720 desc->rqcfg.brst_len = 1;
2721 fill_px(&desc->px, dst, src, period_len);
2722
2723 if (!first)
2724 first = desc;
2725 else
2726 list_add_tail(&desc->node, &first->node);
2727
2728 dma_addr += period_len;
2729 }
2730
2731 if (!desc)
2732 return NULL;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002733
2734 pch->cyclic = true;
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002735 desc->txd.flags = flags;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002736
2737 return &desc->txd;
2738}
2739
Jassi Brarb3040e42010-05-23 20:28:19 -07002740static struct dma_async_tx_descriptor *
2741pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
2742 dma_addr_t src, size_t len, unsigned long flags)
2743{
2744 struct dma_pl330_desc *desc;
2745 struct dma_pl330_chan *pch = to_pchan(chan);
Jassi Brarb3040e42010-05-23 20:28:19 -07002746 struct pl330_info *pi;
2747 int burst;
2748
Rob Herring4e0e6102011-07-25 16:05:04 -05002749 if (unlikely(!pch || !len))
Jassi Brarb3040e42010-05-23 20:28:19 -07002750 return NULL;
2751
Jassi Brarb3040e42010-05-23 20:28:19 -07002752 pi = &pch->dmac->pif;
2753
2754 desc = __pl330_prep_dma_memcpy(pch, dst, src, len);
2755 if (!desc)
2756 return NULL;
2757
2758 desc->rqcfg.src_inc = 1;
2759 desc->rqcfg.dst_inc = 1;
Thomas Abrahamcd072512011-10-24 11:43:11 +02002760 desc->req.rqtype = MEMTOMEM;
Jassi Brarb3040e42010-05-23 20:28:19 -07002761
2762 /* Select max possible burst size */
2763 burst = pi->pcfg.data_bus_width / 8;
2764
2765 while (burst > 1) {
2766 if (!(len % burst))
2767 break;
2768 burst /= 2;
2769 }
2770
2771 desc->rqcfg.brst_size = 0;
2772 while (burst != (1 << desc->rqcfg.brst_size))
2773 desc->rqcfg.brst_size++;
2774
2775 desc->rqcfg.brst_len = get_burst_len(desc, len);
2776
2777 desc->txd.flags = flags;
2778
2779 return &desc->txd;
2780}
2781
Chanho Park52a9d172013-08-09 20:11:33 +09002782static void __pl330_giveback_desc(struct dma_pl330_dmac *pdmac,
2783 struct dma_pl330_desc *first)
2784{
2785 unsigned long flags;
2786 struct dma_pl330_desc *desc;
2787
2788 if (!first)
2789 return;
2790
2791 spin_lock_irqsave(&pdmac->pool_lock, flags);
2792
2793 while (!list_empty(&first->node)) {
2794 desc = list_entry(first->node.next,
2795 struct dma_pl330_desc, node);
2796 list_move_tail(&desc->node, &pdmac->desc_pool);
2797 }
2798
2799 list_move_tail(&first->node, &pdmac->desc_pool);
2800
2801 spin_unlock_irqrestore(&pdmac->pool_lock, flags);
2802}
2803
Jassi Brarb3040e42010-05-23 20:28:19 -07002804static struct dma_async_tx_descriptor *
2805pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
Vinod Kouldb8196d2011-10-13 22:34:23 +05302806 unsigned int sg_len, enum dma_transfer_direction direction,
Alexandre Bounine185ecb52012-03-08 15:35:13 -05002807 unsigned long flg, void *context)
Jassi Brarb3040e42010-05-23 20:28:19 -07002808{
2809 struct dma_pl330_desc *first, *desc = NULL;
2810 struct dma_pl330_chan *pch = to_pchan(chan);
Jassi Brarb3040e42010-05-23 20:28:19 -07002811 struct scatterlist *sg;
Boojin Kim1b9bb712011-09-02 09:44:30 +09002812 int i;
Jassi Brarb3040e42010-05-23 20:28:19 -07002813 dma_addr_t addr;
2814
Thomas Abrahamcd072512011-10-24 11:43:11 +02002815 if (unlikely(!pch || !sgl || !sg_len))
Jassi Brarb3040e42010-05-23 20:28:19 -07002816 return NULL;
2817
Boojin Kim1b9bb712011-09-02 09:44:30 +09002818 addr = pch->fifo_addr;
Jassi Brarb3040e42010-05-23 20:28:19 -07002819
2820 first = NULL;
2821
2822 for_each_sg(sgl, sg, sg_len, i) {
2823
2824 desc = pl330_get_desc(pch);
2825 if (!desc) {
2826 struct dma_pl330_dmac *pdmac = pch->dmac;
2827
2828 dev_err(pch->dmac->pif.dev,
2829 "%s:%d Unable to fetch desc\n",
2830 __func__, __LINE__);
Chanho Park52a9d172013-08-09 20:11:33 +09002831 __pl330_giveback_desc(pdmac, first);
Jassi Brarb3040e42010-05-23 20:28:19 -07002832
2833 return NULL;
2834 }
2835
2836 if (!first)
2837 first = desc;
2838 else
2839 list_add_tail(&desc->node, &first->node);
2840
Vinod Kouldb8196d2011-10-13 22:34:23 +05302841 if (direction == DMA_MEM_TO_DEV) {
Jassi Brarb3040e42010-05-23 20:28:19 -07002842 desc->rqcfg.src_inc = 1;
2843 desc->rqcfg.dst_inc = 0;
Thomas Abrahamcd072512011-10-24 11:43:11 +02002844 desc->req.rqtype = MEMTODEV;
Jassi Brarb3040e42010-05-23 20:28:19 -07002845 fill_px(&desc->px,
2846 addr, sg_dma_address(sg), sg_dma_len(sg));
2847 } else {
2848 desc->rqcfg.src_inc = 0;
2849 desc->rqcfg.dst_inc = 1;
Thomas Abrahamcd072512011-10-24 11:43:11 +02002850 desc->req.rqtype = DEVTOMEM;
Jassi Brarb3040e42010-05-23 20:28:19 -07002851 fill_px(&desc->px,
2852 sg_dma_address(sg), addr, sg_dma_len(sg));
2853 }
2854
Boojin Kim1b9bb712011-09-02 09:44:30 +09002855 desc->rqcfg.brst_size = pch->burst_sz;
Jassi Brarb3040e42010-05-23 20:28:19 -07002856 desc->rqcfg.brst_len = 1;
2857 }
2858
2859 /* Return the last desc in the chain */
2860 desc->txd.flags = flg;
2861 return &desc->txd;
2862}
2863
2864static irqreturn_t pl330_irq_handler(int irq, void *data)
2865{
2866 if (pl330_update(data))
2867 return IRQ_HANDLED;
2868 else
2869 return IRQ_NONE;
2870}
2871
Lars-Peter Clausenca38ff12013-07-15 17:53:08 +02002872#define PL330_DMA_BUSWIDTHS \
2873 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
2874 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
2875 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
2876 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
2877 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
2878
2879static int pl330_dma_device_slave_caps(struct dma_chan *dchan,
2880 struct dma_slave_caps *caps)
2881{
2882 caps->src_addr_widths = PL330_DMA_BUSWIDTHS;
2883 caps->dstn_addr_widths = PL330_DMA_BUSWIDTHS;
2884 caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
2885 caps->cmd_pause = false;
2886 caps->cmd_terminate = true;
2887
Lars-Peter Clausenca38ff12013-07-15 17:53:08 +02002888 return 0;
2889}
2890
Bill Pemberton463a1f82012-11-19 13:22:55 -05002891static int
Russell Kingaa25afa2011-02-19 15:55:00 +00002892pl330_probe(struct amba_device *adev, const struct amba_id *id)
Jassi Brarb3040e42010-05-23 20:28:19 -07002893{
2894 struct dma_pl330_platdata *pdat;
2895 struct dma_pl330_dmac *pdmac;
Padmavathi Venna0b94c572013-03-05 14:55:31 +05302896 struct dma_pl330_chan *pch, *_p;
Jassi Brarb3040e42010-05-23 20:28:19 -07002897 struct pl330_info *pi;
2898 struct dma_device *pd;
2899 struct resource *res;
2900 int i, ret, irq;
Rob Herring4e0e6102011-07-25 16:05:04 -05002901 int num_chan;
Jassi Brarb3040e42010-05-23 20:28:19 -07002902
Jingoo Hand4adcc02013-07-30 17:09:11 +09002903 pdat = dev_get_platdata(&adev->dev);
Jassi Brarb3040e42010-05-23 20:28:19 -07002904
Russell King64113012013-06-27 10:29:32 +01002905 ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32));
2906 if (ret)
2907 return ret;
2908
Jassi Brarb3040e42010-05-23 20:28:19 -07002909 /* Allocate a new DMAC and its Channels */
Sachin Kamate4d43c12012-11-15 06:27:50 +00002910 pdmac = devm_kzalloc(&adev->dev, sizeof(*pdmac), GFP_KERNEL);
Jassi Brarb3040e42010-05-23 20:28:19 -07002911 if (!pdmac) {
2912 dev_err(&adev->dev, "unable to allocate mem\n");
2913 return -ENOMEM;
2914 }
2915
2916 pi = &pdmac->pif;
2917 pi->dev = &adev->dev;
2918 pi->pl330_data = NULL;
Rob Herring4e0e6102011-07-25 16:05:04 -05002919 pi->mcbufsz = pdat ? pdat->mcbuf_sz : 0;
Jassi Brarb3040e42010-05-23 20:28:19 -07002920
2921 res = &adev->res;
Sachin Kamatbcc7fa92013-03-04 14:36:27 +05302922 pi->base = devm_ioremap_resource(&adev->dev, res);
2923 if (IS_ERR(pi->base))
2924 return PTR_ERR(pi->base);
Jassi Brarb3040e42010-05-23 20:28:19 -07002925
Boojin Kima2f52032011-09-02 09:44:29 +09002926 amba_set_drvdata(adev, pdmac);
2927
Dan Carpenter02808b42013-11-08 12:50:24 +03002928 for (i = 0; i < AMBA_NR_IRQS; i++) {
Michal Simeke98b3ca2013-09-30 08:50:48 +02002929 irq = adev->irq[i];
2930 if (irq) {
2931 ret = devm_request_irq(&adev->dev, irq,
2932 pl330_irq_handler, 0,
2933 dev_name(&adev->dev), pi);
2934 if (ret)
2935 return ret;
2936 } else {
2937 break;
2938 }
2939 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002940
Will Deacon09677172013-06-10 19:34:37 +01002941 pi->pcfg.periph_id = adev->periphid;
Jassi Brarb3040e42010-05-23 20:28:19 -07002942 ret = pl330_add(pi);
2943 if (ret)
Michal Simek173e8382013-09-04 16:40:17 +02002944 return ret;
Jassi Brarb3040e42010-05-23 20:28:19 -07002945
2946 INIT_LIST_HEAD(&pdmac->desc_pool);
2947 spin_lock_init(&pdmac->pool_lock);
2948
2949 /* Create a descriptor pool of default size */
2950 if (!add_desc(pdmac, GFP_KERNEL, NR_DEFAULT_DESC))
2951 dev_warn(&adev->dev, "unable to allocate desc\n");
2952
2953 pd = &pdmac->ddma;
2954 INIT_LIST_HEAD(&pd->channels);
2955
2956 /* Initialize channel parameters */
Olof Johanssonc8473822012-04-08 16:26:19 -07002957 if (pdat)
2958 num_chan = max_t(int, pdat->nr_valid_peri, pi->pcfg.num_chan);
2959 else
2960 num_chan = max_t(int, pi->pcfg.num_peri, pi->pcfg.num_chan);
2961
Rob Herring4e0e6102011-07-25 16:05:04 -05002962 pdmac->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL);
Sachin Kamat61c6e752012-09-17 15:20:23 +05302963 if (!pdmac->peripherals) {
2964 ret = -ENOMEM;
2965 dev_err(&adev->dev, "unable to allocate pdmac->peripherals\n");
Sachin Kamate4d43c12012-11-15 06:27:50 +00002966 goto probe_err2;
Sachin Kamat61c6e752012-09-17 15:20:23 +05302967 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002968
Rob Herring4e0e6102011-07-25 16:05:04 -05002969 for (i = 0; i < num_chan; i++) {
2970 pch = &pdmac->peripherals[i];
Thomas Abraham93ed5542011-10-24 11:43:31 +02002971 if (!adev->dev.of_node)
2972 pch->chan.private = pdat ? &pdat->peri_id[i] : NULL;
2973 else
2974 pch->chan.private = adev->dev.of_node;
Jassi Brarb3040e42010-05-23 20:28:19 -07002975
2976 INIT_LIST_HEAD(&pch->work_list);
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02002977 INIT_LIST_HEAD(&pch->completed_list);
Jassi Brarb3040e42010-05-23 20:28:19 -07002978 spin_lock_init(&pch->lock);
2979 pch->pl330_chid = NULL;
Jassi Brarb3040e42010-05-23 20:28:19 -07002980 pch->chan.device = pd;
Jassi Brarb3040e42010-05-23 20:28:19 -07002981 pch->dmac = pdmac;
2982
2983 /* Add the channel to the DMAC list */
Jassi Brarb3040e42010-05-23 20:28:19 -07002984 list_add_tail(&pch->chan.device_node, &pd->channels);
2985 }
2986
2987 pd->dev = &adev->dev;
Thomas Abraham93ed5542011-10-24 11:43:31 +02002988 if (pdat) {
Thomas Abrahamcd072512011-10-24 11:43:11 +02002989 pd->cap_mask = pdat->cap_mask;
Thomas Abraham93ed5542011-10-24 11:43:31 +02002990 } else {
Thomas Abrahamcd072512011-10-24 11:43:11 +02002991 dma_cap_set(DMA_MEMCPY, pd->cap_mask);
Thomas Abraham93ed5542011-10-24 11:43:31 +02002992 if (pi->pcfg.num_peri) {
2993 dma_cap_set(DMA_SLAVE, pd->cap_mask);
2994 dma_cap_set(DMA_CYCLIC, pd->cap_mask);
Tushar Behera5557a412012-08-29 10:16:25 +05302995 dma_cap_set(DMA_PRIVATE, pd->cap_mask);
Thomas Abraham93ed5542011-10-24 11:43:31 +02002996 }
2997 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002998
2999 pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
3000 pd->device_free_chan_resources = pl330_free_chan_resources;
3001 pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09003002 pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
Jassi Brarb3040e42010-05-23 20:28:19 -07003003 pd->device_tx_status = pl330_tx_status;
3004 pd->device_prep_slave_sg = pl330_prep_slave_sg;
3005 pd->device_control = pl330_control;
3006 pd->device_issue_pending = pl330_issue_pending;
Lars-Peter Clausenca38ff12013-07-15 17:53:08 +02003007 pd->device_slave_caps = pl330_dma_device_slave_caps;
Jassi Brarb3040e42010-05-23 20:28:19 -07003008
3009 ret = dma_async_device_register(pd);
3010 if (ret) {
3011 dev_err(&adev->dev, "unable to register DMAC\n");
Padmavathi Venna0b94c572013-03-05 14:55:31 +05303012 goto probe_err3;
3013 }
3014
3015 if (adev->dev.of_node) {
3016 ret = of_dma_controller_register(adev->dev.of_node,
3017 of_dma_pl330_xlate, pdmac);
3018 if (ret) {
3019 dev_err(&adev->dev,
3020 "unable to register DMA to the generic DT DMA helpers\n");
3021 }
Jassi Brarb3040e42010-05-23 20:28:19 -07003022 }
Vinod Kouldbaf6d82013-09-02 21:54:48 +05303023 /*
3024 * This is the limit for transfers with a buswidth of 1, larger
3025 * buswidths will have larger limits.
3026 */
3027 ret = dma_set_max_seg_size(&adev->dev, 1900800);
3028 if (ret)
3029 dev_err(&adev->dev, "unable to set the seg size\n");
3030
Jassi Brarb3040e42010-05-23 20:28:19 -07003031
Jassi Brarb3040e42010-05-23 20:28:19 -07003032 dev_info(&adev->dev,
3033 "Loaded driver for PL330 DMAC-%d\n", adev->periphid);
3034 dev_info(&adev->dev,
3035 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
3036 pi->pcfg.data_buf_dep,
3037 pi->pcfg.data_bus_width / 8, pi->pcfg.num_chan,
3038 pi->pcfg.num_peri, pi->pcfg.num_events);
3039
3040 return 0;
Padmavathi Venna0b94c572013-03-05 14:55:31 +05303041probe_err3:
Padmavathi Venna0b94c572013-03-05 14:55:31 +05303042 /* Idle the DMAC */
3043 list_for_each_entry_safe(pch, _p, &pdmac->ddma.channels,
3044 chan.device_node) {
3045
3046 /* Remove the channel */
3047 list_del(&pch->chan.device_node);
3048
3049 /* Flush the channel */
3050 pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0);
3051 pl330_free_chan_resources(&pch->chan);
3052 }
Jassi Brarb3040e42010-05-23 20:28:19 -07003053probe_err2:
Sachin Kamate4d43c12012-11-15 06:27:50 +00003054 pl330_del(pi);
Jassi Brarb3040e42010-05-23 20:28:19 -07003055
3056 return ret;
3057}
3058
Greg Kroah-Hartman4bf27b82012-12-21 15:09:59 -08003059static int pl330_remove(struct amba_device *adev)
Jassi Brarb3040e42010-05-23 20:28:19 -07003060{
3061 struct dma_pl330_dmac *pdmac = amba_get_drvdata(adev);
3062 struct dma_pl330_chan *pch, *_p;
3063 struct pl330_info *pi;
Jassi Brarb3040e42010-05-23 20:28:19 -07003064
3065 if (!pdmac)
3066 return 0;
3067
Padmavathi Venna0b94c572013-03-05 14:55:31 +05303068 if (adev->dev.of_node)
3069 of_dma_controller_free(adev->dev.of_node);
Padmavathi Venna421da892013-02-14 09:10:07 +05303070
Padmavathi Venna0b94c572013-03-05 14:55:31 +05303071 dma_async_device_unregister(&pdmac->ddma);
Jassi Brarb3040e42010-05-23 20:28:19 -07003072
3073 /* Idle the DMAC */
3074 list_for_each_entry_safe(pch, _p, &pdmac->ddma.channels,
3075 chan.device_node) {
3076
3077 /* Remove the channel */
3078 list_del(&pch->chan.device_node);
3079
3080 /* Flush the channel */
3081 pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0);
3082 pl330_free_chan_resources(&pch->chan);
3083 }
3084
3085 pi = &pdmac->pif;
3086
3087 pl330_del(pi);
3088
Jassi Brarb3040e42010-05-23 20:28:19 -07003089 return 0;
3090}
3091
3092static struct amba_id pl330_ids[] = {
3093 {
3094 .id = 0x00041330,
3095 .mask = 0x000fffff,
3096 },
3097 { 0, 0 },
3098};
3099
Dave Martine8fa5162011-10-05 15:15:20 +01003100MODULE_DEVICE_TABLE(amba, pl330_ids);
3101
Jassi Brarb3040e42010-05-23 20:28:19 -07003102static struct amba_driver pl330_driver = {
3103 .drv = {
3104 .owner = THIS_MODULE,
3105 .name = "dma-pl330",
Jassi Brarb3040e42010-05-23 20:28:19 -07003106 },
3107 .id_table = pl330_ids,
3108 .probe = pl330_probe,
3109 .remove = pl330_remove,
3110};
3111
viresh kumar9e5ed092012-03-15 10:40:38 +01003112module_amba_driver(pl330_driver);
Jassi Brarb3040e42010-05-23 20:28:19 -07003113
3114MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
3115MODULE_DESCRIPTION("API Driver for PL330 DMAC");
3116MODULE_LICENSE("GPL");