Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008-2010 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * Zou Nan hai <nanhai.zou@intel.com> |
| 26 | * Xiang Hai hao<haihao.xiang@intel.com> |
| 27 | * |
| 28 | */ |
| 29 | |
Zeng Zhaoxiu | a4d8a0f | 2015-12-06 18:26:30 +0800 | [diff] [blame] | 30 | #include <linux/log2.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 31 | #include <drm/drmP.h> |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 32 | #include "i915_drv.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 33 | #include <drm/i915_drm.h> |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 34 | #include "i915_trace.h" |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 35 | #include "intel_drv.h" |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 36 | |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 37 | int __intel_ring_space(int head, int tail, int size) |
Chris Wilson | 1cf0ba1 | 2014-05-05 09:07:33 +0100 | [diff] [blame] | 38 | { |
Dave Gordon | 4f54741 | 2014-11-27 11:22:48 +0000 | [diff] [blame] | 39 | int space = head - tail; |
| 40 | if (space <= 0) |
Chris Wilson | 1cf0ba1 | 2014-05-05 09:07:33 +0100 | [diff] [blame] | 41 | space += size; |
Dave Gordon | 4f54741 | 2014-11-27 11:22:48 +0000 | [diff] [blame] | 42 | return space - I915_RING_FREE_SPACE; |
Chris Wilson | 1cf0ba1 | 2014-05-05 09:07:33 +0100 | [diff] [blame] | 43 | } |
| 44 | |
Dave Gordon | ebd0fd4 | 2014-11-27 11:22:49 +0000 | [diff] [blame] | 45 | void intel_ring_update_space(struct intel_ringbuffer *ringbuf) |
| 46 | { |
| 47 | if (ringbuf->last_retired_head != -1) { |
| 48 | ringbuf->head = ringbuf->last_retired_head; |
| 49 | ringbuf->last_retired_head = -1; |
| 50 | } |
| 51 | |
| 52 | ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR, |
| 53 | ringbuf->tail, ringbuf->size); |
| 54 | } |
| 55 | |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 56 | int intel_ring_space(struct intel_ringbuffer *ringbuf) |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 57 | { |
Dave Gordon | ebd0fd4 | 2014-11-27 11:22:49 +0000 | [diff] [blame] | 58 | intel_ring_update_space(ringbuf); |
| 59 | return ringbuf->space; |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 60 | } |
| 61 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 62 | bool intel_ring_stopped(struct intel_engine_cs *engine) |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 63 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 64 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
| 65 | return dev_priv->gpu_error.stop_rings & intel_ring_flag(engine); |
Mika Kuoppala | 88b4aa8 | 2014-03-28 18:18:18 +0200 | [diff] [blame] | 66 | } |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 67 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 68 | static void __intel_ring_advance(struct intel_engine_cs *engine) |
Mika Kuoppala | 88b4aa8 | 2014-03-28 18:18:18 +0200 | [diff] [blame] | 69 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 70 | struct intel_ringbuffer *ringbuf = engine->buffer; |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 71 | ringbuf->tail &= ringbuf->size - 1; |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 72 | if (intel_ring_stopped(engine)) |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 73 | return; |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 74 | engine->write_tail(engine, ringbuf->tail); |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 75 | } |
| 76 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 77 | static int |
John Harrison | a84c3ae | 2015-05-29 17:43:57 +0100 | [diff] [blame] | 78 | gen2_render_ring_flush(struct drm_i915_gem_request *req, |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 79 | u32 invalidate_domains, |
| 80 | u32 flush_domains) |
| 81 | { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 82 | struct intel_engine_cs *engine = req->ring; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 83 | u32 cmd; |
| 84 | int ret; |
| 85 | |
| 86 | cmd = MI_FLUSH; |
Daniel Vetter | 31b14c9 | 2012-04-19 16:45:22 +0200 | [diff] [blame] | 87 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 88 | cmd |= MI_NO_WRITE_FLUSH; |
| 89 | |
| 90 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) |
| 91 | cmd |= MI_READ_FLUSH; |
| 92 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 93 | ret = intel_ring_begin(req, 2); |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 94 | if (ret) |
| 95 | return ret; |
| 96 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 97 | intel_ring_emit(engine, cmd); |
| 98 | intel_ring_emit(engine, MI_NOOP); |
| 99 | intel_ring_advance(engine); |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 100 | |
| 101 | return 0; |
| 102 | } |
| 103 | |
| 104 | static int |
John Harrison | a84c3ae | 2015-05-29 17:43:57 +0100 | [diff] [blame] | 105 | gen4_render_ring_flush(struct drm_i915_gem_request *req, |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 106 | u32 invalidate_domains, |
| 107 | u32 flush_domains) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 108 | { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 109 | struct intel_engine_cs *engine = req->ring; |
| 110 | struct drm_device *dev = engine->dev; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 111 | u32 cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 112 | int ret; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 113 | |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 114 | /* |
| 115 | * read/write caches: |
| 116 | * |
| 117 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is |
| 118 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is |
| 119 | * also flushed at 2d versus 3d pipeline switches. |
| 120 | * |
| 121 | * read-only caches: |
| 122 | * |
| 123 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if |
| 124 | * MI_READ_FLUSH is set, and is always flushed on 965. |
| 125 | * |
| 126 | * I915_GEM_DOMAIN_COMMAND may not exist? |
| 127 | * |
| 128 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is |
| 129 | * invalidated when MI_EXE_FLUSH is set. |
| 130 | * |
| 131 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is |
| 132 | * invalidated with every MI_FLUSH. |
| 133 | * |
| 134 | * TLBs: |
| 135 | * |
| 136 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND |
| 137 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and |
| 138 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER |
| 139 | * are flushed at any MI_FLUSH. |
| 140 | */ |
| 141 | |
| 142 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 143 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 144 | cmd &= ~MI_NO_WRITE_FLUSH; |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 145 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
| 146 | cmd |= MI_EXE_FLUSH; |
| 147 | |
| 148 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
| 149 | (IS_G4X(dev) || IS_GEN5(dev))) |
| 150 | cmd |= MI_INVALIDATE_ISP; |
| 151 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 152 | ret = intel_ring_begin(req, 2); |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 153 | if (ret) |
| 154 | return ret; |
| 155 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 156 | intel_ring_emit(engine, cmd); |
| 157 | intel_ring_emit(engine, MI_NOOP); |
| 158 | intel_ring_advance(engine); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 159 | |
| 160 | return 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 161 | } |
| 162 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 163 | /** |
| 164 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for |
| 165 | * implementing two workarounds on gen6. From section 1.4.7.1 |
| 166 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: |
| 167 | * |
| 168 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those |
| 169 | * produced by non-pipelined state commands), software needs to first |
| 170 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != |
| 171 | * 0. |
| 172 | * |
| 173 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable |
| 174 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. |
| 175 | * |
| 176 | * And the workaround for these two requires this workaround first: |
| 177 | * |
| 178 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent |
| 179 | * BEFORE the pipe-control with a post-sync op and no write-cache |
| 180 | * flushes. |
| 181 | * |
| 182 | * And this last workaround is tricky because of the requirements on |
| 183 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM |
| 184 | * volume 2 part 1: |
| 185 | * |
| 186 | * "1 of the following must also be set: |
| 187 | * - Render Target Cache Flush Enable ([12] of DW1) |
| 188 | * - Depth Cache Flush Enable ([0] of DW1) |
| 189 | * - Stall at Pixel Scoreboard ([1] of DW1) |
| 190 | * - Depth Stall ([13] of DW1) |
| 191 | * - Post-Sync Operation ([13] of DW1) |
| 192 | * - Notify Enable ([8] of DW1)" |
| 193 | * |
| 194 | * The cache flushes require the workaround flush that triggered this |
| 195 | * one, so we can't use it. Depth stall would trigger the same. |
| 196 | * Post-sync nonzero is what triggered this second workaround, so we |
| 197 | * can't use that one either. Notify enable is IRQs, which aren't |
| 198 | * really our business. That leaves only stall at scoreboard. |
| 199 | */ |
| 200 | static int |
John Harrison | f2cf1fc | 2015-05-29 17:43:58 +0100 | [diff] [blame] | 201 | intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req) |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 202 | { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 203 | struct intel_engine_cs *engine = req->ring; |
| 204 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 205 | int ret; |
| 206 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 207 | ret = intel_ring_begin(req, 6); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 208 | if (ret) |
| 209 | return ret; |
| 210 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 211 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5)); |
| 212 | intel_ring_emit(engine, PIPE_CONTROL_CS_STALL | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 213 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 214 | intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
| 215 | intel_ring_emit(engine, 0); /* low dword */ |
| 216 | intel_ring_emit(engine, 0); /* high dword */ |
| 217 | intel_ring_emit(engine, MI_NOOP); |
| 218 | intel_ring_advance(engine); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 219 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 220 | ret = intel_ring_begin(req, 6); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 221 | if (ret) |
| 222 | return ret; |
| 223 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 224 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5)); |
| 225 | intel_ring_emit(engine, PIPE_CONTROL_QW_WRITE); |
| 226 | intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
| 227 | intel_ring_emit(engine, 0); |
| 228 | intel_ring_emit(engine, 0); |
| 229 | intel_ring_emit(engine, MI_NOOP); |
| 230 | intel_ring_advance(engine); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 231 | |
| 232 | return 0; |
| 233 | } |
| 234 | |
| 235 | static int |
John Harrison | a84c3ae | 2015-05-29 17:43:57 +0100 | [diff] [blame] | 236 | gen6_render_ring_flush(struct drm_i915_gem_request *req, |
| 237 | u32 invalidate_domains, u32 flush_domains) |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 238 | { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 239 | struct intel_engine_cs *engine = req->ring; |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 240 | u32 flags = 0; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 241 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 242 | int ret; |
| 243 | |
Paulo Zanoni | b311150 | 2012-08-17 18:35:42 -0300 | [diff] [blame] | 244 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
John Harrison | f2cf1fc | 2015-05-29 17:43:58 +0100 | [diff] [blame] | 245 | ret = intel_emit_post_sync_nonzero_flush(req); |
Paulo Zanoni | b311150 | 2012-08-17 18:35:42 -0300 | [diff] [blame] | 246 | if (ret) |
| 247 | return ret; |
| 248 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 249 | /* Just flush everything. Experiments have shown that reducing the |
| 250 | * number of bits based on the write domains has little performance |
| 251 | * impact. |
| 252 | */ |
Chris Wilson | 7d54a90 | 2012-08-10 10:18:10 +0100 | [diff] [blame] | 253 | if (flush_domains) { |
| 254 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
| 255 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
| 256 | /* |
| 257 | * Ensure that any following seqno writes only happen |
| 258 | * when the render cache is indeed flushed. |
| 259 | */ |
Daniel Vetter | 97f209b | 2012-06-28 09:48:42 +0200 | [diff] [blame] | 260 | flags |= PIPE_CONTROL_CS_STALL; |
Chris Wilson | 7d54a90 | 2012-08-10 10:18:10 +0100 | [diff] [blame] | 261 | } |
| 262 | if (invalidate_domains) { |
| 263 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
| 264 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 265 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 266 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 267 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 268 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
| 269 | /* |
| 270 | * TLB invalidate requires a post-sync write. |
| 271 | */ |
Jesse Barnes | 3ac7831 | 2012-10-25 12:15:47 -0700 | [diff] [blame] | 272 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
Chris Wilson | 7d54a90 | 2012-08-10 10:18:10 +0100 | [diff] [blame] | 273 | } |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 274 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 275 | ret = intel_ring_begin(req, 4); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 276 | if (ret) |
| 277 | return ret; |
| 278 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 279 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4)); |
| 280 | intel_ring_emit(engine, flags); |
| 281 | intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); |
| 282 | intel_ring_emit(engine, 0); |
| 283 | intel_ring_advance(engine); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 284 | |
| 285 | return 0; |
| 286 | } |
| 287 | |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 288 | static int |
John Harrison | f2cf1fc | 2015-05-29 17:43:58 +0100 | [diff] [blame] | 289 | gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req) |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 290 | { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 291 | struct intel_engine_cs *engine = req->ring; |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 292 | int ret; |
| 293 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 294 | ret = intel_ring_begin(req, 4); |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 295 | if (ret) |
| 296 | return ret; |
| 297 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 298 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4)); |
| 299 | intel_ring_emit(engine, PIPE_CONTROL_CS_STALL | |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 300 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 301 | intel_ring_emit(engine, 0); |
| 302 | intel_ring_emit(engine, 0); |
| 303 | intel_ring_advance(engine); |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 304 | |
| 305 | return 0; |
| 306 | } |
| 307 | |
| 308 | static int |
John Harrison | a84c3ae | 2015-05-29 17:43:57 +0100 | [diff] [blame] | 309 | gen7_render_ring_flush(struct drm_i915_gem_request *req, |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 310 | u32 invalidate_domains, u32 flush_domains) |
| 311 | { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 312 | struct intel_engine_cs *engine = req->ring; |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 313 | u32 flags = 0; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 314 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 315 | int ret; |
| 316 | |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 317 | /* |
| 318 | * Ensure that any following seqno writes only happen when the render |
| 319 | * cache is indeed flushed. |
| 320 | * |
| 321 | * Workaround: 4th PIPE_CONTROL command (except the ones with only |
| 322 | * read-cache invalidate bits set) must have the CS_STALL bit set. We |
| 323 | * don't try to be clever and just set it unconditionally. |
| 324 | */ |
| 325 | flags |= PIPE_CONTROL_CS_STALL; |
| 326 | |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 327 | /* Just flush everything. Experiments have shown that reducing the |
| 328 | * number of bits based on the write domains has little performance |
| 329 | * impact. |
| 330 | */ |
| 331 | if (flush_domains) { |
| 332 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
| 333 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
Francisco Jerez | 965fd60 | 2016-01-13 18:59:39 -0800 | [diff] [blame] | 334 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
Chris Wilson | 40a2448 | 2015-08-21 16:08:41 +0100 | [diff] [blame] | 335 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 336 | } |
| 337 | if (invalidate_domains) { |
| 338 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
| 339 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 340 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 341 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 342 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 343 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
Chris Wilson | 148b83d | 2014-12-16 08:44:31 +0000 | [diff] [blame] | 344 | flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 345 | /* |
| 346 | * TLB invalidate requires a post-sync write. |
| 347 | */ |
| 348 | flags |= PIPE_CONTROL_QW_WRITE; |
Ville Syrjälä | b9e1faa | 2013-02-14 21:53:51 +0200 | [diff] [blame] | 349 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 350 | |
Chris Wilson | add284a | 2014-12-16 08:44:32 +0000 | [diff] [blame] | 351 | flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; |
| 352 | |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 353 | /* Workaround: we must issue a pipe_control with CS-stall bit |
| 354 | * set before a pipe_control command that has the state cache |
| 355 | * invalidate bit set. */ |
John Harrison | f2cf1fc | 2015-05-29 17:43:58 +0100 | [diff] [blame] | 356 | gen7_render_ring_cs_stall_wa(req); |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 357 | } |
| 358 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 359 | ret = intel_ring_begin(req, 4); |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 360 | if (ret) |
| 361 | return ret; |
| 362 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 363 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4)); |
| 364 | intel_ring_emit(engine, flags); |
| 365 | intel_ring_emit(engine, scratch_addr); |
| 366 | intel_ring_emit(engine, 0); |
| 367 | intel_ring_advance(engine); |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 368 | |
| 369 | return 0; |
| 370 | } |
| 371 | |
Ben Widawsky | a5f3d68 | 2013-11-02 21:07:27 -0700 | [diff] [blame] | 372 | static int |
John Harrison | f2cf1fc | 2015-05-29 17:43:58 +0100 | [diff] [blame] | 373 | gen8_emit_pipe_control(struct drm_i915_gem_request *req, |
Kenneth Graunke | 884ceac | 2014-06-28 02:04:20 +0300 | [diff] [blame] | 374 | u32 flags, u32 scratch_addr) |
| 375 | { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 376 | struct intel_engine_cs *engine = req->ring; |
Kenneth Graunke | 884ceac | 2014-06-28 02:04:20 +0300 | [diff] [blame] | 377 | int ret; |
| 378 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 379 | ret = intel_ring_begin(req, 6); |
Kenneth Graunke | 884ceac | 2014-06-28 02:04:20 +0300 | [diff] [blame] | 380 | if (ret) |
| 381 | return ret; |
| 382 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 383 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6)); |
| 384 | intel_ring_emit(engine, flags); |
| 385 | intel_ring_emit(engine, scratch_addr); |
| 386 | intel_ring_emit(engine, 0); |
| 387 | intel_ring_emit(engine, 0); |
| 388 | intel_ring_emit(engine, 0); |
| 389 | intel_ring_advance(engine); |
Kenneth Graunke | 884ceac | 2014-06-28 02:04:20 +0300 | [diff] [blame] | 390 | |
| 391 | return 0; |
| 392 | } |
| 393 | |
| 394 | static int |
John Harrison | a84c3ae | 2015-05-29 17:43:57 +0100 | [diff] [blame] | 395 | gen8_render_ring_flush(struct drm_i915_gem_request *req, |
Ben Widawsky | a5f3d68 | 2013-11-02 21:07:27 -0700 | [diff] [blame] | 396 | u32 invalidate_domains, u32 flush_domains) |
| 397 | { |
| 398 | u32 flags = 0; |
John Harrison | f2cf1fc | 2015-05-29 17:43:58 +0100 | [diff] [blame] | 399 | u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
Kenneth Graunke | 02c9f7e | 2014-01-27 14:20:16 -0800 | [diff] [blame] | 400 | int ret; |
Ben Widawsky | a5f3d68 | 2013-11-02 21:07:27 -0700 | [diff] [blame] | 401 | |
| 402 | flags |= PIPE_CONTROL_CS_STALL; |
| 403 | |
| 404 | if (flush_domains) { |
| 405 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
| 406 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
Francisco Jerez | 965fd60 | 2016-01-13 18:59:39 -0800 | [diff] [blame] | 407 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
Chris Wilson | 40a2448 | 2015-08-21 16:08:41 +0100 | [diff] [blame] | 408 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
Ben Widawsky | a5f3d68 | 2013-11-02 21:07:27 -0700 | [diff] [blame] | 409 | } |
| 410 | if (invalidate_domains) { |
| 411 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
| 412 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 413 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 414 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 415 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 416 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
| 417 | flags |= PIPE_CONTROL_QW_WRITE; |
| 418 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
Kenneth Graunke | 02c9f7e | 2014-01-27 14:20:16 -0800 | [diff] [blame] | 419 | |
| 420 | /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ |
John Harrison | f2cf1fc | 2015-05-29 17:43:58 +0100 | [diff] [blame] | 421 | ret = gen8_emit_pipe_control(req, |
Kenneth Graunke | 02c9f7e | 2014-01-27 14:20:16 -0800 | [diff] [blame] | 422 | PIPE_CONTROL_CS_STALL | |
| 423 | PIPE_CONTROL_STALL_AT_SCOREBOARD, |
| 424 | 0); |
| 425 | if (ret) |
| 426 | return ret; |
Ben Widawsky | a5f3d68 | 2013-11-02 21:07:27 -0700 | [diff] [blame] | 427 | } |
| 428 | |
John Harrison | f2cf1fc | 2015-05-29 17:43:58 +0100 | [diff] [blame] | 429 | return gen8_emit_pipe_control(req, flags, scratch_addr); |
Ben Widawsky | a5f3d68 | 2013-11-02 21:07:27 -0700 | [diff] [blame] | 430 | } |
| 431 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 432 | static void ring_write_tail(struct intel_engine_cs *engine, |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 433 | u32 value) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 434 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 435 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
| 436 | I915_WRITE_TAIL(engine, value); |
Xiang, Haihao | d46eefa | 2010-09-16 10:43:12 +0800 | [diff] [blame] | 437 | } |
| 438 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 439 | u64 intel_ring_get_active_head(struct intel_engine_cs *engine) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 440 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 441 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
Chris Wilson | 5087744 | 2014-03-21 12:41:53 +0000 | [diff] [blame] | 442 | u64 acthd; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 443 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 444 | if (INTEL_INFO(engine->dev)->gen >= 8) |
| 445 | acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base), |
| 446 | RING_ACTHD_UDW(engine->mmio_base)); |
| 447 | else if (INTEL_INFO(engine->dev)->gen >= 4) |
| 448 | acthd = I915_READ(RING_ACTHD(engine->mmio_base)); |
Chris Wilson | 5087744 | 2014-03-21 12:41:53 +0000 | [diff] [blame] | 449 | else |
| 450 | acthd = I915_READ(ACTHD); |
| 451 | |
| 452 | return acthd; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 453 | } |
| 454 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 455 | static void ring_setup_phys_status_page(struct intel_engine_cs *engine) |
Daniel Vetter | 035dc1e | 2013-07-03 12:56:54 +0200 | [diff] [blame] | 456 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 457 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
Daniel Vetter | 035dc1e | 2013-07-03 12:56:54 +0200 | [diff] [blame] | 458 | u32 addr; |
| 459 | |
| 460 | addr = dev_priv->status_page_dmah->busaddr; |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 461 | if (INTEL_INFO(engine->dev)->gen >= 4) |
Daniel Vetter | 035dc1e | 2013-07-03 12:56:54 +0200 | [diff] [blame] | 462 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
| 463 | I915_WRITE(HWS_PGA, addr); |
| 464 | } |
| 465 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 466 | static void intel_ring_setup_status_page(struct intel_engine_cs *engine) |
Damien Lespiau | af75f26 | 2015-02-10 19:32:17 +0000 | [diff] [blame] | 467 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 468 | struct drm_device *dev = engine->dev; |
| 469 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 470 | i915_reg_t mmio; |
Damien Lespiau | af75f26 | 2015-02-10 19:32:17 +0000 | [diff] [blame] | 471 | |
| 472 | /* The ring status page addresses are no longer next to the rest of |
| 473 | * the ring registers as of gen7. |
| 474 | */ |
| 475 | if (IS_GEN7(dev)) { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 476 | switch (engine->id) { |
Damien Lespiau | af75f26 | 2015-02-10 19:32:17 +0000 | [diff] [blame] | 477 | case RCS: |
| 478 | mmio = RENDER_HWS_PGA_GEN7; |
| 479 | break; |
| 480 | case BCS: |
| 481 | mmio = BLT_HWS_PGA_GEN7; |
| 482 | break; |
| 483 | /* |
| 484 | * VCS2 actually doesn't exist on Gen7. Only shut up |
| 485 | * gcc switch check warning |
| 486 | */ |
| 487 | case VCS2: |
| 488 | case VCS: |
| 489 | mmio = BSD_HWS_PGA_GEN7; |
| 490 | break; |
| 491 | case VECS: |
| 492 | mmio = VEBOX_HWS_PGA_GEN7; |
| 493 | break; |
| 494 | } |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 495 | } else if (IS_GEN6(engine->dev)) { |
| 496 | mmio = RING_HWS_PGA_GEN6(engine->mmio_base); |
Damien Lespiau | af75f26 | 2015-02-10 19:32:17 +0000 | [diff] [blame] | 497 | } else { |
| 498 | /* XXX: gen8 returns to sanity */ |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 499 | mmio = RING_HWS_PGA(engine->mmio_base); |
Damien Lespiau | af75f26 | 2015-02-10 19:32:17 +0000 | [diff] [blame] | 500 | } |
| 501 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 502 | I915_WRITE(mmio, (u32)engine->status_page.gfx_addr); |
Damien Lespiau | af75f26 | 2015-02-10 19:32:17 +0000 | [diff] [blame] | 503 | POSTING_READ(mmio); |
| 504 | |
| 505 | /* |
| 506 | * Flush the TLB for this page |
| 507 | * |
| 508 | * FIXME: These two bits have disappeared on gen8, so a question |
| 509 | * arises: do we still need this and if so how should we go about |
| 510 | * invalidating the TLB? |
| 511 | */ |
| 512 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 513 | i915_reg_t reg = RING_INSTPM(engine->mmio_base); |
Damien Lespiau | af75f26 | 2015-02-10 19:32:17 +0000 | [diff] [blame] | 514 | |
| 515 | /* ring should be idle before issuing a sync flush*/ |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 516 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
Damien Lespiau | af75f26 | 2015-02-10 19:32:17 +0000 | [diff] [blame] | 517 | |
| 518 | I915_WRITE(reg, |
| 519 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | |
| 520 | INSTPM_SYNC_FLUSH)); |
| 521 | if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0, |
| 522 | 1000)) |
| 523 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 524 | engine->name); |
Damien Lespiau | af75f26 | 2015-02-10 19:32:17 +0000 | [diff] [blame] | 525 | } |
| 526 | } |
| 527 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 528 | static bool stop_ring(struct intel_engine_cs *engine) |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 529 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 530 | struct drm_i915_private *dev_priv = to_i915(engine->dev); |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 531 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 532 | if (!IS_GEN2(engine->dev)) { |
| 533 | I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); |
| 534 | if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) { |
| 535 | DRM_ERROR("%s : timed out trying to stop ring\n", |
| 536 | engine->name); |
Chris Wilson | 9bec9b1 | 2014-08-11 09:21:35 +0100 | [diff] [blame] | 537 | /* Sometimes we observe that the idle flag is not |
| 538 | * set even though the ring is empty. So double |
| 539 | * check before giving up. |
| 540 | */ |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 541 | if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine)) |
Chris Wilson | 9bec9b1 | 2014-08-11 09:21:35 +0100 | [diff] [blame] | 542 | return false; |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 543 | } |
| 544 | } |
| 545 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 546 | I915_WRITE_CTL(engine, 0); |
| 547 | I915_WRITE_HEAD(engine, 0); |
| 548 | engine->write_tail(engine, 0); |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 549 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 550 | if (!IS_GEN2(engine->dev)) { |
| 551 | (void)I915_READ_CTL(engine); |
| 552 | I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING)); |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 553 | } |
| 554 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 555 | return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0; |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 556 | } |
| 557 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 558 | static int init_ring_common(struct intel_engine_cs *engine) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 559 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 560 | struct drm_device *dev = engine->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 561 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 562 | struct intel_ringbuffer *ringbuf = engine->buffer; |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 563 | struct drm_i915_gem_object *obj = ringbuf->obj; |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 564 | int ret = 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 565 | |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 566 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 567 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 568 | if (!stop_ring(engine)) { |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 569 | /* G45 ring initialization often fails to reset head to zero */ |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 570 | DRM_DEBUG_KMS("%s head not reset to zero " |
| 571 | "ctl %08x head %08x tail %08x start %08x\n", |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 572 | engine->name, |
| 573 | I915_READ_CTL(engine), |
| 574 | I915_READ_HEAD(engine), |
| 575 | I915_READ_TAIL(engine), |
| 576 | I915_READ_START(engine)); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 577 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 578 | if (!stop_ring(engine)) { |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 579 | DRM_ERROR("failed to set %s head to zero " |
| 580 | "ctl %08x head %08x tail %08x start %08x\n", |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 581 | engine->name, |
| 582 | I915_READ_CTL(engine), |
| 583 | I915_READ_HEAD(engine), |
| 584 | I915_READ_TAIL(engine), |
| 585 | I915_READ_START(engine)); |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 586 | ret = -EIO; |
| 587 | goto out; |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 588 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 589 | } |
| 590 | |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 591 | if (I915_NEED_GFX_HWS(dev)) |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 592 | intel_ring_setup_status_page(engine); |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 593 | else |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 594 | ring_setup_phys_status_page(engine); |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 595 | |
Jiri Kosina | ece4a17 | 2014-08-07 16:29:53 +0200 | [diff] [blame] | 596 | /* Enforce ordering by reading HEAD register back */ |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 597 | I915_READ_HEAD(engine); |
Jiri Kosina | ece4a17 | 2014-08-07 16:29:53 +0200 | [diff] [blame] | 598 | |
Daniel Vetter | 0d8957c | 2012-08-07 09:54:14 +0200 | [diff] [blame] | 599 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
| 600 | * registers with the above sequence (the readback of the HEAD registers |
| 601 | * also enforces ordering), otherwise the hw might lose the new ring |
| 602 | * register values. */ |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 603 | I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj)); |
Chris Wilson | 9546889 | 2014-08-07 15:39:54 +0100 | [diff] [blame] | 604 | |
| 605 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 606 | if (I915_READ_HEAD(engine)) |
Chris Wilson | 9546889 | 2014-08-07 15:39:54 +0100 | [diff] [blame] | 607 | DRM_DEBUG("%s initialization failed [head=%08x], fudging\n", |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 608 | engine->name, I915_READ_HEAD(engine)); |
| 609 | I915_WRITE_HEAD(engine, 0); |
| 610 | (void)I915_READ_HEAD(engine); |
Chris Wilson | 9546889 | 2014-08-07 15:39:54 +0100 | [diff] [blame] | 611 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 612 | I915_WRITE_CTL(engine, |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 613 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) |
Chris Wilson | 5d031e5 | 2012-02-08 13:34:13 +0000 | [diff] [blame] | 614 | | RING_VALID); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 615 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 616 | /* If the head is still not zero, the ring is dead */ |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 617 | if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 && |
| 618 | I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) && |
| 619 | (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) { |
Chris Wilson | e74cfed | 2010-11-09 10:16:56 +0000 | [diff] [blame] | 620 | DRM_ERROR("%s initialization failed " |
Chris Wilson | 48e48a0 | 2014-04-09 09:19:44 +0100 | [diff] [blame] | 621 | "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n", |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 622 | engine->name, |
| 623 | I915_READ_CTL(engine), |
| 624 | I915_READ_CTL(engine) & RING_VALID, |
| 625 | I915_READ_HEAD(engine), I915_READ_TAIL(engine), |
| 626 | I915_READ_START(engine), |
| 627 | (unsigned long)i915_gem_obj_ggtt_offset(obj)); |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 628 | ret = -EIO; |
| 629 | goto out; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 630 | } |
| 631 | |
Dave Gordon | ebd0fd4 | 2014-11-27 11:22:49 +0000 | [diff] [blame] | 632 | ringbuf->last_retired_head = -1; |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 633 | ringbuf->head = I915_READ_HEAD(engine); |
| 634 | ringbuf->tail = I915_READ_TAIL(engine) & TAIL_ADDR; |
Dave Gordon | ebd0fd4 | 2014-11-27 11:22:49 +0000 | [diff] [blame] | 635 | intel_ring_update_space(ringbuf); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 636 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 637 | memset(&engine->hangcheck, 0, sizeof(engine->hangcheck)); |
Chris Wilson | 50f018d | 2013-06-10 11:20:19 +0100 | [diff] [blame] | 638 | |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 639 | out: |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 640 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 641 | |
| 642 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 643 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 644 | |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 645 | void |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 646 | intel_fini_pipe_control(struct intel_engine_cs *engine) |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 647 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 648 | struct drm_device *dev = engine->dev; |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 649 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 650 | if (engine->scratch.obj == NULL) |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 651 | return; |
| 652 | |
| 653 | if (INTEL_INFO(dev)->gen >= 5) { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 654 | kunmap(sg_page(engine->scratch.obj->pages->sgl)); |
| 655 | i915_gem_object_ggtt_unpin(engine->scratch.obj); |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 656 | } |
| 657 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 658 | drm_gem_object_unreference(&engine->scratch.obj->base); |
| 659 | engine->scratch.obj = NULL; |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 660 | } |
| 661 | |
| 662 | int |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 663 | intel_init_pipe_control(struct intel_engine_cs *engine) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 664 | { |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 665 | int ret; |
| 666 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 667 | WARN_ON(engine->scratch.obj); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 668 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 669 | engine->scratch.obj = i915_gem_alloc_object(engine->dev, 4096); |
| 670 | if (engine->scratch.obj == NULL) { |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 671 | DRM_ERROR("Failed to allocate seqno page\n"); |
| 672 | ret = -ENOMEM; |
| 673 | goto err; |
| 674 | } |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 675 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 676 | ret = i915_gem_object_set_cache_level(engine->scratch.obj, |
| 677 | I915_CACHE_LLC); |
Daniel Vetter | a9cc726 | 2014-02-14 14:01:13 +0100 | [diff] [blame] | 678 | if (ret) |
| 679 | goto err_unref; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 680 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 681 | ret = i915_gem_obj_ggtt_pin(engine->scratch.obj, 4096, 0); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 682 | if (ret) |
| 683 | goto err_unref; |
| 684 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 685 | engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(engine->scratch.obj); |
| 686 | engine->scratch.cpu_page = kmap(sg_page(engine->scratch.obj->pages->sgl)); |
| 687 | if (engine->scratch.cpu_page == NULL) { |
Wei Yongjun | 56b085a | 2013-05-28 17:51:44 +0800 | [diff] [blame] | 688 | ret = -ENOMEM; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 689 | goto err_unpin; |
Wei Yongjun | 56b085a | 2013-05-28 17:51:44 +0800 | [diff] [blame] | 690 | } |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 691 | |
Ville Syrjälä | 2b1086c | 2013-02-12 22:01:38 +0200 | [diff] [blame] | 692 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 693 | engine->name, engine->scratch.gtt_offset); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 694 | return 0; |
| 695 | |
| 696 | err_unpin: |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 697 | i915_gem_object_ggtt_unpin(engine->scratch.obj); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 698 | err_unref: |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 699 | drm_gem_object_unreference(&engine->scratch.obj->base); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 700 | err: |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 701 | return ret; |
| 702 | } |
| 703 | |
John Harrison | e2be4fa | 2015-05-29 17:43:54 +0100 | [diff] [blame] | 704 | static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req) |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 705 | { |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 706 | int ret, i; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 707 | struct intel_engine_cs *engine = req->ring; |
| 708 | struct drm_device *dev = engine->dev; |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 709 | struct drm_i915_private *dev_priv = dev->dev_private; |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 710 | struct i915_workarounds *w = &dev_priv->workarounds; |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 711 | |
Francisco Jerez | 0223580 | 2015-10-07 14:44:01 +0300 | [diff] [blame] | 712 | if (w->count == 0) |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 713 | return 0; |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 714 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 715 | engine->gpu_caches_dirty = true; |
John Harrison | 4866d72 | 2015-05-29 17:43:55 +0100 | [diff] [blame] | 716 | ret = intel_ring_flush_all_caches(req); |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 717 | if (ret) |
| 718 | return ret; |
| 719 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 720 | ret = intel_ring_begin(req, (w->count * 2 + 2)); |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 721 | if (ret) |
| 722 | return ret; |
| 723 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 724 | intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(w->count)); |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 725 | for (i = 0; i < w->count; i++) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 726 | intel_ring_emit_reg(engine, w->reg[i].addr); |
| 727 | intel_ring_emit(engine, w->reg[i].value); |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 728 | } |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 729 | intel_ring_emit(engine, MI_NOOP); |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 730 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 731 | intel_ring_advance(engine); |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 732 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 733 | engine->gpu_caches_dirty = true; |
John Harrison | 4866d72 | 2015-05-29 17:43:55 +0100 | [diff] [blame] | 734 | ret = intel_ring_flush_all_caches(req); |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 735 | if (ret) |
| 736 | return ret; |
| 737 | |
| 738 | DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count); |
| 739 | |
| 740 | return 0; |
| 741 | } |
| 742 | |
John Harrison | 8753181 | 2015-05-29 17:43:44 +0100 | [diff] [blame] | 743 | static int intel_rcs_ctx_init(struct drm_i915_gem_request *req) |
Daniel Vetter | 8f0e2b9 | 2014-12-02 16:19:07 +0100 | [diff] [blame] | 744 | { |
| 745 | int ret; |
| 746 | |
John Harrison | e2be4fa | 2015-05-29 17:43:54 +0100 | [diff] [blame] | 747 | ret = intel_ring_workarounds_emit(req); |
Daniel Vetter | 8f0e2b9 | 2014-12-02 16:19:07 +0100 | [diff] [blame] | 748 | if (ret != 0) |
| 749 | return ret; |
| 750 | |
John Harrison | be01363 | 2015-05-29 17:43:45 +0100 | [diff] [blame] | 751 | ret = i915_gem_render_state_init(req); |
Daniel Vetter | 8f0e2b9 | 2014-12-02 16:19:07 +0100 | [diff] [blame] | 752 | if (ret) |
Chris Wilson | e26e1b9 | 2016-01-29 16:49:05 +0000 | [diff] [blame] | 753 | return ret; |
Daniel Vetter | 8f0e2b9 | 2014-12-02 16:19:07 +0100 | [diff] [blame] | 754 | |
Chris Wilson | e26e1b9 | 2016-01-29 16:49:05 +0000 | [diff] [blame] | 755 | return 0; |
Daniel Vetter | 8f0e2b9 | 2014-12-02 16:19:07 +0100 | [diff] [blame] | 756 | } |
| 757 | |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 758 | static int wa_add(struct drm_i915_private *dev_priv, |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 759 | i915_reg_t addr, |
| 760 | const u32 mask, const u32 val) |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 761 | { |
| 762 | const u32 idx = dev_priv->workarounds.count; |
| 763 | |
| 764 | if (WARN_ON(idx >= I915_MAX_WA_REGS)) |
| 765 | return -ENOSPC; |
| 766 | |
| 767 | dev_priv->workarounds.reg[idx].addr = addr; |
| 768 | dev_priv->workarounds.reg[idx].value = val; |
| 769 | dev_priv->workarounds.reg[idx].mask = mask; |
| 770 | |
| 771 | dev_priv->workarounds.count++; |
| 772 | |
| 773 | return 0; |
| 774 | } |
| 775 | |
Mika Kuoppala | ca5a0fb | 2015-08-11 15:44:31 +0100 | [diff] [blame] | 776 | #define WA_REG(addr, mask, val) do { \ |
Damien Lespiau | cf4b0de | 2014-12-08 17:35:37 +0000 | [diff] [blame] | 777 | const int r = wa_add(dev_priv, (addr), (mask), (val)); \ |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 778 | if (r) \ |
| 779 | return r; \ |
Mika Kuoppala | ca5a0fb | 2015-08-11 15:44:31 +0100 | [diff] [blame] | 780 | } while (0) |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 781 | |
| 782 | #define WA_SET_BIT_MASKED(addr, mask) \ |
Damien Lespiau | 2645934 | 2014-12-08 17:35:38 +0000 | [diff] [blame] | 783 | WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask)) |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 784 | |
| 785 | #define WA_CLR_BIT_MASKED(addr, mask) \ |
Damien Lespiau | 2645934 | 2014-12-08 17:35:38 +0000 | [diff] [blame] | 786 | WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask)) |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 787 | |
Damien Lespiau | 9853325 | 2014-12-08 17:33:51 +0000 | [diff] [blame] | 788 | #define WA_SET_FIELD_MASKED(addr, mask, value) \ |
Damien Lespiau | cf4b0de | 2014-12-08 17:35:37 +0000 | [diff] [blame] | 789 | WA_REG(addr, mask, _MASKED_FIELD(mask, value)) |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 790 | |
Damien Lespiau | cf4b0de | 2014-12-08 17:35:37 +0000 | [diff] [blame] | 791 | #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask)) |
| 792 | #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask)) |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 793 | |
Damien Lespiau | cf4b0de | 2014-12-08 17:35:37 +0000 | [diff] [blame] | 794 | #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val) |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 795 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 796 | static int wa_ring_whitelist_reg(struct intel_engine_cs *engine, |
| 797 | i915_reg_t reg) |
Arun Siluvery | 33136b0 | 2016-01-21 21:43:47 +0000 | [diff] [blame] | 798 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 799 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
Arun Siluvery | 33136b0 | 2016-01-21 21:43:47 +0000 | [diff] [blame] | 800 | struct i915_workarounds *wa = &dev_priv->workarounds; |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 801 | const uint32_t index = wa->hw_whitelist_count[engine->id]; |
Arun Siluvery | 33136b0 | 2016-01-21 21:43:47 +0000 | [diff] [blame] | 802 | |
| 803 | if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS)) |
| 804 | return -EINVAL; |
| 805 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 806 | WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index), |
Arun Siluvery | 33136b0 | 2016-01-21 21:43:47 +0000 | [diff] [blame] | 807 | i915_mmio_reg_offset(reg)); |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 808 | wa->hw_whitelist_count[engine->id]++; |
Arun Siluvery | 33136b0 | 2016-01-21 21:43:47 +0000 | [diff] [blame] | 809 | |
| 810 | return 0; |
| 811 | } |
| 812 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 813 | static int gen8_init_workarounds(struct intel_engine_cs *engine) |
Arun Siluvery | e9a64ad | 2015-09-25 17:40:37 +0100 | [diff] [blame] | 814 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 815 | struct drm_device *dev = engine->dev; |
Arun Siluvery | 68c6198 | 2015-09-25 17:40:38 +0100 | [diff] [blame] | 816 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 817 | |
| 818 | WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); |
Arun Siluvery | e9a64ad | 2015-09-25 17:40:37 +0100 | [diff] [blame] | 819 | |
Arun Siluvery | 717d84d | 2015-09-25 17:40:39 +0100 | [diff] [blame] | 820 | /* WaDisableAsyncFlipPerfMode:bdw,chv */ |
| 821 | WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE); |
| 822 | |
Arun Siluvery | d058119 | 2015-09-25 17:40:40 +0100 | [diff] [blame] | 823 | /* WaDisablePartialInstShootdown:bdw,chv */ |
| 824 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
| 825 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); |
| 826 | |
Arun Siluvery | a340af5 | 2015-09-25 17:40:45 +0100 | [diff] [blame] | 827 | /* Use Force Non-Coherent whenever executing a 3D context. This is a |
| 828 | * workaround for for a possible hang in the unlikely event a TLB |
| 829 | * invalidation occurs during a PSD flush. |
| 830 | */ |
| 831 | /* WaForceEnableNonCoherent:bdw,chv */ |
Arun Siluvery | 120f5d2 | 2015-09-25 17:40:46 +0100 | [diff] [blame] | 832 | /* WaHdcDisableFetchWhenMasked:bdw,chv */ |
Arun Siluvery | a340af5 | 2015-09-25 17:40:45 +0100 | [diff] [blame] | 833 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
Arun Siluvery | 120f5d2 | 2015-09-25 17:40:46 +0100 | [diff] [blame] | 834 | HDC_DONOT_FETCH_MEM_WHEN_MASKED | |
Arun Siluvery | a340af5 | 2015-09-25 17:40:45 +0100 | [diff] [blame] | 835 | HDC_FORCE_NON_COHERENT); |
| 836 | |
Arun Siluvery | 6def8fd | 2015-09-25 17:40:42 +0100 | [diff] [blame] | 837 | /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: |
| 838 | * "The Hierarchical Z RAW Stall Optimization allows non-overlapping |
| 839 | * polygons in the same 8x4 pixel/sample area to be processed without |
| 840 | * stalling waiting for the earlier ones to write to Hierarchical Z |
| 841 | * buffer." |
| 842 | * |
| 843 | * This optimization is off by default for BDW and CHV; turn it on. |
| 844 | */ |
| 845 | WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); |
| 846 | |
Arun Siluvery | 4840463 | 2015-09-25 17:40:43 +0100 | [diff] [blame] | 847 | /* Wa4x4STCOptimizationDisable:bdw,chv */ |
| 848 | WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); |
| 849 | |
Arun Siluvery | 7eebcde | 2015-09-25 17:40:44 +0100 | [diff] [blame] | 850 | /* |
| 851 | * BSpec recommends 8x4 when MSAA is used, |
| 852 | * however in practice 16x4 seems fastest. |
| 853 | * |
| 854 | * Note that PS/WM thread counts depend on the WIZ hashing |
| 855 | * disable bit, which we don't touch here, but it's good |
| 856 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). |
| 857 | */ |
| 858 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, |
| 859 | GEN6_WIZ_HASHING_MASK, |
| 860 | GEN6_WIZ_HASHING_16x4); |
| 861 | |
Arun Siluvery | e9a64ad | 2015-09-25 17:40:37 +0100 | [diff] [blame] | 862 | return 0; |
| 863 | } |
| 864 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 865 | static int bdw_init_workarounds(struct intel_engine_cs *engine) |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 866 | { |
Arun Siluvery | e9a64ad | 2015-09-25 17:40:37 +0100 | [diff] [blame] | 867 | int ret; |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 868 | struct drm_device *dev = engine->dev; |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 869 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 870 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 871 | ret = gen8_init_workarounds(engine); |
Arun Siluvery | e9a64ad | 2015-09-25 17:40:37 +0100 | [diff] [blame] | 872 | if (ret) |
| 873 | return ret; |
| 874 | |
Rodrigo Vivi | 101b376 | 2014-10-09 07:11:47 -0700 | [diff] [blame] | 875 | /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ |
Arun Siluvery | d058119 | 2015-09-25 17:40:40 +0100 | [diff] [blame] | 876 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 877 | |
Rodrigo Vivi | 101b376 | 2014-10-09 07:11:47 -0700 | [diff] [blame] | 878 | /* WaDisableDopClockGating:bdw */ |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 879 | WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, |
| 880 | DOP_CLOCK_GATING_DISABLE); |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 881 | |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 882 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
| 883 | GEN8_SAMPLER_POWER_BYPASS_DIS); |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 884 | |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 885 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
Damien Lespiau | 35cb6f3 | 2015-02-10 10:31:00 +0000 | [diff] [blame] | 886 | /* WaForceContextSaveRestoreNonCoherent:bdw */ |
| 887 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | |
Damien Lespiau | 35cb6f3 | 2015-02-10 10:31:00 +0000 | [diff] [blame] | 888 | /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 889 | (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 890 | |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 891 | return 0; |
| 892 | } |
| 893 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 894 | static int chv_init_workarounds(struct intel_engine_cs *engine) |
Ville Syrjälä | 00e1e62 | 2014-08-27 17:33:12 +0300 | [diff] [blame] | 895 | { |
Arun Siluvery | e9a64ad | 2015-09-25 17:40:37 +0100 | [diff] [blame] | 896 | int ret; |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 897 | struct drm_device *dev = engine->dev; |
Ville Syrjälä | 00e1e62 | 2014-08-27 17:33:12 +0300 | [diff] [blame] | 898 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 899 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 900 | ret = gen8_init_workarounds(engine); |
Arun Siluvery | e9a64ad | 2015-09-25 17:40:37 +0100 | [diff] [blame] | 901 | if (ret) |
| 902 | return ret; |
| 903 | |
Ville Syrjälä | 00e1e62 | 2014-08-27 17:33:12 +0300 | [diff] [blame] | 904 | /* WaDisableThreadStallDopClockGating:chv */ |
Arun Siluvery | d058119 | 2015-09-25 17:40:40 +0100 | [diff] [blame] | 905 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); |
Ville Syrjälä | 00e1e62 | 2014-08-27 17:33:12 +0300 | [diff] [blame] | 906 | |
Kenneth Graunke | d60de81 | 2015-01-10 18:02:22 -0800 | [diff] [blame] | 907 | /* Improve HiZ throughput on CHV. */ |
| 908 | WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); |
| 909 | |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 910 | return 0; |
| 911 | } |
| 912 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 913 | static int gen9_init_workarounds(struct intel_engine_cs *engine) |
Hoath, Nicholas | 3b10653 | 2015-02-05 10:47:16 +0000 | [diff] [blame] | 914 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 915 | struct drm_device *dev = engine->dev; |
Hoath, Nicholas | ab0dfaf | 2015-02-05 10:47:18 +0000 | [diff] [blame] | 916 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | 8ea6f89 | 2015-05-19 17:05:42 +0300 | [diff] [blame] | 917 | uint32_t tmp; |
Arun Siluvery | e0f3fa0 | 2016-01-21 21:43:48 +0000 | [diff] [blame] | 918 | int ret; |
Hoath, Nicholas | ab0dfaf | 2015-02-05 10:47:18 +0000 | [diff] [blame] | 919 | |
Mika Kuoppala | 9c4cbf8 | 2015-10-12 13:20:59 +0300 | [diff] [blame] | 920 | /* WaEnableLbsSlaRetryTimerDecrement:skl */ |
| 921 | I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | |
| 922 | GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); |
| 923 | |
| 924 | /* WaDisableKillLogic:bxt,skl */ |
| 925 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | |
| 926 | ECOCHK_DIS_TLB); |
| 927 | |
Nick Hoath | b0e6f6d | 2015-05-07 14:15:29 +0100 | [diff] [blame] | 928 | /* WaDisablePartialInstShootdown:skl,bxt */ |
Hoath, Nicholas | ab0dfaf | 2015-02-05 10:47:18 +0000 | [diff] [blame] | 929 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
| 930 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); |
| 931 | |
Nick Hoath | a119a6e | 2015-05-07 14:15:30 +0100 | [diff] [blame] | 932 | /* Syncing dependencies between camera and graphics:skl,bxt */ |
Nick Hoath | 8424171 | 2015-02-05 10:47:20 +0000 | [diff] [blame] | 933 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
| 934 | GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC); |
| 935 | |
Jani Nikula | e87a005 | 2015-10-20 15:22:02 +0300 | [diff] [blame] | 936 | /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */ |
| 937 | if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) || |
| 938 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) |
Damien Lespiau | a86eb58 | 2015-02-11 18:21:44 +0000 | [diff] [blame] | 939 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
| 940 | GEN9_DG_MIRROR_FIX_ENABLE); |
Nick Hoath | 1de4582 | 2015-02-05 10:47:19 +0000 | [diff] [blame] | 941 | |
Jani Nikula | e87a005 | 2015-10-20 15:22:02 +0300 | [diff] [blame] | 942 | /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ |
| 943 | if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) || |
| 944 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { |
Damien Lespiau | 183c6da | 2015-02-09 19:33:11 +0000 | [diff] [blame] | 945 | WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1, |
| 946 | GEN9_RHWO_OPTIMIZATION_DISABLE); |
Arun Siluvery | 9b01435 | 2015-07-14 15:01:30 +0100 | [diff] [blame] | 947 | /* |
| 948 | * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set |
| 949 | * but we do that in per ctx batchbuffer as there is an issue |
| 950 | * with this register not getting restored on ctx restore |
| 951 | */ |
Damien Lespiau | 183c6da | 2015-02-09 19:33:11 +0000 | [diff] [blame] | 952 | } |
| 953 | |
Jani Nikula | e87a005 | 2015-10-20 15:22:02 +0300 | [diff] [blame] | 954 | /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */ |
| 955 | if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER) || IS_BROXTON(dev)) |
Nick Hoath | cac23df | 2015-02-05 10:47:22 +0000 | [diff] [blame] | 956 | WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, |
| 957 | GEN9_ENABLE_YV12_BUGFIX); |
Nick Hoath | cac23df | 2015-02-05 10:47:22 +0000 | [diff] [blame] | 958 | |
Nick Hoath | 5068368 | 2015-05-07 14:15:35 +0100 | [diff] [blame] | 959 | /* Wa4x4STCOptimizationDisable:skl,bxt */ |
Nick Hoath | 27160c9 | 2015-05-07 14:15:36 +0100 | [diff] [blame] | 960 | /* WaDisablePartialResolveInVc:skl,bxt */ |
Arun Siluvery | 6029468 | 2015-09-25 14:33:37 +0100 | [diff] [blame] | 961 | WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE | |
| 962 | GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE)); |
Damien Lespiau | 9370cd9 | 2015-02-09 19:33:17 +0000 | [diff] [blame] | 963 | |
Nick Hoath | 16be17a | 2015-05-07 14:15:37 +0100 | [diff] [blame] | 964 | /* WaCcsTlbPrefetchDisable:skl,bxt */ |
Damien Lespiau | e2db707 | 2015-02-09 19:33:21 +0000 | [diff] [blame] | 965 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
| 966 | GEN9_CCS_TLB_PREFETCH_ENABLE); |
| 967 | |
Imre Deak | 5a2ae95 | 2015-05-19 15:04:59 +0300 | [diff] [blame] | 968 | /* WaDisableMaskBasedCammingInRCC:skl,bxt */ |
Jani Nikula | e87a005 | 2015-10-20 15:22:02 +0300 | [diff] [blame] | 969 | if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_C0) || |
| 970 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) |
Ben Widawsky | 38a39a7 | 2015-03-11 10:54:53 +0200 | [diff] [blame] | 971 | WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, |
| 972 | PIXEL_MASK_CAMMING_DISABLE); |
| 973 | |
Imre Deak | 8ea6f89 | 2015-05-19 17:05:42 +0300 | [diff] [blame] | 974 | /* WaForceContextSaveRestoreNonCoherent:skl,bxt */ |
| 975 | tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT; |
Jani Nikula | e87a005 | 2015-10-20 15:22:02 +0300 | [diff] [blame] | 976 | if (IS_SKL_REVID(dev, SKL_REVID_F0, SKL_REVID_F0) || |
| 977 | IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER)) |
Imre Deak | 8ea6f89 | 2015-05-19 17:05:42 +0300 | [diff] [blame] | 978 | tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE; |
| 979 | WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp); |
| 980 | |
Arun Siluvery | 8c76160 | 2015-09-08 10:31:48 +0100 | [diff] [blame] | 981 | /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */ |
Jani Nikula | e87a005 | 2015-10-20 15:22:02 +0300 | [diff] [blame] | 982 | if (IS_SKYLAKE(dev) || IS_BXT_REVID(dev, 0, BXT_REVID_B0)) |
Arun Siluvery | 8c76160 | 2015-09-08 10:31:48 +0100 | [diff] [blame] | 983 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
| 984 | GEN8_SAMPLER_POWER_BYPASS_DIS); |
Arun Siluvery | 8c76160 | 2015-09-08 10:31:48 +0100 | [diff] [blame] | 985 | |
Robert Beckett | 6b6d562 | 2015-09-08 10:31:52 +0100 | [diff] [blame] | 986 | /* WaDisableSTUnitPowerOptimization:skl,bxt */ |
| 987 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); |
| 988 | |
Arun Siluvery | 6ecf56a | 2016-01-21 21:43:54 +0000 | [diff] [blame] | 989 | /* WaOCLCoherentLineFlush:skl,bxt */ |
| 990 | I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | |
| 991 | GEN8_LQSC_FLUSH_COHERENT_LINES)); |
| 992 | |
Arun Siluvery | e0f3fa0 | 2016-01-21 21:43:48 +0000 | [diff] [blame] | 993 | /* WaEnablePreemptionGranularityControlByUMD:skl,bxt */ |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 994 | ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); |
Arun Siluvery | e0f3fa0 | 2016-01-21 21:43:48 +0000 | [diff] [blame] | 995 | if (ret) |
| 996 | return ret; |
| 997 | |
Arun Siluvery | 3669ab6 | 2016-01-21 21:43:49 +0000 | [diff] [blame] | 998 | /* WaAllowUMDToModifyHDCChicken1:skl,bxt */ |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 999 | ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1); |
Arun Siluvery | 3669ab6 | 2016-01-21 21:43:49 +0000 | [diff] [blame] | 1000 | if (ret) |
| 1001 | return ret; |
| 1002 | |
Hoath, Nicholas | 3b10653 | 2015-02-05 10:47:16 +0000 | [diff] [blame] | 1003 | return 0; |
| 1004 | } |
| 1005 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1006 | static int skl_tune_iz_hashing(struct intel_engine_cs *engine) |
Damien Lespiau | 8d20549 | 2015-02-09 19:33:15 +0000 | [diff] [blame] | 1007 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1008 | struct drm_device *dev = engine->dev; |
Damien Lespiau | b766879 | 2015-02-14 18:30:29 +0000 | [diff] [blame] | 1009 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1010 | u8 vals[3] = { 0, 0, 0 }; |
| 1011 | unsigned int i; |
| 1012 | |
| 1013 | for (i = 0; i < 3; i++) { |
| 1014 | u8 ss; |
| 1015 | |
| 1016 | /* |
| 1017 | * Only consider slices where one, and only one, subslice has 7 |
| 1018 | * EUs |
| 1019 | */ |
Zeng Zhaoxiu | a4d8a0f | 2015-12-06 18:26:30 +0800 | [diff] [blame] | 1020 | if (!is_power_of_2(dev_priv->info.subslice_7eu[i])) |
Damien Lespiau | b766879 | 2015-02-14 18:30:29 +0000 | [diff] [blame] | 1021 | continue; |
| 1022 | |
| 1023 | /* |
| 1024 | * subslice_7eu[i] != 0 (because of the check above) and |
| 1025 | * ss_max == 4 (maximum number of subslices possible per slice) |
| 1026 | * |
| 1027 | * -> 0 <= ss <= 3; |
| 1028 | */ |
| 1029 | ss = ffs(dev_priv->info.subslice_7eu[i]) - 1; |
| 1030 | vals[i] = 3 - ss; |
| 1031 | } |
| 1032 | |
| 1033 | if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) |
| 1034 | return 0; |
| 1035 | |
| 1036 | /* Tune IZ hashing. See intel_device_info_runtime_init() */ |
| 1037 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, |
| 1038 | GEN9_IZ_HASHING_MASK(2) | |
| 1039 | GEN9_IZ_HASHING_MASK(1) | |
| 1040 | GEN9_IZ_HASHING_MASK(0), |
| 1041 | GEN9_IZ_HASHING(2, vals[2]) | |
| 1042 | GEN9_IZ_HASHING(1, vals[1]) | |
| 1043 | GEN9_IZ_HASHING(0, vals[0])); |
Damien Lespiau | 8d20549 | 2015-02-09 19:33:15 +0000 | [diff] [blame] | 1044 | |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 1045 | return 0; |
| 1046 | } |
| 1047 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1048 | static int skl_init_workarounds(struct intel_engine_cs *engine) |
Damien Lespiau | 8d20549 | 2015-02-09 19:33:15 +0000 | [diff] [blame] | 1049 | { |
Arun Siluvery | aa0011a | 2015-09-25 14:33:35 +0100 | [diff] [blame] | 1050 | int ret; |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1051 | struct drm_device *dev = engine->dev; |
Damien Lespiau | d0bbbc4 | 2015-02-09 19:33:16 +0000 | [diff] [blame] | 1052 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1053 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1054 | ret = gen9_init_workarounds(engine); |
Arun Siluvery | aa0011a | 2015-09-25 14:33:35 +0100 | [diff] [blame] | 1055 | if (ret) |
| 1056 | return ret; |
Damien Lespiau | 8d20549 | 2015-02-09 19:33:15 +0000 | [diff] [blame] | 1057 | |
Arun Siluvery | a78536e | 2016-01-21 21:43:53 +0000 | [diff] [blame] | 1058 | /* |
| 1059 | * Actual WA is to disable percontext preemption granularity control |
| 1060 | * until D0 which is the default case so this is equivalent to |
| 1061 | * !WaDisablePerCtxtPreemptionGranularityControl:skl |
| 1062 | */ |
| 1063 | if (IS_SKL_REVID(dev, SKL_REVID_E0, REVID_FOREVER)) { |
| 1064 | I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1, |
| 1065 | _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL)); |
| 1066 | } |
| 1067 | |
Jani Nikula | e87a005 | 2015-10-20 15:22:02 +0300 | [diff] [blame] | 1068 | if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) { |
Mika Kuoppala | 9c4cbf8 | 2015-10-12 13:20:59 +0300 | [diff] [blame] | 1069 | /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */ |
| 1070 | I915_WRITE(FF_SLICE_CS_CHICKEN2, |
| 1071 | _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE)); |
| 1072 | } |
| 1073 | |
| 1074 | /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes |
| 1075 | * involving this register should also be added to WA batch as required. |
| 1076 | */ |
Jani Nikula | e87a005 | 2015-10-20 15:22:02 +0300 | [diff] [blame] | 1077 | if (IS_SKL_REVID(dev, 0, SKL_REVID_E0)) |
Mika Kuoppala | 9c4cbf8 | 2015-10-12 13:20:59 +0300 | [diff] [blame] | 1078 | /* WaDisableLSQCROPERFforOCL:skl */ |
| 1079 | I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | |
| 1080 | GEN8_LQSC_RO_PERF_DIS); |
| 1081 | |
| 1082 | /* WaEnableGapsTsvCreditFix:skl */ |
Jani Nikula | e87a005 | 2015-10-20 15:22:02 +0300 | [diff] [blame] | 1083 | if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER)) { |
Mika Kuoppala | 9c4cbf8 | 2015-10-12 13:20:59 +0300 | [diff] [blame] | 1084 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | |
| 1085 | GEN9_GAPS_TSV_CREDIT_DISABLE)); |
| 1086 | } |
| 1087 | |
Damien Lespiau | d0bbbc4 | 2015-02-09 19:33:16 +0000 | [diff] [blame] | 1088 | /* WaDisablePowerCompilerClockGating:skl */ |
Jani Nikula | e87a005 | 2015-10-20 15:22:02 +0300 | [diff] [blame] | 1089 | if (IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0)) |
Damien Lespiau | d0bbbc4 | 2015-02-09 19:33:16 +0000 | [diff] [blame] | 1090 | WA_SET_BIT_MASKED(HIZ_CHICKEN, |
| 1091 | BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE); |
| 1092 | |
Mika Kuoppala | e238659 | 2015-12-18 16:14:53 +0200 | [diff] [blame] | 1093 | if (IS_SKL_REVID(dev, 0, SKL_REVID_F0)) { |
Nick Hoath | b62adbd | 2015-05-07 14:15:34 +0100 | [diff] [blame] | 1094 | /* |
| 1095 | *Use Force Non-Coherent whenever executing a 3D context. This |
| 1096 | * is a workaround for a possible hang in the unlikely event |
| 1097 | * a TLB invalidation occurs during a PSD flush. |
| 1098 | */ |
| 1099 | /* WaForceEnableNonCoherent:skl */ |
| 1100 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
| 1101 | HDC_FORCE_NON_COHERENT); |
Mika Kuoppala | e238659 | 2015-12-18 16:14:53 +0200 | [diff] [blame] | 1102 | |
| 1103 | /* WaDisableHDCInvalidation:skl */ |
| 1104 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | |
| 1105 | BDW_DISABLE_HDC_INVALIDATION); |
Nick Hoath | b62adbd | 2015-05-07 14:15:34 +0100 | [diff] [blame] | 1106 | } |
| 1107 | |
Jani Nikula | e87a005 | 2015-10-20 15:22:02 +0300 | [diff] [blame] | 1108 | /* WaBarrierPerformanceFixDisable:skl */ |
| 1109 | if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0)) |
Ville Syrjälä | 5b6fd12 | 2015-06-02 15:37:35 +0300 | [diff] [blame] | 1110 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
| 1111 | HDC_FENCE_DEST_SLM_DISABLE | |
| 1112 | HDC_BARRIER_PERFORMANCE_DISABLE); |
| 1113 | |
Mika Kuoppala | 9bd9dfb | 2015-08-06 16:51:00 +0300 | [diff] [blame] | 1114 | /* WaDisableSbeCacheDispatchPortSharing:skl */ |
Jani Nikula | e87a005 | 2015-10-20 15:22:02 +0300 | [diff] [blame] | 1115 | if (IS_SKL_REVID(dev, 0, SKL_REVID_F0)) |
Mika Kuoppala | 9bd9dfb | 2015-08-06 16:51:00 +0300 | [diff] [blame] | 1116 | WA_SET_BIT_MASKED( |
| 1117 | GEN7_HALF_SLICE_CHICKEN1, |
| 1118 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); |
Mika Kuoppala | 9bd9dfb | 2015-08-06 16:51:00 +0300 | [diff] [blame] | 1119 | |
Arun Siluvery | 6107497 | 2016-01-21 21:43:52 +0000 | [diff] [blame] | 1120 | /* WaDisableLSQCROPERFforOCL:skl */ |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1121 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); |
Arun Siluvery | 6107497 | 2016-01-21 21:43:52 +0000 | [diff] [blame] | 1122 | if (ret) |
| 1123 | return ret; |
| 1124 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1125 | return skl_tune_iz_hashing(engine); |
Damien Lespiau | 8d20549 | 2015-02-09 19:33:15 +0000 | [diff] [blame] | 1126 | } |
| 1127 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1128 | static int bxt_init_workarounds(struct intel_engine_cs *engine) |
Nick Hoath | cae0437 | 2015-03-17 11:39:38 +0200 | [diff] [blame] | 1129 | { |
Arun Siluvery | aa0011a | 2015-09-25 14:33:35 +0100 | [diff] [blame] | 1130 | int ret; |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1131 | struct drm_device *dev = engine->dev; |
Nick Hoath | dfb601e | 2015-04-10 13:12:24 +0100 | [diff] [blame] | 1132 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1133 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1134 | ret = gen9_init_workarounds(engine); |
Arun Siluvery | aa0011a | 2015-09-25 14:33:35 +0100 | [diff] [blame] | 1135 | if (ret) |
| 1136 | return ret; |
Nick Hoath | cae0437 | 2015-03-17 11:39:38 +0200 | [diff] [blame] | 1137 | |
Mika Kuoppala | 9c4cbf8 | 2015-10-12 13:20:59 +0300 | [diff] [blame] | 1138 | /* WaStoreMultiplePTEenable:bxt */ |
| 1139 | /* This is a requirement according to Hardware specification */ |
Tim Gore | cbdc12a | 2015-10-26 10:48:58 +0000 | [diff] [blame] | 1140 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) |
Mika Kuoppala | 9c4cbf8 | 2015-10-12 13:20:59 +0300 | [diff] [blame] | 1141 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF); |
| 1142 | |
| 1143 | /* WaSetClckGatingDisableMedia:bxt */ |
Tim Gore | cbdc12a | 2015-10-26 10:48:58 +0000 | [diff] [blame] | 1144 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { |
Mika Kuoppala | 9c4cbf8 | 2015-10-12 13:20:59 +0300 | [diff] [blame] | 1145 | I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) & |
| 1146 | ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE)); |
| 1147 | } |
| 1148 | |
Nick Hoath | dfb601e | 2015-04-10 13:12:24 +0100 | [diff] [blame] | 1149 | /* WaDisableThreadStallDopClockGating:bxt */ |
| 1150 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
| 1151 | STALL_DOP_GATING_DISABLE); |
| 1152 | |
Nick Hoath | 983b4b9 | 2015-04-10 13:12:25 +0100 | [diff] [blame] | 1153 | /* WaDisableSbeCacheDispatchPortSharing:bxt */ |
Jani Nikula | e87a005 | 2015-10-20 15:22:02 +0300 | [diff] [blame] | 1154 | if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) { |
Nick Hoath | 983b4b9 | 2015-04-10 13:12:25 +0100 | [diff] [blame] | 1155 | WA_SET_BIT_MASKED( |
| 1156 | GEN7_HALF_SLICE_CHICKEN1, |
| 1157 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); |
| 1158 | } |
| 1159 | |
Arun Siluvery | 2c8580e | 2016-01-21 21:43:50 +0000 | [diff] [blame] | 1160 | /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */ |
| 1161 | /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */ |
| 1162 | /* WaDisableObjectLevelPreemtionForInstanceId:bxt */ |
Arun Siluvery | a786d53 | 2016-01-21 21:43:51 +0000 | [diff] [blame] | 1163 | /* WaDisableLSQCROPERFforOCL:bxt */ |
Arun Siluvery | 2c8580e | 2016-01-21 21:43:50 +0000 | [diff] [blame] | 1164 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1165 | ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1); |
Arun Siluvery | 2c8580e | 2016-01-21 21:43:50 +0000 | [diff] [blame] | 1166 | if (ret) |
| 1167 | return ret; |
Arun Siluvery | a786d53 | 2016-01-21 21:43:51 +0000 | [diff] [blame] | 1168 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1169 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); |
Arun Siluvery | a786d53 | 2016-01-21 21:43:51 +0000 | [diff] [blame] | 1170 | if (ret) |
| 1171 | return ret; |
Arun Siluvery | 2c8580e | 2016-01-21 21:43:50 +0000 | [diff] [blame] | 1172 | } |
| 1173 | |
Nick Hoath | cae0437 | 2015-03-17 11:39:38 +0200 | [diff] [blame] | 1174 | return 0; |
| 1175 | } |
| 1176 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1177 | int init_workarounds_ring(struct intel_engine_cs *engine) |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 1178 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1179 | struct drm_device *dev = engine->dev; |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 1180 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1181 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1182 | WARN_ON(engine->id != RCS); |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 1183 | |
| 1184 | dev_priv->workarounds.count = 0; |
Arun Siluvery | 33136b0 | 2016-01-21 21:43:47 +0000 | [diff] [blame] | 1185 | dev_priv->workarounds.hw_whitelist_count[RCS] = 0; |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 1186 | |
| 1187 | if (IS_BROADWELL(dev)) |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1188 | return bdw_init_workarounds(engine); |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 1189 | |
| 1190 | if (IS_CHERRYVIEW(dev)) |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1191 | return chv_init_workarounds(engine); |
Ville Syrjälä | 00e1e62 | 2014-08-27 17:33:12 +0300 | [diff] [blame] | 1192 | |
Damien Lespiau | 8d20549 | 2015-02-09 19:33:15 +0000 | [diff] [blame] | 1193 | if (IS_SKYLAKE(dev)) |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1194 | return skl_init_workarounds(engine); |
Nick Hoath | cae0437 | 2015-03-17 11:39:38 +0200 | [diff] [blame] | 1195 | |
| 1196 | if (IS_BROXTON(dev)) |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1197 | return bxt_init_workarounds(engine); |
Hoath, Nicholas | 3b10653 | 2015-02-05 10:47:16 +0000 | [diff] [blame] | 1198 | |
Ville Syrjälä | 00e1e62 | 2014-08-27 17:33:12 +0300 | [diff] [blame] | 1199 | return 0; |
| 1200 | } |
| 1201 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1202 | static int init_render_ring(struct intel_engine_cs *engine) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1203 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1204 | struct drm_device *dev = engine->dev; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1205 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1206 | int ret = init_ring_common(engine); |
Konrad Zapalowicz | 9c33baa | 2014-06-19 19:07:15 +0200 | [diff] [blame] | 1207 | if (ret) |
| 1208 | return ret; |
Zhenyu Wang | a69ffdb | 2010-08-30 16:12:42 +0800 | [diff] [blame] | 1209 | |
Akash Goel | 61a563a | 2014-03-25 18:01:50 +0530 | [diff] [blame] | 1210 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
| 1211 | if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 1212 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 1213 | |
| 1214 | /* We need to disable the AsyncFlip performance optimisations in order |
| 1215 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be |
| 1216 | * programmed to '1' on all products. |
Damien Lespiau | 8693a82 | 2013-05-03 18:48:11 +0100 | [diff] [blame] | 1217 | * |
Ville Syrjälä | 2441f87 | 2015-06-02 15:37:37 +0300 | [diff] [blame] | 1218 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 1219 | */ |
Ville Syrjälä | 2441f87 | 2015-06-02 15:37:37 +0300 | [diff] [blame] | 1220 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 1221 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
| 1222 | |
Chris Wilson | f05bb0c | 2013-01-20 16:33:32 +0000 | [diff] [blame] | 1223 | /* Required for the hardware to program scanline values for waiting */ |
Akash Goel | 01fa030 | 2014-03-24 23:00:04 +0530 | [diff] [blame] | 1224 | /* WaEnableFlushTlbInvalidationMode:snb */ |
Chris Wilson | f05bb0c | 2013-01-20 16:33:32 +0000 | [diff] [blame] | 1225 | if (INTEL_INFO(dev)->gen == 6) |
| 1226 | I915_WRITE(GFX_MODE, |
Chris Wilson | aa83e30 | 2014-03-21 17:18:54 +0000 | [diff] [blame] | 1227 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
Chris Wilson | f05bb0c | 2013-01-20 16:33:32 +0000 | [diff] [blame] | 1228 | |
Akash Goel | 01fa030 | 2014-03-24 23:00:04 +0530 | [diff] [blame] | 1229 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 1230 | if (IS_GEN7(dev)) |
| 1231 | I915_WRITE(GFX_MODE_GEN7, |
Akash Goel | 01fa030 | 2014-03-24 23:00:04 +0530 | [diff] [blame] | 1232 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 1233 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1234 | |
Daniel Vetter | 5e13a0c | 2012-05-08 13:39:59 +0200 | [diff] [blame] | 1235 | if (IS_GEN6(dev)) { |
Kenneth Graunke | 3a69ddd | 2012-04-27 12:44:41 -0700 | [diff] [blame] | 1236 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
| 1237 | * "If this bit is set, STCunit will have LRA as replacement |
| 1238 | * policy. [...] This bit must be reset. LRA replacement |
| 1239 | * policy is not supported." |
| 1240 | */ |
| 1241 | I915_WRITE(CACHE_MODE_0, |
Daniel Vetter | 5e13a0c | 2012-05-08 13:39:59 +0200 | [diff] [blame] | 1242 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
Ben Widawsky | 84f9f93 | 2011-12-12 19:21:58 -0800 | [diff] [blame] | 1243 | } |
| 1244 | |
Ville Syrjälä | 9cc8302 | 2015-06-02 15:37:36 +0300 | [diff] [blame] | 1245 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 1246 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1247 | |
Ben Widawsky | 040d2ba | 2013-09-19 11:01:40 -0700 | [diff] [blame] | 1248 | if (HAS_L3_DPF(dev)) |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1249 | I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev)); |
Ben Widawsky | 15b9f80 | 2012-05-25 16:56:23 -0700 | [diff] [blame] | 1250 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1251 | return init_workarounds_ring(engine); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1252 | } |
| 1253 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1254 | static void render_ring_cleanup(struct intel_engine_cs *engine) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1255 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1256 | struct drm_device *dev = engine->dev; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1257 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1258 | |
| 1259 | if (dev_priv->semaphore_obj) { |
| 1260 | i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj); |
| 1261 | drm_gem_object_unreference(&dev_priv->semaphore_obj->base); |
| 1262 | dev_priv->semaphore_obj = NULL; |
| 1263 | } |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1264 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1265 | intel_fini_pipe_control(engine); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1266 | } |
| 1267 | |
John Harrison | f716968 | 2015-05-29 17:44:05 +0100 | [diff] [blame] | 1268 | static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req, |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1269 | unsigned int num_dwords) |
| 1270 | { |
| 1271 | #define MBOX_UPDATE_DWORDS 8 |
John Harrison | f716968 | 2015-05-29 17:44:05 +0100 | [diff] [blame] | 1272 | struct intel_engine_cs *signaller = signaller_req->ring; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1273 | struct drm_device *dev = signaller->dev; |
| 1274 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1275 | struct intel_engine_cs *waiter; |
| 1276 | int i, ret, num_rings; |
| 1277 | |
| 1278 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); |
| 1279 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; |
| 1280 | #undef MBOX_UPDATE_DWORDS |
| 1281 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 1282 | ret = intel_ring_begin(signaller_req, num_dwords); |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1283 | if (ret) |
| 1284 | return ret; |
| 1285 | |
| 1286 | for_each_ring(waiter, dev_priv, i) { |
John Harrison | 6259cea | 2014-11-24 18:49:29 +0000 | [diff] [blame] | 1287 | u32 seqno; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1288 | u64 gtt_offset = signaller->semaphore.signal_ggtt[i]; |
| 1289 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
| 1290 | continue; |
| 1291 | |
John Harrison | f716968 | 2015-05-29 17:44:05 +0100 | [diff] [blame] | 1292 | seqno = i915_gem_request_get_seqno(signaller_req); |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1293 | intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6)); |
| 1294 | intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB | |
| 1295 | PIPE_CONTROL_QW_WRITE | |
| 1296 | PIPE_CONTROL_FLUSH_ENABLE); |
| 1297 | intel_ring_emit(signaller, lower_32_bits(gtt_offset)); |
| 1298 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); |
John Harrison | 6259cea | 2014-11-24 18:49:29 +0000 | [diff] [blame] | 1299 | intel_ring_emit(signaller, seqno); |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1300 | intel_ring_emit(signaller, 0); |
| 1301 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | |
| 1302 | MI_SEMAPHORE_TARGET(waiter->id)); |
| 1303 | intel_ring_emit(signaller, 0); |
| 1304 | } |
| 1305 | |
| 1306 | return 0; |
| 1307 | } |
| 1308 | |
John Harrison | f716968 | 2015-05-29 17:44:05 +0100 | [diff] [blame] | 1309 | static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req, |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1310 | unsigned int num_dwords) |
| 1311 | { |
| 1312 | #define MBOX_UPDATE_DWORDS 6 |
John Harrison | f716968 | 2015-05-29 17:44:05 +0100 | [diff] [blame] | 1313 | struct intel_engine_cs *signaller = signaller_req->ring; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1314 | struct drm_device *dev = signaller->dev; |
| 1315 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1316 | struct intel_engine_cs *waiter; |
| 1317 | int i, ret, num_rings; |
| 1318 | |
| 1319 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); |
| 1320 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; |
| 1321 | #undef MBOX_UPDATE_DWORDS |
| 1322 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 1323 | ret = intel_ring_begin(signaller_req, num_dwords); |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1324 | if (ret) |
| 1325 | return ret; |
| 1326 | |
| 1327 | for_each_ring(waiter, dev_priv, i) { |
John Harrison | 6259cea | 2014-11-24 18:49:29 +0000 | [diff] [blame] | 1328 | u32 seqno; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1329 | u64 gtt_offset = signaller->semaphore.signal_ggtt[i]; |
| 1330 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
| 1331 | continue; |
| 1332 | |
John Harrison | f716968 | 2015-05-29 17:44:05 +0100 | [diff] [blame] | 1333 | seqno = i915_gem_request_get_seqno(signaller_req); |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1334 | intel_ring_emit(signaller, (MI_FLUSH_DW + 1) | |
| 1335 | MI_FLUSH_DW_OP_STOREDW); |
| 1336 | intel_ring_emit(signaller, lower_32_bits(gtt_offset) | |
| 1337 | MI_FLUSH_DW_USE_GTT); |
| 1338 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); |
John Harrison | 6259cea | 2014-11-24 18:49:29 +0000 | [diff] [blame] | 1339 | intel_ring_emit(signaller, seqno); |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1340 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | |
| 1341 | MI_SEMAPHORE_TARGET(waiter->id)); |
| 1342 | intel_ring_emit(signaller, 0); |
| 1343 | } |
| 1344 | |
| 1345 | return 0; |
| 1346 | } |
| 1347 | |
John Harrison | f716968 | 2015-05-29 17:44:05 +0100 | [diff] [blame] | 1348 | static int gen6_signal(struct drm_i915_gem_request *signaller_req, |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 1349 | unsigned int num_dwords) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1350 | { |
John Harrison | f716968 | 2015-05-29 17:44:05 +0100 | [diff] [blame] | 1351 | struct intel_engine_cs *signaller = signaller_req->ring; |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 1352 | struct drm_device *dev = signaller->dev; |
| 1353 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1354 | struct intel_engine_cs *useless; |
Ben Widawsky | a1444b7 | 2014-06-30 09:53:35 -0700 | [diff] [blame] | 1355 | int i, ret, num_rings; |
Ben Widawsky | 78325f2 | 2014-04-29 14:52:29 -0700 | [diff] [blame] | 1356 | |
Ben Widawsky | a1444b7 | 2014-06-30 09:53:35 -0700 | [diff] [blame] | 1357 | #define MBOX_UPDATE_DWORDS 3 |
| 1358 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); |
| 1359 | num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2); |
| 1360 | #undef MBOX_UPDATE_DWORDS |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 1361 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 1362 | ret = intel_ring_begin(signaller_req, num_dwords); |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 1363 | if (ret) |
| 1364 | return ret; |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 1365 | |
Ben Widawsky | 78325f2 | 2014-04-29 14:52:29 -0700 | [diff] [blame] | 1366 | for_each_ring(useless, dev_priv, i) { |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1367 | i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[i]; |
| 1368 | |
| 1369 | if (i915_mmio_reg_valid(mbox_reg)) { |
John Harrison | f716968 | 2015-05-29 17:44:05 +0100 | [diff] [blame] | 1370 | u32 seqno = i915_gem_request_get_seqno(signaller_req); |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1371 | |
Ben Widawsky | 78325f2 | 2014-04-29 14:52:29 -0700 | [diff] [blame] | 1372 | intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1)); |
Ville Syrjälä | f92a916 | 2015-11-04 23:20:07 +0200 | [diff] [blame] | 1373 | intel_ring_emit_reg(signaller, mbox_reg); |
John Harrison | 6259cea | 2014-11-24 18:49:29 +0000 | [diff] [blame] | 1374 | intel_ring_emit(signaller, seqno); |
Ben Widawsky | 78325f2 | 2014-04-29 14:52:29 -0700 | [diff] [blame] | 1375 | } |
| 1376 | } |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 1377 | |
Ben Widawsky | a1444b7 | 2014-06-30 09:53:35 -0700 | [diff] [blame] | 1378 | /* If num_dwords was rounded, make sure the tail pointer is correct */ |
| 1379 | if (num_rings % 2 == 0) |
| 1380 | intel_ring_emit(signaller, MI_NOOP); |
| 1381 | |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 1382 | return 0; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1383 | } |
| 1384 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1385 | /** |
| 1386 | * gen6_add_request - Update the semaphore mailbox registers |
John Harrison | ee044a8 | 2015-05-29 17:44:00 +0100 | [diff] [blame] | 1387 | * |
| 1388 | * @request - request to write to the ring |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1389 | * |
| 1390 | * Update the mailbox registers in the *other* rings with the current seqno. |
| 1391 | * This acts like a signal in the canonical semaphore. |
| 1392 | */ |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1393 | static int |
John Harrison | ee044a8 | 2015-05-29 17:44:00 +0100 | [diff] [blame] | 1394 | gen6_add_request(struct drm_i915_gem_request *req) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1395 | { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1396 | struct intel_engine_cs *engine = req->ring; |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 1397 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1398 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1399 | if (engine->semaphore.signal) |
| 1400 | ret = engine->semaphore.signal(req, 4); |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 1401 | else |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 1402 | ret = intel_ring_begin(req, 4); |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 1403 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1404 | if (ret) |
| 1405 | return ret; |
| 1406 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1407 | intel_ring_emit(engine, MI_STORE_DWORD_INDEX); |
| 1408 | intel_ring_emit(engine, |
| 1409 | I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
| 1410 | intel_ring_emit(engine, i915_gem_request_get_seqno(req)); |
| 1411 | intel_ring_emit(engine, MI_USER_INTERRUPT); |
| 1412 | __intel_ring_advance(engine); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1413 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1414 | return 0; |
| 1415 | } |
| 1416 | |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 1417 | static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev, |
| 1418 | u32 seqno) |
| 1419 | { |
| 1420 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1421 | return dev_priv->last_seqno < seqno; |
| 1422 | } |
| 1423 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1424 | /** |
| 1425 | * intel_ring_sync - sync the waiter to the signaller on seqno |
| 1426 | * |
| 1427 | * @waiter - ring that is waiting |
| 1428 | * @signaller - ring which has, or will signal |
| 1429 | * @seqno - seqno which the waiter will block on |
| 1430 | */ |
Ben Widawsky | 5ee426c | 2014-06-30 09:53:38 -0700 | [diff] [blame] | 1431 | |
| 1432 | static int |
John Harrison | 599d924 | 2015-05-29 17:44:04 +0100 | [diff] [blame] | 1433 | gen8_ring_sync(struct drm_i915_gem_request *waiter_req, |
Ben Widawsky | 5ee426c | 2014-06-30 09:53:38 -0700 | [diff] [blame] | 1434 | struct intel_engine_cs *signaller, |
| 1435 | u32 seqno) |
| 1436 | { |
John Harrison | 599d924 | 2015-05-29 17:44:04 +0100 | [diff] [blame] | 1437 | struct intel_engine_cs *waiter = waiter_req->ring; |
Ben Widawsky | 5ee426c | 2014-06-30 09:53:38 -0700 | [diff] [blame] | 1438 | struct drm_i915_private *dev_priv = waiter->dev->dev_private; |
| 1439 | int ret; |
| 1440 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 1441 | ret = intel_ring_begin(waiter_req, 4); |
Ben Widawsky | 5ee426c | 2014-06-30 09:53:38 -0700 | [diff] [blame] | 1442 | if (ret) |
| 1443 | return ret; |
| 1444 | |
| 1445 | intel_ring_emit(waiter, MI_SEMAPHORE_WAIT | |
| 1446 | MI_SEMAPHORE_GLOBAL_GTT | |
Ben Widawsky | bae4fcd | 2014-06-30 09:53:43 -0700 | [diff] [blame] | 1447 | MI_SEMAPHORE_POLL | |
Ben Widawsky | 5ee426c | 2014-06-30 09:53:38 -0700 | [diff] [blame] | 1448 | MI_SEMAPHORE_SAD_GTE_SDD); |
| 1449 | intel_ring_emit(waiter, seqno); |
| 1450 | intel_ring_emit(waiter, |
| 1451 | lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); |
| 1452 | intel_ring_emit(waiter, |
| 1453 | upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); |
| 1454 | intel_ring_advance(waiter); |
| 1455 | return 0; |
| 1456 | } |
| 1457 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1458 | static int |
John Harrison | 599d924 | 2015-05-29 17:44:04 +0100 | [diff] [blame] | 1459 | gen6_ring_sync(struct drm_i915_gem_request *waiter_req, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1460 | struct intel_engine_cs *signaller, |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 1461 | u32 seqno) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1462 | { |
John Harrison | 599d924 | 2015-05-29 17:44:04 +0100 | [diff] [blame] | 1463 | struct intel_engine_cs *waiter = waiter_req->ring; |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1464 | u32 dw1 = MI_SEMAPHORE_MBOX | |
| 1465 | MI_SEMAPHORE_COMPARE | |
| 1466 | MI_SEMAPHORE_REGISTER; |
Ben Widawsky | ebc348b | 2014-04-29 14:52:28 -0700 | [diff] [blame] | 1467 | u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id]; |
| 1468 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1469 | |
Ben Widawsky | 1500f7e | 2012-04-11 11:18:21 -0700 | [diff] [blame] | 1470 | /* Throughout all of the GEM code, seqno passed implies our current |
| 1471 | * seqno is >= the last seqno executed. However for hardware the |
| 1472 | * comparison is strictly greater than. |
| 1473 | */ |
| 1474 | seqno -= 1; |
| 1475 | |
Ben Widawsky | ebc348b | 2014-04-29 14:52:28 -0700 | [diff] [blame] | 1476 | WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 1477 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 1478 | ret = intel_ring_begin(waiter_req, 4); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1479 | if (ret) |
| 1480 | return ret; |
| 1481 | |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 1482 | /* If seqno wrap happened, omit the wait with no-ops */ |
| 1483 | if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) { |
Ben Widawsky | ebc348b | 2014-04-29 14:52:28 -0700 | [diff] [blame] | 1484 | intel_ring_emit(waiter, dw1 | wait_mbox); |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 1485 | intel_ring_emit(waiter, seqno); |
| 1486 | intel_ring_emit(waiter, 0); |
| 1487 | intel_ring_emit(waiter, MI_NOOP); |
| 1488 | } else { |
| 1489 | intel_ring_emit(waiter, MI_NOOP); |
| 1490 | intel_ring_emit(waiter, MI_NOOP); |
| 1491 | intel_ring_emit(waiter, MI_NOOP); |
| 1492 | intel_ring_emit(waiter, MI_NOOP); |
| 1493 | } |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1494 | intel_ring_advance(waiter); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1495 | |
| 1496 | return 0; |
| 1497 | } |
| 1498 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1499 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
| 1500 | do { \ |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 1501 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
| 1502 | PIPE_CONTROL_DEPTH_STALL); \ |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1503 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
| 1504 | intel_ring_emit(ring__, 0); \ |
| 1505 | intel_ring_emit(ring__, 0); \ |
| 1506 | } while (0) |
| 1507 | |
| 1508 | static int |
John Harrison | ee044a8 | 2015-05-29 17:44:00 +0100 | [diff] [blame] | 1509 | pc_render_add_request(struct drm_i915_gem_request *req) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1510 | { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1511 | struct intel_engine_cs *engine = req->ring; |
| 1512 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1513 | int ret; |
| 1514 | |
| 1515 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently |
| 1516 | * incoherent with writes to memory, i.e. completely fubar, |
| 1517 | * so we need to use PIPE_NOTIFY instead. |
| 1518 | * |
| 1519 | * However, we also need to workaround the qword write |
| 1520 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to |
| 1521 | * memory before requesting an interrupt. |
| 1522 | */ |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 1523 | ret = intel_ring_begin(req, 32); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1524 | if (ret) |
| 1525 | return ret; |
| 1526 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1527 | intel_ring_emit(engine, |
| 1528 | GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
Kenneth Graunke | 9d971b3 | 2011-10-11 23:41:09 +0200 | [diff] [blame] | 1529 | PIPE_CONTROL_WRITE_FLUSH | |
| 1530 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1531 | intel_ring_emit(engine, |
| 1532 | engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
| 1533 | intel_ring_emit(engine, i915_gem_request_get_seqno(req)); |
| 1534 | intel_ring_emit(engine, 0); |
| 1535 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 1536 | scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */ |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1537 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 1538 | scratch_addr += 2 * CACHELINE_BYTES; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1539 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 1540 | scratch_addr += 2 * CACHELINE_BYTES; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1541 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 1542 | scratch_addr += 2 * CACHELINE_BYTES; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1543 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 1544 | scratch_addr += 2 * CACHELINE_BYTES; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1545 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1546 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1547 | intel_ring_emit(engine, |
| 1548 | GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
Kenneth Graunke | 9d971b3 | 2011-10-11 23:41:09 +0200 | [diff] [blame] | 1549 | PIPE_CONTROL_WRITE_FLUSH | |
| 1550 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1551 | PIPE_CONTROL_NOTIFY); |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1552 | intel_ring_emit(engine, |
| 1553 | engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
| 1554 | intel_ring_emit(engine, i915_gem_request_get_seqno(req)); |
| 1555 | intel_ring_emit(engine, 0); |
| 1556 | __intel_ring_advance(engine); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1557 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1558 | return 0; |
| 1559 | } |
| 1560 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1561 | static u32 |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1562 | gen6_ring_get_seqno(struct intel_engine_cs *engine, bool lazy_coherency) |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 1563 | { |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 1564 | /* Workaround to force correct ordering between irq and seqno writes on |
| 1565 | * ivb (and maybe also on snb) by reading from a CS register (like |
| 1566 | * ACTHD) before reading the status page. */ |
Chris Wilson | 5087744 | 2014-03-21 12:41:53 +0000 | [diff] [blame] | 1567 | if (!lazy_coherency) { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1568 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
| 1569 | POSTING_READ(RING_ACTHD(engine->mmio_base)); |
Chris Wilson | 5087744 | 2014-03-21 12:41:53 +0000 | [diff] [blame] | 1570 | } |
| 1571 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1572 | return intel_read_status_page(engine, I915_GEM_HWS_INDEX); |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 1573 | } |
| 1574 | |
| 1575 | static u32 |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1576 | ring_get_seqno(struct intel_engine_cs *engine, bool lazy_coherency) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1577 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1578 | return intel_read_status_page(engine, I915_GEM_HWS_INDEX); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1579 | } |
| 1580 | |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1581 | static void |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1582 | ring_set_seqno(struct intel_engine_cs *engine, u32 seqno) |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1583 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1584 | intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno); |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1585 | } |
| 1586 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1587 | static u32 |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1588 | pc_render_get_seqno(struct intel_engine_cs *engine, bool lazy_coherency) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1589 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1590 | return engine->scratch.cpu_page[0]; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1591 | } |
| 1592 | |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1593 | static void |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1594 | pc_render_set_seqno(struct intel_engine_cs *engine, u32 seqno) |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1595 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1596 | engine->scratch.cpu_page[0] = seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1597 | } |
| 1598 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1599 | static bool |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1600 | gen5_ring_get_irq(struct intel_engine_cs *engine) |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1601 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1602 | struct drm_device *dev = engine->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1603 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1604 | unsigned long flags; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1605 | |
Daniel Vetter | 7cd512f | 2014-09-15 11:38:57 +0200 | [diff] [blame] | 1606 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1607 | return false; |
| 1608 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1609 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1610 | if (engine->irq_refcount++ == 0) |
| 1611 | gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1612 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1613 | |
| 1614 | return true; |
| 1615 | } |
| 1616 | |
| 1617 | static void |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1618 | gen5_ring_put_irq(struct intel_engine_cs *engine) |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1619 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1620 | struct drm_device *dev = engine->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1621 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1622 | unsigned long flags; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1623 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1624 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1625 | if (--engine->irq_refcount == 0) |
| 1626 | gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1627 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1628 | } |
| 1629 | |
| 1630 | static bool |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1631 | i9xx_ring_get_irq(struct intel_engine_cs *engine) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1632 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1633 | struct drm_device *dev = engine->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1634 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1635 | unsigned long flags; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1636 | |
Daniel Vetter | 7cd512f | 2014-09-15 11:38:57 +0200 | [diff] [blame] | 1637 | if (!intel_irqs_enabled(dev_priv)) |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1638 | return false; |
| 1639 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1640 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1641 | if (engine->irq_refcount++ == 0) { |
| 1642 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
Daniel Vetter | f637fde | 2012-04-11 22:12:59 +0200 | [diff] [blame] | 1643 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 1644 | POSTING_READ(IMR); |
| 1645 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1646 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1647 | |
| 1648 | return true; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1649 | } |
| 1650 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1651 | static void |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1652 | i9xx_ring_put_irq(struct intel_engine_cs *engine) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1653 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1654 | struct drm_device *dev = engine->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1655 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1656 | unsigned long flags; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1657 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1658 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1659 | if (--engine->irq_refcount == 0) { |
| 1660 | dev_priv->irq_mask |= engine->irq_enable_mask; |
Daniel Vetter | f637fde | 2012-04-11 22:12:59 +0200 | [diff] [blame] | 1661 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 1662 | POSTING_READ(IMR); |
| 1663 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1664 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1665 | } |
| 1666 | |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1667 | static bool |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1668 | i8xx_ring_get_irq(struct intel_engine_cs *engine) |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1669 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1670 | struct drm_device *dev = engine->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1671 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1672 | unsigned long flags; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1673 | |
Daniel Vetter | 7cd512f | 2014-09-15 11:38:57 +0200 | [diff] [blame] | 1674 | if (!intel_irqs_enabled(dev_priv)) |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1675 | return false; |
| 1676 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1677 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1678 | if (engine->irq_refcount++ == 0) { |
| 1679 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1680 | I915_WRITE16(IMR, dev_priv->irq_mask); |
| 1681 | POSTING_READ16(IMR); |
| 1682 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1683 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1684 | |
| 1685 | return true; |
| 1686 | } |
| 1687 | |
| 1688 | static void |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1689 | i8xx_ring_put_irq(struct intel_engine_cs *engine) |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1690 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1691 | struct drm_device *dev = engine->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1692 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1693 | unsigned long flags; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1694 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1695 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1696 | if (--engine->irq_refcount == 0) { |
| 1697 | dev_priv->irq_mask |= engine->irq_enable_mask; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1698 | I915_WRITE16(IMR, dev_priv->irq_mask); |
| 1699 | POSTING_READ16(IMR); |
| 1700 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1701 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1702 | } |
| 1703 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1704 | static int |
John Harrison | a84c3ae | 2015-05-29 17:43:57 +0100 | [diff] [blame] | 1705 | bsd_ring_flush(struct drm_i915_gem_request *req, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1706 | u32 invalidate_domains, |
| 1707 | u32 flush_domains) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1708 | { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1709 | struct intel_engine_cs *engine = req->ring; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1710 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1711 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 1712 | ret = intel_ring_begin(req, 2); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1713 | if (ret) |
| 1714 | return ret; |
| 1715 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1716 | intel_ring_emit(engine, MI_FLUSH); |
| 1717 | intel_ring_emit(engine, MI_NOOP); |
| 1718 | intel_ring_advance(engine); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1719 | return 0; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1720 | } |
| 1721 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1722 | static int |
John Harrison | ee044a8 | 2015-05-29 17:44:00 +0100 | [diff] [blame] | 1723 | i9xx_add_request(struct drm_i915_gem_request *req) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1724 | { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1725 | struct intel_engine_cs *engine = req->ring; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1726 | int ret; |
| 1727 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 1728 | ret = intel_ring_begin(req, 4); |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1729 | if (ret) |
| 1730 | return ret; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 1731 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1732 | intel_ring_emit(engine, MI_STORE_DWORD_INDEX); |
| 1733 | intel_ring_emit(engine, |
| 1734 | I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
| 1735 | intel_ring_emit(engine, i915_gem_request_get_seqno(req)); |
| 1736 | intel_ring_emit(engine, MI_USER_INTERRUPT); |
| 1737 | __intel_ring_advance(engine); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1738 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1739 | return 0; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1740 | } |
| 1741 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1742 | static bool |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1743 | gen6_ring_get_irq(struct intel_engine_cs *engine) |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1744 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1745 | struct drm_device *dev = engine->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1746 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1747 | unsigned long flags; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1748 | |
Daniel Vetter | 7cd512f | 2014-09-15 11:38:57 +0200 | [diff] [blame] | 1749 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
| 1750 | return false; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1751 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1752 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1753 | if (engine->irq_refcount++ == 0) { |
| 1754 | if (HAS_L3_DPF(dev) && engine->id == RCS) |
| 1755 | I915_WRITE_IMR(engine, |
| 1756 | ~(engine->irq_enable_mask | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1757 | GT_PARITY_ERROR(dev))); |
Ben Widawsky | 15b9f80 | 2012-05-25 16:56:23 -0700 | [diff] [blame] | 1758 | else |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1759 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
| 1760 | gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1761 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1762 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1763 | |
| 1764 | return true; |
| 1765 | } |
| 1766 | |
| 1767 | static void |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1768 | gen6_ring_put_irq(struct intel_engine_cs *engine) |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1769 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1770 | struct drm_device *dev = engine->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1771 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1772 | unsigned long flags; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1773 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1774 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1775 | if (--engine->irq_refcount == 0) { |
| 1776 | if (HAS_L3_DPF(dev) && engine->id == RCS) |
| 1777 | I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev)); |
Ben Widawsky | 15b9f80 | 2012-05-25 16:56:23 -0700 | [diff] [blame] | 1778 | else |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1779 | I915_WRITE_IMR(engine, ~0); |
| 1780 | gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1781 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1782 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1783 | } |
| 1784 | |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1785 | static bool |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1786 | hsw_vebox_get_irq(struct intel_engine_cs *engine) |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1787 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1788 | struct drm_device *dev = engine->dev; |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1789 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1790 | unsigned long flags; |
| 1791 | |
Daniel Vetter | 7cd512f | 2014-09-15 11:38:57 +0200 | [diff] [blame] | 1792 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1793 | return false; |
| 1794 | |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1795 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1796 | if (engine->irq_refcount++ == 0) { |
| 1797 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
| 1798 | gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask); |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1799 | } |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1800 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1801 | |
| 1802 | return true; |
| 1803 | } |
| 1804 | |
| 1805 | static void |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1806 | hsw_vebox_put_irq(struct intel_engine_cs *engine) |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1807 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1808 | struct drm_device *dev = engine->dev; |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1809 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1810 | unsigned long flags; |
| 1811 | |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1812 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1813 | if (--engine->irq_refcount == 0) { |
| 1814 | I915_WRITE_IMR(engine, ~0); |
| 1815 | gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask); |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1816 | } |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1817 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1818 | } |
| 1819 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1820 | static bool |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1821 | gen8_ring_get_irq(struct intel_engine_cs *engine) |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1822 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1823 | struct drm_device *dev = engine->dev; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1824 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1825 | unsigned long flags; |
| 1826 | |
Daniel Vetter | 7cd512f | 2014-09-15 11:38:57 +0200 | [diff] [blame] | 1827 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1828 | return false; |
| 1829 | |
| 1830 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1831 | if (engine->irq_refcount++ == 0) { |
| 1832 | if (HAS_L3_DPF(dev) && engine->id == RCS) { |
| 1833 | I915_WRITE_IMR(engine, |
| 1834 | ~(engine->irq_enable_mask | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1835 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT)); |
| 1836 | } else { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1837 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1838 | } |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1839 | POSTING_READ(RING_IMR(engine->mmio_base)); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1840 | } |
| 1841 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 1842 | |
| 1843 | return true; |
| 1844 | } |
| 1845 | |
| 1846 | static void |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1847 | gen8_ring_put_irq(struct intel_engine_cs *engine) |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1848 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1849 | struct drm_device *dev = engine->dev; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1850 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1851 | unsigned long flags; |
| 1852 | |
| 1853 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1854 | if (--engine->irq_refcount == 0) { |
| 1855 | if (HAS_L3_DPF(dev) && engine->id == RCS) { |
| 1856 | I915_WRITE_IMR(engine, |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1857 | ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT); |
| 1858 | } else { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1859 | I915_WRITE_IMR(engine, ~0); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1860 | } |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1861 | POSTING_READ(RING_IMR(engine->mmio_base)); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1862 | } |
| 1863 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 1864 | } |
| 1865 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1866 | static int |
John Harrison | 53fddaf | 2015-05-29 17:44:02 +0100 | [diff] [blame] | 1867 | i965_dispatch_execbuffer(struct drm_i915_gem_request *req, |
Ben Widawsky | 9bcb144 | 2014-04-28 19:29:25 -0700 | [diff] [blame] | 1868 | u64 offset, u32 length, |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 1869 | unsigned dispatch_flags) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1870 | { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1871 | struct intel_engine_cs *engine = req->ring; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1872 | int ret; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1873 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 1874 | ret = intel_ring_begin(req, 2); |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1875 | if (ret) |
| 1876 | return ret; |
| 1877 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1878 | intel_ring_emit(engine, |
Chris Wilson | 65f5687 | 2012-04-17 16:38:12 +0100 | [diff] [blame] | 1879 | MI_BATCH_BUFFER_START | |
| 1880 | MI_BATCH_GTT | |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 1881 | (dispatch_flags & I915_DISPATCH_SECURE ? |
| 1882 | 0 : MI_BATCH_NON_SECURE_I965)); |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1883 | intel_ring_emit(engine, offset); |
| 1884 | intel_ring_advance(engine); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1885 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1886 | return 0; |
| 1887 | } |
| 1888 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1889 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
| 1890 | #define I830_BATCH_LIMIT (256*1024) |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 1891 | #define I830_TLB_ENTRIES (2) |
| 1892 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1893 | static int |
John Harrison | 53fddaf | 2015-05-29 17:44:02 +0100 | [diff] [blame] | 1894 | i830_dispatch_execbuffer(struct drm_i915_gem_request *req, |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 1895 | u64 offset, u32 len, |
| 1896 | unsigned dispatch_flags) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1897 | { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1898 | struct intel_engine_cs *engine = req->ring; |
| 1899 | u32 cs_offset = engine->scratch.gtt_offset; |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1900 | int ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1901 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 1902 | ret = intel_ring_begin(req, 6); |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 1903 | if (ret) |
| 1904 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1905 | |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 1906 | /* Evict the invalid PTE TLBs */ |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1907 | intel_ring_emit(engine, COLOR_BLT_CMD | BLT_WRITE_RGBA); |
| 1908 | intel_ring_emit(engine, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096); |
| 1909 | intel_ring_emit(engine, I830_TLB_ENTRIES << 16 | 4); /* load each page */ |
| 1910 | intel_ring_emit(engine, cs_offset); |
| 1911 | intel_ring_emit(engine, 0xdeadbeef); |
| 1912 | intel_ring_emit(engine, MI_NOOP); |
| 1913 | intel_ring_advance(engine); |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1914 | |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 1915 | if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) { |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1916 | if (len > I830_BATCH_LIMIT) |
| 1917 | return -ENOSPC; |
| 1918 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 1919 | ret = intel_ring_begin(req, 6 + 2); |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1920 | if (ret) |
| 1921 | return ret; |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 1922 | |
| 1923 | /* Blit the batch (which has now all relocs applied) to the |
| 1924 | * stable batch scratch bo area (so that the CS never |
| 1925 | * stumbles over its tlb invalidation bug) ... |
| 1926 | */ |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1927 | intel_ring_emit(engine, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA); |
| 1928 | intel_ring_emit(engine, |
| 1929 | BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096); |
| 1930 | intel_ring_emit(engine, DIV_ROUND_UP(len, 4096) << 16 | 4096); |
| 1931 | intel_ring_emit(engine, cs_offset); |
| 1932 | intel_ring_emit(engine, 4096); |
| 1933 | intel_ring_emit(engine, offset); |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 1934 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1935 | intel_ring_emit(engine, MI_FLUSH); |
| 1936 | intel_ring_emit(engine, MI_NOOP); |
| 1937 | intel_ring_advance(engine); |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1938 | |
| 1939 | /* ... and execute it. */ |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 1940 | offset = cs_offset; |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1941 | } |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1942 | |
Ville Syrjälä | 9d611c0 | 2015-12-14 18:23:49 +0200 | [diff] [blame] | 1943 | ret = intel_ring_begin(req, 2); |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 1944 | if (ret) |
| 1945 | return ret; |
| 1946 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1947 | intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
| 1948 | intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ? |
| 1949 | 0 : MI_BATCH_NON_SECURE)); |
| 1950 | intel_ring_advance(engine); |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 1951 | |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1952 | return 0; |
| 1953 | } |
| 1954 | |
| 1955 | static int |
John Harrison | 53fddaf | 2015-05-29 17:44:02 +0100 | [diff] [blame] | 1956 | i915_dispatch_execbuffer(struct drm_i915_gem_request *req, |
Ben Widawsky | 9bcb144 | 2014-04-28 19:29:25 -0700 | [diff] [blame] | 1957 | u64 offset, u32 len, |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 1958 | unsigned dispatch_flags) |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1959 | { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1960 | struct intel_engine_cs *engine = req->ring; |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1961 | int ret; |
| 1962 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 1963 | ret = intel_ring_begin(req, 2); |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1964 | if (ret) |
| 1965 | return ret; |
| 1966 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1967 | intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
| 1968 | intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ? |
| 1969 | 0 : MI_BATCH_NON_SECURE)); |
| 1970 | intel_ring_advance(engine); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1971 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1972 | return 0; |
| 1973 | } |
| 1974 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1975 | static void cleanup_phys_status_page(struct intel_engine_cs *engine) |
Ville Syrjälä | 7d3fdff | 2016-01-11 20:48:32 +0200 | [diff] [blame] | 1976 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1977 | struct drm_i915_private *dev_priv = to_i915(engine->dev); |
Ville Syrjälä | 7d3fdff | 2016-01-11 20:48:32 +0200 | [diff] [blame] | 1978 | |
| 1979 | if (!dev_priv->status_page_dmah) |
| 1980 | return; |
| 1981 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1982 | drm_pci_free(engine->dev, dev_priv->status_page_dmah); |
| 1983 | engine->status_page.page_addr = NULL; |
Ville Syrjälä | 7d3fdff | 2016-01-11 20:48:32 +0200 | [diff] [blame] | 1984 | } |
| 1985 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1986 | static void cleanup_status_page(struct intel_engine_cs *engine) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1987 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1988 | struct drm_i915_gem_object *obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1989 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1990 | obj = engine->status_page.obj; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1991 | if (obj == NULL) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1992 | return; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1993 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1994 | kunmap(sg_page(obj->pages->sgl)); |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 1995 | i915_gem_object_ggtt_unpin(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1996 | drm_gem_object_unreference(&obj->base); |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 1997 | engine->status_page.obj = NULL; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1998 | } |
| 1999 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2000 | static int init_status_page(struct intel_engine_cs *engine) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2001 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2002 | struct drm_i915_gem_object *obj = engine->status_page.obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2003 | |
Ville Syrjälä | 7d3fdff | 2016-01-11 20:48:32 +0200 | [diff] [blame] | 2004 | if (obj == NULL) { |
Chris Wilson | 1f767e0 | 2014-07-03 17:33:03 -0400 | [diff] [blame] | 2005 | unsigned flags; |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 2006 | int ret; |
| 2007 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2008 | obj = i915_gem_alloc_object(engine->dev, 4096); |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 2009 | if (obj == NULL) { |
| 2010 | DRM_ERROR("Failed to allocate status page\n"); |
| 2011 | return -ENOMEM; |
| 2012 | } |
| 2013 | |
| 2014 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
| 2015 | if (ret) |
| 2016 | goto err_unref; |
| 2017 | |
Chris Wilson | 1f767e0 | 2014-07-03 17:33:03 -0400 | [diff] [blame] | 2018 | flags = 0; |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2019 | if (!HAS_LLC(engine->dev)) |
Chris Wilson | 1f767e0 | 2014-07-03 17:33:03 -0400 | [diff] [blame] | 2020 | /* On g33, we cannot place HWS above 256MiB, so |
| 2021 | * restrict its pinning to the low mappable arena. |
| 2022 | * Though this restriction is not documented for |
| 2023 | * gen4, gen5, or byt, they also behave similarly |
| 2024 | * and hang if the HWS is placed at the top of the |
| 2025 | * GTT. To generalise, it appears that all !llc |
| 2026 | * platforms have issues with us placing the HWS |
| 2027 | * above the mappable region (even though we never |
| 2028 | * actualy map it). |
| 2029 | */ |
| 2030 | flags |= PIN_MAPPABLE; |
| 2031 | ret = i915_gem_obj_ggtt_pin(obj, 4096, flags); |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 2032 | if (ret) { |
| 2033 | err_unref: |
| 2034 | drm_gem_object_unreference(&obj->base); |
| 2035 | return ret; |
| 2036 | } |
| 2037 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2038 | engine->status_page.obj = obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2039 | } |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 2040 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2041 | engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
| 2042 | engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); |
| 2043 | memset(engine->status_page.page_addr, 0, PAGE_SIZE); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2044 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2045 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2046 | engine->name, engine->status_page.gfx_addr); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2047 | |
| 2048 | return 0; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2049 | } |
| 2050 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2051 | static int init_phys_status_page(struct intel_engine_cs *engine) |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 2052 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2053 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 2054 | |
| 2055 | if (!dev_priv->status_page_dmah) { |
| 2056 | dev_priv->status_page_dmah = |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2057 | drm_pci_alloc(engine->dev, PAGE_SIZE, PAGE_SIZE); |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 2058 | if (!dev_priv->status_page_dmah) |
| 2059 | return -ENOMEM; |
| 2060 | } |
| 2061 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2062 | engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
| 2063 | memset(engine->status_page.page_addr, 0, PAGE_SIZE); |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 2064 | |
| 2065 | return 0; |
| 2066 | } |
| 2067 | |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 2068 | void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
| 2069 | { |
Chris Wilson | def0c5f | 2015-10-08 13:39:54 +0100 | [diff] [blame] | 2070 | if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen) |
| 2071 | vunmap(ringbuf->virtual_start); |
| 2072 | else |
| 2073 | iounmap(ringbuf->virtual_start); |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 2074 | ringbuf->virtual_start = NULL; |
Tvrtko Ursulin | 0eb973d | 2016-01-15 15:10:28 +0000 | [diff] [blame] | 2075 | ringbuf->vma = NULL; |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 2076 | i915_gem_object_ggtt_unpin(ringbuf->obj); |
| 2077 | } |
| 2078 | |
Chris Wilson | def0c5f | 2015-10-08 13:39:54 +0100 | [diff] [blame] | 2079 | static u32 *vmap_obj(struct drm_i915_gem_object *obj) |
| 2080 | { |
| 2081 | struct sg_page_iter sg_iter; |
| 2082 | struct page **pages; |
| 2083 | void *addr; |
| 2084 | int i; |
| 2085 | |
| 2086 | pages = drm_malloc_ab(obj->base.size >> PAGE_SHIFT, sizeof(*pages)); |
| 2087 | if (pages == NULL) |
| 2088 | return NULL; |
| 2089 | |
| 2090 | i = 0; |
| 2091 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) |
| 2092 | pages[i++] = sg_page_iter_page(&sg_iter); |
| 2093 | |
| 2094 | addr = vmap(pages, i, 0, PAGE_KERNEL); |
| 2095 | drm_free_large(pages); |
| 2096 | |
| 2097 | return addr; |
| 2098 | } |
| 2099 | |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 2100 | int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev, |
| 2101 | struct intel_ringbuffer *ringbuf) |
| 2102 | { |
| 2103 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 2104 | struct drm_i915_gem_object *obj = ringbuf->obj; |
| 2105 | int ret; |
| 2106 | |
Chris Wilson | def0c5f | 2015-10-08 13:39:54 +0100 | [diff] [blame] | 2107 | if (HAS_LLC(dev_priv) && !obj->stolen) { |
| 2108 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, 0); |
| 2109 | if (ret) |
| 2110 | return ret; |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 2111 | |
Chris Wilson | def0c5f | 2015-10-08 13:39:54 +0100 | [diff] [blame] | 2112 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
| 2113 | if (ret) { |
| 2114 | i915_gem_object_ggtt_unpin(obj); |
| 2115 | return ret; |
| 2116 | } |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 2117 | |
Chris Wilson | def0c5f | 2015-10-08 13:39:54 +0100 | [diff] [blame] | 2118 | ringbuf->virtual_start = vmap_obj(obj); |
| 2119 | if (ringbuf->virtual_start == NULL) { |
| 2120 | i915_gem_object_ggtt_unpin(obj); |
| 2121 | return -ENOMEM; |
| 2122 | } |
| 2123 | } else { |
| 2124 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE); |
| 2125 | if (ret) |
| 2126 | return ret; |
| 2127 | |
| 2128 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 2129 | if (ret) { |
| 2130 | i915_gem_object_ggtt_unpin(obj); |
| 2131 | return ret; |
| 2132 | } |
| 2133 | |
Daniele Ceraolo Spurio | ff3dc08 | 2016-01-27 15:43:49 +0000 | [diff] [blame] | 2134 | /* Access through the GTT requires the device to be awake. */ |
| 2135 | assert_rpm_wakelock_held(dev_priv); |
| 2136 | |
Chris Wilson | def0c5f | 2015-10-08 13:39:54 +0100 | [diff] [blame] | 2137 | ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base + |
| 2138 | i915_gem_obj_ggtt_offset(obj), ringbuf->size); |
| 2139 | if (ringbuf->virtual_start == NULL) { |
| 2140 | i915_gem_object_ggtt_unpin(obj); |
| 2141 | return -EINVAL; |
| 2142 | } |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 2143 | } |
| 2144 | |
Tvrtko Ursulin | 0eb973d | 2016-01-15 15:10:28 +0000 | [diff] [blame] | 2145 | ringbuf->vma = i915_gem_obj_to_ggtt(obj); |
| 2146 | |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 2147 | return 0; |
| 2148 | } |
| 2149 | |
Chris Wilson | 01101fa | 2015-09-03 13:01:39 +0100 | [diff] [blame] | 2150 | static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 2151 | { |
Oscar Mateo | 2919d29 | 2014-07-03 16:28:02 +0100 | [diff] [blame] | 2152 | drm_gem_object_unreference(&ringbuf->obj->base); |
| 2153 | ringbuf->obj = NULL; |
| 2154 | } |
| 2155 | |
Chris Wilson | 01101fa | 2015-09-03 13:01:39 +0100 | [diff] [blame] | 2156 | static int intel_alloc_ringbuffer_obj(struct drm_device *dev, |
| 2157 | struct intel_ringbuffer *ringbuf) |
Oscar Mateo | 2919d29 | 2014-07-03 16:28:02 +0100 | [diff] [blame] | 2158 | { |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 2159 | struct drm_i915_gem_object *obj; |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 2160 | |
| 2161 | obj = NULL; |
| 2162 | if (!HAS_LLC(dev)) |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 2163 | obj = i915_gem_object_create_stolen(dev, ringbuf->size); |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 2164 | if (obj == NULL) |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 2165 | obj = i915_gem_alloc_object(dev, ringbuf->size); |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 2166 | if (obj == NULL) |
| 2167 | return -ENOMEM; |
| 2168 | |
Akash Goel | 24f3a8c | 2014-06-17 10:59:42 +0530 | [diff] [blame] | 2169 | /* mark ring buffers as read-only from GPU side by default */ |
| 2170 | obj->gt_ro = 1; |
| 2171 | |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 2172 | ringbuf->obj = obj; |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 2173 | |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 2174 | return 0; |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 2175 | } |
| 2176 | |
Chris Wilson | 01101fa | 2015-09-03 13:01:39 +0100 | [diff] [blame] | 2177 | struct intel_ringbuffer * |
| 2178 | intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size) |
| 2179 | { |
| 2180 | struct intel_ringbuffer *ring; |
| 2181 | int ret; |
| 2182 | |
| 2183 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
Chris Wilson | 608c1a5 | 2015-09-03 13:01:40 +0100 | [diff] [blame] | 2184 | if (ring == NULL) { |
| 2185 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n", |
| 2186 | engine->name); |
Chris Wilson | 01101fa | 2015-09-03 13:01:39 +0100 | [diff] [blame] | 2187 | return ERR_PTR(-ENOMEM); |
Chris Wilson | 608c1a5 | 2015-09-03 13:01:40 +0100 | [diff] [blame] | 2188 | } |
Chris Wilson | 01101fa | 2015-09-03 13:01:39 +0100 | [diff] [blame] | 2189 | |
| 2190 | ring->ring = engine; |
Chris Wilson | 608c1a5 | 2015-09-03 13:01:40 +0100 | [diff] [blame] | 2191 | list_add(&ring->link, &engine->buffers); |
Chris Wilson | 01101fa | 2015-09-03 13:01:39 +0100 | [diff] [blame] | 2192 | |
| 2193 | ring->size = size; |
| 2194 | /* Workaround an erratum on the i830 which causes a hang if |
| 2195 | * the TAIL pointer points to within the last 2 cachelines |
| 2196 | * of the buffer. |
| 2197 | */ |
| 2198 | ring->effective_size = size; |
| 2199 | if (IS_I830(engine->dev) || IS_845G(engine->dev)) |
| 2200 | ring->effective_size -= 2 * CACHELINE_BYTES; |
| 2201 | |
| 2202 | ring->last_retired_head = -1; |
| 2203 | intel_ring_update_space(ring); |
| 2204 | |
| 2205 | ret = intel_alloc_ringbuffer_obj(engine->dev, ring); |
| 2206 | if (ret) { |
Chris Wilson | 608c1a5 | 2015-09-03 13:01:40 +0100 | [diff] [blame] | 2207 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n", |
| 2208 | engine->name, ret); |
| 2209 | list_del(&ring->link); |
Chris Wilson | 01101fa | 2015-09-03 13:01:39 +0100 | [diff] [blame] | 2210 | kfree(ring); |
| 2211 | return ERR_PTR(ret); |
| 2212 | } |
| 2213 | |
| 2214 | return ring; |
| 2215 | } |
| 2216 | |
| 2217 | void |
| 2218 | intel_ringbuffer_free(struct intel_ringbuffer *ring) |
| 2219 | { |
| 2220 | intel_destroy_ringbuffer_obj(ring); |
Chris Wilson | 608c1a5 | 2015-09-03 13:01:40 +0100 | [diff] [blame] | 2221 | list_del(&ring->link); |
Chris Wilson | 01101fa | 2015-09-03 13:01:39 +0100 | [diff] [blame] | 2222 | kfree(ring); |
| 2223 | } |
| 2224 | |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 2225 | static int intel_init_ring_buffer(struct drm_device *dev, |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2226 | struct intel_engine_cs *engine) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2227 | { |
Daniel Vetter | bfc882b | 2014-11-20 00:33:08 +0100 | [diff] [blame] | 2228 | struct intel_ringbuffer *ringbuf; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 2229 | int ret; |
| 2230 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2231 | WARN_ON(engine->buffer); |
Daniel Vetter | bfc882b | 2014-11-20 00:33:08 +0100 | [diff] [blame] | 2232 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2233 | engine->dev = dev; |
| 2234 | INIT_LIST_HEAD(&engine->active_list); |
| 2235 | INIT_LIST_HEAD(&engine->request_list); |
| 2236 | INIT_LIST_HEAD(&engine->execlist_queue); |
| 2237 | INIT_LIST_HEAD(&engine->buffers); |
| 2238 | i915_gem_batch_pool_init(dev, &engine->batch_pool); |
| 2239 | memset(engine->semaphore.sync_seqno, 0, |
| 2240 | sizeof(engine->semaphore.sync_seqno)); |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 2241 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2242 | init_waitqueue_head(&engine->irq_queue); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2243 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2244 | ringbuf = intel_engine_create_ringbuffer(engine, 32 * PAGE_SIZE); |
Dave Gordon | b0366a5 | 2015-12-08 15:02:36 +0000 | [diff] [blame] | 2245 | if (IS_ERR(ringbuf)) { |
| 2246 | ret = PTR_ERR(ringbuf); |
| 2247 | goto error; |
| 2248 | } |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2249 | engine->buffer = ringbuf; |
Chris Wilson | 01101fa | 2015-09-03 13:01:39 +0100 | [diff] [blame] | 2250 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2251 | if (I915_NEED_GFX_HWS(dev)) { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2252 | ret = init_status_page(engine); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2253 | if (ret) |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 2254 | goto error; |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 2255 | } else { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2256 | WARN_ON(engine->id != RCS); |
| 2257 | ret = init_phys_status_page(engine); |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 2258 | if (ret) |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 2259 | goto error; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2260 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2261 | |
Daniel Vetter | bfc882b | 2014-11-20 00:33:08 +0100 | [diff] [blame] | 2262 | ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf); |
| 2263 | if (ret) { |
| 2264 | DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n", |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2265 | engine->name, ret); |
Daniel Vetter | bfc882b | 2014-11-20 00:33:08 +0100 | [diff] [blame] | 2266 | intel_destroy_ringbuffer_obj(ringbuf); |
| 2267 | goto error; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2268 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2269 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2270 | ret = i915_cmd_parser_init_ring(engine); |
Brad Volkin | 44e895a | 2014-05-10 14:10:43 -0700 | [diff] [blame] | 2271 | if (ret) |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 2272 | goto error; |
Brad Volkin | 351e3db | 2014-02-18 10:15:46 -0800 | [diff] [blame] | 2273 | |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 2274 | return 0; |
| 2275 | |
| 2276 | error: |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2277 | intel_cleanup_ring_buffer(engine); |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 2278 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2279 | } |
| 2280 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2281 | void intel_cleanup_ring_buffer(struct intel_engine_cs *engine) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2282 | { |
John Harrison | 6402c33 | 2014-10-31 12:00:26 +0000 | [diff] [blame] | 2283 | struct drm_i915_private *dev_priv; |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 2284 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2285 | if (!intel_ring_initialized(engine)) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2286 | return; |
| 2287 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2288 | dev_priv = to_i915(engine->dev); |
John Harrison | 6402c33 | 2014-10-31 12:00:26 +0000 | [diff] [blame] | 2289 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2290 | if (engine->buffer) { |
| 2291 | intel_stop_ring_buffer(engine); |
| 2292 | WARN_ON(!IS_GEN2(engine->dev) && (I915_READ_MODE(engine) & MODE_IDLE) == 0); |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 2293 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2294 | intel_unpin_ringbuffer_obj(engine->buffer); |
| 2295 | intel_ringbuffer_free(engine->buffer); |
| 2296 | engine->buffer = NULL; |
Dave Gordon | b0366a5 | 2015-12-08 15:02:36 +0000 | [diff] [blame] | 2297 | } |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2298 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2299 | if (engine->cleanup) |
| 2300 | engine->cleanup(engine); |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 2301 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2302 | if (I915_NEED_GFX_HWS(engine->dev)) { |
| 2303 | cleanup_status_page(engine); |
Ville Syrjälä | 7d3fdff | 2016-01-11 20:48:32 +0200 | [diff] [blame] | 2304 | } else { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2305 | WARN_ON(engine->id != RCS); |
| 2306 | cleanup_phys_status_page(engine); |
Ville Syrjälä | 7d3fdff | 2016-01-11 20:48:32 +0200 | [diff] [blame] | 2307 | } |
Brad Volkin | 44e895a | 2014-05-10 14:10:43 -0700 | [diff] [blame] | 2308 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2309 | i915_cmd_parser_fini_ring(engine); |
| 2310 | i915_gem_batch_pool_fini(&engine->batch_pool); |
| 2311 | engine->dev = NULL; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2312 | } |
| 2313 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2314 | static int ring_wait_for_space(struct intel_engine_cs *engine, int n) |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2315 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2316 | struct intel_ringbuffer *ringbuf = engine->buffer; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2317 | struct drm_i915_gem_request *request; |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2318 | unsigned space; |
| 2319 | int ret; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2320 | |
Dave Gordon | ebd0fd4 | 2014-11-27 11:22:49 +0000 | [diff] [blame] | 2321 | if (intel_ring_space(ringbuf) >= n) |
| 2322 | return 0; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2323 | |
John Harrison | 79bbcc2 | 2015-06-30 12:40:55 +0100 | [diff] [blame] | 2324 | /* The whole point of reserving space is to not wait! */ |
| 2325 | WARN_ON(ringbuf->reserved_in_use); |
| 2326 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2327 | list_for_each_entry(request, &engine->request_list, list) { |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2328 | space = __intel_ring_space(request->postfix, ringbuf->tail, |
| 2329 | ringbuf->size); |
| 2330 | if (space >= n) |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2331 | break; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2332 | } |
| 2333 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2334 | if (WARN_ON(&request->list == &engine->request_list)) |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2335 | return -ENOSPC; |
| 2336 | |
Daniel Vetter | a4b3a57 | 2014-11-26 14:17:05 +0100 | [diff] [blame] | 2337 | ret = i915_wait_request(request); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2338 | if (ret) |
| 2339 | return ret; |
| 2340 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2341 | ringbuf->space = space; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2342 | return 0; |
| 2343 | } |
| 2344 | |
John Harrison | 79bbcc2 | 2015-06-30 12:40:55 +0100 | [diff] [blame] | 2345 | static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf) |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 2346 | { |
| 2347 | uint32_t __iomem *virt; |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 2348 | int rem = ringbuf->size - ringbuf->tail; |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 2349 | |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 2350 | virt = ringbuf->virtual_start + ringbuf->tail; |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 2351 | rem /= 4; |
| 2352 | while (rem--) |
| 2353 | iowrite32(MI_NOOP, virt++); |
| 2354 | |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 2355 | ringbuf->tail = 0; |
Dave Gordon | ebd0fd4 | 2014-11-27 11:22:49 +0000 | [diff] [blame] | 2356 | intel_ring_update_space(ringbuf); |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 2357 | } |
| 2358 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2359 | int intel_ring_idle(struct intel_engine_cs *engine) |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 2360 | { |
Daniel Vetter | a4b3a57 | 2014-11-26 14:17:05 +0100 | [diff] [blame] | 2361 | struct drm_i915_gem_request *req; |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 2362 | |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 2363 | /* Wait upon the last request to be completed */ |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2364 | if (list_empty(&engine->request_list)) |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 2365 | return 0; |
| 2366 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2367 | req = list_entry(engine->request_list.prev, |
| 2368 | struct drm_i915_gem_request, |
| 2369 | list); |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 2370 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2371 | /* Make sure we do not trigger any retires */ |
| 2372 | return __i915_wait_request(req, |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2373 | atomic_read(&to_i915(engine->dev)->gpu_error.reset_counter), |
| 2374 | to_i915(engine->dev)->mm.interruptible, |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2375 | NULL, NULL); |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 2376 | } |
| 2377 | |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 2378 | int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request) |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2379 | { |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 2380 | request->ringbuf = request->ring->buffer; |
John Harrison | 9eba5d4 | 2014-11-24 18:49:23 +0000 | [diff] [blame] | 2381 | return 0; |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2382 | } |
| 2383 | |
John Harrison | ccd98fe | 2015-05-29 17:44:09 +0100 | [diff] [blame] | 2384 | int intel_ring_reserve_space(struct drm_i915_gem_request *request) |
| 2385 | { |
| 2386 | /* |
| 2387 | * The first call merely notes the reserve request and is common for |
| 2388 | * all back ends. The subsequent localised _begin() call actually |
| 2389 | * ensures that the reservation is available. Without the begin, if |
| 2390 | * the request creator immediately submitted the request without |
| 2391 | * adding any commands to it then there might not actually be |
| 2392 | * sufficient room for the submission commands. |
| 2393 | */ |
| 2394 | intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST); |
| 2395 | |
| 2396 | return intel_ring_begin(request, 0); |
| 2397 | } |
| 2398 | |
John Harrison | 29b1b41 | 2015-06-18 13:10:09 +0100 | [diff] [blame] | 2399 | void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size) |
| 2400 | { |
John Harrison | ccd98fe | 2015-05-29 17:44:09 +0100 | [diff] [blame] | 2401 | WARN_ON(ringbuf->reserved_size); |
John Harrison | 29b1b41 | 2015-06-18 13:10:09 +0100 | [diff] [blame] | 2402 | WARN_ON(ringbuf->reserved_in_use); |
| 2403 | |
| 2404 | ringbuf->reserved_size = size; |
John Harrison | 29b1b41 | 2015-06-18 13:10:09 +0100 | [diff] [blame] | 2405 | } |
| 2406 | |
| 2407 | void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf) |
| 2408 | { |
| 2409 | WARN_ON(ringbuf->reserved_in_use); |
| 2410 | |
| 2411 | ringbuf->reserved_size = 0; |
| 2412 | ringbuf->reserved_in_use = false; |
| 2413 | } |
| 2414 | |
| 2415 | void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf) |
| 2416 | { |
| 2417 | WARN_ON(ringbuf->reserved_in_use); |
| 2418 | |
| 2419 | ringbuf->reserved_in_use = true; |
| 2420 | ringbuf->reserved_tail = ringbuf->tail; |
| 2421 | } |
| 2422 | |
| 2423 | void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf) |
| 2424 | { |
| 2425 | WARN_ON(!ringbuf->reserved_in_use); |
John Harrison | 79bbcc2 | 2015-06-30 12:40:55 +0100 | [diff] [blame] | 2426 | if (ringbuf->tail > ringbuf->reserved_tail) { |
| 2427 | WARN(ringbuf->tail > ringbuf->reserved_tail + ringbuf->reserved_size, |
| 2428 | "request reserved size too small: %d vs %d!\n", |
| 2429 | ringbuf->tail - ringbuf->reserved_tail, ringbuf->reserved_size); |
| 2430 | } else { |
| 2431 | /* |
| 2432 | * The ring was wrapped while the reserved space was in use. |
| 2433 | * That means that some unknown amount of the ring tail was |
| 2434 | * no-op filled and skipped. Thus simply adding the ring size |
| 2435 | * to the tail and doing the above space check will not work. |
| 2436 | * Rather than attempt to track how much tail was skipped, |
| 2437 | * it is much simpler to say that also skipping the sanity |
| 2438 | * check every once in a while is not a big issue. |
| 2439 | */ |
| 2440 | } |
John Harrison | 29b1b41 | 2015-06-18 13:10:09 +0100 | [diff] [blame] | 2441 | |
| 2442 | ringbuf->reserved_size = 0; |
| 2443 | ringbuf->reserved_in_use = false; |
| 2444 | } |
| 2445 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2446 | static int __intel_ring_prepare(struct intel_engine_cs *engine, int bytes) |
Mika Kuoppala | cbcc80d | 2012-12-04 15:12:03 +0200 | [diff] [blame] | 2447 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2448 | struct intel_ringbuffer *ringbuf = engine->buffer; |
John Harrison | 79bbcc2 | 2015-06-30 12:40:55 +0100 | [diff] [blame] | 2449 | int remain_usable = ringbuf->effective_size - ringbuf->tail; |
| 2450 | int remain_actual = ringbuf->size - ringbuf->tail; |
| 2451 | int ret, total_bytes, wait_bytes = 0; |
| 2452 | bool need_wrap = false; |
Mika Kuoppala | cbcc80d | 2012-12-04 15:12:03 +0200 | [diff] [blame] | 2453 | |
John Harrison | 79bbcc2 | 2015-06-30 12:40:55 +0100 | [diff] [blame] | 2454 | if (ringbuf->reserved_in_use) |
| 2455 | total_bytes = bytes; |
| 2456 | else |
| 2457 | total_bytes = bytes + ringbuf->reserved_size; |
John Harrison | 29b1b41 | 2015-06-18 13:10:09 +0100 | [diff] [blame] | 2458 | |
John Harrison | 79bbcc2 | 2015-06-30 12:40:55 +0100 | [diff] [blame] | 2459 | if (unlikely(bytes > remain_usable)) { |
| 2460 | /* |
| 2461 | * Not enough space for the basic request. So need to flush |
| 2462 | * out the remainder and then wait for base + reserved. |
| 2463 | */ |
| 2464 | wait_bytes = remain_actual + total_bytes; |
| 2465 | need_wrap = true; |
| 2466 | } else { |
| 2467 | if (unlikely(total_bytes > remain_usable)) { |
| 2468 | /* |
| 2469 | * The base request will fit but the reserved space |
| 2470 | * falls off the end. So only need to to wait for the |
| 2471 | * reserved size after flushing out the remainder. |
| 2472 | */ |
| 2473 | wait_bytes = remain_actual + ringbuf->reserved_size; |
| 2474 | need_wrap = true; |
| 2475 | } else if (total_bytes > ringbuf->space) { |
| 2476 | /* No wrapping required, just waiting. */ |
| 2477 | wait_bytes = total_bytes; |
John Harrison | 29b1b41 | 2015-06-18 13:10:09 +0100 | [diff] [blame] | 2478 | } |
Mika Kuoppala | cbcc80d | 2012-12-04 15:12:03 +0200 | [diff] [blame] | 2479 | } |
| 2480 | |
John Harrison | 79bbcc2 | 2015-06-30 12:40:55 +0100 | [diff] [blame] | 2481 | if (wait_bytes) { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2482 | ret = ring_wait_for_space(engine, wait_bytes); |
Mika Kuoppala | cbcc80d | 2012-12-04 15:12:03 +0200 | [diff] [blame] | 2483 | if (unlikely(ret)) |
| 2484 | return ret; |
John Harrison | 79bbcc2 | 2015-06-30 12:40:55 +0100 | [diff] [blame] | 2485 | |
| 2486 | if (need_wrap) |
| 2487 | __wrap_ring_buffer(ringbuf); |
Mika Kuoppala | cbcc80d | 2012-12-04 15:12:03 +0200 | [diff] [blame] | 2488 | } |
| 2489 | |
Mika Kuoppala | cbcc80d | 2012-12-04 15:12:03 +0200 | [diff] [blame] | 2490 | return 0; |
| 2491 | } |
| 2492 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 2493 | int intel_ring_begin(struct drm_i915_gem_request *req, |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 2494 | int num_dwords) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2495 | { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2496 | struct intel_engine_cs *engine; |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 2497 | struct drm_i915_private *dev_priv; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 2498 | int ret; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2499 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 2500 | WARN_ON(req == NULL); |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2501 | engine = req->ring; |
| 2502 | dev_priv = engine->dev->dev_private; |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 2503 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 2504 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
| 2505 | dev_priv->mm.interruptible); |
Daniel Vetter | de2b998 | 2012-07-04 22:52:50 +0200 | [diff] [blame] | 2506 | if (ret) |
| 2507 | return ret; |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 2508 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2509 | ret = __intel_ring_prepare(engine, num_dwords * sizeof(uint32_t)); |
Chris Wilson | 304d695 | 2014-01-02 14:32:35 +0000 | [diff] [blame] | 2510 | if (ret) |
| 2511 | return ret; |
| 2512 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2513 | engine->buffer->space -= num_dwords * sizeof(uint32_t); |
Chris Wilson | 304d695 | 2014-01-02 14:32:35 +0000 | [diff] [blame] | 2514 | return 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2515 | } |
| 2516 | |
Ville Syrjälä | 753b1ad | 2014-02-11 19:52:05 +0200 | [diff] [blame] | 2517 | /* Align the ring tail to a cacheline boundary */ |
John Harrison | bba09b1 | 2015-05-29 17:44:06 +0100 | [diff] [blame] | 2518 | int intel_ring_cacheline_align(struct drm_i915_gem_request *req) |
Ville Syrjälä | 753b1ad | 2014-02-11 19:52:05 +0200 | [diff] [blame] | 2519 | { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2520 | struct intel_engine_cs *engine = req->ring; |
| 2521 | int num_dwords = (engine->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); |
Ville Syrjälä | 753b1ad | 2014-02-11 19:52:05 +0200 | [diff] [blame] | 2522 | int ret; |
| 2523 | |
| 2524 | if (num_dwords == 0) |
| 2525 | return 0; |
| 2526 | |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 2527 | num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 2528 | ret = intel_ring_begin(req, num_dwords); |
Ville Syrjälä | 753b1ad | 2014-02-11 19:52:05 +0200 | [diff] [blame] | 2529 | if (ret) |
| 2530 | return ret; |
| 2531 | |
| 2532 | while (num_dwords--) |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2533 | intel_ring_emit(engine, MI_NOOP); |
Ville Syrjälä | 753b1ad | 2014-02-11 19:52:05 +0200 | [diff] [blame] | 2534 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2535 | intel_ring_advance(engine); |
Ville Syrjälä | 753b1ad | 2014-02-11 19:52:05 +0200 | [diff] [blame] | 2536 | |
| 2537 | return 0; |
| 2538 | } |
| 2539 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2540 | void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno) |
Mika Kuoppala | 498d2ac | 2012-12-04 15:12:04 +0200 | [diff] [blame] | 2541 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2542 | struct drm_device *dev = engine->dev; |
Oscar Mateo | 3b2cc8a | 2014-06-11 16:17:16 +0100 | [diff] [blame] | 2543 | struct drm_i915_private *dev_priv = dev->dev_private; |
Mika Kuoppala | 498d2ac | 2012-12-04 15:12:04 +0200 | [diff] [blame] | 2544 | |
Oscar Mateo | 3b2cc8a | 2014-06-11 16:17:16 +0100 | [diff] [blame] | 2545 | if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2546 | I915_WRITE(RING_SYNC_0(engine->mmio_base), 0); |
| 2547 | I915_WRITE(RING_SYNC_1(engine->mmio_base), 0); |
Oscar Mateo | 3b2cc8a | 2014-06-11 16:17:16 +0100 | [diff] [blame] | 2548 | if (HAS_VEBOX(dev)) |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2549 | I915_WRITE(RING_SYNC_2(engine->mmio_base), 0); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2550 | } |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 2551 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2552 | engine->set_seqno(engine, seqno); |
| 2553 | engine->hangcheck.seqno = seqno; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2554 | } |
| 2555 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2556 | static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine, |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 2557 | u32 value) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2558 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2559 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2560 | |
| 2561 | /* Every tail move must follow the sequence below */ |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2562 | |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 2563 | /* Disable notification that the ring is IDLE. The GT |
| 2564 | * will then assume that it is busy and bring it out of rc6. |
| 2565 | */ |
| 2566 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
| 2567 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
| 2568 | |
| 2569 | /* Clear the context id. Here be magic! */ |
| 2570 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); |
| 2571 | |
| 2572 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2573 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 2574 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
| 2575 | 50)) |
| 2576 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2577 | |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 2578 | /* Now that the ring is fully powered up, update the tail */ |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 2579 | I915_WRITE_TAIL(engine, value); |
| 2580 | POSTING_READ(RING_TAIL(engine->mmio_base)); |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 2581 | |
| 2582 | /* Let the ring send IDLE messages to the GT again, |
| 2583 | * and so let it sleep to conserve power when idle. |
| 2584 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2585 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 2586 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2587 | } |
| 2588 | |
John Harrison | a84c3ae | 2015-05-29 17:43:57 +0100 | [diff] [blame] | 2589 | static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req, |
Ben Widawsky | ea25132 | 2013-05-28 19:22:21 -0700 | [diff] [blame] | 2590 | u32 invalidate, u32 flush) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2591 | { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2592 | struct intel_engine_cs *engine = req->ring; |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 2593 | uint32_t cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 2594 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2595 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 2596 | ret = intel_ring_begin(req, 4); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 2597 | if (ret) |
| 2598 | return ret; |
| 2599 | |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 2600 | cmd = MI_FLUSH_DW; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2601 | if (INTEL_INFO(engine->dev)->gen >= 8) |
Ben Widawsky | 075b3bb | 2013-11-02 21:07:13 -0700 | [diff] [blame] | 2602 | cmd += 1; |
Chris Wilson | f0a1fb1 | 2015-01-22 13:42:00 +0000 | [diff] [blame] | 2603 | |
| 2604 | /* We always require a command barrier so that subsequent |
| 2605 | * commands, such as breadcrumb interrupts, are strictly ordered |
| 2606 | * wrt the contents of the write cache being flushed to memory |
| 2607 | * (and thus being coherent from the CPU). |
| 2608 | */ |
| 2609 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; |
| 2610 | |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 2611 | /* |
| 2612 | * Bspec vol 1c.5 - video engine command streamer: |
| 2613 | * "If ENABLED, all TLBs will be invalidated once the flush |
| 2614 | * operation is complete. This bit is only valid when the |
| 2615 | * Post-Sync Operation field is a value of 1h or 3h." |
| 2616 | */ |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 2617 | if (invalidate & I915_GEM_GPU_DOMAINS) |
Chris Wilson | f0a1fb1 | 2015-01-22 13:42:00 +0000 | [diff] [blame] | 2618 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; |
| 2619 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2620 | intel_ring_emit(engine, cmd); |
| 2621 | intel_ring_emit(engine, |
| 2622 | I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
| 2623 | if (INTEL_INFO(engine->dev)->gen >= 8) { |
| 2624 | intel_ring_emit(engine, 0); /* upper addr */ |
| 2625 | intel_ring_emit(engine, 0); /* value */ |
Ben Widawsky | 075b3bb | 2013-11-02 21:07:13 -0700 | [diff] [blame] | 2626 | } else { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2627 | intel_ring_emit(engine, 0); |
| 2628 | intel_ring_emit(engine, MI_NOOP); |
Ben Widawsky | 075b3bb | 2013-11-02 21:07:13 -0700 | [diff] [blame] | 2629 | } |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2630 | intel_ring_advance(engine); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 2631 | return 0; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2632 | } |
| 2633 | |
| 2634 | static int |
John Harrison | 53fddaf | 2015-05-29 17:44:02 +0100 | [diff] [blame] | 2635 | gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
Ben Widawsky | 9bcb144 | 2014-04-28 19:29:25 -0700 | [diff] [blame] | 2636 | u64 offset, u32 len, |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 2637 | unsigned dispatch_flags) |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2638 | { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2639 | struct intel_engine_cs *engine = req->ring; |
| 2640 | bool ppgtt = USES_PPGTT(engine->dev) && |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 2641 | !(dispatch_flags & I915_DISPATCH_SECURE); |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2642 | int ret; |
| 2643 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 2644 | ret = intel_ring_begin(req, 4); |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2645 | if (ret) |
| 2646 | return ret; |
| 2647 | |
| 2648 | /* FIXME(BDW): Address space and security selectors. */ |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2649 | intel_ring_emit(engine, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) | |
Abdiel Janulgue | 919032e | 2015-06-16 13:39:40 +0300 | [diff] [blame] | 2650 | (dispatch_flags & I915_DISPATCH_RS ? |
| 2651 | MI_BATCH_RESOURCE_STREAMER : 0)); |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2652 | intel_ring_emit(engine, lower_32_bits(offset)); |
| 2653 | intel_ring_emit(engine, upper_32_bits(offset)); |
| 2654 | intel_ring_emit(engine, MI_NOOP); |
| 2655 | intel_ring_advance(engine); |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2656 | |
| 2657 | return 0; |
| 2658 | } |
| 2659 | |
| 2660 | static int |
John Harrison | 53fddaf | 2015-05-29 17:44:02 +0100 | [diff] [blame] | 2661 | hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 2662 | u64 offset, u32 len, |
| 2663 | unsigned dispatch_flags) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2664 | { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2665 | struct intel_engine_cs *engine = req->ring; |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2666 | int ret; |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 2667 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 2668 | ret = intel_ring_begin(req, 2); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2669 | if (ret) |
| 2670 | return ret; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 2671 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2672 | intel_ring_emit(engine, |
Chris Wilson | 7707225 | 2014-09-10 12:18:27 +0100 | [diff] [blame] | 2673 | MI_BATCH_BUFFER_START | |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 2674 | (dispatch_flags & I915_DISPATCH_SECURE ? |
Abdiel Janulgue | 919032e | 2015-06-16 13:39:40 +0300 | [diff] [blame] | 2675 | 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) | |
| 2676 | (dispatch_flags & I915_DISPATCH_RS ? |
| 2677 | MI_BATCH_RESOURCE_STREAMER : 0)); |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 2678 | /* bit0-7 is the length on GEN6+ */ |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2679 | intel_ring_emit(engine, offset); |
| 2680 | intel_ring_advance(engine); |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 2681 | |
| 2682 | return 0; |
| 2683 | } |
| 2684 | |
| 2685 | static int |
John Harrison | 53fddaf | 2015-05-29 17:44:02 +0100 | [diff] [blame] | 2686 | gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
Ben Widawsky | 9bcb144 | 2014-04-28 19:29:25 -0700 | [diff] [blame] | 2687 | u64 offset, u32 len, |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 2688 | unsigned dispatch_flags) |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 2689 | { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2690 | struct intel_engine_cs *engine = req->ring; |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 2691 | int ret; |
| 2692 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 2693 | ret = intel_ring_begin(req, 2); |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 2694 | if (ret) |
| 2695 | return ret; |
| 2696 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2697 | intel_ring_emit(engine, |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 2698 | MI_BATCH_BUFFER_START | |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 2699 | (dispatch_flags & I915_DISPATCH_SECURE ? |
| 2700 | 0 : MI_BATCH_NON_SECURE_I965)); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2701 | /* bit0-7 is the length on GEN6+ */ |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2702 | intel_ring_emit(engine, offset); |
| 2703 | intel_ring_advance(engine); |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 2704 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2705 | return 0; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2706 | } |
| 2707 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2708 | /* Blitter support (SandyBridge+) */ |
| 2709 | |
John Harrison | a84c3ae | 2015-05-29 17:43:57 +0100 | [diff] [blame] | 2710 | static int gen6_ring_flush(struct drm_i915_gem_request *req, |
Ben Widawsky | ea25132 | 2013-05-28 19:22:21 -0700 | [diff] [blame] | 2711 | u32 invalidate, u32 flush) |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 2712 | { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2713 | struct intel_engine_cs *engine = req->ring; |
| 2714 | struct drm_device *dev = engine->dev; |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 2715 | uint32_t cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 2716 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2717 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 2718 | ret = intel_ring_begin(req, 4); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 2719 | if (ret) |
| 2720 | return ret; |
| 2721 | |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 2722 | cmd = MI_FLUSH_DW; |
Paulo Zanoni | dbef0f1 | 2015-02-13 17:23:46 -0200 | [diff] [blame] | 2723 | if (INTEL_INFO(dev)->gen >= 8) |
Ben Widawsky | 075b3bb | 2013-11-02 21:07:13 -0700 | [diff] [blame] | 2724 | cmd += 1; |
Chris Wilson | f0a1fb1 | 2015-01-22 13:42:00 +0000 | [diff] [blame] | 2725 | |
| 2726 | /* We always require a command barrier so that subsequent |
| 2727 | * commands, such as breadcrumb interrupts, are strictly ordered |
| 2728 | * wrt the contents of the write cache being flushed to memory |
| 2729 | * (and thus being coherent from the CPU). |
| 2730 | */ |
| 2731 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; |
| 2732 | |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 2733 | /* |
| 2734 | * Bspec vol 1c.3 - blitter engine command streamer: |
| 2735 | * "If ENABLED, all TLBs will be invalidated once the flush |
| 2736 | * operation is complete. This bit is only valid when the |
| 2737 | * Post-Sync Operation field is a value of 1h or 3h." |
| 2738 | */ |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 2739 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
Chris Wilson | f0a1fb1 | 2015-01-22 13:42:00 +0000 | [diff] [blame] | 2740 | cmd |= MI_INVALIDATE_TLB; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2741 | intel_ring_emit(engine, cmd); |
| 2742 | intel_ring_emit(engine, |
| 2743 | I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
Paulo Zanoni | dbef0f1 | 2015-02-13 17:23:46 -0200 | [diff] [blame] | 2744 | if (INTEL_INFO(dev)->gen >= 8) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2745 | intel_ring_emit(engine, 0); /* upper addr */ |
| 2746 | intel_ring_emit(engine, 0); /* value */ |
Ben Widawsky | 075b3bb | 2013-11-02 21:07:13 -0700 | [diff] [blame] | 2747 | } else { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2748 | intel_ring_emit(engine, 0); |
| 2749 | intel_ring_emit(engine, MI_NOOP); |
Ben Widawsky | 075b3bb | 2013-11-02 21:07:13 -0700 | [diff] [blame] | 2750 | } |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2751 | intel_ring_advance(engine); |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 2752 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 2753 | return 0; |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 2754 | } |
| 2755 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 2756 | int intel_init_render_ring_buffer(struct drm_device *dev) |
| 2757 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 2758 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2759 | struct intel_engine_cs *engine = &dev_priv->ring[RCS]; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 2760 | struct drm_i915_gem_object *obj; |
| 2761 | int ret; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 2762 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2763 | engine->name = "render ring"; |
| 2764 | engine->id = RCS; |
| 2765 | engine->exec_id = I915_EXEC_RENDER; |
| 2766 | engine->mmio_base = RENDER_RING_BASE; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 2767 | |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2768 | if (INTEL_INFO(dev)->gen >= 8) { |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 2769 | if (i915_semaphore_is_enabled(dev)) { |
| 2770 | obj = i915_gem_alloc_object(dev, 4096); |
| 2771 | if (obj == NULL) { |
| 2772 | DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n"); |
| 2773 | i915.semaphores = 0; |
| 2774 | } else { |
| 2775 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
| 2776 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK); |
| 2777 | if (ret != 0) { |
| 2778 | drm_gem_object_unreference(&obj->base); |
| 2779 | DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n"); |
| 2780 | i915.semaphores = 0; |
| 2781 | } else |
| 2782 | dev_priv->semaphore_obj = obj; |
| 2783 | } |
| 2784 | } |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 2785 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2786 | engine->init_context = intel_rcs_ctx_init; |
| 2787 | engine->add_request = gen6_add_request; |
| 2788 | engine->flush = gen8_render_ring_flush; |
| 2789 | engine->irq_get = gen8_ring_get_irq; |
| 2790 | engine->irq_put = gen8_ring_put_irq; |
| 2791 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
| 2792 | engine->get_seqno = gen6_ring_get_seqno; |
| 2793 | engine->set_seqno = ring_set_seqno; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2794 | if (i915_semaphore_is_enabled(dev)) { |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 2795 | WARN_ON(!dev_priv->semaphore_obj); |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2796 | engine->semaphore.sync_to = gen8_ring_sync; |
| 2797 | engine->semaphore.signal = gen8_rcs_signal; |
| 2798 | GEN8_RING_SEMAPHORE_INIT(engine); |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2799 | } |
| 2800 | } else if (INTEL_INFO(dev)->gen >= 6) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2801 | engine->init_context = intel_rcs_ctx_init; |
| 2802 | engine->add_request = gen6_add_request; |
| 2803 | engine->flush = gen7_render_ring_flush; |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 2804 | if (INTEL_INFO(dev)->gen == 6) |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2805 | engine->flush = gen6_render_ring_flush; |
| 2806 | engine->irq_get = gen6_ring_get_irq; |
| 2807 | engine->irq_put = gen6_ring_put_irq; |
| 2808 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
| 2809 | engine->get_seqno = gen6_ring_get_seqno; |
| 2810 | engine->set_seqno = ring_set_seqno; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2811 | if (i915_semaphore_is_enabled(dev)) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2812 | engine->semaphore.sync_to = gen6_ring_sync; |
| 2813 | engine->semaphore.signal = gen6_signal; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2814 | /* |
| 2815 | * The current semaphore is only applied on pre-gen8 |
| 2816 | * platform. And there is no VCS2 ring on the pre-gen8 |
| 2817 | * platform. So the semaphore between RCS and VCS2 is |
| 2818 | * initialized as INVALID. Gen8 will initialize the |
| 2819 | * sema between VCS2 and RCS later. |
| 2820 | */ |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2821 | engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID; |
| 2822 | engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV; |
| 2823 | engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB; |
| 2824 | engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE; |
| 2825 | engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; |
| 2826 | engine->semaphore.mbox.signal[RCS] = GEN6_NOSYNC; |
| 2827 | engine->semaphore.mbox.signal[VCS] = GEN6_VRSYNC; |
| 2828 | engine->semaphore.mbox.signal[BCS] = GEN6_BRSYNC; |
| 2829 | engine->semaphore.mbox.signal[VECS] = GEN6_VERSYNC; |
| 2830 | engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2831 | } |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 2832 | } else if (IS_GEN5(dev)) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2833 | engine->add_request = pc_render_add_request; |
| 2834 | engine->flush = gen4_render_ring_flush; |
| 2835 | engine->get_seqno = pc_render_get_seqno; |
| 2836 | engine->set_seqno = pc_render_set_seqno; |
| 2837 | engine->irq_get = gen5_ring_get_irq; |
| 2838 | engine->irq_put = gen5_ring_put_irq; |
| 2839 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT | |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 2840 | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 2841 | } else { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2842 | engine->add_request = i9xx_add_request; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 2843 | if (INTEL_INFO(dev)->gen < 4) |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2844 | engine->flush = gen2_render_ring_flush; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 2845 | else |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2846 | engine->flush = gen4_render_ring_flush; |
| 2847 | engine->get_seqno = ring_get_seqno; |
| 2848 | engine->set_seqno = ring_set_seqno; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 2849 | if (IS_GEN2(dev)) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2850 | engine->irq_get = i8xx_ring_get_irq; |
| 2851 | engine->irq_put = i8xx_ring_put_irq; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 2852 | } else { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2853 | engine->irq_get = i9xx_ring_get_irq; |
| 2854 | engine->irq_put = i9xx_ring_put_irq; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 2855 | } |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2856 | engine->irq_enable_mask = I915_USER_INTERRUPT; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 2857 | } |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2858 | engine->write_tail = ring_write_tail; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2859 | |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 2860 | if (IS_HASWELL(dev)) |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2861 | engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2862 | else if (IS_GEN8(dev)) |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2863 | engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 2864 | else if (INTEL_INFO(dev)->gen >= 6) |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2865 | engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 2866 | else if (INTEL_INFO(dev)->gen >= 4) |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2867 | engine->dispatch_execbuffer = i965_dispatch_execbuffer; |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 2868 | else if (IS_I830(dev) || IS_845G(dev)) |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2869 | engine->dispatch_execbuffer = i830_dispatch_execbuffer; |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 2870 | else |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2871 | engine->dispatch_execbuffer = i915_dispatch_execbuffer; |
| 2872 | engine->init_hw = init_render_ring; |
| 2873 | engine->cleanup = render_ring_cleanup; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 2874 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 2875 | /* Workaround batchbuffer to combat CS tlb bug. */ |
| 2876 | if (HAS_BROKEN_CS_TLB(dev)) { |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 2877 | obj = i915_gem_alloc_object(dev, I830_WA_SIZE); |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 2878 | if (obj == NULL) { |
| 2879 | DRM_ERROR("Failed to allocate batch bo\n"); |
| 2880 | return -ENOMEM; |
| 2881 | } |
| 2882 | |
Daniel Vetter | be1fa12 | 2014-02-14 14:01:14 +0100 | [diff] [blame] | 2883 | ret = i915_gem_obj_ggtt_pin(obj, 0, 0); |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 2884 | if (ret != 0) { |
| 2885 | drm_gem_object_unreference(&obj->base); |
| 2886 | DRM_ERROR("Failed to ping batch bo\n"); |
| 2887 | return ret; |
| 2888 | } |
| 2889 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2890 | engine->scratch.obj = obj; |
| 2891 | engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 2892 | } |
| 2893 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2894 | ret = intel_init_ring_buffer(dev, engine); |
Daniel Vetter | 99be1df | 2014-11-20 00:33:06 +0100 | [diff] [blame] | 2895 | if (ret) |
| 2896 | return ret; |
| 2897 | |
| 2898 | if (INTEL_INFO(dev)->gen >= 5) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2899 | ret = intel_init_pipe_control(engine); |
Daniel Vetter | 99be1df | 2014-11-20 00:33:06 +0100 | [diff] [blame] | 2900 | if (ret) |
| 2901 | return ret; |
| 2902 | } |
| 2903 | |
| 2904 | return 0; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 2905 | } |
| 2906 | |
| 2907 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
| 2908 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 2909 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2910 | struct intel_engine_cs *engine = &dev_priv->ring[VCS]; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 2911 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2912 | engine->name = "bsd ring"; |
| 2913 | engine->id = VCS; |
| 2914 | engine->exec_id = I915_EXEC_BSD; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2915 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2916 | engine->write_tail = ring_write_tail; |
Ben Widawsky | 780f18c | 2013-11-02 21:07:28 -0700 | [diff] [blame] | 2917 | if (INTEL_INFO(dev)->gen >= 6) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2918 | engine->mmio_base = GEN6_BSD_RING_BASE; |
Daniel Vetter | 0fd2c20 | 2012-04-11 22:12:55 +0200 | [diff] [blame] | 2919 | /* gen6 bsd needs a special wa for tail updates */ |
| 2920 | if (IS_GEN6(dev)) |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2921 | engine->write_tail = gen6_bsd_ring_write_tail; |
| 2922 | engine->flush = gen6_bsd_ring_flush; |
| 2923 | engine->add_request = gen6_add_request; |
| 2924 | engine->get_seqno = gen6_ring_get_seqno; |
| 2925 | engine->set_seqno = ring_set_seqno; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2926 | if (INTEL_INFO(dev)->gen >= 8) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2927 | engine->irq_enable_mask = |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2928 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2929 | engine->irq_get = gen8_ring_get_irq; |
| 2930 | engine->irq_put = gen8_ring_put_irq; |
| 2931 | engine->dispatch_execbuffer = |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2932 | gen8_ring_dispatch_execbuffer; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2933 | if (i915_semaphore_is_enabled(dev)) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2934 | engine->semaphore.sync_to = gen8_ring_sync; |
| 2935 | engine->semaphore.signal = gen8_xcs_signal; |
| 2936 | GEN8_RING_SEMAPHORE_INIT(engine); |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2937 | } |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2938 | } else { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2939 | engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
| 2940 | engine->irq_get = gen6_ring_get_irq; |
| 2941 | engine->irq_put = gen6_ring_put_irq; |
| 2942 | engine->dispatch_execbuffer = |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2943 | gen6_ring_dispatch_execbuffer; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2944 | if (i915_semaphore_is_enabled(dev)) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2945 | engine->semaphore.sync_to = gen6_ring_sync; |
| 2946 | engine->semaphore.signal = gen6_signal; |
| 2947 | engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR; |
| 2948 | engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID; |
| 2949 | engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB; |
| 2950 | engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE; |
| 2951 | engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; |
| 2952 | engine->semaphore.mbox.signal[RCS] = GEN6_RVSYNC; |
| 2953 | engine->semaphore.mbox.signal[VCS] = GEN6_NOSYNC; |
| 2954 | engine->semaphore.mbox.signal[BCS] = GEN6_BVSYNC; |
| 2955 | engine->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC; |
| 2956 | engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2957 | } |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2958 | } |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2959 | } else { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2960 | engine->mmio_base = BSD_RING_BASE; |
| 2961 | engine->flush = bsd_ring_flush; |
| 2962 | engine->add_request = i9xx_add_request; |
| 2963 | engine->get_seqno = ring_get_seqno; |
| 2964 | engine->set_seqno = ring_set_seqno; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 2965 | if (IS_GEN5(dev)) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2966 | engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
| 2967 | engine->irq_get = gen5_ring_get_irq; |
| 2968 | engine->irq_put = gen5_ring_put_irq; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 2969 | } else { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2970 | engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
| 2971 | engine->irq_get = i9xx_ring_get_irq; |
| 2972 | engine->irq_put = i9xx_ring_put_irq; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 2973 | } |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2974 | engine->dispatch_execbuffer = i965_dispatch_execbuffer; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2975 | } |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2976 | engine->init_hw = init_ring_common; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2977 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2978 | return intel_init_ring_buffer(dev, engine); |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 2979 | } |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2980 | |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 2981 | /** |
Damien Lespiau | 6265992 | 2015-01-29 14:13:40 +0000 | [diff] [blame] | 2982 | * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3) |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 2983 | */ |
| 2984 | int intel_init_bsd2_ring_buffer(struct drm_device *dev) |
| 2985 | { |
| 2986 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2987 | struct intel_engine_cs *engine = &dev_priv->ring[VCS2]; |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 2988 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2989 | engine->name = "bsd2 ring"; |
| 2990 | engine->id = VCS2; |
| 2991 | engine->exec_id = I915_EXEC_BSD; |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 2992 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2993 | engine->write_tail = ring_write_tail; |
| 2994 | engine->mmio_base = GEN8_BSD2_RING_BASE; |
| 2995 | engine->flush = gen6_bsd_ring_flush; |
| 2996 | engine->add_request = gen6_add_request; |
| 2997 | engine->get_seqno = gen6_ring_get_seqno; |
| 2998 | engine->set_seqno = ring_set_seqno; |
| 2999 | engine->irq_enable_mask = |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 3000 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3001 | engine->irq_get = gen8_ring_get_irq; |
| 3002 | engine->irq_put = gen8_ring_put_irq; |
| 3003 | engine->dispatch_execbuffer = |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 3004 | gen8_ring_dispatch_execbuffer; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 3005 | if (i915_semaphore_is_enabled(dev)) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3006 | engine->semaphore.sync_to = gen8_ring_sync; |
| 3007 | engine->semaphore.signal = gen8_xcs_signal; |
| 3008 | GEN8_RING_SEMAPHORE_INIT(engine); |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 3009 | } |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3010 | engine->init_hw = init_ring_common; |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 3011 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3012 | return intel_init_ring_buffer(dev, engine); |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 3013 | } |
| 3014 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3015 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
| 3016 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 3017 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3018 | struct intel_engine_cs *engine = &dev_priv->ring[BCS]; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3019 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3020 | engine->name = "blitter ring"; |
| 3021 | engine->id = BCS; |
| 3022 | engine->exec_id = I915_EXEC_BLT; |
Daniel Vetter | 3535d9d | 2012-04-11 22:12:50 +0200 | [diff] [blame] | 3023 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3024 | engine->mmio_base = BLT_RING_BASE; |
| 3025 | engine->write_tail = ring_write_tail; |
| 3026 | engine->flush = gen6_ring_flush; |
| 3027 | engine->add_request = gen6_add_request; |
| 3028 | engine->get_seqno = gen6_ring_get_seqno; |
| 3029 | engine->set_seqno = ring_set_seqno; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3030 | if (INTEL_INFO(dev)->gen >= 8) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3031 | engine->irq_enable_mask = |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3032 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3033 | engine->irq_get = gen8_ring_get_irq; |
| 3034 | engine->irq_put = gen8_ring_put_irq; |
| 3035 | engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 3036 | if (i915_semaphore_is_enabled(dev)) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3037 | engine->semaphore.sync_to = gen8_ring_sync; |
| 3038 | engine->semaphore.signal = gen8_xcs_signal; |
| 3039 | GEN8_RING_SEMAPHORE_INIT(engine); |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 3040 | } |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3041 | } else { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3042 | engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
| 3043 | engine->irq_get = gen6_ring_get_irq; |
| 3044 | engine->irq_put = gen6_ring_put_irq; |
| 3045 | engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 3046 | if (i915_semaphore_is_enabled(dev)) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3047 | engine->semaphore.signal = gen6_signal; |
| 3048 | engine->semaphore.sync_to = gen6_ring_sync; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 3049 | /* |
| 3050 | * The current semaphore is only applied on pre-gen8 |
| 3051 | * platform. And there is no VCS2 ring on the pre-gen8 |
| 3052 | * platform. So the semaphore between BCS and VCS2 is |
| 3053 | * initialized as INVALID. Gen8 will initialize the |
| 3054 | * sema between BCS and VCS2 later. |
| 3055 | */ |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3056 | engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR; |
| 3057 | engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV; |
| 3058 | engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID; |
| 3059 | engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE; |
| 3060 | engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; |
| 3061 | engine->semaphore.mbox.signal[RCS] = GEN6_RBSYNC; |
| 3062 | engine->semaphore.mbox.signal[VCS] = GEN6_VBSYNC; |
| 3063 | engine->semaphore.mbox.signal[BCS] = GEN6_NOSYNC; |
| 3064 | engine->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC; |
| 3065 | engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 3066 | } |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3067 | } |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3068 | engine->init_hw = init_ring_common; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3069 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3070 | return intel_init_ring_buffer(dev, engine); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3071 | } |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 3072 | |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 3073 | int intel_init_vebox_ring_buffer(struct drm_device *dev) |
| 3074 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 3075 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3076 | struct intel_engine_cs *engine = &dev_priv->ring[VECS]; |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 3077 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3078 | engine->name = "video enhancement ring"; |
| 3079 | engine->id = VECS; |
| 3080 | engine->exec_id = I915_EXEC_VEBOX; |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 3081 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3082 | engine->mmio_base = VEBOX_RING_BASE; |
| 3083 | engine->write_tail = ring_write_tail; |
| 3084 | engine->flush = gen6_ring_flush; |
| 3085 | engine->add_request = gen6_add_request; |
| 3086 | engine->get_seqno = gen6_ring_get_seqno; |
| 3087 | engine->set_seqno = ring_set_seqno; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3088 | |
| 3089 | if (INTEL_INFO(dev)->gen >= 8) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3090 | engine->irq_enable_mask = |
Daniel Vetter | 40c499f | 2013-11-07 21:40:39 -0800 | [diff] [blame] | 3091 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3092 | engine->irq_get = gen8_ring_get_irq; |
| 3093 | engine->irq_put = gen8_ring_put_irq; |
| 3094 | engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 3095 | if (i915_semaphore_is_enabled(dev)) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3096 | engine->semaphore.sync_to = gen8_ring_sync; |
| 3097 | engine->semaphore.signal = gen8_xcs_signal; |
| 3098 | GEN8_RING_SEMAPHORE_INIT(engine); |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 3099 | } |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3100 | } else { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3101 | engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
| 3102 | engine->irq_get = hsw_vebox_get_irq; |
| 3103 | engine->irq_put = hsw_vebox_put_irq; |
| 3104 | engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 3105 | if (i915_semaphore_is_enabled(dev)) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3106 | engine->semaphore.sync_to = gen6_ring_sync; |
| 3107 | engine->semaphore.signal = gen6_signal; |
| 3108 | engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER; |
| 3109 | engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV; |
| 3110 | engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB; |
| 3111 | engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID; |
| 3112 | engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; |
| 3113 | engine->semaphore.mbox.signal[RCS] = GEN6_RVESYNC; |
| 3114 | engine->semaphore.mbox.signal[VCS] = GEN6_VVESYNC; |
| 3115 | engine->semaphore.mbox.signal[BCS] = GEN6_BVESYNC; |
| 3116 | engine->semaphore.mbox.signal[VECS] = GEN6_NOSYNC; |
| 3117 | engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 3118 | } |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3119 | } |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3120 | engine->init_hw = init_ring_common; |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 3121 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3122 | return intel_init_ring_buffer(dev, engine); |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 3123 | } |
| 3124 | |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 3125 | int |
John Harrison | 4866d72 | 2015-05-29 17:43:55 +0100 | [diff] [blame] | 3126 | intel_ring_flush_all_caches(struct drm_i915_gem_request *req) |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 3127 | { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3128 | struct intel_engine_cs *engine = req->ring; |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 3129 | int ret; |
| 3130 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3131 | if (!engine->gpu_caches_dirty) |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 3132 | return 0; |
| 3133 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3134 | ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS); |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 3135 | if (ret) |
| 3136 | return ret; |
| 3137 | |
John Harrison | a84c3ae | 2015-05-29 17:43:57 +0100 | [diff] [blame] | 3138 | trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS); |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 3139 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3140 | engine->gpu_caches_dirty = false; |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 3141 | return 0; |
| 3142 | } |
| 3143 | |
| 3144 | int |
John Harrison | 2f20055 | 2015-05-29 17:43:53 +0100 | [diff] [blame] | 3145 | intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req) |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 3146 | { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3147 | struct intel_engine_cs *engine = req->ring; |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 3148 | uint32_t flush_domains; |
| 3149 | int ret; |
| 3150 | |
| 3151 | flush_domains = 0; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3152 | if (engine->gpu_caches_dirty) |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 3153 | flush_domains = I915_GEM_GPU_DOMAINS; |
| 3154 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3155 | ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains); |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 3156 | if (ret) |
| 3157 | return ret; |
| 3158 | |
John Harrison | a84c3ae | 2015-05-29 17:43:57 +0100 | [diff] [blame] | 3159 | trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains); |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 3160 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3161 | engine->gpu_caches_dirty = false; |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 3162 | return 0; |
| 3163 | } |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 3164 | |
| 3165 | void |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 3166 | intel_stop_ring_buffer(struct intel_engine_cs *engine) |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 3167 | { |
| 3168 | int ret; |
| 3169 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 3170 | if (!intel_ring_initialized(engine)) |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 3171 | return; |
| 3172 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 3173 | ret = intel_ring_idle(engine); |
| 3174 | if (ret && !i915_reset_in_progress(&to_i915(engine->dev)->gpu_error)) |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 3175 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 3176 | engine->name, ret); |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 3177 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame^] | 3178 | stop_ring(engine); |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 3179 | } |