blob: f1a8b454920afa566ea250fadaf018943a22582a [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001#ifndef _I386_PGTABLE_3LEVEL_H
2#define _I386_PGTABLE_3LEVEL_H
3
4#include <asm-generic/pgtable-nopud.h>
5
6/*
7 * Intel Physical Address Extension (PAE) Mode - three-level page
8 * tables on PPro+ CPUs.
9 *
10 * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
11 */
12
13#define pte_ERROR(e) \
14 printk("%s:%d: bad pte %p(%08lx%08lx).\n", __FILE__, __LINE__, &(e), (e).pte_high, (e).pte_low)
15#define pmd_ERROR(e) \
16 printk("%s:%d: bad pmd %p(%016Lx).\n", __FILE__, __LINE__, &(e), pmd_val(e))
17#define pgd_ERROR(e) \
18 printk("%s:%d: bad pgd %p(%016Lx).\n", __FILE__, __LINE__, &(e), pgd_val(e))
19
20#define pud_none(pud) 0
21#define pud_bad(pud) 0
22#define pud_present(pud) 1
23
24/*
25 * Is the pte executable?
26 */
27static inline int pte_x(pte_t pte)
28{
29 return !(pte_val(pte) & _PAGE_NX);
30}
31
32/*
33 * All present user-pages with !NX bit are user-executable:
34 */
35static inline int pte_exec(pte_t pte)
36{
37 return pte_user(pte) && pte_x(pte);
38}
39/*
40 * All present pages with !NX bit are kernel-executable:
41 */
42static inline int pte_exec_kernel(pte_t pte)
43{
44 return pte_x(pte);
45}
46
47/* Rules for using set_pte: the pte being assigned *must* be
48 * either not present or in a state where the hardware will
49 * not attempt to update the pte. In places where this is
50 * not possible, use pte_get_and_clear to obtain the old pte
51 * value and then use set_pte to update it. -ben
52 */
53static inline void set_pte(pte_t *ptep, pte_t pte)
54{
55 ptep->pte_high = pte.pte_high;
56 smp_wmb();
57 ptep->pte_low = pte.pte_low;
58}
59#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
60
61#define __HAVE_ARCH_SET_PTE_ATOMIC
62#define set_pte_atomic(pteptr,pteval) \
63 set_64bit((unsigned long long *)(pteptr),pte_val(pteval))
64#define set_pmd(pmdptr,pmdval) \
65 set_64bit((unsigned long long *)(pmdptr),pmd_val(pmdval))
66#define set_pud(pudptr,pudval) \
Zachary Amsdenc9b02a22005-09-03 15:56:40 -070067 (*(pudptr) = (pudval))
Linus Torvalds1da177e2005-04-16 15:20:36 -070068
69/*
70 * Pentium-II erratum A13: in PAE mode we explicitly have to flush
71 * the TLB via cr3 if the top-level pgd is changed...
72 * We do not let the generic code free and clear pgd entries due to
73 * this erratum.
74 */
75static inline void pud_clear (pud_t * pud) { }
76
Linus Torvalds1da177e2005-04-16 15:20:36 -070077#define pud_page(pud) \
78((struct page *) __va(pud_val(pud) & PAGE_MASK))
79
80#define pud_page_kernel(pud) \
81((unsigned long) __va(pud_val(pud) & PAGE_MASK))
82
83
84/* Find an entry in the second-level page table.. */
85#define pmd_offset(pud, address) ((pmd_t *) pud_page(*(pud)) + \
86 pmd_index(address))
87
88static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
89{
90 pte_t res;
91
92 /* xchg acts as a barrier before the setting of the high bits */
93 res.pte_low = xchg(&ptep->pte_low, 0);
94 res.pte_high = ptep->pte_high;
95 ptep->pte_high = 0;
96
97 return res;
98}
99
100static inline int pte_same(pte_t a, pte_t b)
101{
102 return a.pte_low == b.pte_low && a.pte_high == b.pte_high;
103}
104
105#define pte_page(x) pfn_to_page(pte_pfn(x))
106
107static inline int pte_none(pte_t pte)
108{
109 return !pte.pte_low && !pte.pte_high;
110}
111
112static inline unsigned long pte_pfn(pte_t pte)
113{
114 return (pte.pte_low >> PAGE_SHIFT) |
115 (pte.pte_high << (32 - PAGE_SHIFT));
116}
117
118extern unsigned long long __supported_pte_mask;
119
120static inline pte_t pfn_pte(unsigned long page_nr, pgprot_t pgprot)
121{
122 pte_t pte;
123
124 pte.pte_high = (page_nr >> (32 - PAGE_SHIFT)) | \
125 (pgprot_val(pgprot) >> 32);
126 pte.pte_high &= (__supported_pte_mask >> 32);
127 pte.pte_low = ((page_nr << PAGE_SHIFT) | pgprot_val(pgprot)) & \
128 __supported_pte_mask;
129 return pte;
130}
131
132static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot)
133{
134 return __pmd((((unsigned long long)page_nr << PAGE_SHIFT) | \
135 pgprot_val(pgprot)) & __supported_pte_mask);
136}
137
138/*
139 * Bits 0, 6 and 7 are taken in the low part of the pte,
140 * put the 32 bits of offset into the high part.
141 */
142#define pte_to_pgoff(pte) ((pte).pte_high)
143#define pgoff_to_pte(off) ((pte_t) { _PAGE_FILE, (off) })
144#define PTE_FILE_MAX_BITS 32
145
146/* Encode and de-code a swap entry */
147#define __swp_type(x) (((x).val) & 0x1f)
148#define __swp_offset(x) ((x).val >> 5)
149#define __swp_entry(type, offset) ((swp_entry_t){(type) | (offset) << 5})
150#define __pte_to_swp_entry(pte) ((swp_entry_t){ (pte).pte_high })
151#define __swp_entry_to_pte(x) ((pte_t){ 0, (x).val })
152
153#define __pmd_free_tlb(tlb, x) do { } while (0)
154
155#endif /* _I386_PGTABLE_3LEVEL_H */