Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 1 | /* |
Grant Likely | ca632f5 | 2011-06-06 01:16:30 -0600 | [diff] [blame] | 2 | * au1550 psc spi controller driver |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 3 | * may work also with au1200, au1210, au1250 |
| 4 | * will not work on au1000, au1100 and au1500 (no full spi controller there) |
| 5 | * |
| 6 | * Copyright (c) 2006 ATRON electronic GmbH |
| 7 | * Author: Jan Nikitenko <jan.nikitenko@gmail.com> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 18 | */ |
| 19 | |
| 20 | #include <linux/init.h> |
| 21 | #include <linux/interrupt.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 22 | #include <linux/slab.h> |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 23 | #include <linux/errno.h> |
Paul Gortmaker | d7614de | 2011-07-03 15:44:29 -0400 | [diff] [blame] | 24 | #include <linux/module.h> |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 25 | #include <linux/device.h> |
| 26 | #include <linux/platform_device.h> |
Manuel Lauss | 3a93a15 | 2008-07-23 21:29:56 -0700 | [diff] [blame] | 27 | #include <linux/resource.h> |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 28 | #include <linux/spi/spi.h> |
| 29 | #include <linux/spi/spi_bitbang.h> |
| 30 | #include <linux/dma-mapping.h> |
| 31 | #include <linux/completion.h> |
| 32 | #include <asm/mach-au1x00/au1000.h> |
| 33 | #include <asm/mach-au1x00/au1xxx_psc.h> |
| 34 | #include <asm/mach-au1x00/au1xxx_dbdma.h> |
| 35 | |
| 36 | #include <asm/mach-au1x00/au1550_spi.h> |
| 37 | |
| 38 | static unsigned usedma = 1; |
| 39 | module_param(usedma, uint, 0644); |
| 40 | |
| 41 | /* |
| 42 | #define AU1550_SPI_DEBUG_LOOPBACK |
| 43 | */ |
| 44 | |
| 45 | |
| 46 | #define AU1550_SPI_DBDMA_DESCRIPTORS 1 |
| 47 | #define AU1550_SPI_DMA_RXTMP_MINSIZE 2048U |
| 48 | |
| 49 | struct au1550_spi { |
| 50 | struct spi_bitbang bitbang; |
| 51 | |
| 52 | volatile psc_spi_t __iomem *regs; |
| 53 | int irq; |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 54 | |
| 55 | unsigned len; |
| 56 | unsigned tx_count; |
| 57 | unsigned rx_count; |
| 58 | const u8 *tx; |
| 59 | u8 *rx; |
| 60 | |
| 61 | void (*rx_word)(struct au1550_spi *hw); |
| 62 | void (*tx_word)(struct au1550_spi *hw); |
| 63 | int (*txrx_bufs)(struct spi_device *spi, struct spi_transfer *t); |
| 64 | irqreturn_t (*irq_callback)(struct au1550_spi *hw); |
| 65 | |
| 66 | struct completion master_done; |
| 67 | |
| 68 | unsigned usedma; |
| 69 | u32 dma_tx_id; |
| 70 | u32 dma_rx_id; |
| 71 | u32 dma_tx_ch; |
| 72 | u32 dma_rx_ch; |
| 73 | |
| 74 | u8 *dma_rx_tmpbuf; |
| 75 | unsigned dma_rx_tmpbuf_size; |
| 76 | u32 dma_rx_tmpbuf_addr; |
| 77 | |
| 78 | struct spi_master *master; |
| 79 | struct device *dev; |
| 80 | struct au1550_spi_info *pdata; |
Manuel Lauss | 3a93a15 | 2008-07-23 21:29:56 -0700 | [diff] [blame] | 81 | struct resource *ioarea; |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 82 | }; |
| 83 | |
| 84 | |
| 85 | /* we use an 8-bit memory device for dma transfers to/from spi fifo */ |
| 86 | static dbdev_tab_t au1550_spi_mem_dbdev = |
| 87 | { |
| 88 | .dev_id = DBDMA_MEM_CHAN, |
| 89 | .dev_flags = DEV_FLAGS_ANYUSE|DEV_FLAGS_SYNC, |
| 90 | .dev_tsize = 0, |
| 91 | .dev_devwidth = 8, |
| 92 | .dev_physaddr = 0x00000000, |
| 93 | .dev_intlevel = 0, |
| 94 | .dev_intpolarity = 0 |
| 95 | }; |
| 96 | |
Manuel Lauss | 3a93a15 | 2008-07-23 21:29:56 -0700 | [diff] [blame] | 97 | static int ddma_memid; /* id to above mem dma device */ |
| 98 | |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 99 | static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw); |
| 100 | |
| 101 | |
Jan Nikitenko | 40369e1 | 2008-03-13 12:32:38 -0700 | [diff] [blame] | 102 | /* |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 103 | * compute BRG and DIV bits to setup spi clock based on main input clock rate |
| 104 | * that was specified in platform data structure |
| 105 | * according to au1550 datasheet: |
| 106 | * psc_tempclk = psc_mainclk / (2 << DIV) |
| 107 | * spiclk = psc_tempclk / (2 * (BRG + 1)) |
| 108 | * BRG valid range is 4..63 |
| 109 | * DIV valid range is 0..3 |
| 110 | */ |
| 111 | static u32 au1550_spi_baudcfg(struct au1550_spi *hw, unsigned speed_hz) |
| 112 | { |
| 113 | u32 mainclk_hz = hw->pdata->mainclk_hz; |
| 114 | u32 div, brg; |
| 115 | |
| 116 | for (div = 0; div < 4; div++) { |
| 117 | brg = mainclk_hz / speed_hz / (4 << div); |
| 118 | /* now we have BRG+1 in brg, so count with that */ |
| 119 | if (brg < (4 + 1)) { |
| 120 | brg = (4 + 1); /* speed_hz too big */ |
| 121 | break; /* set lowest brg (div is == 0) */ |
| 122 | } |
| 123 | if (brg <= (63 + 1)) |
| 124 | break; /* we have valid brg and div */ |
| 125 | } |
| 126 | if (div == 4) { |
| 127 | div = 3; /* speed_hz too small */ |
| 128 | brg = (63 + 1); /* set highest brg and div */ |
| 129 | } |
| 130 | brg--; |
| 131 | return PSC_SPICFG_SET_BAUD(brg) | PSC_SPICFG_SET_DIV(div); |
| 132 | } |
| 133 | |
| 134 | static inline void au1550_spi_mask_ack_all(struct au1550_spi *hw) |
| 135 | { |
| 136 | hw->regs->psc_spimsk = |
| 137 | PSC_SPIMSK_MM | PSC_SPIMSK_RR | PSC_SPIMSK_RO |
| 138 | | PSC_SPIMSK_RU | PSC_SPIMSK_TR | PSC_SPIMSK_TO |
| 139 | | PSC_SPIMSK_TU | PSC_SPIMSK_SD | PSC_SPIMSK_MD; |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 140 | wmb(); /* drain writebuffer */ |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 141 | |
| 142 | hw->regs->psc_spievent = |
| 143 | PSC_SPIEVNT_MM | PSC_SPIEVNT_RR | PSC_SPIEVNT_RO |
| 144 | | PSC_SPIEVNT_RU | PSC_SPIEVNT_TR | PSC_SPIEVNT_TO |
| 145 | | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD | PSC_SPIEVNT_MD; |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 146 | wmb(); /* drain writebuffer */ |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 147 | } |
| 148 | |
| 149 | static void au1550_spi_reset_fifos(struct au1550_spi *hw) |
| 150 | { |
| 151 | u32 pcr; |
| 152 | |
| 153 | hw->regs->psc_spipcr = PSC_SPIPCR_RC | PSC_SPIPCR_TC; |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 154 | wmb(); /* drain writebuffer */ |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 155 | do { |
| 156 | pcr = hw->regs->psc_spipcr; |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 157 | wmb(); /* drain writebuffer */ |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 158 | } while (pcr != 0); |
| 159 | } |
| 160 | |
| 161 | /* |
| 162 | * dma transfers are used for the most common spi word size of 8-bits |
| 163 | * we cannot easily change already set up dma channels' width, so if we wanted |
| 164 | * dma support for more than 8-bit words (up to 24 bits), we would need to |
| 165 | * setup dma channels from scratch on each spi transfer, based on bits_per_word |
| 166 | * instead we have pre set up 8 bit dma channels supporting spi 4 to 8 bits |
| 167 | * transfers, and 9 to 24 bits spi transfers will be done in pio irq based mode |
| 168 | * callbacks to handle dma or pio are set up in au1550_spi_bits_handlers_set() |
| 169 | */ |
| 170 | static void au1550_spi_chipsel(struct spi_device *spi, int value) |
| 171 | { |
| 172 | struct au1550_spi *hw = spi_master_get_devdata(spi->master); |
| 173 | unsigned cspol = spi->mode & SPI_CS_HIGH ? 1 : 0; |
| 174 | u32 cfg, stat; |
| 175 | |
| 176 | switch (value) { |
| 177 | case BITBANG_CS_INACTIVE: |
| 178 | if (hw->pdata->deactivate_cs) |
| 179 | hw->pdata->deactivate_cs(hw->pdata, spi->chip_select, |
| 180 | cspol); |
| 181 | break; |
| 182 | |
| 183 | case BITBANG_CS_ACTIVE: |
| 184 | au1550_spi_bits_handlers_set(hw, spi->bits_per_word); |
| 185 | |
| 186 | cfg = hw->regs->psc_spicfg; |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 187 | wmb(); /* drain writebuffer */ |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 188 | hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE; |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 189 | wmb(); /* drain writebuffer */ |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 190 | |
| 191 | if (spi->mode & SPI_CPOL) |
| 192 | cfg |= PSC_SPICFG_BI; |
| 193 | else |
| 194 | cfg &= ~PSC_SPICFG_BI; |
| 195 | if (spi->mode & SPI_CPHA) |
| 196 | cfg &= ~PSC_SPICFG_CDE; |
| 197 | else |
| 198 | cfg |= PSC_SPICFG_CDE; |
| 199 | |
| 200 | if (spi->mode & SPI_LSB_FIRST) |
| 201 | cfg |= PSC_SPICFG_MLF; |
| 202 | else |
| 203 | cfg &= ~PSC_SPICFG_MLF; |
| 204 | |
| 205 | if (hw->usedma && spi->bits_per_word <= 8) |
| 206 | cfg &= ~PSC_SPICFG_DD_DISABLE; |
| 207 | else |
| 208 | cfg |= PSC_SPICFG_DD_DISABLE; |
| 209 | cfg = PSC_SPICFG_CLR_LEN(cfg); |
| 210 | cfg |= PSC_SPICFG_SET_LEN(spi->bits_per_word); |
| 211 | |
| 212 | cfg = PSC_SPICFG_CLR_BAUD(cfg); |
| 213 | cfg &= ~PSC_SPICFG_SET_DIV(3); |
| 214 | cfg |= au1550_spi_baudcfg(hw, spi->max_speed_hz); |
| 215 | |
| 216 | hw->regs->psc_spicfg = cfg | PSC_SPICFG_DE_ENABLE; |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 217 | wmb(); /* drain writebuffer */ |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 218 | do { |
| 219 | stat = hw->regs->psc_spistat; |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 220 | wmb(); /* drain writebuffer */ |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 221 | } while ((stat & PSC_SPISTAT_DR) == 0); |
| 222 | |
| 223 | if (hw->pdata->activate_cs) |
| 224 | hw->pdata->activate_cs(hw->pdata, spi->chip_select, |
| 225 | cspol); |
| 226 | break; |
| 227 | } |
| 228 | } |
| 229 | |
| 230 | static int au1550_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t) |
| 231 | { |
| 232 | struct au1550_spi *hw = spi_master_get_devdata(spi->master); |
| 233 | unsigned bpw, hz; |
| 234 | u32 cfg, stat; |
| 235 | |
Jan Nikitenko | 04ba24b | 2009-12-07 12:50:30 +0000 | [diff] [blame] | 236 | if (t) { |
Jarkko Nikula | 0beb0a6 | 2015-09-15 16:26:18 +0300 | [diff] [blame^] | 237 | bpw = t->bits_per_word; |
| 238 | hz = t->speed_hz; |
| 239 | } else { |
| 240 | bpw = spi->bits_per_word; |
| 241 | hz = spi->max_speed_hz; |
Jan Nikitenko | 04ba24b | 2009-12-07 12:50:30 +0000 | [diff] [blame] | 242 | } |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 243 | |
Axel Lin | 0dd26e5 | 2014-02-11 20:49:07 +0800 | [diff] [blame] | 244 | if (!hz) |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 245 | return -EINVAL; |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 246 | |
| 247 | au1550_spi_bits_handlers_set(hw, spi->bits_per_word); |
| 248 | |
| 249 | cfg = hw->regs->psc_spicfg; |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 250 | wmb(); /* drain writebuffer */ |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 251 | hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE; |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 252 | wmb(); /* drain writebuffer */ |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 253 | |
| 254 | if (hw->usedma && bpw <= 8) |
| 255 | cfg &= ~PSC_SPICFG_DD_DISABLE; |
| 256 | else |
| 257 | cfg |= PSC_SPICFG_DD_DISABLE; |
| 258 | cfg = PSC_SPICFG_CLR_LEN(cfg); |
| 259 | cfg |= PSC_SPICFG_SET_LEN(bpw); |
| 260 | |
| 261 | cfg = PSC_SPICFG_CLR_BAUD(cfg); |
| 262 | cfg &= ~PSC_SPICFG_SET_DIV(3); |
| 263 | cfg |= au1550_spi_baudcfg(hw, hz); |
| 264 | |
| 265 | hw->regs->psc_spicfg = cfg; |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 266 | wmb(); /* drain writebuffer */ |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 267 | |
| 268 | if (cfg & PSC_SPICFG_DE_ENABLE) { |
| 269 | do { |
| 270 | stat = hw->regs->psc_spistat; |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 271 | wmb(); /* drain writebuffer */ |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 272 | } while ((stat & PSC_SPISTAT_DR) == 0); |
| 273 | } |
| 274 | |
| 275 | au1550_spi_reset_fifos(hw); |
| 276 | au1550_spi_mask_ack_all(hw); |
| 277 | return 0; |
| 278 | } |
| 279 | |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 280 | /* |
| 281 | * for dma spi transfers, we have to setup rx channel, otherwise there is |
| 282 | * no reliable way how to recognize that spi transfer is done |
| 283 | * dma complete callbacks are called before real spi transfer is finished |
| 284 | * and if only tx dma channel is set up (and rx fifo overflow event masked) |
| 285 | * spi master done event irq is not generated unless rx fifo is empty (emptied) |
| 286 | * so we need rx tmp buffer to use for rx dma if user does not provide one |
| 287 | */ |
| 288 | static int au1550_spi_dma_rxtmp_alloc(struct au1550_spi *hw, unsigned size) |
| 289 | { |
| 290 | hw->dma_rx_tmpbuf = kmalloc(size, GFP_KERNEL); |
| 291 | if (!hw->dma_rx_tmpbuf) |
| 292 | return -ENOMEM; |
| 293 | hw->dma_rx_tmpbuf_size = size; |
| 294 | hw->dma_rx_tmpbuf_addr = dma_map_single(hw->dev, hw->dma_rx_tmpbuf, |
| 295 | size, DMA_FROM_DEVICE); |
FUJITA Tomonori | 8d8bb39 | 2008-07-25 19:44:49 -0700 | [diff] [blame] | 296 | if (dma_mapping_error(hw->dev, hw->dma_rx_tmpbuf_addr)) { |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 297 | kfree(hw->dma_rx_tmpbuf); |
| 298 | hw->dma_rx_tmpbuf = 0; |
| 299 | hw->dma_rx_tmpbuf_size = 0; |
| 300 | return -EFAULT; |
| 301 | } |
| 302 | return 0; |
| 303 | } |
| 304 | |
| 305 | static void au1550_spi_dma_rxtmp_free(struct au1550_spi *hw) |
| 306 | { |
| 307 | dma_unmap_single(hw->dev, hw->dma_rx_tmpbuf_addr, |
| 308 | hw->dma_rx_tmpbuf_size, DMA_FROM_DEVICE); |
| 309 | kfree(hw->dma_rx_tmpbuf); |
| 310 | hw->dma_rx_tmpbuf = 0; |
| 311 | hw->dma_rx_tmpbuf_size = 0; |
| 312 | } |
| 313 | |
| 314 | static int au1550_spi_dma_txrxb(struct spi_device *spi, struct spi_transfer *t) |
| 315 | { |
| 316 | struct au1550_spi *hw = spi_master_get_devdata(spi->master); |
| 317 | dma_addr_t dma_tx_addr; |
| 318 | dma_addr_t dma_rx_addr; |
| 319 | u32 res; |
| 320 | |
| 321 | hw->len = t->len; |
| 322 | hw->tx_count = 0; |
| 323 | hw->rx_count = 0; |
| 324 | |
| 325 | hw->tx = t->tx_buf; |
| 326 | hw->rx = t->rx_buf; |
| 327 | dma_tx_addr = t->tx_dma; |
| 328 | dma_rx_addr = t->rx_dma; |
| 329 | |
| 330 | /* |
Jan Nikitenko | 4e253d2 | 2008-12-01 13:13:56 -0800 | [diff] [blame] | 331 | * check if buffers are already dma mapped, map them otherwise: |
| 332 | * - first map the TX buffer, so cache data gets written to memory |
| 333 | * - then map the RX buffer, so that cache entries (with |
| 334 | * soon-to-be-stale data) get removed |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 335 | * use rx buffer in place of tx if tx buffer was not provided |
| 336 | * use temp rx buffer (preallocated or realloc to fit) for rx dma |
| 337 | */ |
Jan Nikitenko | 4e253d2 | 2008-12-01 13:13:56 -0800 | [diff] [blame] | 338 | if (t->tx_buf) { |
| 339 | if (t->tx_dma == 0) { /* if DMA_ADDR_INVALID, map it */ |
| 340 | dma_tx_addr = dma_map_single(hw->dev, |
| 341 | (void *)t->tx_buf, |
| 342 | t->len, DMA_TO_DEVICE); |
| 343 | if (dma_mapping_error(hw->dev, dma_tx_addr)) |
| 344 | dev_err(hw->dev, "tx dma map error\n"); |
| 345 | } |
| 346 | } |
| 347 | |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 348 | if (t->rx_buf) { |
| 349 | if (t->rx_dma == 0) { /* if DMA_ADDR_INVALID, map it */ |
| 350 | dma_rx_addr = dma_map_single(hw->dev, |
| 351 | (void *)t->rx_buf, |
| 352 | t->len, DMA_FROM_DEVICE); |
FUJITA Tomonori | 8d8bb39 | 2008-07-25 19:44:49 -0700 | [diff] [blame] | 353 | if (dma_mapping_error(hw->dev, dma_rx_addr)) |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 354 | dev_err(hw->dev, "rx dma map error\n"); |
| 355 | } |
| 356 | } else { |
| 357 | if (t->len > hw->dma_rx_tmpbuf_size) { |
| 358 | int ret; |
| 359 | |
| 360 | au1550_spi_dma_rxtmp_free(hw); |
| 361 | ret = au1550_spi_dma_rxtmp_alloc(hw, max(t->len, |
| 362 | AU1550_SPI_DMA_RXTMP_MINSIZE)); |
| 363 | if (ret < 0) |
| 364 | return ret; |
| 365 | } |
| 366 | hw->rx = hw->dma_rx_tmpbuf; |
| 367 | dma_rx_addr = hw->dma_rx_tmpbuf_addr; |
| 368 | dma_sync_single_for_device(hw->dev, dma_rx_addr, |
| 369 | t->len, DMA_FROM_DEVICE); |
| 370 | } |
Jan Nikitenko | 4e253d2 | 2008-12-01 13:13:56 -0800 | [diff] [blame] | 371 | |
| 372 | if (!t->tx_buf) { |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 373 | dma_sync_single_for_device(hw->dev, dma_rx_addr, |
| 374 | t->len, DMA_BIDIRECTIONAL); |
| 375 | hw->tx = hw->rx; |
| 376 | } |
| 377 | |
| 378 | /* put buffers on the ring */ |
Manuel Lauss | 963accb | 2009-10-13 20:22:35 +0200 | [diff] [blame] | 379 | res = au1xxx_dbdma_put_dest(hw->dma_rx_ch, virt_to_phys(hw->rx), |
Manuel Lauss | ea071cc | 2009-10-13 20:22:34 +0200 | [diff] [blame] | 380 | t->len, DDMA_FLAGS_IE); |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 381 | if (!res) |
| 382 | dev_err(hw->dev, "rx dma put dest error\n"); |
| 383 | |
Manuel Lauss | 963accb | 2009-10-13 20:22:35 +0200 | [diff] [blame] | 384 | res = au1xxx_dbdma_put_source(hw->dma_tx_ch, virt_to_phys(hw->tx), |
Manuel Lauss | ea071cc | 2009-10-13 20:22:34 +0200 | [diff] [blame] | 385 | t->len, DDMA_FLAGS_IE); |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 386 | if (!res) |
| 387 | dev_err(hw->dev, "tx dma put source error\n"); |
| 388 | |
| 389 | au1xxx_dbdma_start(hw->dma_rx_ch); |
| 390 | au1xxx_dbdma_start(hw->dma_tx_ch); |
| 391 | |
| 392 | /* by default enable nearly all events interrupt */ |
| 393 | hw->regs->psc_spimsk = PSC_SPIMSK_SD; |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 394 | wmb(); /* drain writebuffer */ |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 395 | |
| 396 | /* start the transfer */ |
| 397 | hw->regs->psc_spipcr = PSC_SPIPCR_MS; |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 398 | wmb(); /* drain writebuffer */ |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 399 | |
| 400 | wait_for_completion(&hw->master_done); |
| 401 | |
| 402 | au1xxx_dbdma_stop(hw->dma_tx_ch); |
| 403 | au1xxx_dbdma_stop(hw->dma_rx_ch); |
| 404 | |
| 405 | if (!t->rx_buf) { |
| 406 | /* using the temporal preallocated and premapped buffer */ |
| 407 | dma_sync_single_for_cpu(hw->dev, dma_rx_addr, t->len, |
| 408 | DMA_FROM_DEVICE); |
| 409 | } |
| 410 | /* unmap buffers if mapped above */ |
| 411 | if (t->rx_buf && t->rx_dma == 0 ) |
| 412 | dma_unmap_single(hw->dev, dma_rx_addr, t->len, |
| 413 | DMA_FROM_DEVICE); |
| 414 | if (t->tx_buf && t->tx_dma == 0 ) |
| 415 | dma_unmap_single(hw->dev, dma_tx_addr, t->len, |
| 416 | DMA_TO_DEVICE); |
| 417 | |
| 418 | return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count; |
| 419 | } |
| 420 | |
| 421 | static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw) |
| 422 | { |
| 423 | u32 stat, evnt; |
| 424 | |
| 425 | stat = hw->regs->psc_spistat; |
| 426 | evnt = hw->regs->psc_spievent; |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 427 | wmb(); /* drain writebuffer */ |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 428 | if ((stat & PSC_SPISTAT_DI) == 0) { |
| 429 | dev_err(hw->dev, "Unexpected IRQ!\n"); |
| 430 | return IRQ_NONE; |
| 431 | } |
| 432 | |
| 433 | if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO |
| 434 | | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO |
| 435 | | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD)) |
| 436 | != 0) { |
| 437 | /* |
| 438 | * due to an spi error we consider transfer as done, |
| 439 | * so mask all events until before next transfer start |
Masanari Iida | 886db6ac | 2012-07-30 23:16:14 +0900 | [diff] [blame] | 440 | * and stop the possibly running dma immediately |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 441 | */ |
| 442 | au1550_spi_mask_ack_all(hw); |
| 443 | au1xxx_dbdma_stop(hw->dma_rx_ch); |
| 444 | au1xxx_dbdma_stop(hw->dma_tx_ch); |
| 445 | |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 446 | /* get number of transferred bytes */ |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 447 | hw->rx_count = hw->len - au1xxx_get_dma_residue(hw->dma_rx_ch); |
| 448 | hw->tx_count = hw->len - au1xxx_get_dma_residue(hw->dma_tx_ch); |
| 449 | |
| 450 | au1xxx_dbdma_reset(hw->dma_rx_ch); |
| 451 | au1xxx_dbdma_reset(hw->dma_tx_ch); |
| 452 | au1550_spi_reset_fifos(hw); |
| 453 | |
Jan Nikitenko | bbe48ec | 2008-07-23 21:29:57 -0700 | [diff] [blame] | 454 | if (evnt == PSC_SPIEVNT_RO) |
| 455 | dev_err(hw->dev, |
| 456 | "dma transfer: receive FIFO overflow!\n"); |
| 457 | else |
| 458 | dev_err(hw->dev, |
| 459 | "dma transfer: unexpected SPI error " |
| 460 | "(event=0x%x stat=0x%x)!\n", evnt, stat); |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 461 | |
| 462 | complete(&hw->master_done); |
| 463 | return IRQ_HANDLED; |
| 464 | } |
| 465 | |
| 466 | if ((evnt & PSC_SPIEVNT_MD) != 0) { |
| 467 | /* transfer completed successfully */ |
| 468 | au1550_spi_mask_ack_all(hw); |
| 469 | hw->rx_count = hw->len; |
| 470 | hw->tx_count = hw->len; |
| 471 | complete(&hw->master_done); |
| 472 | } |
| 473 | return IRQ_HANDLED; |
| 474 | } |
| 475 | |
| 476 | |
| 477 | /* routines to handle different word sizes in pio mode */ |
| 478 | #define AU1550_SPI_RX_WORD(size, mask) \ |
| 479 | static void au1550_spi_rx_word_##size(struct au1550_spi *hw) \ |
| 480 | { \ |
| 481 | u32 fifoword = hw->regs->psc_spitxrx & (u32)(mask); \ |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 482 | wmb(); /* drain writebuffer */ \ |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 483 | if (hw->rx) { \ |
| 484 | *(u##size *)hw->rx = (u##size)fifoword; \ |
| 485 | hw->rx += (size) / 8; \ |
| 486 | } \ |
| 487 | hw->rx_count += (size) / 8; \ |
| 488 | } |
| 489 | |
| 490 | #define AU1550_SPI_TX_WORD(size, mask) \ |
| 491 | static void au1550_spi_tx_word_##size(struct au1550_spi *hw) \ |
| 492 | { \ |
| 493 | u32 fifoword = 0; \ |
| 494 | if (hw->tx) { \ |
| 495 | fifoword = *(u##size *)hw->tx & (u32)(mask); \ |
| 496 | hw->tx += (size) / 8; \ |
| 497 | } \ |
| 498 | hw->tx_count += (size) / 8; \ |
| 499 | if (hw->tx_count >= hw->len) \ |
| 500 | fifoword |= PSC_SPITXRX_LC; \ |
| 501 | hw->regs->psc_spitxrx = fifoword; \ |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 502 | wmb(); /* drain writebuffer */ \ |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 503 | } |
| 504 | |
| 505 | AU1550_SPI_RX_WORD(8,0xff) |
| 506 | AU1550_SPI_RX_WORD(16,0xffff) |
| 507 | AU1550_SPI_RX_WORD(32,0xffffff) |
| 508 | AU1550_SPI_TX_WORD(8,0xff) |
| 509 | AU1550_SPI_TX_WORD(16,0xffff) |
| 510 | AU1550_SPI_TX_WORD(32,0xffffff) |
| 511 | |
| 512 | static int au1550_spi_pio_txrxb(struct spi_device *spi, struct spi_transfer *t) |
| 513 | { |
| 514 | u32 stat, mask; |
| 515 | struct au1550_spi *hw = spi_master_get_devdata(spi->master); |
| 516 | |
| 517 | hw->tx = t->tx_buf; |
| 518 | hw->rx = t->rx_buf; |
| 519 | hw->len = t->len; |
| 520 | hw->tx_count = 0; |
| 521 | hw->rx_count = 0; |
| 522 | |
| 523 | /* by default enable nearly all events after filling tx fifo */ |
| 524 | mask = PSC_SPIMSK_SD; |
| 525 | |
| 526 | /* fill the transmit FIFO */ |
| 527 | while (hw->tx_count < hw->len) { |
| 528 | |
| 529 | hw->tx_word(hw); |
| 530 | |
| 531 | if (hw->tx_count >= hw->len) { |
| 532 | /* mask tx fifo request interrupt as we are done */ |
| 533 | mask |= PSC_SPIMSK_TR; |
| 534 | } |
| 535 | |
| 536 | stat = hw->regs->psc_spistat; |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 537 | wmb(); /* drain writebuffer */ |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 538 | if (stat & PSC_SPISTAT_TF) |
| 539 | break; |
| 540 | } |
| 541 | |
| 542 | /* enable event interrupts */ |
| 543 | hw->regs->psc_spimsk = mask; |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 544 | wmb(); /* drain writebuffer */ |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 545 | |
| 546 | /* start the transfer */ |
| 547 | hw->regs->psc_spipcr = PSC_SPIPCR_MS; |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 548 | wmb(); /* drain writebuffer */ |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 549 | |
| 550 | wait_for_completion(&hw->master_done); |
| 551 | |
| 552 | return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count; |
| 553 | } |
| 554 | |
| 555 | static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw) |
| 556 | { |
| 557 | int busy; |
| 558 | u32 stat, evnt; |
| 559 | |
| 560 | stat = hw->regs->psc_spistat; |
| 561 | evnt = hw->regs->psc_spievent; |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 562 | wmb(); /* drain writebuffer */ |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 563 | if ((stat & PSC_SPISTAT_DI) == 0) { |
| 564 | dev_err(hw->dev, "Unexpected IRQ!\n"); |
| 565 | return IRQ_NONE; |
| 566 | } |
| 567 | |
| 568 | if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO |
| 569 | | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO |
Jan Nikitenko | bbe48ec | 2008-07-23 21:29:57 -0700 | [diff] [blame] | 570 | | PSC_SPIEVNT_SD)) |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 571 | != 0) { |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 572 | /* |
| 573 | * due to an error we consider transfer as done, |
| 574 | * so mask all events until before next transfer start |
| 575 | */ |
| 576 | au1550_spi_mask_ack_all(hw); |
| 577 | au1550_spi_reset_fifos(hw); |
Jan Nikitenko | bbe48ec | 2008-07-23 21:29:57 -0700 | [diff] [blame] | 578 | dev_err(hw->dev, |
| 579 | "pio transfer: unexpected SPI error " |
| 580 | "(event=0x%x stat=0x%x)!\n", evnt, stat); |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 581 | complete(&hw->master_done); |
| 582 | return IRQ_HANDLED; |
| 583 | } |
| 584 | |
| 585 | /* |
| 586 | * while there is something to read from rx fifo |
| 587 | * or there is a space to write to tx fifo: |
| 588 | */ |
| 589 | do { |
| 590 | busy = 0; |
| 591 | stat = hw->regs->psc_spistat; |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 592 | wmb(); /* drain writebuffer */ |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 593 | |
Jan Nikitenko | bbe48ec | 2008-07-23 21:29:57 -0700 | [diff] [blame] | 594 | /* |
| 595 | * Take care to not let the Rx FIFO overflow. |
| 596 | * |
| 597 | * We only write a byte if we have read one at least. Initially, |
| 598 | * the write fifo is full, so we should read from the read fifo |
| 599 | * first. |
| 600 | * In case we miss a word from the read fifo, we should get a |
| 601 | * RO event and should back out. |
| 602 | */ |
| 603 | if (!(stat & PSC_SPISTAT_RE) && hw->rx_count < hw->len) { |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 604 | hw->rx_word(hw); |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 605 | busy = 1; |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 606 | |
Jan Nikitenko | bbe48ec | 2008-07-23 21:29:57 -0700 | [diff] [blame] | 607 | if (!(stat & PSC_SPISTAT_TF) && hw->tx_count < hw->len) |
| 608 | hw->tx_word(hw); |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 609 | } |
| 610 | } while (busy); |
| 611 | |
Jan Nikitenko | bbe48ec | 2008-07-23 21:29:57 -0700 | [diff] [blame] | 612 | hw->regs->psc_spievent = PSC_SPIEVNT_RR | PSC_SPIEVNT_TR; |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 613 | wmb(); /* drain writebuffer */ |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 614 | |
Jan Nikitenko | bbe48ec | 2008-07-23 21:29:57 -0700 | [diff] [blame] | 615 | /* |
| 616 | * Restart the SPI transmission in case of a transmit underflow. |
| 617 | * This seems to work despite the notes in the Au1550 data book |
| 618 | * of Figure 8-4 with flowchart for SPI master operation: |
| 619 | * |
| 620 | * """Note 1: An XFR Error Interrupt occurs, unless masked, |
| 621 | * for any of the following events: Tx FIFO Underflow, |
| 622 | * Rx FIFO Overflow, or Multiple-master Error |
| 623 | * Note 2: In case of a Tx Underflow Error, all zeroes are |
| 624 | * transmitted.""" |
| 625 | * |
| 626 | * By simply restarting the spi transfer on Tx Underflow Error, |
| 627 | * we assume that spi transfer was paused instead of zeroes |
| 628 | * transmittion mentioned in the Note 2 of Au1550 data book. |
| 629 | */ |
| 630 | if (evnt & PSC_SPIEVNT_TU) { |
| 631 | hw->regs->psc_spievent = PSC_SPIEVNT_TU | PSC_SPIEVNT_MD; |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 632 | wmb(); /* drain writebuffer */ |
Jan Nikitenko | bbe48ec | 2008-07-23 21:29:57 -0700 | [diff] [blame] | 633 | hw->regs->psc_spipcr = PSC_SPIPCR_MS; |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 634 | wmb(); /* drain writebuffer */ |
Jan Nikitenko | bbe48ec | 2008-07-23 21:29:57 -0700 | [diff] [blame] | 635 | } |
| 636 | |
| 637 | if (hw->rx_count >= hw->len) { |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 638 | /* transfer completed successfully */ |
| 639 | au1550_spi_mask_ack_all(hw); |
| 640 | complete(&hw->master_done); |
| 641 | } |
| 642 | return IRQ_HANDLED; |
| 643 | } |
| 644 | |
| 645 | static int au1550_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) |
| 646 | { |
| 647 | struct au1550_spi *hw = spi_master_get_devdata(spi->master); |
| 648 | return hw->txrx_bufs(spi, t); |
| 649 | } |
| 650 | |
Jan Nikitenko | 40369e1 | 2008-03-13 12:32:38 -0700 | [diff] [blame] | 651 | static irqreturn_t au1550_spi_irq(int irq, void *dev) |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 652 | { |
| 653 | struct au1550_spi *hw = dev; |
| 654 | return hw->irq_callback(hw); |
| 655 | } |
| 656 | |
| 657 | static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw) |
| 658 | { |
| 659 | if (bpw <= 8) { |
| 660 | if (hw->usedma) { |
| 661 | hw->txrx_bufs = &au1550_spi_dma_txrxb; |
| 662 | hw->irq_callback = &au1550_spi_dma_irq_callback; |
| 663 | } else { |
| 664 | hw->rx_word = &au1550_spi_rx_word_8; |
| 665 | hw->tx_word = &au1550_spi_tx_word_8; |
| 666 | hw->txrx_bufs = &au1550_spi_pio_txrxb; |
| 667 | hw->irq_callback = &au1550_spi_pio_irq_callback; |
| 668 | } |
| 669 | } else if (bpw <= 16) { |
| 670 | hw->rx_word = &au1550_spi_rx_word_16; |
| 671 | hw->tx_word = &au1550_spi_tx_word_16; |
| 672 | hw->txrx_bufs = &au1550_spi_pio_txrxb; |
| 673 | hw->irq_callback = &au1550_spi_pio_irq_callback; |
| 674 | } else { |
| 675 | hw->rx_word = &au1550_spi_rx_word_32; |
| 676 | hw->tx_word = &au1550_spi_tx_word_32; |
| 677 | hw->txrx_bufs = &au1550_spi_pio_txrxb; |
| 678 | hw->irq_callback = &au1550_spi_pio_irq_callback; |
| 679 | } |
| 680 | } |
| 681 | |
Grant Likely | 2deff8d | 2013-02-05 13:27:35 +0000 | [diff] [blame] | 682 | static void au1550_spi_setup_psc_as_spi(struct au1550_spi *hw) |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 683 | { |
| 684 | u32 stat, cfg; |
| 685 | |
| 686 | /* set up the PSC for SPI mode */ |
| 687 | hw->regs->psc_ctrl = PSC_CTRL_DISABLE; |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 688 | wmb(); /* drain writebuffer */ |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 689 | hw->regs->psc_sel = PSC_SEL_PS_SPIMODE; |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 690 | wmb(); /* drain writebuffer */ |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 691 | |
| 692 | hw->regs->psc_spicfg = 0; |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 693 | wmb(); /* drain writebuffer */ |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 694 | |
| 695 | hw->regs->psc_ctrl = PSC_CTRL_ENABLE; |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 696 | wmb(); /* drain writebuffer */ |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 697 | |
| 698 | do { |
| 699 | stat = hw->regs->psc_spistat; |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 700 | wmb(); /* drain writebuffer */ |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 701 | } while ((stat & PSC_SPISTAT_SR) == 0); |
| 702 | |
| 703 | |
| 704 | cfg = hw->usedma ? 0 : PSC_SPICFG_DD_DISABLE; |
| 705 | cfg |= PSC_SPICFG_SET_LEN(8); |
| 706 | cfg |= PSC_SPICFG_RT_FIFO8 | PSC_SPICFG_TT_FIFO8; |
| 707 | /* use minimal allowed brg and div values as initial setting: */ |
| 708 | cfg |= PSC_SPICFG_SET_BAUD(4) | PSC_SPICFG_SET_DIV(0); |
| 709 | |
| 710 | #ifdef AU1550_SPI_DEBUG_LOOPBACK |
| 711 | cfg |= PSC_SPICFG_LB; |
| 712 | #endif |
| 713 | |
| 714 | hw->regs->psc_spicfg = cfg; |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 715 | wmb(); /* drain writebuffer */ |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 716 | |
| 717 | au1550_spi_mask_ack_all(hw); |
| 718 | |
| 719 | hw->regs->psc_spicfg |= PSC_SPICFG_DE_ENABLE; |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 720 | wmb(); /* drain writebuffer */ |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 721 | |
| 722 | do { |
| 723 | stat = hw->regs->psc_spistat; |
Manuel Lauss | 2f73bfb | 2014-07-23 16:36:26 +0200 | [diff] [blame] | 724 | wmb(); /* drain writebuffer */ |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 725 | } while ((stat & PSC_SPISTAT_DR) == 0); |
Jan Nikitenko | bbe48ec | 2008-07-23 21:29:57 -0700 | [diff] [blame] | 726 | |
| 727 | au1550_spi_reset_fifos(hw); |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 728 | } |
| 729 | |
| 730 | |
Grant Likely | 2deff8d | 2013-02-05 13:27:35 +0000 | [diff] [blame] | 731 | static int au1550_spi_probe(struct platform_device *pdev) |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 732 | { |
| 733 | struct au1550_spi *hw; |
| 734 | struct spi_master *master; |
Manuel Lauss | 3a93a15 | 2008-07-23 21:29:56 -0700 | [diff] [blame] | 735 | struct resource *r; |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 736 | int err = 0; |
| 737 | |
| 738 | master = spi_alloc_master(&pdev->dev, sizeof(struct au1550_spi)); |
| 739 | if (master == NULL) { |
| 740 | dev_err(&pdev->dev, "No memory for spi_master\n"); |
| 741 | err = -ENOMEM; |
| 742 | goto err_nomem; |
| 743 | } |
| 744 | |
David Brownell | e7db06b | 2009-06-17 16:26:04 -0700 | [diff] [blame] | 745 | /* the spi->mode bits understood by this driver: */ |
| 746 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; |
Stephen Warren | 24778be | 2013-05-21 20:36:35 -0600 | [diff] [blame] | 747 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 24); |
David Brownell | e7db06b | 2009-06-17 16:26:04 -0700 | [diff] [blame] | 748 | |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 749 | hw = spi_master_get_devdata(master); |
| 750 | |
Axel Lin | 94c69f7 | 2013-09-10 15:43:41 +0800 | [diff] [blame] | 751 | hw->master = master; |
Jingoo Han | 8074cf0 | 2013-07-30 16:58:59 +0900 | [diff] [blame] | 752 | hw->pdata = dev_get_platdata(&pdev->dev); |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 753 | hw->dev = &pdev->dev; |
| 754 | |
| 755 | if (hw->pdata == NULL) { |
| 756 | dev_err(&pdev->dev, "No platform data supplied\n"); |
| 757 | err = -ENOENT; |
| 758 | goto err_no_pdata; |
| 759 | } |
| 760 | |
Manuel Lauss | 3a93a15 | 2008-07-23 21:29:56 -0700 | [diff] [blame] | 761 | r = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
| 762 | if (!r) { |
| 763 | dev_err(&pdev->dev, "no IRQ\n"); |
| 764 | err = -ENODEV; |
| 765 | goto err_no_iores; |
| 766 | } |
| 767 | hw->irq = r->start; |
| 768 | |
| 769 | hw->usedma = 0; |
| 770 | r = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
| 771 | if (r) { |
| 772 | hw->dma_tx_id = r->start; |
| 773 | r = platform_get_resource(pdev, IORESOURCE_DMA, 1); |
| 774 | if (r) { |
| 775 | hw->dma_rx_id = r->start; |
| 776 | if (usedma && ddma_memid) { |
| 777 | if (pdev->dev.dma_mask == NULL) |
| 778 | dev_warn(&pdev->dev, "no dma mask\n"); |
| 779 | else |
| 780 | hw->usedma = 1; |
| 781 | } |
| 782 | } |
| 783 | } |
| 784 | |
| 785 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 786 | if (!r) { |
| 787 | dev_err(&pdev->dev, "no mmio resource\n"); |
| 788 | err = -ENODEV; |
| 789 | goto err_no_iores; |
| 790 | } |
| 791 | |
| 792 | hw->ioarea = request_mem_region(r->start, sizeof(psc_spi_t), |
| 793 | pdev->name); |
| 794 | if (!hw->ioarea) { |
| 795 | dev_err(&pdev->dev, "Cannot reserve iomem region\n"); |
| 796 | err = -ENXIO; |
| 797 | goto err_no_iores; |
| 798 | } |
| 799 | |
| 800 | hw->regs = (psc_spi_t __iomem *)ioremap(r->start, sizeof(psc_spi_t)); |
| 801 | if (!hw->regs) { |
| 802 | dev_err(&pdev->dev, "cannot ioremap\n"); |
| 803 | err = -ENXIO; |
| 804 | goto err_ioremap; |
| 805 | } |
| 806 | |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 807 | platform_set_drvdata(pdev, hw); |
| 808 | |
| 809 | init_completion(&hw->master_done); |
| 810 | |
| 811 | hw->bitbang.master = hw->master; |
| 812 | hw->bitbang.setup_transfer = au1550_spi_setupxfer; |
| 813 | hw->bitbang.chipselect = au1550_spi_chipsel; |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 814 | hw->bitbang.txrx_bufs = au1550_spi_txrx_bufs; |
| 815 | |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 816 | if (hw->usedma) { |
Manuel Lauss | 3a93a15 | 2008-07-23 21:29:56 -0700 | [diff] [blame] | 817 | hw->dma_tx_ch = au1xxx_dbdma_chan_alloc(ddma_memid, |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 818 | hw->dma_tx_id, NULL, (void *)hw); |
| 819 | if (hw->dma_tx_ch == 0) { |
| 820 | dev_err(&pdev->dev, |
| 821 | "Cannot allocate tx dma channel\n"); |
| 822 | err = -ENXIO; |
| 823 | goto err_no_txdma; |
| 824 | } |
| 825 | au1xxx_dbdma_set_devwidth(hw->dma_tx_ch, 8); |
| 826 | if (au1xxx_dbdma_ring_alloc(hw->dma_tx_ch, |
| 827 | AU1550_SPI_DBDMA_DESCRIPTORS) == 0) { |
| 828 | dev_err(&pdev->dev, |
| 829 | "Cannot allocate tx dma descriptors\n"); |
| 830 | err = -ENXIO; |
| 831 | goto err_no_txdma_descr; |
| 832 | } |
| 833 | |
| 834 | |
| 835 | hw->dma_rx_ch = au1xxx_dbdma_chan_alloc(hw->dma_rx_id, |
Manuel Lauss | 3a93a15 | 2008-07-23 21:29:56 -0700 | [diff] [blame] | 836 | ddma_memid, NULL, (void *)hw); |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 837 | if (hw->dma_rx_ch == 0) { |
| 838 | dev_err(&pdev->dev, |
| 839 | "Cannot allocate rx dma channel\n"); |
| 840 | err = -ENXIO; |
| 841 | goto err_no_rxdma; |
| 842 | } |
| 843 | au1xxx_dbdma_set_devwidth(hw->dma_rx_ch, 8); |
| 844 | if (au1xxx_dbdma_ring_alloc(hw->dma_rx_ch, |
| 845 | AU1550_SPI_DBDMA_DESCRIPTORS) == 0) { |
| 846 | dev_err(&pdev->dev, |
| 847 | "Cannot allocate rx dma descriptors\n"); |
| 848 | err = -ENXIO; |
| 849 | goto err_no_rxdma_descr; |
| 850 | } |
| 851 | |
| 852 | err = au1550_spi_dma_rxtmp_alloc(hw, |
| 853 | AU1550_SPI_DMA_RXTMP_MINSIZE); |
| 854 | if (err < 0) { |
| 855 | dev_err(&pdev->dev, |
| 856 | "Cannot allocate initial rx dma tmp buffer\n"); |
| 857 | goto err_dma_rxtmp_alloc; |
| 858 | } |
| 859 | } |
| 860 | |
| 861 | au1550_spi_bits_handlers_set(hw, 8); |
| 862 | |
| 863 | err = request_irq(hw->irq, au1550_spi_irq, 0, pdev->name, hw); |
| 864 | if (err) { |
| 865 | dev_err(&pdev->dev, "Cannot claim IRQ\n"); |
| 866 | goto err_no_irq; |
| 867 | } |
| 868 | |
Manuel Lauss | 3a93a15 | 2008-07-23 21:29:56 -0700 | [diff] [blame] | 869 | master->bus_num = pdev->id; |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 870 | master->num_chipselect = hw->pdata->num_chipselect; |
| 871 | |
| 872 | /* |
| 873 | * precompute valid range for spi freq - from au1550 datasheet: |
| 874 | * psc_tempclk = psc_mainclk / (2 << DIV) |
| 875 | * spiclk = psc_tempclk / (2 * (BRG + 1)) |
| 876 | * BRG valid range is 4..63 |
| 877 | * DIV valid range is 0..3 |
| 878 | * round the min and max frequencies to values that would still |
| 879 | * produce valid brg and div |
| 880 | */ |
| 881 | { |
| 882 | int min_div = (2 << 0) * (2 * (4 + 1)); |
| 883 | int max_div = (2 << 3) * (2 * (63 + 1)); |
Axel Lin | 0dd26e5 | 2014-02-11 20:49:07 +0800 | [diff] [blame] | 884 | master->max_speed_hz = hw->pdata->mainclk_hz / min_div; |
| 885 | master->min_speed_hz = |
| 886 | hw->pdata->mainclk_hz / (max_div + 1) + 1; |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 887 | } |
| 888 | |
| 889 | au1550_spi_setup_psc_as_spi(hw); |
| 890 | |
| 891 | err = spi_bitbang_start(&hw->bitbang); |
| 892 | if (err) { |
| 893 | dev_err(&pdev->dev, "Failed to register SPI master\n"); |
| 894 | goto err_register; |
| 895 | } |
| 896 | |
| 897 | dev_info(&pdev->dev, |
| 898 | "spi master registered: bus_num=%d num_chipselect=%d\n", |
| 899 | master->bus_num, master->num_chipselect); |
| 900 | |
| 901 | return 0; |
| 902 | |
| 903 | err_register: |
| 904 | free_irq(hw->irq, hw); |
| 905 | |
| 906 | err_no_irq: |
| 907 | au1550_spi_dma_rxtmp_free(hw); |
| 908 | |
| 909 | err_dma_rxtmp_alloc: |
| 910 | err_no_rxdma_descr: |
| 911 | if (hw->usedma) |
| 912 | au1xxx_dbdma_chan_free(hw->dma_rx_ch); |
| 913 | |
| 914 | err_no_rxdma: |
| 915 | err_no_txdma_descr: |
| 916 | if (hw->usedma) |
| 917 | au1xxx_dbdma_chan_free(hw->dma_tx_ch); |
| 918 | |
| 919 | err_no_txdma: |
Manuel Lauss | 3a93a15 | 2008-07-23 21:29:56 -0700 | [diff] [blame] | 920 | iounmap((void __iomem *)hw->regs); |
| 921 | |
| 922 | err_ioremap: |
Himangi Saraogi | 3067053 | 2014-07-04 23:09:49 +0530 | [diff] [blame] | 923 | release_mem_region(r->start, sizeof(psc_spi_t)); |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 924 | |
| 925 | err_no_iores: |
| 926 | err_no_pdata: |
| 927 | spi_master_put(hw->master); |
| 928 | |
| 929 | err_nomem: |
| 930 | return err; |
| 931 | } |
| 932 | |
Grant Likely | 2deff8d | 2013-02-05 13:27:35 +0000 | [diff] [blame] | 933 | static int au1550_spi_remove(struct platform_device *pdev) |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 934 | { |
| 935 | struct au1550_spi *hw = platform_get_drvdata(pdev); |
| 936 | |
| 937 | dev_info(&pdev->dev, "spi master remove: bus_num=%d\n", |
| 938 | hw->master->bus_num); |
| 939 | |
| 940 | spi_bitbang_stop(&hw->bitbang); |
| 941 | free_irq(hw->irq, hw); |
Manuel Lauss | 3a93a15 | 2008-07-23 21:29:56 -0700 | [diff] [blame] | 942 | iounmap((void __iomem *)hw->regs); |
Manuel Lauss | 61a2381 | 2014-08-19 19:18:44 +0200 | [diff] [blame] | 943 | release_mem_region(hw->ioarea->start, sizeof(psc_spi_t)); |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 944 | |
| 945 | if (hw->usedma) { |
| 946 | au1550_spi_dma_rxtmp_free(hw); |
| 947 | au1xxx_dbdma_chan_free(hw->dma_rx_ch); |
| 948 | au1xxx_dbdma_chan_free(hw->dma_tx_ch); |
| 949 | } |
| 950 | |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 951 | spi_master_put(hw->master); |
| 952 | return 0; |
| 953 | } |
| 954 | |
Kay Sievers | 7e38c3c | 2008-04-10 21:29:20 -0700 | [diff] [blame] | 955 | /* work with hotplug and coldplug */ |
| 956 | MODULE_ALIAS("platform:au1550-spi"); |
| 957 | |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 958 | static struct platform_driver au1550_spi_drv = { |
Wolfram Sang | 75dab1b | 2013-10-08 22:35:37 +0200 | [diff] [blame] | 959 | .probe = au1550_spi_probe, |
Grant Likely | 2deff8d | 2013-02-05 13:27:35 +0000 | [diff] [blame] | 960 | .remove = au1550_spi_remove, |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 961 | .driver = { |
| 962 | .name = "au1550-spi", |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 963 | }, |
| 964 | }; |
| 965 | |
| 966 | static int __init au1550_spi_init(void) |
| 967 | { |
Manuel Lauss | 3a93a15 | 2008-07-23 21:29:56 -0700 | [diff] [blame] | 968 | /* |
| 969 | * create memory device with 8 bits dev_devwidth |
| 970 | * needed for proper byte ordering to spi fifo |
| 971 | */ |
Manuel Lauss | 970e268 | 2014-02-20 14:59:24 +0100 | [diff] [blame] | 972 | switch (alchemy_get_cputype()) { |
| 973 | case ALCHEMY_CPU_AU1550: |
| 974 | case ALCHEMY_CPU_AU1200: |
| 975 | case ALCHEMY_CPU_AU1300: |
| 976 | break; |
| 977 | default: |
| 978 | return -ENODEV; |
| 979 | } |
| 980 | |
Manuel Lauss | 3a93a15 | 2008-07-23 21:29:56 -0700 | [diff] [blame] | 981 | if (usedma) { |
| 982 | ddma_memid = au1xxx_ddma_add_device(&au1550_spi_mem_dbdev); |
| 983 | if (!ddma_memid) |
| 984 | printk(KERN_ERR "au1550-spi: cannot add memory" |
| 985 | "dbdma device\n"); |
| 986 | } |
Wolfram Sang | 75dab1b | 2013-10-08 22:35:37 +0200 | [diff] [blame] | 987 | return platform_driver_register(&au1550_spi_drv); |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 988 | } |
| 989 | module_init(au1550_spi_init); |
| 990 | |
| 991 | static void __exit au1550_spi_exit(void) |
| 992 | { |
Manuel Lauss | 3a93a15 | 2008-07-23 21:29:56 -0700 | [diff] [blame] | 993 | if (usedma && ddma_memid) |
| 994 | au1xxx_ddma_del_device(ddma_memid); |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 995 | platform_driver_unregister(&au1550_spi_drv); |
| 996 | } |
| 997 | module_exit(au1550_spi_exit); |
| 998 | |
| 999 | MODULE_DESCRIPTION("Au1550 PSC SPI Driver"); |
| 1000 | MODULE_AUTHOR("Jan Nikitenko <jan.nikitenko@gmail.com>"); |
| 1001 | MODULE_LICENSE("GPL"); |