blob: 132854f646baa41cab58ab30a85479fa3350fb61 [file] [log] [blame]
Auke Kok9a799d72007-09-15 14:07:45 -07001/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
Peter P Waskiewiczb4617242008-09-11 20:04:46 -07004 Copyright(c) 1999 - 2008 Intel Corporation.
Auke Kok9a799d72007-09-15 14:07:45 -07005
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
Auke Kok9a799d72007-09-15 14:07:45 -070023 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBE_H_
29#define _IXGBE_H_
30
31#include <linux/types.h>
32#include <linux/pci.h>
33#include <linux/netdevice.h>
Mallikarjuna R Chilakala177db6f2008-06-18 15:32:19 -070034#include <linux/inet_lro.h>
Auke Kok9a799d72007-09-15 14:07:45 -070035
36#include "ixgbe_type.h"
37#include "ixgbe_common.h"
38
Jeff Garzik5dd2d332008-10-16 05:09:31 -040039#ifdef CONFIG_IXGBE_DCA
Jeb Cramerbd0362d2008-03-03 15:04:02 -080040#include <linux/dca.h>
41#endif
Auke Kok9a799d72007-09-15 14:07:45 -070042
Auke Kok9a799d72007-09-15 14:07:45 -070043#define PFX "ixgbe: "
44#define DPRINTK(nlevel, klevel, fmt, args...) \
45 ((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
46 printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
Harvey Harrisonb39d66a2008-08-20 16:52:04 -070047 __func__ , ## args)))
Auke Kok9a799d72007-09-15 14:07:45 -070048
49/* TX/RX descriptor defines */
50#define IXGBE_DEFAULT_TXD 1024
51#define IXGBE_MAX_TXD 4096
52#define IXGBE_MIN_TXD 64
53
54#define IXGBE_DEFAULT_RXD 1024
55#define IXGBE_MAX_RXD 4096
56#define IXGBE_MIN_RXD 64
57
Auke Kok9a799d72007-09-15 14:07:45 -070058/* flow control */
59#define IXGBE_DEFAULT_FCRTL 0x10000
Jesse Brandeburg2b9ade92008-08-26 04:27:10 -070060#define IXGBE_MIN_FCRTL 0x40
Auke Kok9a799d72007-09-15 14:07:45 -070061#define IXGBE_MAX_FCRTL 0x7FF80
62#define IXGBE_DEFAULT_FCRTH 0x20000
Jesse Brandeburg2b9ade92008-08-26 04:27:10 -070063#define IXGBE_MIN_FCRTH 0x600
Auke Kok9a799d72007-09-15 14:07:45 -070064#define IXGBE_MAX_FCRTH 0x7FFF0
Jesse Brandeburg2b9ade92008-08-26 04:27:10 -070065#define IXGBE_DEFAULT_FCPAUSE 0xFFFF
Auke Kok9a799d72007-09-15 14:07:45 -070066#define IXGBE_MIN_FCPAUSE 0
67#define IXGBE_MAX_FCPAUSE 0xFFFF
68
69/* Supported Rx Buffer Sizes */
70#define IXGBE_RXBUFFER_64 64 /* Used for packet split */
71#define IXGBE_RXBUFFER_128 128 /* Used for packet split */
72#define IXGBE_RXBUFFER_256 256 /* Used for packet split */
73#define IXGBE_RXBUFFER_2048 2048
74
75#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
76
77#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
78
Auke Kok9a799d72007-09-15 14:07:45 -070079/* How many Rx Buffers do we bundle into one write to the hardware ? */
80#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
81
82#define IXGBE_TX_FLAGS_CSUM (u32)(1)
83#define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
84#define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
85#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
86#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
87#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
88
Mallikarjuna R Chilakala177db6f2008-06-18 15:32:19 -070089#define IXGBE_MAX_LRO_DESCRIPTORS 8
90#define IXGBE_MAX_LRO_AGGREGATE 32
91
Auke Kok9a799d72007-09-15 14:07:45 -070092/* wrapper around a pointer to a socket buffer,
93 * so a DMA handle can be stored along with the buffer */
94struct ixgbe_tx_buffer {
95 struct sk_buff *skb;
96 dma_addr_t dma;
97 unsigned long time_stamp;
98 u16 length;
99 u16 next_to_watch;
100};
101
102struct ixgbe_rx_buffer {
103 struct sk_buff *skb;
104 dma_addr_t dma;
105 struct page *page;
106 dma_addr_t page_dma;
Jesse Brandeburg762f4c52008-09-11 19:58:43 -0700107 unsigned int page_offset;
Auke Kok9a799d72007-09-15 14:07:45 -0700108};
109
110struct ixgbe_queue_stats {
111 u64 packets;
112 u64 bytes;
113};
114
115struct ixgbe_ring {
Auke Kok9a799d72007-09-15 14:07:45 -0700116 void *desc; /* descriptor ring memory */
117 dma_addr_t dma; /* phys. address of descriptor ring */
118 unsigned int size; /* length in bytes */
119 unsigned int count; /* amount of descriptors */
120 unsigned int next_to_use;
121 unsigned int next_to_clean;
122
Ayyappan Veeraiyan021230d2008-03-03 15:03:45 -0800123 int queue_index; /* needed for multiqueue queue management */
Auke Kok9a799d72007-09-15 14:07:45 -0700124 union {
125 struct ixgbe_tx_buffer *tx_buffer_info;
126 struct ixgbe_rx_buffer *rx_buffer_info;
127 };
128
129 u16 head;
130 u16 tail;
131
Ayyappan Veeraiyanf494e8f2008-03-03 15:03:57 -0800132 unsigned int total_bytes;
133 unsigned int total_packets;
Auke Kok9a799d72007-09-15 14:07:45 -0700134
Ayyappan Veeraiyan021230d2008-03-03 15:03:45 -0800135 u16 reg_idx; /* holds the special value that gets the hardware register
136 * offset associated with this ring, which is different
137 * for DCE and RSS modes */
Jeb Cramerbd0362d2008-03-03 15:04:02 -0800138
Jeff Garzik5dd2d332008-10-16 05:09:31 -0400139#ifdef CONFIG_IXGBE_DCA
Jeb Cramerbd0362d2008-03-03 15:04:02 -0800140 /* cpu for tx queue */
141 int cpu;
142#endif
Mallikarjuna R Chilakala177db6f2008-06-18 15:32:19 -0700143 struct net_lro_mgr lro_mgr;
144 bool lro_used;
Auke Kok9a799d72007-09-15 14:07:45 -0700145 struct ixgbe_queue_stats stats;
Jesse Brandeburgff819cf2008-09-11 19:58:29 -0700146 u16 v_idx; /* maps directly to the index for this ring in the hardware
147 * vector array, can also be used for finding the bit in EICR
148 * and friends that represents the vector for this ring */
Auke Kok9a799d72007-09-15 14:07:45 -0700149
Auke Kok9a799d72007-09-15 14:07:45 -0700150
Auke Kok9a799d72007-09-15 14:07:45 -0700151 u16 work_limit; /* max work per interrupt */
Jesse Brandeburg7c6e0a42008-08-26 04:27:16 -0700152 u16 rx_buf_len;
Auke Kok9a799d72007-09-15 14:07:45 -0700153};
154
Ayyappan Veeraiyan021230d2008-03-03 15:03:45 -0800155#define RING_F_VMDQ 1
156#define RING_F_RSS 2
157#define IXGBE_MAX_RSS_INDICES 16
158#define IXGBE_MAX_VMDQ_INDICES 16
159struct ixgbe_ring_feature {
160 int indices;
161 int mask;
162};
163
164#define MAX_RX_QUEUES 64
165#define MAX_TX_QUEUES 32
166
167/* MAX_MSIX_Q_VECTORS of these are allocated,
168 * but we only use one per queue-specific vector.
169 */
170struct ixgbe_q_vector {
171 struct ixgbe_adapter *adapter;
172 struct napi_struct napi;
173 DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
174 DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
175 u8 rxr_count; /* Rx ring count assigned to this vector */
176 u8 txr_count; /* Tx ring count assigned to this vector */
Jesse Brandeburg30efa5a2008-09-11 19:58:14 -0700177 u8 tx_itr;
178 u8 rx_itr;
Ayyappan Veeraiyan021230d2008-03-03 15:03:45 -0800179 u32 eitr;
180};
181
Auke Kok9a799d72007-09-15 14:07:45 -0700182/* Helper macros to switch between ints/sec and what the register uses.
183 * And yes, it's the same math going both ways.
184 */
185#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
186 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 0)
187#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
188
189#define IXGBE_DESC_UNUSED(R) \
190 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
191 (R)->next_to_clean - (R)->next_to_use - 1)
192
193#define IXGBE_RX_DESC_ADV(R, i) \
194 (&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
195#define IXGBE_TX_DESC_ADV(R, i) \
196 (&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
197#define IXGBE_TX_CTXTDESC_ADV(R, i) \
198 (&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))
199
200#define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
201
Ayyappan Veeraiyan021230d2008-03-03 15:03:45 -0800202#define OTHER_VECTOR 1
203#define NON_Q_VECTORS (OTHER_VECTOR)
204
205#define MAX_MSIX_Q_VECTORS 16
206#define MIN_MSIX_Q_VECTORS 2
207#define MAX_MSIX_COUNT (MAX_MSIX_Q_VECTORS + NON_Q_VECTORS)
208#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
209
Auke Kok9a799d72007-09-15 14:07:45 -0700210/* board specific private data structure */
211struct ixgbe_adapter {
212 struct timer_list watchdog_timer;
213 struct vlan_group *vlgrp;
214 u16 bd_number;
Auke Kok9a799d72007-09-15 14:07:45 -0700215 struct work_struct reset_task;
Ayyappan Veeraiyan021230d2008-03-03 15:03:45 -0800216 struct ixgbe_q_vector q_vector[MAX_MSIX_Q_VECTORS];
217 char name[MAX_MSIX_COUNT][IFNAMSIZ + 5];
Auke Kok9a799d72007-09-15 14:07:45 -0700218
Ayyappan Veeraiyanf494e8f2008-03-03 15:03:57 -0800219 /* Interrupt Throttle Rate */
220 u32 itr_setting;
221 u16 eitr_low;
222 u16 eitr_high;
223
Auke Kok9a799d72007-09-15 14:07:45 -0700224 /* TX */
225 struct ixgbe_ring *tx_ring; /* One per active queue */
Jesse Brandeburg30efa5a2008-09-11 19:58:14 -0700226 int num_tx_queues;
Auke Kok9a799d72007-09-15 14:07:45 -0700227 u64 restart_queue;
Jesse Brandeburg30efa5a2008-09-11 19:58:14 -0700228 u64 hw_csum_tx_good;
Auke Kok9a799d72007-09-15 14:07:45 -0700229 u64 lsc_int;
230 u64 hw_tso_ctxt;
231 u64 hw_tso6_ctxt;
232 u32 tx_timeout_count;
233 bool detect_tx_hung;
234
235 /* RX */
236 struct ixgbe_ring *rx_ring; /* One per active queue */
Jesse Brandeburg30efa5a2008-09-11 19:58:14 -0700237 int num_rx_queues;
Auke Kok9a799d72007-09-15 14:07:45 -0700238 u64 hw_csum_rx_error;
239 u64 hw_csum_rx_good;
240 u64 non_eop_descs;
Ayyappan Veeraiyan021230d2008-03-03 15:03:45 -0800241 int num_msix_vectors;
242 struct ixgbe_ring_feature ring_feature[3];
Auke Kok9a799d72007-09-15 14:07:45 -0700243 struct msix_entry *msix_entries;
244
245 u64 rx_hdr_split;
246 u32 alloc_rx_page_failed;
247 u32 alloc_rx_buff_failed;
248
Ayyappan Veeraiyan021230d2008-03-03 15:03:45 -0800249 /* Some features need tri-state capability,
250 * thus the additional *_CAPABLE flags.
251 */
Auke Kok9a799d72007-09-15 14:07:45 -0700252 u32 flags;
Jesse Brandeburg96b0e0f2008-08-26 04:27:21 -0700253#define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
254#define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
255#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
256#define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
257#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
258#define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
259#define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
260#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
261#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
262#define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
263#define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
264#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
265#define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
266#define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
267#define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
268#define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
269#define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
Jesse Brandeburg0befdb32008-10-31 00:46:40 -0700270#define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
Jesse Brandeburg96b0e0f2008-08-26 04:27:21 -0700271#define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
272#define IXGBE_FLAG_IN_WATCHDOG_TASK (u32)(1 << 23)
273
274/* default to trying for four seconds */
275#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
Auke Kok9a799d72007-09-15 14:07:45 -0700276
277 /* OS defined structs */
278 struct net_device *netdev;
279 struct pci_dev *pdev;
280 struct net_device_stats net_stats;
281
282 /* structs defined in ixgbe_hw.h */
283 struct ixgbe_hw hw;
284 u16 msg_enable;
285 struct ixgbe_hw_stats stats;
Ayyappan Veeraiyan021230d2008-03-03 15:03:45 -0800286
287 /* Interrupt Throttle Rate */
Jesse Brandeburg30efa5a2008-09-11 19:58:14 -0700288 u32 eitr_param;
Auke Kok9a799d72007-09-15 14:07:45 -0700289
290 unsigned long state;
291 u64 tx_busy;
Mallikarjuna R Chilakala177db6f2008-06-18 15:32:19 -0700292 u64 lro_aggregated;
293 u64 lro_flushed;
294 u64 lro_no_desc;
Jesse Brandeburg30efa5a2008-09-11 19:58:14 -0700295 unsigned int tx_ring_count;
296 unsigned int rx_ring_count;
Jesse Brandeburgcf8280e2008-09-11 19:55:32 -0700297
298 u32 link_speed;
299 bool link_up;
300 unsigned long link_check_timeout;
301
302 struct work_struct watchdog_task;
Auke Kok9a799d72007-09-15 14:07:45 -0700303};
304
305enum ixbge_state_t {
306 __IXGBE_TESTING,
307 __IXGBE_RESETTING,
308 __IXGBE_DOWN
309};
310
311enum ixgbe_boards {
Auke Kok3957d632007-10-31 15:22:10 -0700312 board_82598,
Auke Kok9a799d72007-09-15 14:07:45 -0700313};
314
Auke Kok3957d632007-10-31 15:22:10 -0700315extern struct ixgbe_info ixgbe_82598_info;
Auke Kok9a799d72007-09-15 14:07:45 -0700316
317extern char ixgbe_driver_name[];
Stephen Hemminger9c8eb722007-10-29 10:46:24 -0700318extern const char ixgbe_driver_version[];
Auke Kok9a799d72007-09-15 14:07:45 -0700319
320extern int ixgbe_up(struct ixgbe_adapter *adapter);
321extern void ixgbe_down(struct ixgbe_adapter *adapter);
Ayyappan Veeraiyand4f80882008-02-01 15:58:41 -0800322extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
Auke Kok9a799d72007-09-15 14:07:45 -0700323extern void ixgbe_reset(struct ixgbe_adapter *adapter);
Auke Kok9a799d72007-09-15 14:07:45 -0700324extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
Peter P Waskiewiczb4617242008-09-11 20:04:46 -0700325extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
326extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
327extern void ixgbe_free_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
328extern void ixgbe_free_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
329extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
Auke Kok9a799d72007-09-15 14:07:45 -0700330
331#endif /* _IXGBE_H_ */