blob: 8f7bcf56f1498d17064916d9986433e4e557631b [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * drivers/pci/setup-bus.c
3 *
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
8 *
9 * Support routines for initializing a PCI subsystem.
10 */
11
12/*
13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
14 * PCI-PCI bridges cleanup, sorted resource allocation.
15 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 * Converted to allocation in 3 passes, which gives
17 * tighter packing. Prefetchable range support.
18 */
19
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/pci.h>
24#include <linux/errno.h>
25#include <linux/ioport.h>
26#include <linux/cache.h>
27#include <linux/slab.h>
28
29
30#define DEBUG_CONFIG 1
31#if DEBUG_CONFIG
32#define DBG(x...) printk(x)
33#else
34#define DBG(x...)
35#endif
36
37#define ROUND_UP(x, a) (((x) + (a) - 1) & ~((a) - 1))
38
39/*
40 * FIXME: IO should be max 256 bytes. However, since we may
41 * have a P2P bridge below a cardbus bridge, we need 4K.
42 */
Linus Torvalds4196c3a2005-10-23 16:31:16 -070043#define CARDBUS_IO_SIZE (256)
Linus Torvalds1da177e2005-04-16 15:20:36 -070044#define CARDBUS_MEM_SIZE (32*1024*1024)
45
46static void __devinit
47pbus_assign_resources_sorted(struct pci_bus *bus)
48{
49 struct pci_dev *dev;
50 struct resource *res;
51 struct resource_list head, *list, *tmp;
52 int idx;
53
Linus Torvalds1da177e2005-04-16 15:20:36 -070054 head.next = NULL;
55 list_for_each_entry(dev, &bus->devices, bus_list) {
56 u16 class = dev->class >> 8;
57
Kenji Kaneshige9bded002006-10-04 02:15:34 -070058 /* Don't touch classless devices or host bridges or ioapics. */
Linus Torvalds1da177e2005-04-16 15:20:36 -070059 if (class == PCI_CLASS_NOT_DEFINED ||
Satoru Takeuchi23186272006-09-12 10:21:44 -070060 class == PCI_CLASS_BRIDGE_HOST)
Linus Torvalds1da177e2005-04-16 15:20:36 -070061 continue;
62
Kenji Kaneshige9bded002006-10-04 02:15:34 -070063 /* Don't touch ioapic devices already enabled by firmware */
Satoru Takeuchi23186272006-09-12 10:21:44 -070064 if (class == PCI_CLASS_SYSTEM_PIC) {
Kenji Kaneshige9bded002006-10-04 02:15:34 -070065 u16 command;
66 pci_read_config_word(dev, PCI_COMMAND, &command);
67 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
Satoru Takeuchi23186272006-09-12 10:21:44 -070068 continue;
69 }
70
Linus Torvalds1da177e2005-04-16 15:20:36 -070071 pdev_sort_resources(dev, &head);
72 }
73
74 for (list = head.next; list;) {
75 res = list->res;
76 idx = res - &list->dev->resource[0];
Rajesh Shah542df5d2005-04-28 00:25:50 -070077 if (pci_assign_resource(list->dev, idx)) {
78 res->start = 0;
Ivan Kokshaysky960b8462005-07-07 03:07:56 +040079 res->end = 0;
Rajesh Shah542df5d2005-04-28 00:25:50 -070080 res->flags = 0;
81 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070082 tmp = list;
83 list = list->next;
84 kfree(tmp);
85 }
86}
87
Dominik Brodowskib3743fa2005-09-09 13:03:23 -070088void pci_setup_cardbus(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -070089{
90 struct pci_dev *bridge = bus->self;
91 struct pci_bus_region region;
92
93 printk("PCI: Bus %d, cardbus bridge: %s\n",
94 bus->number, pci_name(bridge));
95
96 pcibios_resource_to_bus(bridge, &region, bus->resource[0]);
97 if (bus->resource[0]->flags & IORESOURCE_IO) {
98 /*
99 * The IO resource is allocated a range twice as large as it
100 * would normally need. This allows us to set both IO regs.
101 */
102 printk(" IO window: %08lx-%08lx\n",
103 region.start, region.end);
104 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
105 region.start);
106 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
107 region.end);
108 }
109
110 pcibios_resource_to_bus(bridge, &region, bus->resource[1]);
111 if (bus->resource[1]->flags & IORESOURCE_IO) {
112 printk(" IO window: %08lx-%08lx\n",
113 region.start, region.end);
114 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
115 region.start);
116 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
117 region.end);
118 }
119
120 pcibios_resource_to_bus(bridge, &region, bus->resource[2]);
121 if (bus->resource[2]->flags & IORESOURCE_MEM) {
122 printk(" PREFETCH window: %08lx-%08lx\n",
123 region.start, region.end);
124 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
125 region.start);
126 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
127 region.end);
128 }
129
130 pcibios_resource_to_bus(bridge, &region, bus->resource[3]);
131 if (bus->resource[3]->flags & IORESOURCE_MEM) {
132 printk(" MEM window: %08lx-%08lx\n",
133 region.start, region.end);
134 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
135 region.start);
136 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
137 region.end);
138 }
139}
Dominik Brodowskib3743fa2005-09-09 13:03:23 -0700140EXPORT_SYMBOL(pci_setup_cardbus);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700141
142/* Initialize bridges with base/limit values we have collected.
143 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
144 requires that if there is no I/O ports or memory behind the
145 bridge, corresponding range must be turned off by writing base
146 value greater than limit to the bridge's base/limit registers.
147
148 Note: care must be taken when updating I/O base/limit registers
149 of bridges which support 32-bit I/O. This update requires two
150 config space writes, so it's quite possible that an I/O window of
151 the bridge will have some undesirable address (e.g. 0) after the
152 first write. Ditto 64-bit prefetchable MMIO. */
153static void __devinit
154pci_setup_bridge(struct pci_bus *bus)
155{
156 struct pci_dev *bridge = bus->self;
157 struct pci_bus_region region;
158 u32 l, io_upper16;
159
160 DBG(KERN_INFO "PCI: Bridge: %s\n", pci_name(bridge));
161
162 /* Set up the top and bottom of the PCI I/O segment for this bus. */
163 pcibios_resource_to_bus(bridge, &region, bus->resource[0]);
164 if (bus->resource[0]->flags & IORESOURCE_IO) {
165 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
166 l &= 0xffff0000;
167 l |= (region.start >> 8) & 0x00f0;
168 l |= region.end & 0xf000;
169 /* Set up upper 16 bits of I/O base/limit. */
170 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
171 DBG(KERN_INFO " IO window: %04lx-%04lx\n",
172 region.start, region.end);
173 }
174 else {
175 /* Clear upper 16 bits of I/O base/limit. */
176 io_upper16 = 0;
177 l = 0x00f0;
178 DBG(KERN_INFO " IO window: disabled.\n");
179 }
180 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
181 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
182 /* Update lower 16 bits of I/O base/limit. */
183 pci_write_config_dword(bridge, PCI_IO_BASE, l);
184 /* Update upper 16 bits of I/O base/limit. */
185 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
186
187 /* Set up the top and bottom of the PCI Memory segment
188 for this bus. */
189 pcibios_resource_to_bus(bridge, &region, bus->resource[1]);
190 if (bus->resource[1]->flags & IORESOURCE_MEM) {
191 l = (region.start >> 16) & 0xfff0;
192 l |= region.end & 0xfff00000;
193 DBG(KERN_INFO " MEM window: %08lx-%08lx\n",
194 region.start, region.end);
195 }
196 else {
197 l = 0x0000fff0;
198 DBG(KERN_INFO " MEM window: disabled.\n");
199 }
200 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
201
202 /* Clear out the upper 32 bits of PREF limit.
203 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
204 disables PREF range, which is ok. */
205 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
206
207 /* Set up PREF base/limit. */
208 pcibios_resource_to_bus(bridge, &region, bus->resource[2]);
209 if (bus->resource[2]->flags & IORESOURCE_PREFETCH) {
210 l = (region.start >> 16) & 0xfff0;
211 l |= region.end & 0xfff00000;
212 DBG(KERN_INFO " PREFETCH window: %08lx-%08lx\n",
213 region.start, region.end);
214 }
215 else {
216 l = 0x0000fff0;
217 DBG(KERN_INFO " PREFETCH window: disabled.\n");
218 }
219 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
220
221 /* Clear out the upper 32 bits of PREF base. */
222 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 0);
223
224 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
225}
226
227/* Check whether the bridge supports optional I/O and
228 prefetchable memory ranges. If not, the respective
229 base/limit registers must be read-only and read as 0. */
230static void __devinit
231pci_bridge_check_ranges(struct pci_bus *bus)
232{
233 u16 io;
234 u32 pmem;
235 struct pci_dev *bridge = bus->self;
236 struct resource *b_res;
237
238 b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
239 b_res[1].flags |= IORESOURCE_MEM;
240
241 pci_read_config_word(bridge, PCI_IO_BASE, &io);
242 if (!io) {
243 pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
244 pci_read_config_word(bridge, PCI_IO_BASE, &io);
245 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
246 }
247 if (io)
248 b_res[0].flags |= IORESOURCE_IO;
249 /* DECchip 21050 pass 2 errata: the bridge may miss an address
250 disconnect boundary by one PCI data phase.
251 Workaround: do not use prefetching on this device. */
252 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
253 return;
254 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
255 if (!pmem) {
256 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
257 0xfff0fff0);
258 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
259 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
260 }
261 if (pmem)
262 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
263}
264
265/* Helper function for sizing routines: find first available
266 bus resource of a given type. Note: we intentionally skip
267 the bus resources which have already been assigned (that is,
268 have non-NULL parent resource). */
269static struct resource * __devinit
270find_free_bus_resource(struct pci_bus *bus, unsigned long type)
271{
272 int i;
273 struct resource *r;
274 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
275 IORESOURCE_PREFETCH;
276
277 for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
278 r = bus->resource[i];
Ivan Kokshaysky299de032005-06-15 18:59:27 +0400279 if (r == &ioport_resource || r == &iomem_resource)
280 continue;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700281 if (r && (r->flags & type_mask) == type && !r->parent)
282 return r;
283 }
284 return NULL;
285}
286
287/* Sizing the IO windows of the PCI-PCI bridge is trivial,
288 since these windows have 4K granularity and the IO ranges
289 of non-bridge PCI devices are limited to 256 bytes.
290 We must be careful with the ISA aliasing though. */
291static void __devinit
292pbus_size_io(struct pci_bus *bus)
293{
294 struct pci_dev *dev;
295 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
296 unsigned long size = 0, size1 = 0;
297
298 if (!b_res)
299 return;
300
301 list_for_each_entry(dev, &bus->devices, bus_list) {
302 int i;
303
304 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
305 struct resource *r = &dev->resource[i];
306 unsigned long r_size;
307
308 if (r->parent || !(r->flags & IORESOURCE_IO))
309 continue;
310 r_size = r->end - r->start + 1;
311
312 if (r_size < 0x400)
313 /* Might be re-aligned for ISA */
314 size += r_size;
315 else
316 size1 += r_size;
317 }
318 }
319/* To be fixed in 2.5: we should have sort of HAVE_ISA
320 flag in the struct pci_bus. */
321#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
322 size = (size & 0xff) + ((size & ~0xffUL) << 2);
323#endif
324 size = ROUND_UP(size + size1, 4096);
325 if (!size) {
326 b_res->flags = 0;
327 return;
328 }
329 /* Alignment of the IO window is always 4K */
330 b_res->start = 4096;
331 b_res->end = b_res->start + size - 1;
332}
333
334/* Calculate the size of the bus and minimal alignment which
335 guarantees that all child resources fit in this size. */
336static int __devinit
337pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long type)
338{
339 struct pci_dev *dev;
340 unsigned long min_align, align, size;
341 unsigned long aligns[12]; /* Alignments from 1Mb to 2Gb */
342 int order, max_order;
343 struct resource *b_res = find_free_bus_resource(bus, type);
344
345 if (!b_res)
346 return 0;
347
348 memset(aligns, 0, sizeof(aligns));
349 max_order = 0;
350 size = 0;
351
352 list_for_each_entry(dev, &bus->devices, bus_list) {
353 int i;
354
355 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
356 struct resource *r = &dev->resource[i];
357 unsigned long r_size;
358
359 if (r->parent || (r->flags & mask) != type)
360 continue;
361 r_size = r->end - r->start + 1;
362 /* For bridges size != alignment */
363 align = (i < PCI_BRIDGE_RESOURCES) ? r_size : r->start;
364 order = __ffs(align) - 20;
365 if (order > 11) {
366 printk(KERN_WARNING "PCI: region %s/%d "
Greg Kroah-Hartman1396a8c2006-06-12 15:14:29 -0700367 "too large: %llx-%llx\n",
368 pci_name(dev), i,
369 (unsigned long long)r->start,
370 (unsigned long long)r->end);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700371 r->flags = 0;
372 continue;
373 }
374 size += r_size;
375 if (order < 0)
376 order = 0;
377 /* Exclude ranges with size > align from
378 calculation of the alignment. */
379 if (r_size == align)
380 aligns[order] += align;
381 if (order > max_order)
382 max_order = order;
383 }
384 }
385
386 align = 0;
387 min_align = 0;
388 for (order = 0; order <= max_order; order++) {
389 unsigned long align1 = 1UL << (order + 20);
390
391 if (!align)
392 min_align = align1;
393 else if (ROUND_UP(align + min_align, min_align) < align1)
394 min_align = align1 >> 1;
395 align += aligns[order];
396 }
397 size = ROUND_UP(size, min_align);
398 if (!size) {
399 b_res->flags = 0;
400 return 1;
401 }
402 b_res->start = min_align;
403 b_res->end = size + min_align - 1;
404 return 1;
405}
406
407static void __devinit
408pci_bus_size_cardbus(struct pci_bus *bus)
409{
410 struct pci_dev *bridge = bus->self;
411 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
412 u16 ctrl;
413
414 /*
415 * Reserve some resources for CardBus. We reserve
416 * a fixed amount of bus space for CardBus bridges.
417 */
418 b_res[0].start = CARDBUS_IO_SIZE;
419 b_res[0].end = b_res[0].start + CARDBUS_IO_SIZE - 1;
420 b_res[0].flags |= IORESOURCE_IO;
421
422 b_res[1].start = CARDBUS_IO_SIZE;
423 b_res[1].end = b_res[1].start + CARDBUS_IO_SIZE - 1;
424 b_res[1].flags |= IORESOURCE_IO;
425
426 /*
427 * Check whether prefetchable memory is supported
428 * by this bridge.
429 */
430 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
431 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
432 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
433 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
434 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
435 }
436
437 /*
438 * If we have prefetchable memory support, allocate
439 * two regions. Otherwise, allocate one region of
440 * twice the size.
441 */
442 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
443 b_res[2].start = CARDBUS_MEM_SIZE;
444 b_res[2].end = b_res[2].start + CARDBUS_MEM_SIZE - 1;
445 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
446
447 b_res[3].start = CARDBUS_MEM_SIZE;
448 b_res[3].end = b_res[3].start + CARDBUS_MEM_SIZE - 1;
449 b_res[3].flags |= IORESOURCE_MEM;
450 } else {
451 b_res[3].start = CARDBUS_MEM_SIZE * 2;
452 b_res[3].end = b_res[3].start + CARDBUS_MEM_SIZE * 2 - 1;
453 b_res[3].flags |= IORESOURCE_MEM;
454 }
455}
456
457void __devinit
458pci_bus_size_bridges(struct pci_bus *bus)
459{
460 struct pci_dev *dev;
461 unsigned long mask, prefmask;
462
463 list_for_each_entry(dev, &bus->devices, bus_list) {
464 struct pci_bus *b = dev->subordinate;
465 if (!b)
466 continue;
467
468 switch (dev->class >> 8) {
469 case PCI_CLASS_BRIDGE_CARDBUS:
470 pci_bus_size_cardbus(b);
471 break;
472
473 case PCI_CLASS_BRIDGE_PCI:
474 default:
475 pci_bus_size_bridges(b);
476 break;
477 }
478 }
479
480 /* The root bus? */
481 if (!bus->self)
482 return;
483
484 switch (bus->self->class >> 8) {
485 case PCI_CLASS_BRIDGE_CARDBUS:
486 /* don't size cardbuses yet. */
487 break;
488
489 case PCI_CLASS_BRIDGE_PCI:
490 pci_bridge_check_ranges(bus);
491 default:
492 pbus_size_io(bus);
493 /* If the bridge supports prefetchable range, size it
494 separately. If it doesn't, or its prefetchable window
495 has already been allocated by arch code, try
496 non-prefetchable range for both types of PCI memory
497 resources. */
498 mask = IORESOURCE_MEM;
499 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
500 if (pbus_size_mem(bus, prefmask, prefmask))
501 mask = prefmask; /* Success, size non-prefetch only. */
502 pbus_size_mem(bus, mask, IORESOURCE_MEM);
503 break;
504 }
505}
506EXPORT_SYMBOL(pci_bus_size_bridges);
507
508void __devinit
509pci_bus_assign_resources(struct pci_bus *bus)
510{
511 struct pci_bus *b;
512 struct pci_dev *dev;
513
514 pbus_assign_resources_sorted(bus);
515
Linus Torvalds1da177e2005-04-16 15:20:36 -0700516 list_for_each_entry(dev, &bus->devices, bus_list) {
517 b = dev->subordinate;
518 if (!b)
519 continue;
520
521 pci_bus_assign_resources(b);
522
523 switch (dev->class >> 8) {
524 case PCI_CLASS_BRIDGE_PCI:
525 pci_setup_bridge(b);
526 break;
527
528 case PCI_CLASS_BRIDGE_CARDBUS:
529 pci_setup_cardbus(b);
530 break;
531
532 default:
533 printk(KERN_INFO "PCI: not setting up bridge %s "
534 "for bus %d\n", pci_name(dev), b->number);
535 break;
536 }
537 }
538}
539EXPORT_SYMBOL(pci_bus_assign_resources);
540
541void __init
542pci_assign_unassigned_resources(void)
543{
544 struct pci_bus *bus;
545
546 /* Depth first, calculate sizes and alignments of all
547 subordinate buses. */
548 list_for_each_entry(bus, &pci_root_buses, node) {
549 pci_bus_size_bridges(bus);
550 }
551 /* Depth last, allocate resources and update the hardware. */
552 list_for_each_entry(bus, &pci_root_buses, node) {
553 pci_bus_assign_resources(bus);
554 pci_enable_bridges(bus);
555 }
556}