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Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +00001/*
2 * Renesas SuperH DMA Engine support
3 *
4 * base is drivers/dma/flsdma.c
5 *
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +02006 * Copyright (C) 2011-2012 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +00007 * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
8 * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
9 * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
10 *
11 * This is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * - DMA of SuperH does not have Hardware DMA chain mode.
17 * - MAX DMA size is 16MB.
18 *
19 */
20
Laurent Pincharta5cdc1c2014-05-13 01:02:11 +020021#include <linux/delay.h>
22#include <linux/dmaengine.h>
Laurent Pinchartc46b9af2014-05-13 01:02:12 +020023#include <linux/err.h>
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +000024#include <linux/init.h>
Laurent Pincharta5cdc1c2014-05-13 01:02:11 +020025#include <linux/interrupt.h>
26#include <linux/kdebug.h>
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +000027#include <linux/module.h>
Laurent Pincharta5cdc1c2014-05-13 01:02:11 +020028#include <linux/notifier.h>
Guennadi Liakhovetski4981c4d2013-08-02 16:50:36 +020029#include <linux/of.h>
30#include <linux/of_device.h>
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +000031#include <linux/platform_device.h>
Guennadi Liakhovetski20f2a3b2010-02-11 16:50:18 +000032#include <linux/pm_runtime.h>
Paul Mundt03aa18f2010-12-17 19:16:10 +090033#include <linux/rculist.h>
Laurent Pincharta5cdc1c2014-05-13 01:02:11 +020034#include <linux/sh_dma.h>
35#include <linux/slab.h>
36#include <linux/spinlock.h>
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +000037
Guennadi Liakhovetskie95be942012-07-02 22:30:53 +020038#include "../dmaengine.h"
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +000039#include "shdma.h"
40
Geert Uytterhoeven6b32faf2014-06-20 14:37:38 +020041/* DMA registers */
42#define SAR 0x00 /* Source Address Register */
43#define DAR 0x04 /* Destination Address Register */
44#define TCR 0x08 /* Transfer Count Register */
45#define CHCR 0x0C /* Channel Control Register */
46#define DMAOR 0x40 /* DMA Operation Register */
Guennadi Liakhovetski4620ad52013-08-02 16:50:37 +020047
48#define TEND 0x18 /* USB-DMAC */
49
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +020050#define SH_DMAE_DRV_NAME "sh-dma-engine"
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +000051
Guennadi Liakhovetski8b1935e2010-02-11 16:50:14 +000052/* Default MEMCPY transfer size = 2^2 = 4 bytes */
53#define LOG2_DEFAULT_XFER_SIZE 2
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +020054#define SH_DMA_SLAVE_NUMBER 256
55#define SH_DMA_TCR_MAX (16 * 1024 * 1024 - 1)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +000056
Paul Mundt03aa18f2010-12-17 19:16:10 +090057/*
58 * Used for write-side mutual exclusion for the global device list,
Guennadi Liakhovetski2dc66662011-04-29 17:09:21 +000059 * read-side synchronization by way of RCU, and per-controller data.
Paul Mundt03aa18f2010-12-17 19:16:10 +090060 */
61static DEFINE_SPINLOCK(sh_dmae_lock);
62static LIST_HEAD(sh_dmae_devices);
63
Guennadi Liakhovetskica8b3872013-07-10 12:09:47 +020064/*
65 * Different DMAC implementations provide different ways to clear DMA channels:
66 * (1) none - no CHCLR registers are available
67 * (2) one CHCLR register per channel - 0 has to be written to it to clear
68 * channel buffers
69 * (3) one CHCLR per several channels - 1 has to be written to the bit,
70 * corresponding to the specific channel to reset it
71 */
Guennadi Liakhovetskia28a94e2013-07-02 17:37:58 +020072static void channel_clear(struct sh_dmae_chan *sh_dc)
Guennadi Liakhovetskic11b46c322012-01-04 15:34:17 +010073{
74 struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
Guennadi Liakhovetskica8b3872013-07-10 12:09:47 +020075 const struct sh_dmae_channel *chan_pdata = shdev->pdata->channel +
76 sh_dc->shdma_chan.id;
77 u32 val = shdev->pdata->chclr_bitwise ? 1 << chan_pdata->chclr_bit : 0;
Guennadi Liakhovetskic11b46c322012-01-04 15:34:17 +010078
Guennadi Liakhovetskica8b3872013-07-10 12:09:47 +020079 __raw_writel(val, shdev->chan_reg + chan_pdata->chclr_offset);
Guennadi Liakhovetskic11b46c322012-01-04 15:34:17 +010080}
Guennadi Liakhovetski3542a112009-12-17 09:41:39 -070081
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +000082static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg)
83{
Guennadi Liakhovetski115357e2013-07-02 17:46:01 +020084 __raw_writel(data, sh_dc->base + reg);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +000085}
86
87static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg)
88{
Guennadi Liakhovetski115357e2013-07-02 17:46:01 +020089 return __raw_readl(sh_dc->base + reg);
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +000090}
91
92static u16 dmaor_read(struct sh_dmae_device *shdev)
93{
Guennadi Liakhovetski115357e2013-07-02 17:46:01 +020094 void __iomem *addr = shdev->chan_reg + DMAOR;
Kuninori Morimotoe76c3af2011-06-17 08:20:56 +000095
96 if (shdev->pdata->dmaor_is_32bit)
97 return __raw_readl(addr);
98 else
99 return __raw_readw(addr);
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000100}
101
102static void dmaor_write(struct sh_dmae_device *shdev, u16 data)
103{
Guennadi Liakhovetski115357e2013-07-02 17:46:01 +0200104 void __iomem *addr = shdev->chan_reg + DMAOR;
Kuninori Morimotoe76c3af2011-06-17 08:20:56 +0000105
106 if (shdev->pdata->dmaor_is_32bit)
107 __raw_writel(data, addr);
108 else
109 __raw_writew(data, addr);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000110}
111
Kuninori Morimoto5899a722011-06-17 08:20:40 +0000112static void chcr_write(struct sh_dmae_chan *sh_dc, u32 data)
113{
114 struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
115
Guennadi Liakhovetski115357e2013-07-02 17:46:01 +0200116 __raw_writel(data, sh_dc->base + shdev->chcr_offset);
Kuninori Morimoto5899a722011-06-17 08:20:40 +0000117}
118
119static u32 chcr_read(struct sh_dmae_chan *sh_dc)
120{
121 struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
122
Guennadi Liakhovetski115357e2013-07-02 17:46:01 +0200123 return __raw_readl(sh_dc->base + shdev->chcr_offset);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000124}
125
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000126/*
127 * Reset DMA controller
128 *
129 * SH7780 has two DMAOR register
130 */
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000131static void sh_dmae_ctl_stop(struct sh_dmae_device *shdev)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000132{
Guennadi Liakhovetski2dc66662011-04-29 17:09:21 +0000133 unsigned short dmaor;
134 unsigned long flags;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000135
Guennadi Liakhovetski2dc66662011-04-29 17:09:21 +0000136 spin_lock_irqsave(&sh_dmae_lock, flags);
137
138 dmaor = dmaor_read(shdev);
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000139 dmaor_write(shdev, dmaor & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME));
Guennadi Liakhovetski2dc66662011-04-29 17:09:21 +0000140
141 spin_unlock_irqrestore(&sh_dmae_lock, flags);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000142}
143
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000144static int sh_dmae_rst(struct sh_dmae_device *shdev)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000145{
146 unsigned short dmaor;
Guennadi Liakhovetski2dc66662011-04-29 17:09:21 +0000147 unsigned long flags;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000148
Guennadi Liakhovetski2dc66662011-04-29 17:09:21 +0000149 spin_lock_irqsave(&sh_dmae_lock, flags);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000150
Guennadi Liakhovetski2dc66662011-04-29 17:09:21 +0000151 dmaor = dmaor_read(shdev) & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME);
152
Guennadi Liakhovetskic11b46c322012-01-04 15:34:17 +0100153 if (shdev->pdata->chclr_present) {
154 int i;
155 for (i = 0; i < shdev->pdata->channel_num; i++) {
156 struct sh_dmae_chan *sh_chan = shdev->chan[i];
157 if (sh_chan)
Guennadi Liakhovetskia28a94e2013-07-02 17:37:58 +0200158 channel_clear(sh_chan);
Guennadi Liakhovetskic11b46c322012-01-04 15:34:17 +0100159 }
160 }
161
Guennadi Liakhovetski2dc66662011-04-29 17:09:21 +0000162 dmaor_write(shdev, dmaor | shdev->pdata->dmaor_init);
163
164 dmaor = dmaor_read(shdev);
165
166 spin_unlock_irqrestore(&sh_dmae_lock, flags);
167
168 if (dmaor & (DMAOR_AE | DMAOR_NMIF)) {
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200169 dev_warn(shdev->shdma_dev.dma_dev.dev, "Can't initialize DMAOR.\n");
Guennadi Liakhovetski2dc66662011-04-29 17:09:21 +0000170 return -EIO;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000171 }
Guennadi Liakhovetskic11b46c322012-01-04 15:34:17 +0100172 if (shdev->pdata->dmaor_init & ~dmaor)
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200173 dev_warn(shdev->shdma_dev.dma_dev.dev,
Guennadi Liakhovetskic11b46c322012-01-04 15:34:17 +0100174 "DMAOR=0x%x hasn't latched the initial value 0x%x.\n",
175 dmaor, shdev->pdata->dmaor_init);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000176 return 0;
177}
178
Guennadi Liakhovetskifc461852010-01-19 07:24:55 +0000179static bool dmae_is_busy(struct sh_dmae_chan *sh_chan)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000180{
Kuninori Morimoto5899a722011-06-17 08:20:40 +0000181 u32 chcr = chcr_read(sh_chan);
Guennadi Liakhovetskifc461852010-01-19 07:24:55 +0000182
183 if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE)
184 return true; /* working */
185
186 return false; /* waiting */
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000187}
188
Guennadi Liakhovetski8b1935e2010-02-11 16:50:14 +0000189static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000190{
Kuninori Morimotoc4e0dd72011-06-16 05:08:09 +0000191 struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
Guennadi Liakhovetski2833c472013-08-02 16:18:09 +0200192 const struct sh_dmae_pdata *pdata = shdev->pdata;
Guennadi Liakhovetski8b1935e2010-02-11 16:50:14 +0000193 int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) |
194 ((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift);
Guennadi Liakhovetski623b4ac2010-02-03 14:44:12 +0000195
Guennadi Liakhovetski8b1935e2010-02-11 16:50:14 +0000196 if (cnt >= pdata->ts_shift_num)
197 cnt = 0;
198
199 return pdata->ts_shift[cnt];
200}
201
202static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size)
203{
Kuninori Morimotoc4e0dd72011-06-16 05:08:09 +0000204 struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
Guennadi Liakhovetski2833c472013-08-02 16:18:09 +0200205 const struct sh_dmae_pdata *pdata = shdev->pdata;
Guennadi Liakhovetski8b1935e2010-02-11 16:50:14 +0000206 int i;
207
208 for (i = 0; i < pdata->ts_shift_num; i++)
209 if (pdata->ts_shift[i] == l2size)
210 break;
211
212 if (i == pdata->ts_shift_num)
213 i = 0;
214
215 return ((i << pdata->ts_low_shift) & pdata->ts_low_mask) |
216 ((i << pdata->ts_high_shift) & pdata->ts_high_mask);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000217}
218
Guennadi Liakhovetski3542a112009-12-17 09:41:39 -0700219static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000220{
Guennadi Liakhovetski3542a112009-12-17 09:41:39 -0700221 sh_dmae_writel(sh_chan, hw->sar, SAR);
222 sh_dmae_writel(sh_chan, hw->dar, DAR);
Guennadi Liakhovetskicfefe992010-02-03 14:46:41 +0000223 sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000224}
225
226static void dmae_start(struct sh_dmae_chan *sh_chan)
227{
Kuninori Morimoto67c62692011-06-17 08:20:51 +0000228 struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
Kuninori Morimoto5899a722011-06-17 08:20:40 +0000229 u32 chcr = chcr_read(sh_chan);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000230
Kuninori Morimoto260bf2c2011-06-17 08:21:05 +0000231 if (shdev->pdata->needs_tend_set)
232 sh_dmae_writel(sh_chan, 0xFFFFFFFF, TEND);
233
Kuninori Morimoto67c62692011-06-17 08:20:51 +0000234 chcr |= CHCR_DE | shdev->chcr_ie_bit;
Kuninori Morimoto5899a722011-06-17 08:20:40 +0000235 chcr_write(sh_chan, chcr & ~CHCR_TE);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000236}
237
Guennadi Liakhovetskicfefe992010-02-03 14:46:41 +0000238static void dmae_init(struct sh_dmae_chan *sh_chan)
239{
Guennadi Liakhovetski8b1935e2010-02-11 16:50:14 +0000240 /*
241 * Default configuration for dual address memory-memory transfer.
Guennadi Liakhovetski8b1935e2010-02-11 16:50:14 +0000242 */
Geert Uytterhoeven0cdbee332014-06-20 14:37:41 +0200243 u32 chcr = DM_INC | SM_INC | RS_AUTO | log2size_to_chcr(sh_chan,
Guennadi Liakhovetski8b1935e2010-02-11 16:50:14 +0000244 LOG2_DEFAULT_XFER_SIZE);
245 sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr);
Kuninori Morimoto5899a722011-06-17 08:20:40 +0000246 chcr_write(sh_chan, chcr);
Guennadi Liakhovetskicfefe992010-02-03 14:46:41 +0000247}
248
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000249static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val)
250{
Guennadi Liakhovetski2dc66662011-04-29 17:09:21 +0000251 /* If DMA is active, cannot set CHCR. TODO: remove this superfluous check */
Guennadi Liakhovetskifc461852010-01-19 07:24:55 +0000252 if (dmae_is_busy(sh_chan))
253 return -EBUSY;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000254
Guennadi Liakhovetski8b1935e2010-02-11 16:50:14 +0000255 sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val);
Kuninori Morimoto5899a722011-06-17 08:20:40 +0000256 chcr_write(sh_chan, val);
Guennadi Liakhovetskicfefe992010-02-03 14:46:41 +0000257
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000258 return 0;
259}
260
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000261static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val)
262{
Kuninori Morimotoc4e0dd72011-06-16 05:08:09 +0000263 struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
Guennadi Liakhovetski2833c472013-08-02 16:18:09 +0200264 const struct sh_dmae_pdata *pdata = shdev->pdata;
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200265 const struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->shdma_chan.id];
Guennadi Liakhovetski115357e2013-07-02 17:46:01 +0200266 void __iomem *addr = shdev->dmars;
Kuninori Morimoto090b9182011-06-16 05:08:28 +0000267 unsigned int shift = chan_pdata->dmars_bit;
Guennadi Liakhovetskifc461852010-01-19 07:24:55 +0000268
269 if (dmae_is_busy(sh_chan))
270 return -EBUSY;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000271
Kuninori Morimoto260bf2c2011-06-17 08:21:05 +0000272 if (pdata->no_dmars)
273 return 0;
274
Magnus Damm26fc02a2011-05-24 10:31:12 +0000275 /* in the case of a missing DMARS resource use first memory window */
276 if (!addr)
Guennadi Liakhovetski115357e2013-07-02 17:46:01 +0200277 addr = shdev->chan_reg;
278 addr += chan_pdata->dmars;
Magnus Damm26fc02a2011-05-24 10:31:12 +0000279
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000280 __raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift),
281 addr);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000282
283 return 0;
284}
285
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200286static void sh_dmae_start_xfer(struct shdma_chan *schan,
287 struct shdma_desc *sdesc)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000288{
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200289 struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
290 shdma_chan);
291 struct sh_dmae_desc *sh_desc = container_of(sdesc,
292 struct sh_dmae_desc, shdma_desc);
293 dev_dbg(sh_chan->shdma_chan.dev, "Queue #%d to %d: %u@%x -> %x\n",
294 sdesc->async_tx.cookie, sh_chan->shdma_chan.id,
295 sh_desc->hw.tcr, sh_desc->hw.sar, sh_desc->hw.dar);
296 /* Get the ld start address from ld_queue */
297 dmae_set_reg(sh_chan, &sh_desc->hw);
298 dmae_start(sh_chan);
299}
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000300
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200301static bool sh_dmae_channel_busy(struct shdma_chan *schan)
302{
303 struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
304 shdma_chan);
305 return dmae_is_busy(sh_chan);
306}
Guennadi Liakhovetski7a1cd9a2011-08-18 16:55:27 +0200307
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200308static void sh_dmae_setup_xfer(struct shdma_chan *schan,
Guennadi Liakhovetskic2cdb7e2012-07-05 12:29:41 +0200309 int slave_id)
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200310{
311 struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
312 shdma_chan);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000313
Guennadi Liakhovetskic2cdb7e2012-07-05 12:29:41 +0200314 if (slave_id >= 0) {
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200315 const struct sh_dmae_slave_config *cfg =
Guennadi Liakhovetskiecf90fb2012-07-05 12:29:40 +0200316 sh_chan->config;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000317
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200318 dmae_set_dmars(sh_chan, cfg->mid_rid);
319 dmae_set_chcr(sh_chan, cfg->chcr);
Guennadi Liakhovetskic11b46c322012-01-04 15:34:17 +0100320 } else {
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200321 dmae_init(sh_chan);
Guennadi Liakhovetski7a1cd9a2011-08-18 16:55:27 +0200322 }
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000323}
324
Guennadi Liakhovetski67eacc12013-06-18 18:16:57 +0200325/*
326 * Find a slave channel configuration from the contoller list by either a slave
327 * ID in the non-DT case, or by a MID/RID value in the DT case
328 */
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200329static const struct sh_dmae_slave_config *dmae_find_slave(
Guennadi Liakhovetski67eacc12013-06-18 18:16:57 +0200330 struct sh_dmae_chan *sh_chan, int match)
Guennadi Liakhovetskicfefe992010-02-03 14:46:41 +0000331{
Kuninori Morimotoc4e0dd72011-06-16 05:08:09 +0000332 struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
Guennadi Liakhovetski2833c472013-08-02 16:18:09 +0200333 const struct sh_dmae_pdata *pdata = shdev->pdata;
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200334 const struct sh_dmae_slave_config *cfg;
Guennadi Liakhovetskicfefe992010-02-03 14:46:41 +0000335 int i;
336
Guennadi Liakhovetski67eacc12013-06-18 18:16:57 +0200337 if (!sh_chan->shdma_chan.dev->of_node) {
338 if (match >= SH_DMA_SLAVE_NUMBER)
339 return NULL;
Guennadi Liakhovetskicfefe992010-02-03 14:46:41 +0000340
Guennadi Liakhovetski67eacc12013-06-18 18:16:57 +0200341 for (i = 0, cfg = pdata->slave; i < pdata->slave_num; i++, cfg++)
342 if (cfg->slave_id == match)
343 return cfg;
344 } else {
345 for (i = 0, cfg = pdata->slave; i < pdata->slave_num; i++, cfg++)
346 if (cfg->mid_rid == match) {
Guennadi Liakhovetski4981c4d2013-08-02 16:50:36 +0200347 sh_chan->shdma_chan.slave_id = i;
Guennadi Liakhovetski67eacc12013-06-18 18:16:57 +0200348 return cfg;
349 }
350 }
Guennadi Liakhovetskicfefe992010-02-03 14:46:41 +0000351
352 return NULL;
353}
354
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200355static int sh_dmae_set_slave(struct shdma_chan *schan,
Guennadi Liakhovetski4981c4d2013-08-02 16:50:36 +0200356 int slave_id, dma_addr_t slave_addr, bool try)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000357{
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200358 struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
359 shdma_chan);
Guennadi Liakhovetskic2cdb7e2012-07-05 12:29:41 +0200360 const struct sh_dmae_slave_config *cfg = dmae_find_slave(sh_chan, slave_id);
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200361 if (!cfg)
Guennadi Liakhovetski7c1119b2012-11-28 06:49:47 +0000362 return -ENXIO;
Guennadi Liakhovetskicfefe992010-02-03 14:46:41 +0000363
Guennadi Liakhovetski4981c4d2013-08-02 16:50:36 +0200364 if (!try) {
Guennadi Liakhovetski1ff8df42012-07-05 12:29:42 +0200365 sh_chan->config = cfg;
Guennadi Liakhovetski4981c4d2013-08-02 16:50:36 +0200366 sh_chan->slave_addr = slave_addr ? : cfg->addr;
367 }
Linus Walleijc3635c72010-03-26 16:44:01 -0700368
369 return 0;
Guennadi Liakhovetskicfefe992010-02-03 14:46:41 +0000370}
371
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200372static void dmae_halt(struct sh_dmae_chan *sh_chan)
Guennadi Liakhovetski3542a112009-12-17 09:41:39 -0700373{
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200374 struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
375 u32 chcr = chcr_read(sh_chan);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000376
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200377 chcr &= ~(CHCR_DE | CHCR_TE | shdev->chcr_ie_bit);
378 chcr_write(sh_chan, chcr);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000379}
380
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200381static int sh_dmae_desc_setup(struct shdma_chan *schan,
382 struct shdma_desc *sdesc,
383 dma_addr_t src, dma_addr_t dst, size_t *len)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000384{
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200385 struct sh_dmae_desc *sh_desc = container_of(sdesc,
386 struct sh_dmae_desc, shdma_desc);
387
388 if (*len > schan->max_xfer_len)
389 *len = schan->max_xfer_len;
390
391 sh_desc->hw.sar = src;
392 sh_desc->hw.dar = dst;
393 sh_desc->hw.tcr = *len;
394
395 return 0;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000396}
397
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200398static void sh_dmae_halt(struct shdma_chan *schan)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000399{
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200400 struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
401 shdma_chan);
402 dmae_halt(sh_chan);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000403}
404
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200405static bool sh_dmae_chan_irq(struct shdma_chan *schan, int irq)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000406{
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200407 struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
408 shdma_chan);
Guennadi Liakhovetski7a1cd9a2011-08-18 16:55:27 +0200409
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200410 if (!(chcr_read(sh_chan) & CHCR_TE))
411 return false;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000412
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200413 /* DMA stop */
414 dmae_halt(sh_chan);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000415
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200416 return true;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000417}
418
Guennadi Liakhovetski4f46f8a2012-07-30 21:28:27 +0200419static size_t sh_dmae_get_partial(struct shdma_chan *schan,
420 struct shdma_desc *sdesc)
421{
422 struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
423 shdma_chan);
424 struct sh_dmae_desc *sh_desc = container_of(sdesc,
425 struct sh_dmae_desc, shdma_desc);
Kuninori Morimoto3c4d9272013-07-23 23:12:41 -0700426 return sh_desc->hw.tcr -
427 (sh_dmae_readl(sh_chan, TCR) << sh_chan->xmit_shift);
Guennadi Liakhovetski4f46f8a2012-07-30 21:28:27 +0200428}
429
Guennadi Liakhovetski2dc66662011-04-29 17:09:21 +0000430/* Called from error IRQ or NMI */
431static bool sh_dmae_reset(struct sh_dmae_device *shdev)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000432{
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200433 bool ret;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000434
Guennadi Liakhovetski47a4dc22010-02-11 16:50:05 +0000435 /* halt the dma controller */
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000436 sh_dmae_ctl_stop(shdev);
Guennadi Liakhovetski47a4dc22010-02-11 16:50:05 +0000437
438 /* We cannot detect, which channel caused the error, have to reset all */
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200439 ret = shdma_reset(&shdev->shdma_dev);
Paul Mundt03aa18f2010-12-17 19:16:10 +0900440
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000441 sh_dmae_rst(shdev);
Guennadi Liakhovetski47a4dc22010-02-11 16:50:05 +0000442
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200443 return ret;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000444}
Paul Mundt03aa18f2010-12-17 19:16:10 +0900445
Laurent Pinchart52d6a5e2013-12-11 13:43:05 +0100446#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARM)
Paul Mundt03aa18f2010-12-17 19:16:10 +0900447static irqreturn_t sh_dmae_err(int irq, void *data)
448{
Yoshihiro Shimodaff7690b2011-02-09 07:46:47 +0000449 struct sh_dmae_device *shdev = data;
450
Guennadi Liakhovetski2dc66662011-04-29 17:09:21 +0000451 if (!(dmaor_read(shdev) & DMAOR_AE))
Yoshihiro Shimodaff7690b2011-02-09 07:46:47 +0000452 return IRQ_NONE;
Guennadi Liakhovetski2dc66662011-04-29 17:09:21 +0000453
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200454 sh_dmae_reset(shdev);
Guennadi Liakhovetski2dc66662011-04-29 17:09:21 +0000455 return IRQ_HANDLED;
Paul Mundt03aa18f2010-12-17 19:16:10 +0900456}
Laurent Pinchart52d6a5e2013-12-11 13:43:05 +0100457#endif
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000458
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200459static bool sh_dmae_desc_completed(struct shdma_chan *schan,
460 struct shdma_desc *sdesc)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000461{
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200462 struct sh_dmae_chan *sh_chan = container_of(schan,
463 struct sh_dmae_chan, shdma_chan);
464 struct sh_dmae_desc *sh_desc = container_of(sdesc,
465 struct sh_dmae_desc, shdma_desc);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000466 u32 sar_buf = sh_dmae_readl(sh_chan, SAR);
Guennadi Liakhovetskicfefe992010-02-03 14:46:41 +0000467 u32 dar_buf = sh_dmae_readl(sh_chan, DAR);
Guennadi Liakhovetski86d61b32009-12-10 18:35:07 +0100468
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200469 return (sdesc->direction == DMA_DEV_TO_MEM &&
470 (sh_desc->hw.dar + sh_desc->hw.tcr) == dar_buf) ||
471 (sdesc->direction != DMA_DEV_TO_MEM &&
472 (sh_desc->hw.sar + sh_desc->hw.tcr) == sar_buf);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000473}
474
Paul Mundt03aa18f2010-12-17 19:16:10 +0900475static bool sh_dmae_nmi_notify(struct sh_dmae_device *shdev)
476{
Paul Mundt03aa18f2010-12-17 19:16:10 +0900477 /* Fast path out if NMIF is not asserted for this controller */
478 if ((dmaor_read(shdev) & DMAOR_NMIF) == 0)
479 return false;
480
Guennadi Liakhovetski2dc66662011-04-29 17:09:21 +0000481 return sh_dmae_reset(shdev);
Paul Mundt03aa18f2010-12-17 19:16:10 +0900482}
483
484static int sh_dmae_nmi_handler(struct notifier_block *self,
485 unsigned long cmd, void *data)
486{
487 struct sh_dmae_device *shdev;
488 int ret = NOTIFY_DONE;
489 bool triggered;
490
491 /*
492 * Only concern ourselves with NMI events.
493 *
494 * Normally we would check the die chain value, but as this needs
495 * to be architecture independent, check for NMI context instead.
496 */
497 if (!in_nmi())
498 return NOTIFY_DONE;
499
500 rcu_read_lock();
501 list_for_each_entry_rcu(shdev, &sh_dmae_devices, node) {
502 /*
503 * Only stop if one of the controllers has NMIF asserted,
504 * we do not want to interfere with regular address error
505 * handling or NMI events that don't concern the DMACs.
506 */
507 triggered = sh_dmae_nmi_notify(shdev);
508 if (triggered == true)
509 ret = NOTIFY_OK;
510 }
511 rcu_read_unlock();
512
513 return ret;
514}
515
516static struct notifier_block sh_dmae_nmi_notifier __read_mostly = {
517 .notifier_call = sh_dmae_nmi_handler,
518
519 /* Run before NMI debug handler and KGDB */
520 .priority = 1,
521};
522
Bill Pemberton463a1f82012-11-19 13:22:55 -0500523static int sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id,
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000524 int irq, unsigned long flags)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000525{
Guennadi Liakhovetski5bac9422010-04-21 15:36:49 +0000526 const struct sh_dmae_channel *chan_pdata = &shdev->pdata->channel[id];
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200527 struct shdma_dev *sdev = &shdev->shdma_dev;
528 struct platform_device *pdev = to_platform_device(sdev->dma_dev.dev);
529 struct sh_dmae_chan *sh_chan;
530 struct shdma_chan *schan;
531 int err;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000532
Guennadi Liakhovetskic1c63a12013-07-02 17:45:55 +0200533 sh_chan = devm_kzalloc(sdev->dma_dev.dev, sizeof(struct sh_dmae_chan),
534 GFP_KERNEL);
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200535 if (!sh_chan) {
536 dev_err(sdev->dma_dev.dev,
Guennadi Liakhovetski86d61b32009-12-10 18:35:07 +0100537 "No free memory for allocating dma channels!\n");
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000538 return -ENOMEM;
539 }
540
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200541 schan = &sh_chan->shdma_chan;
542 schan->max_xfer_len = SH_DMA_TCR_MAX + 1;
Guennadi Liakhovetski7a1cd9a2011-08-18 16:55:27 +0200543
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200544 shdma_chan_probe(sdev, schan, id);
Guennadi Liakhovetski8b1935e2010-02-11 16:50:14 +0000545
Guennadi Liakhovetski115357e2013-07-02 17:46:01 +0200546 sh_chan->base = shdev->chan_reg + chan_pdata->offset;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000547
548 /* set up channel irq */
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200549 if (pdev->id >= 0)
550 snprintf(sh_chan->dev_id, sizeof(sh_chan->dev_id),
551 "sh-dmae%d.%d", pdev->id, id);
552 else
553 snprintf(sh_chan->dev_id, sizeof(sh_chan->dev_id),
554 "sh-dma%d", id);
555
556 err = shdma_request_irq(schan, irq, flags, sh_chan->dev_id);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000557 if (err) {
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200558 dev_err(sdev->dma_dev.dev,
559 "DMA channel %d request_irq error %d\n",
560 id, err);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000561 goto err_no_irq;
562 }
563
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200564 shdev->chan[id] = sh_chan;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000565 return 0;
566
567err_no_irq:
568 /* remove from dmaengine device node */
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200569 shdma_chan_remove(schan);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000570 return err;
571}
572
573static void sh_dmae_chan_remove(struct sh_dmae_device *shdev)
574{
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200575 struct dma_device *dma_dev = &shdev->shdma_dev.dma_dev;
576 struct shdma_chan *schan;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000577 int i;
578
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200579 shdma_for_each_chan(schan, &shdev->shdma_dev, i) {
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200580 BUG_ON(!schan);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000581
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200582 shdma_chan_remove(schan);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000583 }
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200584 dma_dev->chancnt = 0;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000585}
586
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200587static void sh_dmae_shutdown(struct platform_device *pdev)
588{
589 struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
590 sh_dmae_ctl_stop(shdev);
591}
592
593static int sh_dmae_runtime_suspend(struct device *dev)
594{
595 return 0;
596}
597
598static int sh_dmae_runtime_resume(struct device *dev)
599{
600 struct sh_dmae_device *shdev = dev_get_drvdata(dev);
601
602 return sh_dmae_rst(shdev);
603}
604
605#ifdef CONFIG_PM
606static int sh_dmae_suspend(struct device *dev)
607{
608 return 0;
609}
610
611static int sh_dmae_resume(struct device *dev)
612{
613 struct sh_dmae_device *shdev = dev_get_drvdata(dev);
614 int i, ret;
615
616 ret = sh_dmae_rst(shdev);
617 if (ret < 0)
618 dev_err(dev, "Failed to reset!\n");
619
620 for (i = 0; i < shdev->pdata->channel_num; i++) {
621 struct sh_dmae_chan *sh_chan = shdev->chan[i];
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200622
623 if (!sh_chan->shdma_chan.desc_num)
624 continue;
625
Guennadi Liakhovetskic2cdb7e2012-07-05 12:29:41 +0200626 if (sh_chan->shdma_chan.slave_id >= 0) {
Guennadi Liakhovetskiecf90fb2012-07-05 12:29:40 +0200627 const struct sh_dmae_slave_config *cfg = sh_chan->config;
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200628 dmae_set_dmars(sh_chan, cfg->mid_rid);
629 dmae_set_chcr(sh_chan, cfg->chcr);
630 } else {
631 dmae_init(sh_chan);
632 }
633 }
634
635 return 0;
636}
637#else
638#define sh_dmae_suspend NULL
639#define sh_dmae_resume NULL
640#endif
641
Laurent Pinchart51455ec2013-12-11 13:43:06 +0100642static const struct dev_pm_ops sh_dmae_pm = {
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200643 .suspend = sh_dmae_suspend,
644 .resume = sh_dmae_resume,
645 .runtime_suspend = sh_dmae_runtime_suspend,
646 .runtime_resume = sh_dmae_runtime_resume,
647};
648
649static dma_addr_t sh_dmae_slave_addr(struct shdma_chan *schan)
650{
Guennadi Liakhovetskiecf90fb2012-07-05 12:29:40 +0200651 struct sh_dmae_chan *sh_chan = container_of(schan,
652 struct sh_dmae_chan, shdma_chan);
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200653
654 /*
Guennadi Liakhovetskiecf90fb2012-07-05 12:29:40 +0200655 * Implicit BUG_ON(!sh_chan->config)
656 * This is an exclusive slave DMA operation, may only be called after a
657 * successful slave configuration.
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200658 */
Guennadi Liakhovetski4981c4d2013-08-02 16:50:36 +0200659 return sh_chan->slave_addr;
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200660}
661
662static struct shdma_desc *sh_dmae_embedded_desc(void *buf, int i)
663{
664 return &((struct sh_dmae_desc *)buf)[i].shdma_desc;
665}
666
667static const struct shdma_ops sh_dmae_shdma_ops = {
668 .desc_completed = sh_dmae_desc_completed,
669 .halt_channel = sh_dmae_halt,
670 .channel_busy = sh_dmae_channel_busy,
671 .slave_addr = sh_dmae_slave_addr,
672 .desc_setup = sh_dmae_desc_setup,
673 .set_slave = sh_dmae_set_slave,
674 .setup_xfer = sh_dmae_setup_xfer,
675 .start_xfer = sh_dmae_start_xfer,
676 .embedded_desc = sh_dmae_embedded_desc,
677 .chan_irq = sh_dmae_chan_irq,
Guennadi Liakhovetski4f46f8a2012-07-30 21:28:27 +0200678 .get_partial = sh_dmae_get_partial,
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200679};
680
Guennadi Liakhovetski4981c4d2013-08-02 16:50:36 +0200681static const struct of_device_id sh_dmae_of_match[] = {
Guennadi Liakhovetski1e696532013-08-02 16:50:39 +0200682 {.compatible = "renesas,shdma-r8a73a4", .data = r8a73a4_shdma_devid,},
Guennadi Liakhovetski4981c4d2013-08-02 16:50:36 +0200683 {}
684};
685MODULE_DEVICE_TABLE(of, sh_dmae_of_match);
686
Bill Pemberton463a1f82012-11-19 13:22:55 -0500687static int sh_dmae_probe(struct platform_device *pdev)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000688{
Guennadi Liakhovetski4981c4d2013-08-02 16:50:36 +0200689 const struct sh_dmae_pdata *pdata;
Laurent Pinchart52d6a5e2013-12-11 13:43:05 +0100690 unsigned long chan_flag[SH_DMAE_MAX_CHANNELS] = {};
691 int chan_irq[SH_DMAE_MAX_CHANNELS];
692#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARM)
693 unsigned long irqflags = 0;
694 int errirq;
695#endif
Magnus Damm300e5f92011-05-24 10:31:20 +0000696 int err, i, irq_cnt = 0, irqres = 0, irq_cap = 0;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000697 struct sh_dmae_device *shdev;
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200698 struct dma_device *dma_dev;
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000699 struct resource *chan, *dmars, *errirq_res, *chanirq_res;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000700
Guennadi Liakhovetski4981c4d2013-08-02 16:50:36 +0200701 if (pdev->dev.of_node)
702 pdata = of_match_device(sh_dmae_of_match, &pdev->dev)->data;
703 else
Vinod Koul265d9c62013-09-02 17:42:35 +0530704 pdata = dev_get_platdata(&pdev->dev);
Guennadi Liakhovetski4981c4d2013-08-02 16:50:36 +0200705
Dan Williams56adf7e2009-11-22 12:10:10 -0700706 /* get platform data */
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000707 if (!pdata || !pdata->channel_num)
Dan Williams56adf7e2009-11-22 12:10:10 -0700708 return -ENODEV;
709
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000710 chan = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Magnus Damm26fc02a2011-05-24 10:31:12 +0000711 /* DMARS area is optional */
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000712 dmars = platform_get_resource(pdev, IORESOURCE_MEM, 1);
713 /*
714 * IRQ resources:
715 * 1. there always must be at least one IRQ IO-resource. On SH4 it is
716 * the error IRQ, in which case it is the only IRQ in this resource:
717 * start == end. If it is the only IRQ resource, all channels also
718 * use the same IRQ.
719 * 2. DMA channel IRQ resources can be specified one per resource or in
720 * ranges (start != end)
721 * 3. iff all events (channels and, optionally, error) on this
722 * controller use the same IRQ, only one IRQ resource can be
723 * specified, otherwise there must be one IRQ per channel, even if
724 * some of them are equal
725 * 4. if all IRQs on this controller are equal or if some specific IRQs
726 * specify IORESOURCE_IRQ_SHAREABLE in their resources, they will be
727 * requested with the IRQF_SHARED flag
728 */
729 errirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
730 if (!chan || !errirq_res)
731 return -ENODEV;
732
Guennadi Liakhovetskic1c63a12013-07-02 17:45:55 +0200733 shdev = devm_kzalloc(&pdev->dev, sizeof(struct sh_dmae_device),
734 GFP_KERNEL);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000735 if (!shdev) {
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000736 dev_err(&pdev->dev, "Not enough memory\n");
Guennadi Liakhovetskic1c63a12013-07-02 17:45:55 +0200737 return -ENOMEM;
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000738 }
739
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200740 dma_dev = &shdev->shdma_dev.dma_dev;
741
Guennadi Liakhovetskic1c63a12013-07-02 17:45:55 +0200742 shdev->chan_reg = devm_ioremap_resource(&pdev->dev, chan);
743 if (IS_ERR(shdev->chan_reg))
744 return PTR_ERR(shdev->chan_reg);
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000745 if (dmars) {
Guennadi Liakhovetskic1c63a12013-07-02 17:45:55 +0200746 shdev->dmars = devm_ioremap_resource(&pdev->dev, dmars);
747 if (IS_ERR(shdev->dmars))
748 return PTR_ERR(shdev->dmars);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000749 }
750
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200751 if (!pdata->slave_only)
752 dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
753 if (pdata->slave && pdata->slave_num)
754 dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
755
756 /* Default transfer size of 32 bytes requires 32-byte alignment */
757 dma_dev->copy_align = LOG2_DEFAULT_XFER_SIZE;
758
759 shdev->shdma_dev.ops = &sh_dmae_shdma_ops;
760 shdev->shdma_dev.desc_size = sizeof(struct sh_dmae_desc);
761 err = shdma_init(&pdev->dev, &shdev->shdma_dev,
762 pdata->channel_num);
763 if (err < 0)
764 goto eshdma;
765
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000766 /* platform data */
Guennadi Liakhovetskifa743262013-06-06 17:37:13 +0200767 shdev->pdata = pdata;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000768
Kuninori Morimoto5899a722011-06-17 08:20:40 +0000769 if (pdata->chcr_offset)
770 shdev->chcr_offset = pdata->chcr_offset;
771 else
772 shdev->chcr_offset = CHCR;
773
Kuninori Morimoto67c62692011-06-17 08:20:51 +0000774 if (pdata->chcr_ie_bit)
775 shdev->chcr_ie_bit = pdata->chcr_ie_bit;
776 else
777 shdev->chcr_ie_bit = CHCR_IE;
778
Paul Mundt5c2de442011-05-31 15:53:03 +0900779 platform_set_drvdata(pdev, shdev);
780
Guennadi Liakhovetski20f2a3b2010-02-11 16:50:18 +0000781 pm_runtime_enable(&pdev->dev);
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200782 err = pm_runtime_get_sync(&pdev->dev);
783 if (err < 0)
784 dev_err(&pdev->dev, "%s(): GET = %d\n", __func__, err);
Guennadi Liakhovetski20f2a3b2010-02-11 16:50:18 +0000785
Guennadi Liakhovetski31705e22011-05-02 07:59:02 +0000786 spin_lock_irq(&sh_dmae_lock);
Paul Mundt03aa18f2010-12-17 19:16:10 +0900787 list_add_tail_rcu(&shdev->node, &sh_dmae_devices);
Guennadi Liakhovetski31705e22011-05-02 07:59:02 +0000788 spin_unlock_irq(&sh_dmae_lock);
Paul Mundt03aa18f2010-12-17 19:16:10 +0900789
Guennadi Liakhovetski2dc66662011-04-29 17:09:21 +0000790 /* reset dma controller - only needed as a test */
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000791 err = sh_dmae_rst(shdev);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000792 if (err)
793 goto rst_err;
794
Magnus Damm927a7c92010-03-19 04:47:19 +0000795#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000796 chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
797
798 if (!chanirq_res)
799 chanirq_res = errirq_res;
800 else
801 irqres++;
802
803 if (chanirq_res == errirq_res ||
804 (errirq_res->flags & IORESOURCE_BITS) == IORESOURCE_IRQ_SHAREABLE)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000805 irqflags = IRQF_SHARED;
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000806
807 errirq = errirq_res->start;
808
Guennadi Liakhovetskic1c63a12013-07-02 17:45:55 +0200809 err = devm_request_irq(&pdev->dev, errirq, sh_dmae_err, irqflags,
810 "DMAC Address Error", shdev);
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000811 if (err) {
812 dev_err(&pdev->dev,
813 "DMA failed requesting irq #%d, error %d\n",
814 errirq, err);
815 goto eirq_err;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000816 }
817
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000818#else
819 chanirq_res = errirq_res;
Magnus Damm927a7c92010-03-19 04:47:19 +0000820#endif /* CONFIG_CPU_SH4 || CONFIG_ARCH_SHMOBILE */
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000821
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000822 if (chanirq_res->start == chanirq_res->end &&
823 !platform_get_resource(pdev, IORESOURCE_IRQ, 1)) {
824 /* Special case - all multiplexed */
825 for (; irq_cnt < pdata->channel_num; irq_cnt++) {
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200826 if (irq_cnt < SH_DMAE_MAX_CHANNELS) {
Magnus Damm300e5f92011-05-24 10:31:20 +0000827 chan_irq[irq_cnt] = chanirq_res->start;
828 chan_flag[irq_cnt] = IRQF_SHARED;
829 } else {
830 irq_cap = 1;
831 break;
832 }
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000833 }
834 } else {
835 do {
836 for (i = chanirq_res->start; i <= chanirq_res->end; i++) {
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200837 if (irq_cnt >= SH_DMAE_MAX_CHANNELS) {
Magnus Dammdcee0bb2011-06-09 06:35:08 +0000838 irq_cap = 1;
839 break;
840 }
841
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000842 if ((errirq_res->flags & IORESOURCE_BITS) ==
843 IORESOURCE_IRQ_SHAREABLE)
844 chan_flag[irq_cnt] = IRQF_SHARED;
845 else
Michael Opdenacker174b5372013-10-13 07:10:51 +0200846 chan_flag[irq_cnt] = 0;
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000847 dev_dbg(&pdev->dev,
848 "Found IRQ %d for channel %d\n",
849 i, irq_cnt);
850 chan_irq[irq_cnt++] = i;
Magnus Damm300e5f92011-05-24 10:31:20 +0000851 }
852
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200853 if (irq_cnt >= SH_DMAE_MAX_CHANNELS)
Magnus Damm300e5f92011-05-24 10:31:20 +0000854 break;
Magnus Dammdcee0bb2011-06-09 06:35:08 +0000855
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000856 chanirq_res = platform_get_resource(pdev,
857 IORESOURCE_IRQ, ++irqres);
858 } while (irq_cnt < pdata->channel_num && chanirq_res);
859 }
860
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000861 /* Create DMA Channel */
Magnus Damm300e5f92011-05-24 10:31:20 +0000862 for (i = 0; i < irq_cnt; i++) {
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000863 err = sh_dmae_chan_probe(shdev, i, chan_irq[i], chan_flag[i]);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000864 if (err)
865 goto chan_probe_err;
866 }
867
Magnus Damm300e5f92011-05-24 10:31:20 +0000868 if (irq_cap)
869 dev_notice(&pdev->dev, "Attempting to register %d DMA "
870 "channels when a maximum of %d are supported.\n",
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200871 pdata->channel_num, SH_DMAE_MAX_CHANNELS);
Magnus Damm300e5f92011-05-24 10:31:20 +0000872
Guennadi Liakhovetski20f2a3b2010-02-11 16:50:18 +0000873 pm_runtime_put(&pdev->dev);
874
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200875 err = dma_async_device_register(&shdev->shdma_dev.dma_dev);
876 if (err < 0)
877 goto edmadevreg;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000878
879 return err;
880
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200881edmadevreg:
882 pm_runtime_get(&pdev->dev);
883
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000884chan_probe_err:
885 sh_dmae_chan_remove(shdev);
Magnus Damm300e5f92011-05-24 10:31:20 +0000886
Magnus Damm927a7c92010-03-19 04:47:19 +0000887#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000888eirq_err:
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000889#endif
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000890rst_err:
Guennadi Liakhovetski31705e22011-05-02 07:59:02 +0000891 spin_lock_irq(&sh_dmae_lock);
Paul Mundt03aa18f2010-12-17 19:16:10 +0900892 list_del_rcu(&shdev->node);
Guennadi Liakhovetski31705e22011-05-02 07:59:02 +0000893 spin_unlock_irq(&sh_dmae_lock);
Paul Mundt03aa18f2010-12-17 19:16:10 +0900894
Guennadi Liakhovetski20f2a3b2010-02-11 16:50:18 +0000895 pm_runtime_put(&pdev->dev);
Guennadi Liakhovetski467017b2011-04-29 17:09:25 +0000896 pm_runtime_disable(&pdev->dev);
897
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200898 shdma_cleanup(&shdev->shdma_dev);
899eshdma:
Guennadi Liakhovetski31705e22011-05-02 07:59:02 +0000900 synchronize_rcu();
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000901
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000902 return err;
903}
904
Greg Kroah-Hartman4bf27b82012-12-21 15:09:59 -0800905static int sh_dmae_remove(struct platform_device *pdev)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000906{
907 struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200908 struct dma_device *dma_dev = &shdev->shdma_dev.dma_dev;
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000909
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200910 dma_async_device_unregister(dma_dev);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000911
Guennadi Liakhovetski31705e22011-05-02 07:59:02 +0000912 spin_lock_irq(&sh_dmae_lock);
Paul Mundt03aa18f2010-12-17 19:16:10 +0900913 list_del_rcu(&shdev->node);
Guennadi Liakhovetski31705e22011-05-02 07:59:02 +0000914 spin_unlock_irq(&sh_dmae_lock);
Paul Mundt03aa18f2010-12-17 19:16:10 +0900915
Guennadi Liakhovetski20f2a3b2010-02-11 16:50:18 +0000916 pm_runtime_disable(&pdev->dev);
917
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200918 sh_dmae_chan_remove(shdev);
919 shdma_cleanup(&shdev->shdma_dev);
920
Guennadi Liakhovetski31705e22011-05-02 07:59:02 +0000921 synchronize_rcu();
Guennadi Liakhovetski027811b2010-02-11 16:50:10 +0000922
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000923 return 0;
924}
925
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000926static struct platform_driver sh_dmae_driver = {
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200927 .driver = {
Guennadi Liakhovetski7a5c1062010-05-21 15:28:51 +0000928 .owner = THIS_MODULE,
Guennadi Liakhovetski467017b2011-04-29 17:09:25 +0000929 .pm = &sh_dmae_pm,
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200930 .name = SH_DMAE_DRV_NAME,
Guennadi Liakhovetski67eacc12013-06-18 18:16:57 +0200931 .of_match_table = sh_dmae_of_match,
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000932 },
Bill Pembertona7d6e3e2012-11-19 13:20:04 -0500933 .remove = sh_dmae_remove,
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200934 .shutdown = sh_dmae_shutdown,
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000935};
936
937static int __init sh_dmae_init(void)
938{
Guennadi Liakhovetski661382f2011-01-06 17:04:50 +0000939 /* Wire up NMI handling */
940 int err = register_die_notifier(&sh_dmae_nmi_notifier);
941 if (err)
942 return err;
943
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000944 return platform_driver_probe(&sh_dmae_driver, sh_dmae_probe);
945}
946module_init(sh_dmae_init);
947
948static void __exit sh_dmae_exit(void)
949{
950 platform_driver_unregister(&sh_dmae_driver);
Guennadi Liakhovetski661382f2011-01-06 17:04:50 +0000951
952 unregister_die_notifier(&sh_dmae_nmi_notifier);
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000953}
954module_exit(sh_dmae_exit);
955
956MODULE_AUTHOR("Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>");
957MODULE_DESCRIPTION("Renesas SH DMA Engine driver");
958MODULE_LICENSE("GPL");
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +0200959MODULE_ALIAS("platform:" SH_DMAE_DRV_NAME);