blob: 4aeda56ce37279006a5cb8be93f9146d7e3d56d7 [file] [log] [blame]
Sascha Hauera547b812012-03-19 12:36:10 +01001#include <linux/kernel.h>
2#include <linux/clk.h>
3#include <linux/io.h>
4#include <linux/errno.h>
5#include <linux/delay.h>
6#include <linux/slab.h>
7#include <linux/err.h>
8
9#include <asm/div64.h>
10
11#include "clk.h"
12
13#define to_clk_pllv2(clk) (container_of(clk, struct clk_pllv2, clk))
14
15/* PLL Register Offsets */
16#define MXC_PLL_DP_CTL 0x00
17#define MXC_PLL_DP_CONFIG 0x04
18#define MXC_PLL_DP_OP 0x08
19#define MXC_PLL_DP_MFD 0x0C
20#define MXC_PLL_DP_MFN 0x10
21#define MXC_PLL_DP_MFNMINUS 0x14
22#define MXC_PLL_DP_MFNPLUS 0x18
23#define MXC_PLL_DP_HFS_OP 0x1C
24#define MXC_PLL_DP_HFS_MFD 0x20
25#define MXC_PLL_DP_HFS_MFN 0x24
26#define MXC_PLL_DP_MFN_TOGC 0x28
27#define MXC_PLL_DP_DESTAT 0x2c
28
29/* PLL Register Bit definitions */
30#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000
31#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
32#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12
33#define MXC_PLL_DP_CTL_ADE 0x800
34#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
35#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
36#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8
37#define MXC_PLL_DP_CTL_HFSM 0x80
38#define MXC_PLL_DP_CTL_PRE 0x40
39#define MXC_PLL_DP_CTL_UPEN 0x20
40#define MXC_PLL_DP_CTL_RST 0x10
41#define MXC_PLL_DP_CTL_RCP 0x8
42#define MXC_PLL_DP_CTL_PLM 0x4
43#define MXC_PLL_DP_CTL_BRM0 0x2
44#define MXC_PLL_DP_CTL_LRF 0x1
45
46#define MXC_PLL_DP_CONFIG_BIST 0x8
47#define MXC_PLL_DP_CONFIG_SJC_CE 0x4
48#define MXC_PLL_DP_CONFIG_AREN 0x2
49#define MXC_PLL_DP_CONFIG_LDREQ 0x1
50
51#define MXC_PLL_DP_OP_MFI_OFFSET 4
52#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4)
53#define MXC_PLL_DP_OP_PDF_OFFSET 0
54#define MXC_PLL_DP_OP_PDF_MASK 0xF
55
56#define MXC_PLL_DP_MFD_OFFSET 0
57#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF
58
59#define MXC_PLL_DP_MFN_OFFSET 0x0
60#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF
61
62#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17)
63#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16)
64#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
65#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF
66
67#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31)
68#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF
69
70#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */
71
72struct clk_pllv2 {
73 struct clk_hw hw;
74 void __iomem *base;
75};
76
Sascha Hauer9ca41bc2012-06-04 14:51:32 +020077static unsigned long __clk_pllv2_recalc_rate(unsigned long parent_rate,
78 u32 dp_ctl, u32 dp_op, u32 dp_mfd, u32 dp_mfn)
Sascha Hauera547b812012-03-19 12:36:10 +010079{
Martin Kepplinger53fdc8f2015-09-29 13:32:27 +020080 long mfi, mfn, mfd, pdf, ref_clk;
Sascha Hauer9ca41bc2012-06-04 14:51:32 +020081 unsigned long dbl;
Nicolas Pitre0d2681e2015-11-03 20:01:40 -050082 u64 temp;
Sascha Hauera547b812012-03-19 12:36:10 +010083
Sascha Hauera547b812012-03-19 12:36:10 +010084 dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
85
Sascha Hauera547b812012-03-19 12:36:10 +010086 pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
87 mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;
88 mfi = (mfi <= 5) ? 5 : mfi;
89 mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
Martin Kepplinger53fdc8f2015-09-29 13:32:27 +020090 mfn = dp_mfn & MXC_PLL_DP_MFN_MASK;
91 mfn = sign_extend32(mfn, 26);
Sascha Hauera547b812012-03-19 12:36:10 +010092
93 ref_clk = 2 * parent_rate;
94 if (dbl != 0)
95 ref_clk *= 2;
96
97 ref_clk /= (pdf + 1);
Martin Kepplinger53fdc8f2015-09-29 13:32:27 +020098 temp = (u64) ref_clk * abs(mfn);
Sascha Hauera547b812012-03-19 12:36:10 +010099 do_div(temp, mfd + 1);
100 if (mfn < 0)
Nicolas Pitre0d2681e2015-11-03 20:01:40 -0500101 temp = (ref_clk * mfi) - temp;
102 else
103 temp = (ref_clk * mfi) + temp;
Sascha Hauera547b812012-03-19 12:36:10 +0100104
105 return temp;
106}
107
Sascha Hauer9ca41bc2012-06-04 14:51:32 +0200108static unsigned long clk_pllv2_recalc_rate(struct clk_hw *hw,
Sascha Hauera547b812012-03-19 12:36:10 +0100109 unsigned long parent_rate)
110{
Sascha Hauer9ca41bc2012-06-04 14:51:32 +0200111 u32 dp_op, dp_mfd, dp_mfn, dp_ctl;
Sascha Hauera547b812012-03-19 12:36:10 +0100112 void __iomem *pllbase;
Sascha Hauer9ca41bc2012-06-04 14:51:32 +0200113 struct clk_pllv2 *pll = to_clk_pllv2(hw);
114
115 pllbase = pll->base;
116
117 dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
118 dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
119 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
120 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
121
122 return __clk_pllv2_recalc_rate(parent_rate, dp_ctl, dp_op, dp_mfd, dp_mfn);
123}
124
125static int __clk_pllv2_set_rate(unsigned long rate, unsigned long parent_rate,
126 u32 *dp_op, u32 *dp_mfd, u32 *dp_mfn)
127{
128 u32 reg;
Sascha Hauera547b812012-03-19 12:36:10 +0100129 long mfi, pdf, mfn, mfd = 999999;
Nicolas Pitre0d2681e2015-11-03 20:01:40 -0500130 u64 temp64;
Sascha Hauera547b812012-03-19 12:36:10 +0100131 unsigned long quad_parent_rate;
Sascha Hauera547b812012-03-19 12:36:10 +0100132
133 quad_parent_rate = 4 * parent_rate;
134 pdf = mfi = -1;
135 while (++pdf < 16 && mfi < 5)
136 mfi = rate * (pdf+1) / quad_parent_rate;
137 if (mfi > 15)
138 return -EINVAL;
139 pdf--;
140
Sascha Hauer9ca41bc2012-06-04 14:51:32 +0200141 temp64 = rate * (pdf + 1) - quad_parent_rate * mfi;
142 do_div(temp64, quad_parent_rate / 1000000);
Sascha Hauera547b812012-03-19 12:36:10 +0100143 mfn = (long)temp64;
144
Sascha Hauer9ca41bc2012-06-04 14:51:32 +0200145 reg = mfi << 4 | pdf;
146
147 *dp_op = reg;
148 *dp_mfd = mfd;
149 *dp_mfn = mfn;
150
151 return 0;
152}
153
154static int clk_pllv2_set_rate(struct clk_hw *hw, unsigned long rate,
155 unsigned long parent_rate)
156{
157 struct clk_pllv2 *pll = to_clk_pllv2(hw);
158 void __iomem *pllbase;
159 u32 dp_ctl, dp_op, dp_mfd, dp_mfn;
160 int ret;
161
162 pllbase = pll->base;
163
164
165 ret = __clk_pllv2_set_rate(rate, parent_rate, &dp_op, &dp_mfd, &dp_mfn);
166 if (ret)
167 return ret;
168
Sascha Hauera547b812012-03-19 12:36:10 +0100169 dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
170 /* use dpdck0_2 */
171 __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
Sascha Hauer6cc90d62012-06-04 12:21:21 +0200172
Sascha Hauer9ca41bc2012-06-04 14:51:32 +0200173 __raw_writel(dp_op, pllbase + MXC_PLL_DP_OP);
174 __raw_writel(dp_mfd, pllbase + MXC_PLL_DP_MFD);
175 __raw_writel(dp_mfn, pllbase + MXC_PLL_DP_MFN);
Sascha Hauera547b812012-03-19 12:36:10 +0100176
177 return 0;
178}
179
180static long clk_pllv2_round_rate(struct clk_hw *hw, unsigned long rate,
181 unsigned long *prate)
182{
Sascha Hauer9ca41bc2012-06-04 14:51:32 +0200183 u32 dp_op, dp_mfd, dp_mfn;
184
185 __clk_pllv2_set_rate(rate, *prate, &dp_op, &dp_mfd, &dp_mfn);
186 return __clk_pllv2_recalc_rate(*prate, MXC_PLL_DP_CTL_DPDCK0_2_EN,
187 dp_op, dp_mfd, dp_mfn);
Sascha Hauera547b812012-03-19 12:36:10 +0100188}
189
190static int clk_pllv2_prepare(struct clk_hw *hw)
191{
192 struct clk_pllv2 *pll = to_clk_pllv2(hw);
193 u32 reg;
194 void __iomem *pllbase;
195 int i = 0;
196
197 pllbase = pll->base;
198 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN;
199 __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
200
201 /* Wait for lock */
202 do {
203 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
204 if (reg & MXC_PLL_DP_CTL_LRF)
205 break;
206
207 udelay(1);
208 } while (++i < MAX_DPLL_WAIT_TRIES);
209
210 if (i == MAX_DPLL_WAIT_TRIES) {
211 pr_err("MX5: pll locking failed\n");
212 return -EINVAL;
213 }
214
215 return 0;
216}
217
218static void clk_pllv2_unprepare(struct clk_hw *hw)
219{
220 struct clk_pllv2 *pll = to_clk_pllv2(hw);
221 u32 reg;
222 void __iomem *pllbase;
223
224 pllbase = pll->base;
225 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN;
226 __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
227}
228
Fabio Estevam191f1622013-03-25 09:20:34 -0300229static struct clk_ops clk_pllv2_ops = {
Sascha Hauera547b812012-03-19 12:36:10 +0100230 .prepare = clk_pllv2_prepare,
231 .unprepare = clk_pllv2_unprepare,
232 .recalc_rate = clk_pllv2_recalc_rate,
233 .round_rate = clk_pllv2_round_rate,
234 .set_rate = clk_pllv2_set_rate,
235};
236
237struct clk *imx_clk_pllv2(const char *name, const char *parent,
238 void __iomem *base)
239{
240 struct clk_pllv2 *pll;
241 struct clk *clk;
242 struct clk_init_data init;
243
244 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
245 if (!pll)
246 return ERR_PTR(-ENOMEM);
247
248 pll->base = base;
249
250 init.name = name;
251 init.ops = &clk_pllv2_ops;
252 init.flags = 0;
253 init.parent_names = &parent;
254 init.num_parents = 1;
255
256 pll->hw.init = &init;
257
258 clk = clk_register(NULL, &pll->hw);
259 if (IS_ERR(clk))
260 kfree(pll);
261
262 return clk;
263}