Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 1 | /* |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 2 | * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 3 | * |
Paul Walmsley | 78183f3 | 2011-07-09 19:14:05 -0600 | [diff] [blame] | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 5 | * Paul Walmsley |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | * |
| 11 | * XXX handle crossbar/shared link difference for L3? |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 12 | * XXX these should be marked initdata for multi-OMAP kernels |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 13 | */ |
Tony Lindgren | ce491cf | 2009-10-20 09:40:47 -0700 | [diff] [blame] | 14 | #include <plat/omap_hwmod.h> |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 15 | #include <mach/irqs.h> |
Tony Lindgren | ce491cf | 2009-10-20 09:40:47 -0700 | [diff] [blame] | 16 | #include <plat/cpu.h> |
| 17 | #include <plat/dma.h> |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 18 | #include <plat/serial.h> |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 19 | #include <plat/i2c.h> |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 20 | #include <plat/gpio.h> |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 21 | #include <plat/mcspi.h> |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 22 | #include <plat/dmtimer.h> |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 23 | #include <plat/l3_2xxx.h> |
| 24 | #include <plat/l4_2xxx.h> |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 25 | |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 26 | #include "omap_hwmod_common_data.h" |
| 27 | |
Varadarajan, Charulatha | a714b9c | 2010-09-23 20:02:39 +0530 | [diff] [blame] | 28 | #include "cm-regbits-24xx.h" |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 29 | #include "prm-regbits-24xx.h" |
Paul Walmsley | ff2516f | 2010-12-21 15:39:15 -0700 | [diff] [blame] | 30 | #include "wd_timer.h" |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 31 | |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 32 | /* |
| 33 | * OMAP2420 hardware module integration data |
| 34 | * |
| 35 | * ALl of the data in this section should be autogeneratable from the |
| 36 | * TI hardware database or other technical documentation. Data that |
| 37 | * is driver-specific or driver-kernel integration-specific belongs |
| 38 | * elsewhere. |
| 39 | */ |
| 40 | |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 41 | static struct omap_hwmod omap2420_mpu_hwmod; |
Paul Walmsley | 08072ac | 2010-07-26 16:34:33 -0600 | [diff] [blame] | 42 | static struct omap_hwmod omap2420_iva_hwmod; |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 43 | static struct omap_hwmod omap2420_l3_main_hwmod; |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 44 | static struct omap_hwmod omap2420_l4_core_hwmod; |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 45 | static struct omap_hwmod omap2420_dss_core_hwmod; |
| 46 | static struct omap_hwmod omap2420_dss_dispc_hwmod; |
| 47 | static struct omap_hwmod omap2420_dss_rfbi_hwmod; |
| 48 | static struct omap_hwmod omap2420_dss_venc_hwmod; |
Varadarajan, Charulatha | a714b9c | 2010-09-23 20:02:39 +0530 | [diff] [blame] | 49 | static struct omap_hwmod omap2420_wd_timer2_hwmod; |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 50 | static struct omap_hwmod omap2420_gpio1_hwmod; |
| 51 | static struct omap_hwmod omap2420_gpio2_hwmod; |
| 52 | static struct omap_hwmod omap2420_gpio3_hwmod; |
| 53 | static struct omap_hwmod omap2420_gpio4_hwmod; |
G, Manjunath Kondaiah | 745685df9 | 2010-12-20 18:27:18 -0800 | [diff] [blame] | 54 | static struct omap_hwmod omap2420_dma_system_hwmod; |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 55 | static struct omap_hwmod omap2420_mcspi1_hwmod; |
| 56 | static struct omap_hwmod omap2420_mcspi2_hwmod; |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 57 | |
| 58 | /* L3 -> L4_CORE interface */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 59 | static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { |
| 60 | .master = &omap2420_l3_main_hwmod, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 61 | .slave = &omap2420_l4_core_hwmod, |
| 62 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 63 | }; |
| 64 | |
| 65 | /* MPU -> L3 interface */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 66 | static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = { |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 67 | .master = &omap2420_mpu_hwmod, |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 68 | .slave = &omap2420_l3_main_hwmod, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 69 | .user = OCP_USER_MPU, |
| 70 | }; |
| 71 | |
| 72 | /* Slave interfaces on the L3 interconnect */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 73 | static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = { |
| 74 | &omap2420_mpu__l3_main, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 75 | }; |
| 76 | |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 77 | /* DSS -> l3 */ |
| 78 | static struct omap_hwmod_ocp_if omap2420_dss__l3 = { |
| 79 | .master = &omap2420_dss_core_hwmod, |
| 80 | .slave = &omap2420_l3_main_hwmod, |
| 81 | .fw = { |
| 82 | .omap2 = { |
| 83 | .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, |
| 84 | .flags = OMAP_FIREWALL_L3, |
| 85 | } |
| 86 | }, |
| 87 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 88 | }; |
| 89 | |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 90 | /* Master interfaces on the L3 interconnect */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 91 | static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = { |
| 92 | &omap2420_l3_main__l4_core, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 93 | }; |
| 94 | |
| 95 | /* L3 */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 96 | static struct omap_hwmod omap2420_l3_main_hwmod = { |
Benoit Cousson | fa98347 | 2010-07-26 16:34:29 -0600 | [diff] [blame] | 97 | .name = "l3_main", |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 98 | .class = &l3_hwmod_class, |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 99 | .masters = omap2420_l3_main_masters, |
| 100 | .masters_cnt = ARRAY_SIZE(omap2420_l3_main_masters), |
| 101 | .slaves = omap2420_l3_main_slaves, |
| 102 | .slaves_cnt = ARRAY_SIZE(omap2420_l3_main_slaves), |
Kevin Hilman | 2eb1875 | 2010-07-26 16:34:28 -0600 | [diff] [blame] | 103 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 104 | .flags = HWMOD_NO_IDLEST, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 105 | }; |
| 106 | |
| 107 | static struct omap_hwmod omap2420_l4_wkup_hwmod; |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 108 | static struct omap_hwmod omap2420_uart1_hwmod; |
| 109 | static struct omap_hwmod omap2420_uart2_hwmod; |
| 110 | static struct omap_hwmod omap2420_uart3_hwmod; |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 111 | static struct omap_hwmod omap2420_i2c1_hwmod; |
| 112 | static struct omap_hwmod omap2420_i2c2_hwmod; |
Charulatha V | 3cb72fa | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 113 | static struct omap_hwmod omap2420_mcbsp1_hwmod; |
| 114 | static struct omap_hwmod omap2420_mcbsp2_hwmod; |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 115 | |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 116 | /* l4 core -> mcspi1 interface */ |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 117 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = { |
| 118 | .master = &omap2420_l4_core_hwmod, |
| 119 | .slave = &omap2420_mcspi1_hwmod, |
| 120 | .clk = "mcspi1_ick", |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 121 | .addr = omap2_mcspi1_addr_space, |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 122 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 123 | }; |
| 124 | |
| 125 | /* l4 core -> mcspi2 interface */ |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 126 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = { |
| 127 | .master = &omap2420_l4_core_hwmod, |
| 128 | .slave = &omap2420_mcspi2_hwmod, |
| 129 | .clk = "mcspi2_ick", |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 130 | .addr = omap2_mcspi2_addr_space, |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 131 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 132 | }; |
| 133 | |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 134 | /* L4_CORE -> L4_WKUP interface */ |
| 135 | static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { |
| 136 | .master = &omap2420_l4_core_hwmod, |
| 137 | .slave = &omap2420_l4_wkup_hwmod, |
| 138 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 139 | }; |
| 140 | |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 141 | /* L4 CORE -> UART1 interface */ |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 142 | static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { |
| 143 | .master = &omap2420_l4_core_hwmod, |
| 144 | .slave = &omap2420_uart1_hwmod, |
| 145 | .clk = "uart1_ick", |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 146 | .addr = omap2xxx_uart1_addr_space, |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 147 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 148 | }; |
| 149 | |
| 150 | /* L4 CORE -> UART2 interface */ |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 151 | static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { |
| 152 | .master = &omap2420_l4_core_hwmod, |
| 153 | .slave = &omap2420_uart2_hwmod, |
| 154 | .clk = "uart2_ick", |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 155 | .addr = omap2xxx_uart2_addr_space, |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 156 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 157 | }; |
| 158 | |
| 159 | /* L4 PER -> UART3 interface */ |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 160 | static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { |
| 161 | .master = &omap2420_l4_core_hwmod, |
| 162 | .slave = &omap2420_uart3_hwmod, |
| 163 | .clk = "uart3_ick", |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 164 | .addr = omap2xxx_uart3_addr_space, |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 165 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 166 | }; |
| 167 | |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 168 | /* L4 CORE -> I2C1 interface */ |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 169 | static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = { |
| 170 | .master = &omap2420_l4_core_hwmod, |
| 171 | .slave = &omap2420_i2c1_hwmod, |
| 172 | .clk = "i2c1_ick", |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 173 | .addr = omap2_i2c1_addr_space, |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 174 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 175 | }; |
| 176 | |
| 177 | /* L4 CORE -> I2C2 interface */ |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 178 | static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = { |
| 179 | .master = &omap2420_l4_core_hwmod, |
| 180 | .slave = &omap2420_i2c2_hwmod, |
| 181 | .clk = "i2c2_ick", |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 182 | .addr = omap2_i2c2_addr_space, |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 183 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 184 | }; |
| 185 | |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 186 | /* Slave interfaces on the L4_CORE interconnect */ |
| 187 | static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = { |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 188 | &omap2420_l3_main__l4_core, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 189 | }; |
| 190 | |
| 191 | /* Master interfaces on the L4_CORE interconnect */ |
| 192 | static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = { |
| 193 | &omap2420_l4_core__l4_wkup, |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 194 | &omap2_l4_core__uart1, |
| 195 | &omap2_l4_core__uart2, |
| 196 | &omap2_l4_core__uart3, |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 197 | &omap2420_l4_core__i2c1, |
| 198 | &omap2420_l4_core__i2c2 |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 199 | }; |
| 200 | |
| 201 | /* L4 CORE */ |
| 202 | static struct omap_hwmod omap2420_l4_core_hwmod = { |
Benoit Cousson | fa98347 | 2010-07-26 16:34:29 -0600 | [diff] [blame] | 203 | .name = "l4_core", |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 204 | .class = &l4_hwmod_class, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 205 | .masters = omap2420_l4_core_masters, |
| 206 | .masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters), |
| 207 | .slaves = omap2420_l4_core_slaves, |
| 208 | .slaves_cnt = ARRAY_SIZE(omap2420_l4_core_slaves), |
Kevin Hilman | 2eb1875 | 2010-07-26 16:34:28 -0600 | [diff] [blame] | 209 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 210 | .flags = HWMOD_NO_IDLEST, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 211 | }; |
| 212 | |
| 213 | /* Slave interfaces on the L4_WKUP interconnect */ |
| 214 | static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = { |
| 215 | &omap2420_l4_core__l4_wkup, |
| 216 | }; |
| 217 | |
| 218 | /* Master interfaces on the L4_WKUP interconnect */ |
| 219 | static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = { |
| 220 | }; |
| 221 | |
| 222 | /* L4 WKUP */ |
| 223 | static struct omap_hwmod omap2420_l4_wkup_hwmod = { |
Benoit Cousson | fa98347 | 2010-07-26 16:34:29 -0600 | [diff] [blame] | 224 | .name = "l4_wkup", |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 225 | .class = &l4_hwmod_class, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 226 | .masters = omap2420_l4_wkup_masters, |
| 227 | .masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters), |
| 228 | .slaves = omap2420_l4_wkup_slaves, |
| 229 | .slaves_cnt = ARRAY_SIZE(omap2420_l4_wkup_slaves), |
Kevin Hilman | 2eb1875 | 2010-07-26 16:34:28 -0600 | [diff] [blame] | 230 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 231 | .flags = HWMOD_NO_IDLEST, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 232 | }; |
| 233 | |
| 234 | /* Master interfaces on the MPU device */ |
| 235 | static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = { |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 236 | &omap2420_mpu__l3_main, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 237 | }; |
| 238 | |
| 239 | /* MPU */ |
| 240 | static struct omap_hwmod omap2420_mpu_hwmod = { |
Benoit Cousson | 5c2c029 | 2010-05-20 12:31:10 -0600 | [diff] [blame] | 241 | .name = "mpu", |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 242 | .class = &mpu_hwmod_class, |
Paul Walmsley | 50ebdac | 2010-02-22 22:09:31 -0700 | [diff] [blame] | 243 | .main_clk = "mpu_ck", |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 244 | .masters = omap2420_mpu_masters, |
| 245 | .masters_cnt = ARRAY_SIZE(omap2420_mpu_masters), |
| 246 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 247 | }; |
| 248 | |
Paul Walmsley | 08072ac | 2010-07-26 16:34:33 -0600 | [diff] [blame] | 249 | /* |
| 250 | * IVA1 interface data |
| 251 | */ |
| 252 | |
| 253 | /* IVA <- L3 interface */ |
| 254 | static struct omap_hwmod_ocp_if omap2420_l3__iva = { |
| 255 | .master = &omap2420_l3_main_hwmod, |
| 256 | .slave = &omap2420_iva_hwmod, |
| 257 | .clk = "iva1_ifck", |
| 258 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 259 | }; |
| 260 | |
| 261 | static struct omap_hwmod_ocp_if *omap2420_iva_masters[] = { |
| 262 | &omap2420_l3__iva, |
| 263 | }; |
| 264 | |
| 265 | /* |
| 266 | * IVA2 (IVA2) |
| 267 | */ |
| 268 | |
| 269 | static struct omap_hwmod omap2420_iva_hwmod = { |
| 270 | .name = "iva", |
| 271 | .class = &iva_hwmod_class, |
| 272 | .masters = omap2420_iva_masters, |
| 273 | .masters_cnt = ARRAY_SIZE(omap2420_iva_masters), |
| 274 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
| 275 | }; |
| 276 | |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 277 | /* Timer Common */ |
| 278 | static struct omap_hwmod_class_sysconfig omap2420_timer_sysc = { |
| 279 | .rev_offs = 0x0000, |
| 280 | .sysc_offs = 0x0010, |
| 281 | .syss_offs = 0x0014, |
| 282 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | |
| 283 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
| 284 | SYSC_HAS_AUTOIDLE), |
| 285 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 286 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 287 | }; |
| 288 | |
| 289 | static struct omap_hwmod_class omap2420_timer_hwmod_class = { |
| 290 | .name = "timer", |
| 291 | .sysc = &omap2420_timer_sysc, |
| 292 | .rev = OMAP_TIMER_IP_VERSION_1, |
| 293 | }; |
| 294 | |
| 295 | /* timer1 */ |
| 296 | static struct omap_hwmod omap2420_timer1_hwmod; |
| 297 | static struct omap_hwmod_irq_info omap2420_timer1_mpu_irqs[] = { |
| 298 | { .irq = 37, }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame^] | 299 | { .irq = -1 } |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 300 | }; |
| 301 | |
| 302 | static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = { |
| 303 | { |
| 304 | .pa_start = 0x48028000, |
| 305 | .pa_end = 0x48028000 + SZ_1K - 1, |
| 306 | .flags = ADDR_TYPE_RT |
| 307 | }, |
Paul Walmsley | 78183f3 | 2011-07-09 19:14:05 -0600 | [diff] [blame] | 308 | { } |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 309 | }; |
| 310 | |
| 311 | /* l4_wkup -> timer1 */ |
| 312 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { |
| 313 | .master = &omap2420_l4_wkup_hwmod, |
| 314 | .slave = &omap2420_timer1_hwmod, |
| 315 | .clk = "gpt1_ick", |
| 316 | .addr = omap2420_timer1_addrs, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 317 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 318 | }; |
| 319 | |
| 320 | /* timer1 slave port */ |
| 321 | static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = { |
| 322 | &omap2420_l4_wkup__timer1, |
| 323 | }; |
| 324 | |
| 325 | /* timer1 hwmod */ |
| 326 | static struct omap_hwmod omap2420_timer1_hwmod = { |
| 327 | .name = "timer1", |
| 328 | .mpu_irqs = omap2420_timer1_mpu_irqs, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 329 | .main_clk = "gpt1_fck", |
| 330 | .prcm = { |
| 331 | .omap2 = { |
| 332 | .prcm_reg_id = 1, |
| 333 | .module_bit = OMAP24XX_EN_GPT1_SHIFT, |
| 334 | .module_offs = WKUP_MOD, |
| 335 | .idlest_reg_id = 1, |
| 336 | .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, |
| 337 | }, |
| 338 | }, |
| 339 | .slaves = omap2420_timer1_slaves, |
| 340 | .slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves), |
| 341 | .class = &omap2420_timer_hwmod_class, |
| 342 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
| 343 | }; |
| 344 | |
| 345 | /* timer2 */ |
| 346 | static struct omap_hwmod omap2420_timer2_hwmod; |
| 347 | static struct omap_hwmod_irq_info omap2420_timer2_mpu_irqs[] = { |
| 348 | { .irq = 38, }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame^] | 349 | { .irq = -1 } |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 350 | }; |
| 351 | |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 352 | |
| 353 | /* l4_core -> timer2 */ |
| 354 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = { |
| 355 | .master = &omap2420_l4_core_hwmod, |
| 356 | .slave = &omap2420_timer2_hwmod, |
| 357 | .clk = "gpt2_ick", |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 358 | .addr = omap2xxx_timer2_addrs, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 359 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 360 | }; |
| 361 | |
| 362 | /* timer2 slave port */ |
| 363 | static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = { |
| 364 | &omap2420_l4_core__timer2, |
| 365 | }; |
| 366 | |
| 367 | /* timer2 hwmod */ |
| 368 | static struct omap_hwmod omap2420_timer2_hwmod = { |
| 369 | .name = "timer2", |
| 370 | .mpu_irqs = omap2420_timer2_mpu_irqs, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 371 | .main_clk = "gpt2_fck", |
| 372 | .prcm = { |
| 373 | .omap2 = { |
| 374 | .prcm_reg_id = 1, |
| 375 | .module_bit = OMAP24XX_EN_GPT2_SHIFT, |
| 376 | .module_offs = CORE_MOD, |
| 377 | .idlest_reg_id = 1, |
| 378 | .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, |
| 379 | }, |
| 380 | }, |
| 381 | .slaves = omap2420_timer2_slaves, |
| 382 | .slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves), |
| 383 | .class = &omap2420_timer_hwmod_class, |
| 384 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
| 385 | }; |
| 386 | |
| 387 | /* timer3 */ |
| 388 | static struct omap_hwmod omap2420_timer3_hwmod; |
| 389 | static struct omap_hwmod_irq_info omap2420_timer3_mpu_irqs[] = { |
| 390 | { .irq = 39, }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame^] | 391 | { .irq = -1 } |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 392 | }; |
| 393 | |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 394 | /* l4_core -> timer3 */ |
| 395 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = { |
| 396 | .master = &omap2420_l4_core_hwmod, |
| 397 | .slave = &omap2420_timer3_hwmod, |
| 398 | .clk = "gpt3_ick", |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 399 | .addr = omap2xxx_timer3_addrs, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 400 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 401 | }; |
| 402 | |
| 403 | /* timer3 slave port */ |
| 404 | static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = { |
| 405 | &omap2420_l4_core__timer3, |
| 406 | }; |
| 407 | |
| 408 | /* timer3 hwmod */ |
| 409 | static struct omap_hwmod omap2420_timer3_hwmod = { |
| 410 | .name = "timer3", |
| 411 | .mpu_irqs = omap2420_timer3_mpu_irqs, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 412 | .main_clk = "gpt3_fck", |
| 413 | .prcm = { |
| 414 | .omap2 = { |
| 415 | .prcm_reg_id = 1, |
| 416 | .module_bit = OMAP24XX_EN_GPT3_SHIFT, |
| 417 | .module_offs = CORE_MOD, |
| 418 | .idlest_reg_id = 1, |
| 419 | .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, |
| 420 | }, |
| 421 | }, |
| 422 | .slaves = omap2420_timer3_slaves, |
| 423 | .slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves), |
| 424 | .class = &omap2420_timer_hwmod_class, |
| 425 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
| 426 | }; |
| 427 | |
| 428 | /* timer4 */ |
| 429 | static struct omap_hwmod omap2420_timer4_hwmod; |
| 430 | static struct omap_hwmod_irq_info omap2420_timer4_mpu_irqs[] = { |
| 431 | { .irq = 40, }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame^] | 432 | { .irq = -1 } |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 433 | }; |
| 434 | |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 435 | /* l4_core -> timer4 */ |
| 436 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = { |
| 437 | .master = &omap2420_l4_core_hwmod, |
| 438 | .slave = &omap2420_timer4_hwmod, |
| 439 | .clk = "gpt4_ick", |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 440 | .addr = omap2xxx_timer4_addrs, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 441 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 442 | }; |
| 443 | |
| 444 | /* timer4 slave port */ |
| 445 | static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = { |
| 446 | &omap2420_l4_core__timer4, |
| 447 | }; |
| 448 | |
| 449 | /* timer4 hwmod */ |
| 450 | static struct omap_hwmod omap2420_timer4_hwmod = { |
| 451 | .name = "timer4", |
| 452 | .mpu_irqs = omap2420_timer4_mpu_irqs, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 453 | .main_clk = "gpt4_fck", |
| 454 | .prcm = { |
| 455 | .omap2 = { |
| 456 | .prcm_reg_id = 1, |
| 457 | .module_bit = OMAP24XX_EN_GPT4_SHIFT, |
| 458 | .module_offs = CORE_MOD, |
| 459 | .idlest_reg_id = 1, |
| 460 | .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, |
| 461 | }, |
| 462 | }, |
| 463 | .slaves = omap2420_timer4_slaves, |
| 464 | .slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves), |
| 465 | .class = &omap2420_timer_hwmod_class, |
| 466 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
| 467 | }; |
| 468 | |
| 469 | /* timer5 */ |
| 470 | static struct omap_hwmod omap2420_timer5_hwmod; |
| 471 | static struct omap_hwmod_irq_info omap2420_timer5_mpu_irqs[] = { |
| 472 | { .irq = 41, }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame^] | 473 | { .irq = -1 } |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 474 | }; |
| 475 | |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 476 | /* l4_core -> timer5 */ |
| 477 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = { |
| 478 | .master = &omap2420_l4_core_hwmod, |
| 479 | .slave = &omap2420_timer5_hwmod, |
| 480 | .clk = "gpt5_ick", |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 481 | .addr = omap2xxx_timer5_addrs, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 482 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 483 | }; |
| 484 | |
| 485 | /* timer5 slave port */ |
| 486 | static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = { |
| 487 | &omap2420_l4_core__timer5, |
| 488 | }; |
| 489 | |
| 490 | /* timer5 hwmod */ |
| 491 | static struct omap_hwmod omap2420_timer5_hwmod = { |
| 492 | .name = "timer5", |
| 493 | .mpu_irqs = omap2420_timer5_mpu_irqs, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 494 | .main_clk = "gpt5_fck", |
| 495 | .prcm = { |
| 496 | .omap2 = { |
| 497 | .prcm_reg_id = 1, |
| 498 | .module_bit = OMAP24XX_EN_GPT5_SHIFT, |
| 499 | .module_offs = CORE_MOD, |
| 500 | .idlest_reg_id = 1, |
| 501 | .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, |
| 502 | }, |
| 503 | }, |
| 504 | .slaves = omap2420_timer5_slaves, |
| 505 | .slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves), |
| 506 | .class = &omap2420_timer_hwmod_class, |
| 507 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
| 508 | }; |
| 509 | |
| 510 | |
| 511 | /* timer6 */ |
| 512 | static struct omap_hwmod omap2420_timer6_hwmod; |
| 513 | static struct omap_hwmod_irq_info omap2420_timer6_mpu_irqs[] = { |
| 514 | { .irq = 42, }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame^] | 515 | { .irq = -1 } |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 516 | }; |
| 517 | |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 518 | /* l4_core -> timer6 */ |
| 519 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = { |
| 520 | .master = &omap2420_l4_core_hwmod, |
| 521 | .slave = &omap2420_timer6_hwmod, |
| 522 | .clk = "gpt6_ick", |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 523 | .addr = omap2xxx_timer6_addrs, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 524 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 525 | }; |
| 526 | |
| 527 | /* timer6 slave port */ |
| 528 | static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = { |
| 529 | &omap2420_l4_core__timer6, |
| 530 | }; |
| 531 | |
| 532 | /* timer6 hwmod */ |
| 533 | static struct omap_hwmod omap2420_timer6_hwmod = { |
| 534 | .name = "timer6", |
| 535 | .mpu_irqs = omap2420_timer6_mpu_irqs, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 536 | .main_clk = "gpt6_fck", |
| 537 | .prcm = { |
| 538 | .omap2 = { |
| 539 | .prcm_reg_id = 1, |
| 540 | .module_bit = OMAP24XX_EN_GPT6_SHIFT, |
| 541 | .module_offs = CORE_MOD, |
| 542 | .idlest_reg_id = 1, |
| 543 | .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, |
| 544 | }, |
| 545 | }, |
| 546 | .slaves = omap2420_timer6_slaves, |
| 547 | .slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves), |
| 548 | .class = &omap2420_timer_hwmod_class, |
| 549 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
| 550 | }; |
| 551 | |
| 552 | /* timer7 */ |
| 553 | static struct omap_hwmod omap2420_timer7_hwmod; |
| 554 | static struct omap_hwmod_irq_info omap2420_timer7_mpu_irqs[] = { |
| 555 | { .irq = 43, }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame^] | 556 | { .irq = -1 } |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 557 | }; |
| 558 | |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 559 | /* l4_core -> timer7 */ |
| 560 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = { |
| 561 | .master = &omap2420_l4_core_hwmod, |
| 562 | .slave = &omap2420_timer7_hwmod, |
| 563 | .clk = "gpt7_ick", |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 564 | .addr = omap2xxx_timer7_addrs, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 565 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 566 | }; |
| 567 | |
| 568 | /* timer7 slave port */ |
| 569 | static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = { |
| 570 | &omap2420_l4_core__timer7, |
| 571 | }; |
| 572 | |
| 573 | /* timer7 hwmod */ |
| 574 | static struct omap_hwmod omap2420_timer7_hwmod = { |
| 575 | .name = "timer7", |
| 576 | .mpu_irqs = omap2420_timer7_mpu_irqs, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 577 | .main_clk = "gpt7_fck", |
| 578 | .prcm = { |
| 579 | .omap2 = { |
| 580 | .prcm_reg_id = 1, |
| 581 | .module_bit = OMAP24XX_EN_GPT7_SHIFT, |
| 582 | .module_offs = CORE_MOD, |
| 583 | .idlest_reg_id = 1, |
| 584 | .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, |
| 585 | }, |
| 586 | }, |
| 587 | .slaves = omap2420_timer7_slaves, |
| 588 | .slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves), |
| 589 | .class = &omap2420_timer_hwmod_class, |
| 590 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
| 591 | }; |
| 592 | |
| 593 | /* timer8 */ |
| 594 | static struct omap_hwmod omap2420_timer8_hwmod; |
| 595 | static struct omap_hwmod_irq_info omap2420_timer8_mpu_irqs[] = { |
| 596 | { .irq = 44, }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame^] | 597 | { .irq = -1 } |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 598 | }; |
| 599 | |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 600 | /* l4_core -> timer8 */ |
| 601 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = { |
| 602 | .master = &omap2420_l4_core_hwmod, |
| 603 | .slave = &omap2420_timer8_hwmod, |
| 604 | .clk = "gpt8_ick", |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 605 | .addr = omap2xxx_timer8_addrs, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 606 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 607 | }; |
| 608 | |
| 609 | /* timer8 slave port */ |
| 610 | static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = { |
| 611 | &omap2420_l4_core__timer8, |
| 612 | }; |
| 613 | |
| 614 | /* timer8 hwmod */ |
| 615 | static struct omap_hwmod omap2420_timer8_hwmod = { |
| 616 | .name = "timer8", |
| 617 | .mpu_irqs = omap2420_timer8_mpu_irqs, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 618 | .main_clk = "gpt8_fck", |
| 619 | .prcm = { |
| 620 | .omap2 = { |
| 621 | .prcm_reg_id = 1, |
| 622 | .module_bit = OMAP24XX_EN_GPT8_SHIFT, |
| 623 | .module_offs = CORE_MOD, |
| 624 | .idlest_reg_id = 1, |
| 625 | .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, |
| 626 | }, |
| 627 | }, |
| 628 | .slaves = omap2420_timer8_slaves, |
| 629 | .slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves), |
| 630 | .class = &omap2420_timer_hwmod_class, |
| 631 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
| 632 | }; |
| 633 | |
| 634 | /* timer9 */ |
| 635 | static struct omap_hwmod omap2420_timer9_hwmod; |
| 636 | static struct omap_hwmod_irq_info omap2420_timer9_mpu_irqs[] = { |
| 637 | { .irq = 45, }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame^] | 638 | { .irq = -1 } |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 639 | }; |
| 640 | |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 641 | /* l4_core -> timer9 */ |
| 642 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = { |
| 643 | .master = &omap2420_l4_core_hwmod, |
| 644 | .slave = &omap2420_timer9_hwmod, |
| 645 | .clk = "gpt9_ick", |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 646 | .addr = omap2xxx_timer9_addrs, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 647 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 648 | }; |
| 649 | |
| 650 | /* timer9 slave port */ |
| 651 | static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = { |
| 652 | &omap2420_l4_core__timer9, |
| 653 | }; |
| 654 | |
| 655 | /* timer9 hwmod */ |
| 656 | static struct omap_hwmod omap2420_timer9_hwmod = { |
| 657 | .name = "timer9", |
| 658 | .mpu_irqs = omap2420_timer9_mpu_irqs, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 659 | .main_clk = "gpt9_fck", |
| 660 | .prcm = { |
| 661 | .omap2 = { |
| 662 | .prcm_reg_id = 1, |
| 663 | .module_bit = OMAP24XX_EN_GPT9_SHIFT, |
| 664 | .module_offs = CORE_MOD, |
| 665 | .idlest_reg_id = 1, |
| 666 | .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, |
| 667 | }, |
| 668 | }, |
| 669 | .slaves = omap2420_timer9_slaves, |
| 670 | .slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves), |
| 671 | .class = &omap2420_timer_hwmod_class, |
| 672 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
| 673 | }; |
| 674 | |
| 675 | /* timer10 */ |
| 676 | static struct omap_hwmod omap2420_timer10_hwmod; |
| 677 | static struct omap_hwmod_irq_info omap2420_timer10_mpu_irqs[] = { |
| 678 | { .irq = 46, }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame^] | 679 | { .irq = -1 } |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 680 | }; |
| 681 | |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 682 | /* l4_core -> timer10 */ |
| 683 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = { |
| 684 | .master = &omap2420_l4_core_hwmod, |
| 685 | .slave = &omap2420_timer10_hwmod, |
| 686 | .clk = "gpt10_ick", |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 687 | .addr = omap2_timer10_addrs, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 688 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 689 | }; |
| 690 | |
| 691 | /* timer10 slave port */ |
| 692 | static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = { |
| 693 | &omap2420_l4_core__timer10, |
| 694 | }; |
| 695 | |
| 696 | /* timer10 hwmod */ |
| 697 | static struct omap_hwmod omap2420_timer10_hwmod = { |
| 698 | .name = "timer10", |
| 699 | .mpu_irqs = omap2420_timer10_mpu_irqs, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 700 | .main_clk = "gpt10_fck", |
| 701 | .prcm = { |
| 702 | .omap2 = { |
| 703 | .prcm_reg_id = 1, |
| 704 | .module_bit = OMAP24XX_EN_GPT10_SHIFT, |
| 705 | .module_offs = CORE_MOD, |
| 706 | .idlest_reg_id = 1, |
| 707 | .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, |
| 708 | }, |
| 709 | }, |
| 710 | .slaves = omap2420_timer10_slaves, |
| 711 | .slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves), |
| 712 | .class = &omap2420_timer_hwmod_class, |
| 713 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
| 714 | }; |
| 715 | |
| 716 | /* timer11 */ |
| 717 | static struct omap_hwmod omap2420_timer11_hwmod; |
| 718 | static struct omap_hwmod_irq_info omap2420_timer11_mpu_irqs[] = { |
| 719 | { .irq = 47, }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame^] | 720 | { .irq = -1 } |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 721 | }; |
| 722 | |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 723 | /* l4_core -> timer11 */ |
| 724 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = { |
| 725 | .master = &omap2420_l4_core_hwmod, |
| 726 | .slave = &omap2420_timer11_hwmod, |
| 727 | .clk = "gpt11_ick", |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 728 | .addr = omap2_timer11_addrs, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 729 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 730 | }; |
| 731 | |
| 732 | /* timer11 slave port */ |
| 733 | static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = { |
| 734 | &omap2420_l4_core__timer11, |
| 735 | }; |
| 736 | |
| 737 | /* timer11 hwmod */ |
| 738 | static struct omap_hwmod omap2420_timer11_hwmod = { |
| 739 | .name = "timer11", |
| 740 | .mpu_irqs = omap2420_timer11_mpu_irqs, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 741 | .main_clk = "gpt11_fck", |
| 742 | .prcm = { |
| 743 | .omap2 = { |
| 744 | .prcm_reg_id = 1, |
| 745 | .module_bit = OMAP24XX_EN_GPT11_SHIFT, |
| 746 | .module_offs = CORE_MOD, |
| 747 | .idlest_reg_id = 1, |
| 748 | .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, |
| 749 | }, |
| 750 | }, |
| 751 | .slaves = omap2420_timer11_slaves, |
| 752 | .slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves), |
| 753 | .class = &omap2420_timer_hwmod_class, |
| 754 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
| 755 | }; |
| 756 | |
| 757 | /* timer12 */ |
| 758 | static struct omap_hwmod omap2420_timer12_hwmod; |
| 759 | static struct omap_hwmod_irq_info omap2420_timer12_mpu_irqs[] = { |
| 760 | { .irq = 48, }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame^] | 761 | { .irq = -1 } |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 762 | }; |
| 763 | |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 764 | /* l4_core -> timer12 */ |
| 765 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = { |
| 766 | .master = &omap2420_l4_core_hwmod, |
| 767 | .slave = &omap2420_timer12_hwmod, |
| 768 | .clk = "gpt12_ick", |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 769 | .addr = omap2xxx_timer12_addrs, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 770 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 771 | }; |
| 772 | |
| 773 | /* timer12 slave port */ |
| 774 | static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = { |
| 775 | &omap2420_l4_core__timer12, |
| 776 | }; |
| 777 | |
| 778 | /* timer12 hwmod */ |
| 779 | static struct omap_hwmod omap2420_timer12_hwmod = { |
| 780 | .name = "timer12", |
| 781 | .mpu_irqs = omap2420_timer12_mpu_irqs, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 782 | .main_clk = "gpt12_fck", |
| 783 | .prcm = { |
| 784 | .omap2 = { |
| 785 | .prcm_reg_id = 1, |
| 786 | .module_bit = OMAP24XX_EN_GPT12_SHIFT, |
| 787 | .module_offs = CORE_MOD, |
| 788 | .idlest_reg_id = 1, |
| 789 | .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, |
| 790 | }, |
| 791 | }, |
| 792 | .slaves = omap2420_timer12_slaves, |
| 793 | .slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves), |
| 794 | .class = &omap2420_timer_hwmod_class, |
| 795 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
| 796 | }; |
| 797 | |
Varadarajan, Charulatha | a714b9c | 2010-09-23 20:02:39 +0530 | [diff] [blame] | 798 | /* l4_wkup -> wd_timer2 */ |
| 799 | static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { |
| 800 | { |
| 801 | .pa_start = 0x48022000, |
| 802 | .pa_end = 0x4802207f, |
| 803 | .flags = ADDR_TYPE_RT |
| 804 | }, |
Paul Walmsley | 78183f3 | 2011-07-09 19:14:05 -0600 | [diff] [blame] | 805 | { } |
Varadarajan, Charulatha | a714b9c | 2010-09-23 20:02:39 +0530 | [diff] [blame] | 806 | }; |
| 807 | |
| 808 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { |
| 809 | .master = &omap2420_l4_wkup_hwmod, |
| 810 | .slave = &omap2420_wd_timer2_hwmod, |
| 811 | .clk = "mpu_wdt_ick", |
| 812 | .addr = omap2420_wd_timer2_addrs, |
Varadarajan, Charulatha | a714b9c | 2010-09-23 20:02:39 +0530 | [diff] [blame] | 813 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 814 | }; |
| 815 | |
| 816 | /* |
| 817 | * 'wd_timer' class |
| 818 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on |
| 819 | * overflow condition |
| 820 | */ |
| 821 | |
| 822 | static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = { |
| 823 | .rev_offs = 0x0000, |
| 824 | .sysc_offs = 0x0010, |
| 825 | .syss_offs = 0x0014, |
| 826 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | |
Avinash.H.M | d73d65f | 2011-03-03 14:22:46 -0700 | [diff] [blame] | 827 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), |
Varadarajan, Charulatha | a714b9c | 2010-09-23 20:02:39 +0530 | [diff] [blame] | 828 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 829 | }; |
| 830 | |
| 831 | static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = { |
Paul Walmsley | ff2516f | 2010-12-21 15:39:15 -0700 | [diff] [blame] | 832 | .name = "wd_timer", |
| 833 | .sysc = &omap2420_wd_timer_sysc, |
| 834 | .pre_shutdown = &omap2_wd_timer_disable |
Varadarajan, Charulatha | a714b9c | 2010-09-23 20:02:39 +0530 | [diff] [blame] | 835 | }; |
| 836 | |
| 837 | /* wd_timer2 */ |
| 838 | static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = { |
| 839 | &omap2420_l4_wkup__wd_timer2, |
| 840 | }; |
| 841 | |
| 842 | static struct omap_hwmod omap2420_wd_timer2_hwmod = { |
| 843 | .name = "wd_timer2", |
| 844 | .class = &omap2420_wd_timer_hwmod_class, |
| 845 | .main_clk = "mpu_wdt_fck", |
| 846 | .prcm = { |
| 847 | .omap2 = { |
| 848 | .prcm_reg_id = 1, |
| 849 | .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, |
| 850 | .module_offs = WKUP_MOD, |
| 851 | .idlest_reg_id = 1, |
| 852 | .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, |
| 853 | }, |
| 854 | }, |
| 855 | .slaves = omap2420_wd_timer2_slaves, |
| 856 | .slaves_cnt = ARRAY_SIZE(omap2420_wd_timer2_slaves), |
| 857 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 858 | }; |
| 859 | |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 860 | /* UART */ |
| 861 | |
| 862 | static struct omap_hwmod_class_sysconfig uart_sysc = { |
| 863 | .rev_offs = 0x50, |
| 864 | .sysc_offs = 0x54, |
| 865 | .syss_offs = 0x58, |
| 866 | .sysc_flags = (SYSC_HAS_SIDLEMODE | |
| 867 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
Avinash.H.M | d73d65f | 2011-03-03 14:22:46 -0700 | [diff] [blame] | 868 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 869 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 870 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 871 | }; |
| 872 | |
| 873 | static struct omap_hwmod_class uart_class = { |
| 874 | .name = "uart", |
| 875 | .sysc = &uart_sysc, |
| 876 | }; |
| 877 | |
| 878 | /* UART1 */ |
| 879 | |
| 880 | static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { |
| 881 | { .irq = INT_24XX_UART1_IRQ, }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame^] | 882 | { .irq = -1 } |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 883 | }; |
| 884 | |
| 885 | static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { |
| 886 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, |
| 887 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, |
| 888 | }; |
| 889 | |
| 890 | static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = { |
| 891 | &omap2_l4_core__uart1, |
| 892 | }; |
| 893 | |
| 894 | static struct omap_hwmod omap2420_uart1_hwmod = { |
| 895 | .name = "uart1", |
| 896 | .mpu_irqs = uart1_mpu_irqs, |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 897 | .sdma_reqs = uart1_sdma_reqs, |
| 898 | .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), |
| 899 | .main_clk = "uart1_fck", |
| 900 | .prcm = { |
| 901 | .omap2 = { |
| 902 | .module_offs = CORE_MOD, |
| 903 | .prcm_reg_id = 1, |
| 904 | .module_bit = OMAP24XX_EN_UART1_SHIFT, |
| 905 | .idlest_reg_id = 1, |
| 906 | .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, |
| 907 | }, |
| 908 | }, |
| 909 | .slaves = omap2420_uart1_slaves, |
| 910 | .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves), |
| 911 | .class = &uart_class, |
| 912 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 913 | }; |
| 914 | |
| 915 | /* UART2 */ |
| 916 | |
| 917 | static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { |
| 918 | { .irq = INT_24XX_UART2_IRQ, }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame^] | 919 | { .irq = -1 } |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 920 | }; |
| 921 | |
| 922 | static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { |
| 923 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, |
| 924 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, |
| 925 | }; |
| 926 | |
| 927 | static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = { |
| 928 | &omap2_l4_core__uart2, |
| 929 | }; |
| 930 | |
| 931 | static struct omap_hwmod omap2420_uart2_hwmod = { |
| 932 | .name = "uart2", |
| 933 | .mpu_irqs = uart2_mpu_irqs, |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 934 | .sdma_reqs = uart2_sdma_reqs, |
| 935 | .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), |
| 936 | .main_clk = "uart2_fck", |
| 937 | .prcm = { |
| 938 | .omap2 = { |
| 939 | .module_offs = CORE_MOD, |
| 940 | .prcm_reg_id = 1, |
| 941 | .module_bit = OMAP24XX_EN_UART2_SHIFT, |
| 942 | .idlest_reg_id = 1, |
| 943 | .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, |
| 944 | }, |
| 945 | }, |
| 946 | .slaves = omap2420_uart2_slaves, |
| 947 | .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves), |
| 948 | .class = &uart_class, |
| 949 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 950 | }; |
| 951 | |
| 952 | /* UART3 */ |
| 953 | |
| 954 | static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { |
| 955 | { .irq = INT_24XX_UART3_IRQ, }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame^] | 956 | { .irq = -1 } |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 957 | }; |
| 958 | |
| 959 | static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { |
| 960 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, |
| 961 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, |
| 962 | }; |
| 963 | |
| 964 | static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = { |
| 965 | &omap2_l4_core__uart3, |
| 966 | }; |
| 967 | |
| 968 | static struct omap_hwmod omap2420_uart3_hwmod = { |
| 969 | .name = "uart3", |
| 970 | .mpu_irqs = uart3_mpu_irqs, |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 971 | .sdma_reqs = uart3_sdma_reqs, |
| 972 | .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), |
| 973 | .main_clk = "uart3_fck", |
| 974 | .prcm = { |
| 975 | .omap2 = { |
| 976 | .module_offs = CORE_MOD, |
| 977 | .prcm_reg_id = 2, |
| 978 | .module_bit = OMAP24XX_EN_UART3_SHIFT, |
| 979 | .idlest_reg_id = 2, |
| 980 | .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, |
| 981 | }, |
| 982 | }, |
| 983 | .slaves = omap2420_uart3_slaves, |
| 984 | .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves), |
| 985 | .class = &uart_class, |
| 986 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 987 | }; |
| 988 | |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 989 | /* |
| 990 | * 'dss' class |
| 991 | * display sub-system |
| 992 | */ |
| 993 | |
| 994 | static struct omap_hwmod_class_sysconfig omap2420_dss_sysc = { |
| 995 | .rev_offs = 0x0000, |
| 996 | .sysc_offs = 0x0010, |
| 997 | .syss_offs = 0x0014, |
| 998 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), |
| 999 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 1000 | }; |
| 1001 | |
| 1002 | static struct omap_hwmod_class omap2420_dss_hwmod_class = { |
| 1003 | .name = "dss", |
| 1004 | .sysc = &omap2420_dss_sysc, |
| 1005 | }; |
| 1006 | |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 1007 | static struct omap_hwmod_dma_info omap2420_dss_sdma_chs[] = { |
| 1008 | { .name = "dispc", .dma_req = 5 }, |
| 1009 | }; |
| 1010 | |
| 1011 | /* dss */ |
| 1012 | /* dss master ports */ |
| 1013 | static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = { |
| 1014 | &omap2420_dss__l3, |
| 1015 | }; |
| 1016 | |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 1017 | /* l4_core -> dss */ |
| 1018 | static struct omap_hwmod_ocp_if omap2420_l4_core__dss = { |
| 1019 | .master = &omap2420_l4_core_hwmod, |
| 1020 | .slave = &omap2420_dss_core_hwmod, |
| 1021 | .clk = "dss_ick", |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 1022 | .addr = omap2_dss_addrs, |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 1023 | .fw = { |
| 1024 | .omap2 = { |
| 1025 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, |
| 1026 | .flags = OMAP_FIREWALL_L4, |
| 1027 | } |
| 1028 | }, |
| 1029 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1030 | }; |
| 1031 | |
| 1032 | /* dss slave ports */ |
| 1033 | static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = { |
| 1034 | &omap2420_l4_core__dss, |
| 1035 | }; |
| 1036 | |
| 1037 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { |
| 1038 | { .role = "tv_clk", .clk = "dss_54m_fck" }, |
| 1039 | { .role = "sys_clk", .clk = "dss2_fck" }, |
| 1040 | }; |
| 1041 | |
| 1042 | static struct omap_hwmod omap2420_dss_core_hwmod = { |
| 1043 | .name = "dss_core", |
| 1044 | .class = &omap2420_dss_hwmod_class, |
| 1045 | .main_clk = "dss1_fck", /* instead of dss_fck */ |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 1046 | .sdma_reqs = omap2420_dss_sdma_chs, |
| 1047 | .sdma_reqs_cnt = ARRAY_SIZE(omap2420_dss_sdma_chs), |
| 1048 | .prcm = { |
| 1049 | .omap2 = { |
| 1050 | .prcm_reg_id = 1, |
| 1051 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, |
| 1052 | .module_offs = CORE_MOD, |
| 1053 | .idlest_reg_id = 1, |
| 1054 | .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, |
| 1055 | }, |
| 1056 | }, |
| 1057 | .opt_clks = dss_opt_clks, |
| 1058 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), |
| 1059 | .slaves = omap2420_dss_slaves, |
| 1060 | .slaves_cnt = ARRAY_SIZE(omap2420_dss_slaves), |
| 1061 | .masters = omap2420_dss_masters, |
| 1062 | .masters_cnt = ARRAY_SIZE(omap2420_dss_masters), |
| 1063 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1064 | .flags = HWMOD_NO_IDLEST, |
| 1065 | }; |
| 1066 | |
| 1067 | /* |
| 1068 | * 'dispc' class |
| 1069 | * display controller |
| 1070 | */ |
| 1071 | |
| 1072 | static struct omap_hwmod_class_sysconfig omap2420_dispc_sysc = { |
| 1073 | .rev_offs = 0x0000, |
| 1074 | .sysc_offs = 0x0010, |
| 1075 | .syss_offs = 0x0014, |
| 1076 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | |
| 1077 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), |
| 1078 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 1079 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), |
| 1080 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 1081 | }; |
| 1082 | |
| 1083 | static struct omap_hwmod_class omap2420_dispc_hwmod_class = { |
| 1084 | .name = "dispc", |
| 1085 | .sysc = &omap2420_dispc_sysc, |
| 1086 | }; |
| 1087 | |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 1088 | static struct omap_hwmod_irq_info omap2420_dispc_irqs[] = { |
| 1089 | { .irq = 25 }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame^] | 1090 | { .irq = -1 } |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 1091 | }; |
| 1092 | |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 1093 | /* l4_core -> dss_dispc */ |
| 1094 | static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = { |
| 1095 | .master = &omap2420_l4_core_hwmod, |
| 1096 | .slave = &omap2420_dss_dispc_hwmod, |
| 1097 | .clk = "dss_ick", |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 1098 | .addr = omap2_dss_dispc_addrs, |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 1099 | .fw = { |
| 1100 | .omap2 = { |
| 1101 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, |
| 1102 | .flags = OMAP_FIREWALL_L4, |
| 1103 | } |
| 1104 | }, |
| 1105 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1106 | }; |
| 1107 | |
| 1108 | /* dss_dispc slave ports */ |
| 1109 | static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = { |
| 1110 | &omap2420_l4_core__dss_dispc, |
| 1111 | }; |
| 1112 | |
| 1113 | static struct omap_hwmod omap2420_dss_dispc_hwmod = { |
| 1114 | .name = "dss_dispc", |
| 1115 | .class = &omap2420_dispc_hwmod_class, |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 1116 | .mpu_irqs = omap2420_dispc_irqs, |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 1117 | .main_clk = "dss1_fck", |
| 1118 | .prcm = { |
| 1119 | .omap2 = { |
| 1120 | .prcm_reg_id = 1, |
| 1121 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, |
| 1122 | .module_offs = CORE_MOD, |
| 1123 | .idlest_reg_id = 1, |
| 1124 | .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, |
| 1125 | }, |
| 1126 | }, |
| 1127 | .slaves = omap2420_dss_dispc_slaves, |
| 1128 | .slaves_cnt = ARRAY_SIZE(omap2420_dss_dispc_slaves), |
| 1129 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1130 | .flags = HWMOD_NO_IDLEST, |
| 1131 | }; |
| 1132 | |
| 1133 | /* |
| 1134 | * 'rfbi' class |
| 1135 | * remote frame buffer interface |
| 1136 | */ |
| 1137 | |
| 1138 | static struct omap_hwmod_class_sysconfig omap2420_rfbi_sysc = { |
| 1139 | .rev_offs = 0x0000, |
| 1140 | .sysc_offs = 0x0010, |
| 1141 | .syss_offs = 0x0014, |
| 1142 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | |
| 1143 | SYSC_HAS_AUTOIDLE), |
| 1144 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 1145 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 1146 | }; |
| 1147 | |
| 1148 | static struct omap_hwmod_class omap2420_rfbi_hwmod_class = { |
| 1149 | .name = "rfbi", |
| 1150 | .sysc = &omap2420_rfbi_sysc, |
| 1151 | }; |
| 1152 | |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 1153 | /* l4_core -> dss_rfbi */ |
| 1154 | static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = { |
| 1155 | .master = &omap2420_l4_core_hwmod, |
| 1156 | .slave = &omap2420_dss_rfbi_hwmod, |
| 1157 | .clk = "dss_ick", |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 1158 | .addr = omap2_dss_rfbi_addrs, |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 1159 | .fw = { |
| 1160 | .omap2 = { |
| 1161 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, |
| 1162 | .flags = OMAP_FIREWALL_L4, |
| 1163 | } |
| 1164 | }, |
| 1165 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1166 | }; |
| 1167 | |
| 1168 | /* dss_rfbi slave ports */ |
| 1169 | static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = { |
| 1170 | &omap2420_l4_core__dss_rfbi, |
| 1171 | }; |
| 1172 | |
| 1173 | static struct omap_hwmod omap2420_dss_rfbi_hwmod = { |
| 1174 | .name = "dss_rfbi", |
| 1175 | .class = &omap2420_rfbi_hwmod_class, |
| 1176 | .main_clk = "dss1_fck", |
| 1177 | .prcm = { |
| 1178 | .omap2 = { |
| 1179 | .prcm_reg_id = 1, |
| 1180 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, |
| 1181 | .module_offs = CORE_MOD, |
| 1182 | }, |
| 1183 | }, |
| 1184 | .slaves = omap2420_dss_rfbi_slaves, |
| 1185 | .slaves_cnt = ARRAY_SIZE(omap2420_dss_rfbi_slaves), |
| 1186 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1187 | .flags = HWMOD_NO_IDLEST, |
| 1188 | }; |
| 1189 | |
| 1190 | /* |
| 1191 | * 'venc' class |
| 1192 | * video encoder |
| 1193 | */ |
| 1194 | |
| 1195 | static struct omap_hwmod_class omap2420_venc_hwmod_class = { |
| 1196 | .name = "venc", |
| 1197 | }; |
| 1198 | |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 1199 | /* l4_core -> dss_venc */ |
| 1200 | static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = { |
| 1201 | .master = &omap2420_l4_core_hwmod, |
| 1202 | .slave = &omap2420_dss_venc_hwmod, |
| 1203 | .clk = "dss_54m_fck", |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 1204 | .addr = omap2_dss_venc_addrs, |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 1205 | .fw = { |
| 1206 | .omap2 = { |
| 1207 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, |
| 1208 | .flags = OMAP_FIREWALL_L4, |
| 1209 | } |
| 1210 | }, |
Paul Walmsley | c39bee8 | 2011-03-04 06:02:15 +0000 | [diff] [blame] | 1211 | .flags = OCPIF_SWSUP_IDLE, |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 1212 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1213 | }; |
| 1214 | |
| 1215 | /* dss_venc slave ports */ |
| 1216 | static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = { |
| 1217 | &omap2420_l4_core__dss_venc, |
| 1218 | }; |
| 1219 | |
| 1220 | static struct omap_hwmod omap2420_dss_venc_hwmod = { |
| 1221 | .name = "dss_venc", |
| 1222 | .class = &omap2420_venc_hwmod_class, |
| 1223 | .main_clk = "dss1_fck", |
| 1224 | .prcm = { |
| 1225 | .omap2 = { |
| 1226 | .prcm_reg_id = 1, |
| 1227 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, |
| 1228 | .module_offs = CORE_MOD, |
| 1229 | }, |
| 1230 | }, |
| 1231 | .slaves = omap2420_dss_venc_slaves, |
| 1232 | .slaves_cnt = ARRAY_SIZE(omap2420_dss_venc_slaves), |
| 1233 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1234 | .flags = HWMOD_NO_IDLEST, |
| 1235 | }; |
| 1236 | |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 1237 | /* I2C common */ |
| 1238 | static struct omap_hwmod_class_sysconfig i2c_sysc = { |
| 1239 | .rev_offs = 0x00, |
| 1240 | .sysc_offs = 0x20, |
| 1241 | .syss_offs = 0x10, |
Avinash.H.M | d73d65f | 2011-03-03 14:22:46 -0700 | [diff] [blame] | 1242 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 1243 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 1244 | }; |
| 1245 | |
| 1246 | static struct omap_hwmod_class i2c_class = { |
| 1247 | .name = "i2c", |
| 1248 | .sysc = &i2c_sysc, |
| 1249 | }; |
| 1250 | |
| 1251 | static struct omap_i2c_dev_attr i2c_dev_attr; |
| 1252 | |
| 1253 | /* I2C1 */ |
| 1254 | |
| 1255 | static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { |
| 1256 | { .irq = INT_24XX_I2C1_IRQ, }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame^] | 1257 | { .irq = -1 } |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 1258 | }; |
| 1259 | |
| 1260 | static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = { |
| 1261 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX }, |
| 1262 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX }, |
| 1263 | }; |
| 1264 | |
| 1265 | static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = { |
| 1266 | &omap2420_l4_core__i2c1, |
| 1267 | }; |
| 1268 | |
| 1269 | static struct omap_hwmod omap2420_i2c1_hwmod = { |
| 1270 | .name = "i2c1", |
| 1271 | .mpu_irqs = i2c1_mpu_irqs, |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 1272 | .sdma_reqs = i2c1_sdma_reqs, |
| 1273 | .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs), |
| 1274 | .main_clk = "i2c1_fck", |
| 1275 | .prcm = { |
| 1276 | .omap2 = { |
| 1277 | .module_offs = CORE_MOD, |
| 1278 | .prcm_reg_id = 1, |
| 1279 | .module_bit = OMAP2420_EN_I2C1_SHIFT, |
| 1280 | .idlest_reg_id = 1, |
| 1281 | .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT, |
| 1282 | }, |
| 1283 | }, |
| 1284 | .slaves = omap2420_i2c1_slaves, |
| 1285 | .slaves_cnt = ARRAY_SIZE(omap2420_i2c1_slaves), |
| 1286 | .class = &i2c_class, |
| 1287 | .dev_attr = &i2c_dev_attr, |
| 1288 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1289 | .flags = HWMOD_16BIT_REG, |
| 1290 | }; |
| 1291 | |
| 1292 | /* I2C2 */ |
| 1293 | |
| 1294 | static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { |
| 1295 | { .irq = INT_24XX_I2C2_IRQ, }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame^] | 1296 | { .irq = -1 } |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 1297 | }; |
| 1298 | |
| 1299 | static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = { |
| 1300 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX }, |
| 1301 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX }, |
| 1302 | }; |
| 1303 | |
| 1304 | static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = { |
| 1305 | &omap2420_l4_core__i2c2, |
| 1306 | }; |
| 1307 | |
| 1308 | static struct omap_hwmod omap2420_i2c2_hwmod = { |
| 1309 | .name = "i2c2", |
| 1310 | .mpu_irqs = i2c2_mpu_irqs, |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 1311 | .sdma_reqs = i2c2_sdma_reqs, |
| 1312 | .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs), |
| 1313 | .main_clk = "i2c2_fck", |
| 1314 | .prcm = { |
| 1315 | .omap2 = { |
| 1316 | .module_offs = CORE_MOD, |
| 1317 | .prcm_reg_id = 1, |
| 1318 | .module_bit = OMAP2420_EN_I2C2_SHIFT, |
| 1319 | .idlest_reg_id = 1, |
| 1320 | .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT, |
| 1321 | }, |
| 1322 | }, |
| 1323 | .slaves = omap2420_i2c2_slaves, |
| 1324 | .slaves_cnt = ARRAY_SIZE(omap2420_i2c2_slaves), |
| 1325 | .class = &i2c_class, |
| 1326 | .dev_attr = &i2c_dev_attr, |
| 1327 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1328 | .flags = HWMOD_16BIT_REG, |
| 1329 | }; |
| 1330 | |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 1331 | /* l4_wkup -> gpio1 */ |
| 1332 | static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = { |
| 1333 | { |
| 1334 | .pa_start = 0x48018000, |
| 1335 | .pa_end = 0x480181ff, |
| 1336 | .flags = ADDR_TYPE_RT |
| 1337 | }, |
Paul Walmsley | 78183f3 | 2011-07-09 19:14:05 -0600 | [diff] [blame] | 1338 | { } |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 1339 | }; |
| 1340 | |
| 1341 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = { |
| 1342 | .master = &omap2420_l4_wkup_hwmod, |
| 1343 | .slave = &omap2420_gpio1_hwmod, |
| 1344 | .clk = "gpios_ick", |
| 1345 | .addr = omap2420_gpio1_addr_space, |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 1346 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1347 | }; |
| 1348 | |
| 1349 | /* l4_wkup -> gpio2 */ |
| 1350 | static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = { |
| 1351 | { |
| 1352 | .pa_start = 0x4801a000, |
| 1353 | .pa_end = 0x4801a1ff, |
| 1354 | .flags = ADDR_TYPE_RT |
| 1355 | }, |
Paul Walmsley | 78183f3 | 2011-07-09 19:14:05 -0600 | [diff] [blame] | 1356 | { } |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 1357 | }; |
| 1358 | |
| 1359 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = { |
| 1360 | .master = &omap2420_l4_wkup_hwmod, |
| 1361 | .slave = &omap2420_gpio2_hwmod, |
| 1362 | .clk = "gpios_ick", |
| 1363 | .addr = omap2420_gpio2_addr_space, |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 1364 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1365 | }; |
| 1366 | |
| 1367 | /* l4_wkup -> gpio3 */ |
| 1368 | static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = { |
| 1369 | { |
| 1370 | .pa_start = 0x4801c000, |
| 1371 | .pa_end = 0x4801c1ff, |
| 1372 | .flags = ADDR_TYPE_RT |
| 1373 | }, |
Paul Walmsley | 78183f3 | 2011-07-09 19:14:05 -0600 | [diff] [blame] | 1374 | { } |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 1375 | }; |
| 1376 | |
| 1377 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = { |
| 1378 | .master = &omap2420_l4_wkup_hwmod, |
| 1379 | .slave = &omap2420_gpio3_hwmod, |
| 1380 | .clk = "gpios_ick", |
| 1381 | .addr = omap2420_gpio3_addr_space, |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 1382 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1383 | }; |
| 1384 | |
| 1385 | /* l4_wkup -> gpio4 */ |
| 1386 | static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = { |
| 1387 | { |
| 1388 | .pa_start = 0x4801e000, |
| 1389 | .pa_end = 0x4801e1ff, |
| 1390 | .flags = ADDR_TYPE_RT |
| 1391 | }, |
Paul Walmsley | 78183f3 | 2011-07-09 19:14:05 -0600 | [diff] [blame] | 1392 | { } |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 1393 | }; |
| 1394 | |
| 1395 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { |
| 1396 | .master = &omap2420_l4_wkup_hwmod, |
| 1397 | .slave = &omap2420_gpio4_hwmod, |
| 1398 | .clk = "gpios_ick", |
| 1399 | .addr = omap2420_gpio4_addr_space, |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 1400 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1401 | }; |
| 1402 | |
| 1403 | /* gpio dev_attr */ |
| 1404 | static struct omap_gpio_dev_attr gpio_dev_attr = { |
| 1405 | .bank_width = 32, |
| 1406 | .dbck_flag = false, |
| 1407 | }; |
| 1408 | |
| 1409 | static struct omap_hwmod_class_sysconfig omap242x_gpio_sysc = { |
| 1410 | .rev_offs = 0x0000, |
| 1411 | .sysc_offs = 0x0010, |
| 1412 | .syss_offs = 0x0014, |
| 1413 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | |
Avinash.H.M | d73d65f | 2011-03-03 14:22:46 -0700 | [diff] [blame] | 1414 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | |
| 1415 | SYSS_HAS_RESET_STATUS), |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 1416 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 1417 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 1418 | }; |
| 1419 | |
| 1420 | /* |
| 1421 | * 'gpio' class |
| 1422 | * general purpose io module |
| 1423 | */ |
| 1424 | static struct omap_hwmod_class omap242x_gpio_hwmod_class = { |
| 1425 | .name = "gpio", |
| 1426 | .sysc = &omap242x_gpio_sysc, |
| 1427 | .rev = 0, |
| 1428 | }; |
| 1429 | |
| 1430 | /* gpio1 */ |
| 1431 | static struct omap_hwmod_irq_info omap242x_gpio1_irqs[] = { |
| 1432 | { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */ |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame^] | 1433 | { .irq = -1 } |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 1434 | }; |
| 1435 | |
| 1436 | static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = { |
| 1437 | &omap2420_l4_wkup__gpio1, |
| 1438 | }; |
| 1439 | |
| 1440 | static struct omap_hwmod omap2420_gpio1_hwmod = { |
| 1441 | .name = "gpio1", |
Avinash.H.M | f95440c | 2011-04-05 21:10:15 +0530 | [diff] [blame] | 1442 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 1443 | .mpu_irqs = omap242x_gpio1_irqs, |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 1444 | .main_clk = "gpios_fck", |
| 1445 | .prcm = { |
| 1446 | .omap2 = { |
| 1447 | .prcm_reg_id = 1, |
| 1448 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| 1449 | .module_offs = WKUP_MOD, |
| 1450 | .idlest_reg_id = 1, |
| 1451 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, |
| 1452 | }, |
| 1453 | }, |
| 1454 | .slaves = omap2420_gpio1_slaves, |
| 1455 | .slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves), |
| 1456 | .class = &omap242x_gpio_hwmod_class, |
| 1457 | .dev_attr = &gpio_dev_attr, |
| 1458 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1459 | }; |
| 1460 | |
| 1461 | /* gpio2 */ |
| 1462 | static struct omap_hwmod_irq_info omap242x_gpio2_irqs[] = { |
| 1463 | { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */ |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame^] | 1464 | { .irq = -1 } |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 1465 | }; |
| 1466 | |
| 1467 | static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = { |
| 1468 | &omap2420_l4_wkup__gpio2, |
| 1469 | }; |
| 1470 | |
| 1471 | static struct omap_hwmod omap2420_gpio2_hwmod = { |
| 1472 | .name = "gpio2", |
Avinash.H.M | f95440c | 2011-04-05 21:10:15 +0530 | [diff] [blame] | 1473 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 1474 | .mpu_irqs = omap242x_gpio2_irqs, |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 1475 | .main_clk = "gpios_fck", |
| 1476 | .prcm = { |
| 1477 | .omap2 = { |
| 1478 | .prcm_reg_id = 1, |
| 1479 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| 1480 | .module_offs = WKUP_MOD, |
| 1481 | .idlest_reg_id = 1, |
| 1482 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, |
| 1483 | }, |
| 1484 | }, |
| 1485 | .slaves = omap2420_gpio2_slaves, |
| 1486 | .slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves), |
| 1487 | .class = &omap242x_gpio_hwmod_class, |
| 1488 | .dev_attr = &gpio_dev_attr, |
| 1489 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1490 | }; |
| 1491 | |
| 1492 | /* gpio3 */ |
| 1493 | static struct omap_hwmod_irq_info omap242x_gpio3_irqs[] = { |
| 1494 | { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */ |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame^] | 1495 | { .irq = -1 } |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 1496 | }; |
| 1497 | |
| 1498 | static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = { |
| 1499 | &omap2420_l4_wkup__gpio3, |
| 1500 | }; |
| 1501 | |
| 1502 | static struct omap_hwmod omap2420_gpio3_hwmod = { |
| 1503 | .name = "gpio3", |
Avinash.H.M | f95440c | 2011-04-05 21:10:15 +0530 | [diff] [blame] | 1504 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 1505 | .mpu_irqs = omap242x_gpio3_irqs, |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 1506 | .main_clk = "gpios_fck", |
| 1507 | .prcm = { |
| 1508 | .omap2 = { |
| 1509 | .prcm_reg_id = 1, |
| 1510 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| 1511 | .module_offs = WKUP_MOD, |
| 1512 | .idlest_reg_id = 1, |
| 1513 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, |
| 1514 | }, |
| 1515 | }, |
| 1516 | .slaves = omap2420_gpio3_slaves, |
| 1517 | .slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves), |
| 1518 | .class = &omap242x_gpio_hwmod_class, |
| 1519 | .dev_attr = &gpio_dev_attr, |
| 1520 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1521 | }; |
| 1522 | |
| 1523 | /* gpio4 */ |
| 1524 | static struct omap_hwmod_irq_info omap242x_gpio4_irqs[] = { |
| 1525 | { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */ |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame^] | 1526 | { .irq = -1 } |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 1527 | }; |
| 1528 | |
| 1529 | static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = { |
| 1530 | &omap2420_l4_wkup__gpio4, |
| 1531 | }; |
| 1532 | |
| 1533 | static struct omap_hwmod omap2420_gpio4_hwmod = { |
| 1534 | .name = "gpio4", |
Avinash.H.M | f95440c | 2011-04-05 21:10:15 +0530 | [diff] [blame] | 1535 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 1536 | .mpu_irqs = omap242x_gpio4_irqs, |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 1537 | .main_clk = "gpios_fck", |
| 1538 | .prcm = { |
| 1539 | .omap2 = { |
| 1540 | .prcm_reg_id = 1, |
| 1541 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| 1542 | .module_offs = WKUP_MOD, |
| 1543 | .idlest_reg_id = 1, |
| 1544 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, |
| 1545 | }, |
| 1546 | }, |
| 1547 | .slaves = omap2420_gpio4_slaves, |
| 1548 | .slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves), |
| 1549 | .class = &omap242x_gpio_hwmod_class, |
| 1550 | .dev_attr = &gpio_dev_attr, |
| 1551 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1552 | }; |
| 1553 | |
G, Manjunath Kondaiah | 745685df9 | 2010-12-20 18:27:18 -0800 | [diff] [blame] | 1554 | /* system dma */ |
| 1555 | static struct omap_hwmod_class_sysconfig omap2420_dma_sysc = { |
| 1556 | .rev_offs = 0x0000, |
| 1557 | .sysc_offs = 0x002c, |
| 1558 | .syss_offs = 0x0028, |
| 1559 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE | |
| 1560 | SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE | |
Avinash.H.M | d73d65f | 2011-03-03 14:22:46 -0700 | [diff] [blame] | 1561 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), |
G, Manjunath Kondaiah | 745685df9 | 2010-12-20 18:27:18 -0800 | [diff] [blame] | 1562 | .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), |
| 1563 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 1564 | }; |
| 1565 | |
| 1566 | static struct omap_hwmod_class omap2420_dma_hwmod_class = { |
| 1567 | .name = "dma", |
| 1568 | .sysc = &omap2420_dma_sysc, |
| 1569 | }; |
| 1570 | |
| 1571 | /* dma attributes */ |
| 1572 | static struct omap_dma_dev_attr dma_dev_attr = { |
| 1573 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | |
| 1574 | IS_CSSA_32 | IS_CDSA_32, |
| 1575 | .lch_count = 32, |
| 1576 | }; |
| 1577 | |
| 1578 | static struct omap_hwmod_irq_info omap2420_dma_system_irqs[] = { |
| 1579 | { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */ |
| 1580 | { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */ |
| 1581 | { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */ |
| 1582 | { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */ |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame^] | 1583 | { .irq = -1 } |
G, Manjunath Kondaiah | 745685df9 | 2010-12-20 18:27:18 -0800 | [diff] [blame] | 1584 | }; |
| 1585 | |
G, Manjunath Kondaiah | 745685df9 | 2010-12-20 18:27:18 -0800 | [diff] [blame] | 1586 | /* dma_system -> L3 */ |
| 1587 | static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = { |
| 1588 | .master = &omap2420_dma_system_hwmod, |
| 1589 | .slave = &omap2420_l3_main_hwmod, |
| 1590 | .clk = "core_l3_ck", |
| 1591 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1592 | }; |
| 1593 | |
| 1594 | /* dma_system master ports */ |
| 1595 | static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = { |
| 1596 | &omap2420_dma_system__l3, |
| 1597 | }; |
| 1598 | |
| 1599 | /* l4_core -> dma_system */ |
| 1600 | static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = { |
| 1601 | .master = &omap2420_l4_core_hwmod, |
| 1602 | .slave = &omap2420_dma_system_hwmod, |
| 1603 | .clk = "sdma_ick", |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 1604 | .addr = omap2_dma_system_addrs, |
G, Manjunath Kondaiah | 745685df9 | 2010-12-20 18:27:18 -0800 | [diff] [blame] | 1605 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1606 | }; |
| 1607 | |
| 1608 | /* dma_system slave ports */ |
| 1609 | static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = { |
| 1610 | &omap2420_l4_core__dma_system, |
| 1611 | }; |
| 1612 | |
| 1613 | static struct omap_hwmod omap2420_dma_system_hwmod = { |
| 1614 | .name = "dma", |
| 1615 | .class = &omap2420_dma_hwmod_class, |
| 1616 | .mpu_irqs = omap2420_dma_system_irqs, |
G, Manjunath Kondaiah | 745685df9 | 2010-12-20 18:27:18 -0800 | [diff] [blame] | 1617 | .main_clk = "core_l3_ck", |
| 1618 | .slaves = omap2420_dma_system_slaves, |
| 1619 | .slaves_cnt = ARRAY_SIZE(omap2420_dma_system_slaves), |
| 1620 | .masters = omap2420_dma_system_masters, |
| 1621 | .masters_cnt = ARRAY_SIZE(omap2420_dma_system_masters), |
| 1622 | .dev_attr = &dma_dev_attr, |
| 1623 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1624 | .flags = HWMOD_NO_IDLEST, |
| 1625 | }; |
| 1626 | |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 1627 | /* |
Omar Ramirez Luna | fca1ab5 | 2011-02-24 12:51:32 -0800 | [diff] [blame] | 1628 | * 'mailbox' class |
| 1629 | * mailbox module allowing communication between the on-chip processors |
| 1630 | * using a queued mailbox-interrupt mechanism. |
| 1631 | */ |
| 1632 | |
| 1633 | static struct omap_hwmod_class_sysconfig omap2420_mailbox_sysc = { |
| 1634 | .rev_offs = 0x000, |
| 1635 | .sysc_offs = 0x010, |
| 1636 | .syss_offs = 0x014, |
| 1637 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | |
| 1638 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), |
| 1639 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 1640 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 1641 | }; |
| 1642 | |
| 1643 | static struct omap_hwmod_class omap2420_mailbox_hwmod_class = { |
| 1644 | .name = "mailbox", |
| 1645 | .sysc = &omap2420_mailbox_sysc, |
| 1646 | }; |
| 1647 | |
| 1648 | /* mailbox */ |
| 1649 | static struct omap_hwmod omap2420_mailbox_hwmod; |
| 1650 | static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { |
| 1651 | { .name = "dsp", .irq = 26 }, |
| 1652 | { .name = "iva", .irq = 34 }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame^] | 1653 | { .irq = -1 } |
Omar Ramirez Luna | fca1ab5 | 2011-02-24 12:51:32 -0800 | [diff] [blame] | 1654 | }; |
| 1655 | |
Omar Ramirez Luna | fca1ab5 | 2011-02-24 12:51:32 -0800 | [diff] [blame] | 1656 | /* l4_core -> mailbox */ |
| 1657 | static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = { |
| 1658 | .master = &omap2420_l4_core_hwmod, |
| 1659 | .slave = &omap2420_mailbox_hwmod, |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 1660 | .addr = omap2_mailbox_addrs, |
Omar Ramirez Luna | fca1ab5 | 2011-02-24 12:51:32 -0800 | [diff] [blame] | 1661 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1662 | }; |
| 1663 | |
| 1664 | /* mailbox slave ports */ |
| 1665 | static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = { |
| 1666 | &omap2420_l4_core__mailbox, |
| 1667 | }; |
| 1668 | |
| 1669 | static struct omap_hwmod omap2420_mailbox_hwmod = { |
| 1670 | .name = "mailbox", |
| 1671 | .class = &omap2420_mailbox_hwmod_class, |
| 1672 | .mpu_irqs = omap2420_mailbox_irqs, |
Omar Ramirez Luna | fca1ab5 | 2011-02-24 12:51:32 -0800 | [diff] [blame] | 1673 | .main_clk = "mailboxes_ick", |
| 1674 | .prcm = { |
| 1675 | .omap2 = { |
| 1676 | .prcm_reg_id = 1, |
| 1677 | .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, |
| 1678 | .module_offs = CORE_MOD, |
| 1679 | .idlest_reg_id = 1, |
| 1680 | .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, |
| 1681 | }, |
| 1682 | }, |
| 1683 | .slaves = omap2420_mailbox_slaves, |
| 1684 | .slaves_cnt = ARRAY_SIZE(omap2420_mailbox_slaves), |
| 1685 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1686 | }; |
| 1687 | |
| 1688 | /* |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 1689 | * 'mcspi' class |
| 1690 | * multichannel serial port interface (mcspi) / master/slave synchronous serial |
| 1691 | * bus |
| 1692 | */ |
| 1693 | |
| 1694 | static struct omap_hwmod_class_sysconfig omap2420_mcspi_sysc = { |
| 1695 | .rev_offs = 0x0000, |
| 1696 | .sysc_offs = 0x0010, |
| 1697 | .syss_offs = 0x0014, |
| 1698 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | |
| 1699 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
| 1700 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), |
| 1701 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 1702 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 1703 | }; |
| 1704 | |
| 1705 | static struct omap_hwmod_class omap2420_mcspi_class = { |
| 1706 | .name = "mcspi", |
| 1707 | .sysc = &omap2420_mcspi_sysc, |
| 1708 | .rev = OMAP2_MCSPI_REV, |
| 1709 | }; |
| 1710 | |
| 1711 | /* mcspi1 */ |
| 1712 | static struct omap_hwmod_irq_info omap2420_mcspi1_mpu_irqs[] = { |
| 1713 | { .irq = 65 }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame^] | 1714 | { .irq = -1 } |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 1715 | }; |
| 1716 | |
| 1717 | static struct omap_hwmod_dma_info omap2420_mcspi1_sdma_reqs[] = { |
| 1718 | { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */ |
| 1719 | { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */ |
| 1720 | { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */ |
| 1721 | { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */ |
| 1722 | { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */ |
| 1723 | { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */ |
| 1724 | { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */ |
| 1725 | { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */ |
| 1726 | }; |
| 1727 | |
| 1728 | static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = { |
| 1729 | &omap2420_l4_core__mcspi1, |
| 1730 | }; |
| 1731 | |
| 1732 | static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { |
| 1733 | .num_chipselect = 4, |
| 1734 | }; |
| 1735 | |
| 1736 | static struct omap_hwmod omap2420_mcspi1_hwmod = { |
| 1737 | .name = "mcspi1_hwmod", |
| 1738 | .mpu_irqs = omap2420_mcspi1_mpu_irqs, |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 1739 | .sdma_reqs = omap2420_mcspi1_sdma_reqs, |
| 1740 | .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi1_sdma_reqs), |
| 1741 | .main_clk = "mcspi1_fck", |
| 1742 | .prcm = { |
| 1743 | .omap2 = { |
| 1744 | .module_offs = CORE_MOD, |
| 1745 | .prcm_reg_id = 1, |
| 1746 | .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, |
| 1747 | .idlest_reg_id = 1, |
| 1748 | .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, |
| 1749 | }, |
| 1750 | }, |
| 1751 | .slaves = omap2420_mcspi1_slaves, |
| 1752 | .slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves), |
| 1753 | .class = &omap2420_mcspi_class, |
| 1754 | .dev_attr = &omap_mcspi1_dev_attr, |
| 1755 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1756 | }; |
| 1757 | |
| 1758 | /* mcspi2 */ |
| 1759 | static struct omap_hwmod_irq_info omap2420_mcspi2_mpu_irqs[] = { |
| 1760 | { .irq = 66 }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame^] | 1761 | { .irq = -1 } |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 1762 | }; |
| 1763 | |
| 1764 | static struct omap_hwmod_dma_info omap2420_mcspi2_sdma_reqs[] = { |
| 1765 | { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */ |
| 1766 | { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */ |
| 1767 | { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */ |
| 1768 | { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */ |
| 1769 | }; |
| 1770 | |
| 1771 | static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = { |
| 1772 | &omap2420_l4_core__mcspi2, |
| 1773 | }; |
| 1774 | |
| 1775 | static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { |
| 1776 | .num_chipselect = 2, |
| 1777 | }; |
| 1778 | |
| 1779 | static struct omap_hwmod omap2420_mcspi2_hwmod = { |
| 1780 | .name = "mcspi2_hwmod", |
| 1781 | .mpu_irqs = omap2420_mcspi2_mpu_irqs, |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 1782 | .sdma_reqs = omap2420_mcspi2_sdma_reqs, |
| 1783 | .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi2_sdma_reqs), |
| 1784 | .main_clk = "mcspi2_fck", |
| 1785 | .prcm = { |
| 1786 | .omap2 = { |
| 1787 | .module_offs = CORE_MOD, |
| 1788 | .prcm_reg_id = 1, |
| 1789 | .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, |
| 1790 | .idlest_reg_id = 1, |
| 1791 | .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, |
| 1792 | }, |
| 1793 | }, |
| 1794 | .slaves = omap2420_mcspi2_slaves, |
| 1795 | .slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves), |
| 1796 | .class = &omap2420_mcspi_class, |
| 1797 | .dev_attr = &omap_mcspi2_dev_attr, |
| 1798 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1799 | }; |
| 1800 | |
Charulatha V | 3cb72fa | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 1801 | /* |
| 1802 | * 'mcbsp' class |
| 1803 | * multi channel buffered serial port controller |
| 1804 | */ |
| 1805 | |
| 1806 | static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = { |
| 1807 | .name = "mcbsp", |
| 1808 | }; |
| 1809 | |
| 1810 | /* mcbsp1 */ |
| 1811 | static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { |
| 1812 | { .name = "tx", .irq = 59 }, |
| 1813 | { .name = "rx", .irq = 60 }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame^] | 1814 | { .irq = -1 } |
Charulatha V | 3cb72fa | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 1815 | }; |
| 1816 | |
| 1817 | static struct omap_hwmod_dma_info omap2420_mcbsp1_sdma_chs[] = { |
| 1818 | { .name = "rx", .dma_req = 32 }, |
| 1819 | { .name = "tx", .dma_req = 31 }, |
| 1820 | }; |
| 1821 | |
Charulatha V | 3cb72fa | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 1822 | /* l4_core -> mcbsp1 */ |
| 1823 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = { |
| 1824 | .master = &omap2420_l4_core_hwmod, |
| 1825 | .slave = &omap2420_mcbsp1_hwmod, |
| 1826 | .clk = "mcbsp1_ick", |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 1827 | .addr = omap2_mcbsp1_addrs, |
Charulatha V | 3cb72fa | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 1828 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1829 | }; |
| 1830 | |
| 1831 | /* mcbsp1 slave ports */ |
| 1832 | static struct omap_hwmod_ocp_if *omap2420_mcbsp1_slaves[] = { |
| 1833 | &omap2420_l4_core__mcbsp1, |
| 1834 | }; |
| 1835 | |
| 1836 | static struct omap_hwmod omap2420_mcbsp1_hwmod = { |
| 1837 | .name = "mcbsp1", |
| 1838 | .class = &omap2420_mcbsp_hwmod_class, |
| 1839 | .mpu_irqs = omap2420_mcbsp1_irqs, |
Charulatha V | 3cb72fa | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 1840 | .sdma_reqs = omap2420_mcbsp1_sdma_chs, |
| 1841 | .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcbsp1_sdma_chs), |
| 1842 | .main_clk = "mcbsp1_fck", |
| 1843 | .prcm = { |
| 1844 | .omap2 = { |
| 1845 | .prcm_reg_id = 1, |
| 1846 | .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, |
| 1847 | .module_offs = CORE_MOD, |
| 1848 | .idlest_reg_id = 1, |
| 1849 | .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, |
| 1850 | }, |
| 1851 | }, |
| 1852 | .slaves = omap2420_mcbsp1_slaves, |
| 1853 | .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp1_slaves), |
| 1854 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1855 | }; |
| 1856 | |
| 1857 | /* mcbsp2 */ |
| 1858 | static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = { |
| 1859 | { .name = "tx", .irq = 62 }, |
| 1860 | { .name = "rx", .irq = 63 }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame^] | 1861 | { .irq = -1 } |
Charulatha V | 3cb72fa | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 1862 | }; |
| 1863 | |
| 1864 | static struct omap_hwmod_dma_info omap2420_mcbsp2_sdma_chs[] = { |
| 1865 | { .name = "rx", .dma_req = 34 }, |
| 1866 | { .name = "tx", .dma_req = 33 }, |
| 1867 | }; |
| 1868 | |
Charulatha V | 3cb72fa | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 1869 | /* l4_core -> mcbsp2 */ |
| 1870 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = { |
| 1871 | .master = &omap2420_l4_core_hwmod, |
| 1872 | .slave = &omap2420_mcbsp2_hwmod, |
| 1873 | .clk = "mcbsp2_ick", |
Paul Walmsley | ded1138 | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 1874 | .addr = omap2xxx_mcbsp2_addrs, |
Charulatha V | 3cb72fa | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 1875 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1876 | }; |
| 1877 | |
| 1878 | /* mcbsp2 slave ports */ |
| 1879 | static struct omap_hwmod_ocp_if *omap2420_mcbsp2_slaves[] = { |
| 1880 | &omap2420_l4_core__mcbsp2, |
| 1881 | }; |
| 1882 | |
| 1883 | static struct omap_hwmod omap2420_mcbsp2_hwmod = { |
| 1884 | .name = "mcbsp2", |
| 1885 | .class = &omap2420_mcbsp_hwmod_class, |
| 1886 | .mpu_irqs = omap2420_mcbsp2_irqs, |
Charulatha V | 3cb72fa | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 1887 | .sdma_reqs = omap2420_mcbsp2_sdma_chs, |
| 1888 | .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcbsp2_sdma_chs), |
| 1889 | .main_clk = "mcbsp2_fck", |
| 1890 | .prcm = { |
| 1891 | .omap2 = { |
| 1892 | .prcm_reg_id = 1, |
| 1893 | .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, |
| 1894 | .module_offs = CORE_MOD, |
| 1895 | .idlest_reg_id = 1, |
| 1896 | .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, |
| 1897 | }, |
| 1898 | }, |
| 1899 | .slaves = omap2420_mcbsp2_slaves, |
| 1900 | .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp2_slaves), |
| 1901 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1902 | }; |
| 1903 | |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 1904 | static __initdata struct omap_hwmod *omap2420_hwmods[] = { |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 1905 | &omap2420_l3_main_hwmod, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 1906 | &omap2420_l4_core_hwmod, |
| 1907 | &omap2420_l4_wkup_hwmod, |
| 1908 | &omap2420_mpu_hwmod, |
Paul Walmsley | 08072ac | 2010-07-26 16:34:33 -0600 | [diff] [blame] | 1909 | &omap2420_iva_hwmod, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 1910 | |
| 1911 | &omap2420_timer1_hwmod, |
| 1912 | &omap2420_timer2_hwmod, |
| 1913 | &omap2420_timer3_hwmod, |
| 1914 | &omap2420_timer4_hwmod, |
| 1915 | &omap2420_timer5_hwmod, |
| 1916 | &omap2420_timer6_hwmod, |
| 1917 | &omap2420_timer7_hwmod, |
| 1918 | &omap2420_timer8_hwmod, |
| 1919 | &omap2420_timer9_hwmod, |
| 1920 | &omap2420_timer10_hwmod, |
| 1921 | &omap2420_timer11_hwmod, |
| 1922 | &omap2420_timer12_hwmod, |
| 1923 | |
Varadarajan, Charulatha | a714b9c | 2010-09-23 20:02:39 +0530 | [diff] [blame] | 1924 | &omap2420_wd_timer2_hwmod, |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 1925 | &omap2420_uart1_hwmod, |
| 1926 | &omap2420_uart2_hwmod, |
| 1927 | &omap2420_uart3_hwmod, |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 1928 | /* dss class */ |
| 1929 | &omap2420_dss_core_hwmod, |
| 1930 | &omap2420_dss_dispc_hwmod, |
| 1931 | &omap2420_dss_rfbi_hwmod, |
| 1932 | &omap2420_dss_venc_hwmod, |
| 1933 | /* i2c class */ |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 1934 | &omap2420_i2c1_hwmod, |
| 1935 | &omap2420_i2c2_hwmod, |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 1936 | |
| 1937 | /* gpio class */ |
| 1938 | &omap2420_gpio1_hwmod, |
| 1939 | &omap2420_gpio2_hwmod, |
| 1940 | &omap2420_gpio3_hwmod, |
| 1941 | &omap2420_gpio4_hwmod, |
G, Manjunath Kondaiah | 745685df9 | 2010-12-20 18:27:18 -0800 | [diff] [blame] | 1942 | |
| 1943 | /* dma_system class*/ |
| 1944 | &omap2420_dma_system_hwmod, |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 1945 | |
Omar Ramirez Luna | fca1ab5 | 2011-02-24 12:51:32 -0800 | [diff] [blame] | 1946 | /* mailbox class */ |
| 1947 | &omap2420_mailbox_hwmod, |
| 1948 | |
Charulatha V | 3cb72fa | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 1949 | /* mcbsp class */ |
| 1950 | &omap2420_mcbsp1_hwmod, |
| 1951 | &omap2420_mcbsp2_hwmod, |
| 1952 | |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 1953 | /* mcspi class */ |
| 1954 | &omap2420_mcspi1_hwmod, |
| 1955 | &omap2420_mcspi2_hwmod, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 1956 | NULL, |
| 1957 | }; |
| 1958 | |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 1959 | int __init omap2420_hwmod_init(void) |
| 1960 | { |
Paul Walmsley | 550c809 | 2011-02-28 11:58:14 -0700 | [diff] [blame] | 1961 | return omap_hwmod_register(omap2420_hwmods); |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 1962 | } |