Keshavamurthy, Anil S | 10e5247 | 2007-10-21 16:41:41 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2006, Intel Corporation. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms and conditions of the GNU General Public License, |
| 6 | * version 2, as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 11 | * more details. |
| 12 | * |
| 13 | * You should have received a copy of the GNU General Public License along with |
| 14 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple |
| 15 | * Place - Suite 330, Boston, MA 02111-1307 USA. |
| 16 | * |
| 17 | * Copyright (C) Ashok Raj <ashok.raj@intel.com> |
| 18 | * Copyright (C) Shaohua Li <shaohua.li@intel.com> |
| 19 | */ |
| 20 | |
| 21 | #ifndef __DMAR_H__ |
| 22 | #define __DMAR_H__ |
| 23 | |
| 24 | #include <linux/acpi.h> |
| 25 | #include <linux/types.h> |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 26 | #include <linux/msi.h> |
Suresh Siddha | 1531a6a | 2009-03-16 17:04:57 -0700 | [diff] [blame] | 27 | #include <linux/irqreturn.h> |
Jiang Liu | 3a5670e | 2014-02-19 14:07:33 +0800 | [diff] [blame] | 28 | #include <linux/rwsem.h> |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame^] | 29 | #include <linux/rcupdate.h> |
Keshavamurthy, Anil S | 10e5247 | 2007-10-21 16:41:41 -0700 | [diff] [blame] | 30 | |
Andrew Morton | 6eea69d | 2011-10-31 17:06:29 -0700 | [diff] [blame] | 31 | struct acpi_dmar_header; |
| 32 | |
Suresh Siddha | 41750d3 | 2011-08-23 17:05:18 -0700 | [diff] [blame] | 33 | /* DMAR Flags */ |
| 34 | #define DMAR_INTR_REMAP 0x1 |
| 35 | #define DMAR_X2APIC_OPT_OUT 0x2 |
| 36 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 37 | struct intel_iommu; |
Jiang Liu | 694835d | 2014-01-06 14:18:16 +0800 | [diff] [blame] | 38 | |
Suresh Siddha | d3f1381 | 2011-08-23 17:05:25 -0700 | [diff] [blame] | 39 | #ifdef CONFIG_DMAR_TABLE |
Suresh Siddha | 41750d3 | 2011-08-23 17:05:18 -0700 | [diff] [blame] | 40 | extern struct acpi_table_header *dmar_tbl; |
Keshavamurthy, Anil S | 10e5247 | 2007-10-21 16:41:41 -0700 | [diff] [blame] | 41 | struct dmar_drhd_unit { |
| 42 | struct list_head list; /* list of drhd units */ |
Suresh Siddha | 1886e8a | 2008-07-10 11:16:37 -0700 | [diff] [blame] | 43 | struct acpi_dmar_header *hdr; /* ACPI header */ |
Keshavamurthy, Anil S | 10e5247 | 2007-10-21 16:41:41 -0700 | [diff] [blame] | 44 | u64 reg_base_addr; /* register base address*/ |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame^] | 45 | struct pci_dev __rcu **devices;/* target device array */ |
Keshavamurthy, Anil S | 10e5247 | 2007-10-21 16:41:41 -0700 | [diff] [blame] | 46 | int devices_cnt; /* target device count */ |
David Woodhouse | 276dbf99 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 47 | u16 segment; /* PCI domain */ |
Keshavamurthy, Anil S | 10e5247 | 2007-10-21 16:41:41 -0700 | [diff] [blame] | 48 | u8 ignored:1; /* ignore drhd */ |
| 49 | u8 include_all:1; |
| 50 | struct intel_iommu *iommu; |
| 51 | }; |
| 52 | |
Jiang Liu | 3a5670e | 2014-02-19 14:07:33 +0800 | [diff] [blame] | 53 | extern struct rw_semaphore dmar_global_lock; |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 54 | extern struct list_head dmar_drhd_units; |
| 55 | |
| 56 | #define for_each_drhd_unit(drhd) \ |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame^] | 57 | list_for_each_entry_rcu(drhd, &dmar_drhd_units, list) |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 58 | |
Jiang Liu | 7c91977 | 2014-01-06 14:18:18 +0800 | [diff] [blame] | 59 | #define for_each_active_drhd_unit(drhd) \ |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame^] | 60 | list_for_each_entry_rcu(drhd, &dmar_drhd_units, list) \ |
Jiang Liu | 7c91977 | 2014-01-06 14:18:18 +0800 | [diff] [blame] | 61 | if (drhd->ignored) {} else |
| 62 | |
David Woodhouse | 8f912ba | 2009-04-03 15:19:32 +0100 | [diff] [blame] | 63 | #define for_each_active_iommu(i, drhd) \ |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame^] | 64 | list_for_each_entry_rcu(drhd, &dmar_drhd_units, list) \ |
David Woodhouse | 8f912ba | 2009-04-03 15:19:32 +0100 | [diff] [blame] | 65 | if (i=drhd->iommu, drhd->ignored) {} else |
| 66 | |
| 67 | #define for_each_iommu(i, drhd) \ |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame^] | 68 | list_for_each_entry_rcu(drhd, &dmar_drhd_units, list) \ |
David Woodhouse | 8f912ba | 2009-04-03 15:19:32 +0100 | [diff] [blame] | 69 | if (i=drhd->iommu, 0) {} else |
| 70 | |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame^] | 71 | static inline bool dmar_rcu_check(void) |
| 72 | { |
| 73 | return rwsem_is_locked(&dmar_global_lock) || |
| 74 | system_state == SYSTEM_BOOTING; |
| 75 | } |
| 76 | |
| 77 | #define dmar_rcu_dereference(p) rcu_dereference_check((p), dmar_rcu_check()) |
| 78 | |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 79 | #define for_each_dev_scope(a, c, p, d) \ |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame^] | 80 | for ((p) = 0; ((d) = (p) < (c) ? dmar_rcu_dereference((a)[(p)]) : \ |
| 81 | NULL, (p) < (c)); (p)++) |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 82 | |
| 83 | #define for_each_active_dev_scope(a, c, p, d) \ |
| 84 | for_each_dev_scope((a), (c), (p), (d)) if (!(d)) { continue; } else |
| 85 | |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 86 | extern int dmar_table_init(void); |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 87 | extern int dmar_dev_scope_init(void); |
Jiang Liu | ada4d4b | 2014-01-06 14:18:09 +0800 | [diff] [blame] | 88 | extern int dmar_parse_dev_scope(void *start, void *end, int *cnt, |
| 89 | struct pci_dev ***devices, u16 segment); |
Jiang Liu | bb3a6b7 | 2014-02-19 14:07:24 +0800 | [diff] [blame] | 90 | extern void *dmar_alloc_dev_scope(void *start, void *end, int *cnt); |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame^] | 91 | extern void dmar_free_dev_scope(struct pci_dev __rcu ***devices, int *cnt); |
Jiang Liu | ada4d4b | 2014-01-06 14:18:09 +0800 | [diff] [blame] | 92 | extern void dmar_free_dev_scope(struct pci_dev ***devices, int *cnt); |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 93 | |
| 94 | /* Intel IOMMU detection */ |
Konrad Rzeszutek Wilk | 480125b | 2010-08-26 13:57:57 -0400 | [diff] [blame] | 95 | extern int detect_intel_iommu(void); |
Suresh Siddha | 9d783ba | 2009-03-16 17:04:55 -0700 | [diff] [blame] | 96 | extern int enable_drhd_fault_handling(void); |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 97 | #else |
Konrad Rzeszutek Wilk | 480125b | 2010-08-26 13:57:57 -0400 | [diff] [blame] | 98 | static inline int detect_intel_iommu(void) |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 99 | { |
Konrad Rzeszutek Wilk | 480125b | 2010-08-26 13:57:57 -0400 | [diff] [blame] | 100 | return -ENODEV; |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 101 | } |
| 102 | |
| 103 | static inline int dmar_table_init(void) |
| 104 | { |
| 105 | return -ENODEV; |
| 106 | } |
Suresh Siddha | 29b61be | 2009-03-16 17:05:02 -0700 | [diff] [blame] | 107 | static inline int enable_drhd_fault_handling(void) |
| 108 | { |
| 109 | return -1; |
| 110 | } |
Suresh Siddha | d3f1381 | 2011-08-23 17:05:25 -0700 | [diff] [blame] | 111 | #endif /* !CONFIG_DMAR_TABLE */ |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 112 | |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 113 | struct irte { |
| 114 | union { |
| 115 | struct { |
| 116 | __u64 present : 1, |
| 117 | fpd : 1, |
| 118 | dst_mode : 1, |
| 119 | redir_hint : 1, |
| 120 | trigger_mode : 1, |
| 121 | dlvry_mode : 3, |
| 122 | avail : 4, |
| 123 | __reserved_1 : 4, |
| 124 | vector : 8, |
| 125 | __reserved_2 : 8, |
| 126 | dest_id : 32; |
| 127 | }; |
| 128 | __u64 low; |
| 129 | }; |
| 130 | |
| 131 | union { |
| 132 | struct { |
| 133 | __u64 sid : 16, |
| 134 | sq : 2, |
| 135 | svt : 2, |
| 136 | __reserved_3 : 44; |
| 137 | }; |
| 138 | __u64 high; |
| 139 | }; |
| 140 | }; |
Thomas Gleixner | 423f085 | 2010-10-10 11:39:09 +0200 | [diff] [blame] | 141 | |
Suresh Siddha | 41750d3 | 2011-08-23 17:05:18 -0700 | [diff] [blame] | 142 | enum { |
| 143 | IRQ_REMAP_XAPIC_MODE, |
| 144 | IRQ_REMAP_X2APIC_MODE, |
| 145 | }; |
| 146 | |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 147 | /* Can't use the common MSI interrupt functions |
| 148 | * since DMAR is not a pci device |
| 149 | */ |
Thomas Gleixner | 5c2837f | 2010-09-28 17:15:11 +0200 | [diff] [blame] | 150 | struct irq_data; |
| 151 | extern void dmar_msi_unmask(struct irq_data *data); |
| 152 | extern void dmar_msi_mask(struct irq_data *data); |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 153 | extern void dmar_msi_read(int irq, struct msi_msg *msg); |
| 154 | extern void dmar_msi_write(int irq, struct msi_msg *msg); |
| 155 | extern int dmar_set_interrupt(struct intel_iommu *iommu); |
Suresh Siddha | 1531a6a | 2009-03-16 17:04:57 -0700 | [diff] [blame] | 156 | extern irqreturn_t dmar_fault(int irq, void *dev_id); |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 157 | extern int arch_setup_dmar_msi(unsigned int irq); |
| 158 | |
Suresh Siddha | d3f1381 | 2011-08-23 17:05:25 -0700 | [diff] [blame] | 159 | #ifdef CONFIG_INTEL_IOMMU |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 160 | extern int iommu_detected, no_iommu; |
Jiang Liu | b94e411 | 2014-02-19 14:07:25 +0800 | [diff] [blame] | 161 | extern int dmar_parse_rmrr_atsr_dev(void); |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 162 | extern int dmar_parse_one_rmrr(struct acpi_dmar_header *header); |
| 163 | extern int dmar_parse_one_atsr(struct acpi_dmar_header *header); |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 164 | extern int intel_iommu_init(void); |
Suresh Siddha | d3f1381 | 2011-08-23 17:05:25 -0700 | [diff] [blame] | 165 | #else /* !CONFIG_INTEL_IOMMU: */ |
FUJITA Tomonori | 9d5ce73 | 2009-11-10 19:46:16 +0900 | [diff] [blame] | 166 | static inline int intel_iommu_init(void) { return -ENODEV; } |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 167 | static inline int dmar_parse_one_rmrr(struct acpi_dmar_header *header) |
| 168 | { |
| 169 | return 0; |
| 170 | } |
| 171 | static inline int dmar_parse_one_atsr(struct acpi_dmar_header *header) |
| 172 | { |
| 173 | return 0; |
| 174 | } |
| 175 | static inline int dmar_parse_rmrr_atsr_dev(void) |
| 176 | { |
| 177 | return 0; |
| 178 | } |
Suresh Siddha | d3f1381 | 2011-08-23 17:05:25 -0700 | [diff] [blame] | 179 | #endif /* CONFIG_INTEL_IOMMU */ |
FUJITA Tomonori | 9d5ce73 | 2009-11-10 19:46:16 +0900 | [diff] [blame] | 180 | |
Keshavamurthy, Anil S | 10e5247 | 2007-10-21 16:41:41 -0700 | [diff] [blame] | 181 | #endif /* __DMAR_H__ */ |