Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 1 | #undef DEBUG |
| 2 | |
| 3 | /* |
| 4 | * ARM performance counter support. |
| 5 | * |
| 6 | * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 7 | * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com> |
Jean PIHET | 796d129 | 2010-01-26 18:51:05 +0100 | [diff] [blame] | 8 | * |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 9 | * This code is based on the sparc64 perf event code, which is in turn based |
| 10 | * on the x86 code. Callchain code is based on the ARM OProfile backtrace |
| 11 | * code. |
| 12 | */ |
| 13 | #define pr_fmt(fmt) "hw perfevents: " fmt |
| 14 | |
| 15 | #include <linux/interrupt.h> |
| 16 | #include <linux/kernel.h> |
Will Deacon | 181193f | 2010-04-30 11:32:44 +0100 | [diff] [blame] | 17 | #include <linux/module.h> |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 18 | #include <linux/perf_event.h> |
Will Deacon | 49c006b | 2010-04-29 17:13:24 +0100 | [diff] [blame] | 19 | #include <linux/platform_device.h> |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 20 | #include <linux/spinlock.h> |
| 21 | #include <linux/uaccess.h> |
| 22 | |
| 23 | #include <asm/cputype.h> |
| 24 | #include <asm/irq.h> |
| 25 | #include <asm/irq_regs.h> |
| 26 | #include <asm/pmu.h> |
| 27 | #include <asm/stacktrace.h> |
| 28 | |
Will Deacon | 49c006b | 2010-04-29 17:13:24 +0100 | [diff] [blame] | 29 | static struct platform_device *pmu_device; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 30 | |
| 31 | /* |
| 32 | * Hardware lock to serialize accesses to PMU registers. Needed for the |
| 33 | * read/modify/write sequences. |
| 34 | */ |
Will Deacon | 961ec6da | 2010-12-02 18:01:49 +0100 | [diff] [blame] | 35 | static DEFINE_RAW_SPINLOCK(pmu_lock); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 36 | |
| 37 | /* |
| 38 | * ARMv6 supports a maximum of 3 events, starting from index 1. If we add |
| 39 | * another platform that supports more, we need to increase this to be the |
| 40 | * largest of all platforms. |
Jean PIHET | 796d129 | 2010-01-26 18:51:05 +0100 | [diff] [blame] | 41 | * |
| 42 | * ARMv7 supports up to 32 events: |
| 43 | * cycle counter CCNT + 31 events counters CNT0..30. |
| 44 | * Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters. |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 45 | */ |
Jean PIHET | 796d129 | 2010-01-26 18:51:05 +0100 | [diff] [blame] | 46 | #define ARMPMU_MAX_HWEVENTS 33 |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 47 | |
| 48 | /* The events for a given CPU. */ |
| 49 | struct cpu_hw_events { |
| 50 | /* |
| 51 | * The events that are active on the CPU for the given index. Index 0 |
| 52 | * is reserved. |
| 53 | */ |
| 54 | struct perf_event *events[ARMPMU_MAX_HWEVENTS]; |
| 55 | |
| 56 | /* |
| 57 | * A 1 bit for an index indicates that the counter is being used for |
| 58 | * an event. A 0 means that the counter can be used. |
| 59 | */ |
| 60 | unsigned long used_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)]; |
| 61 | |
| 62 | /* |
| 63 | * A 1 bit for an index indicates that the counter is actively being |
| 64 | * used. |
| 65 | */ |
| 66 | unsigned long active_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)]; |
| 67 | }; |
Will Deacon | 4d6b7a7 | 2010-11-30 18:15:53 +0100 | [diff] [blame] | 68 | static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); |
Will Deacon | 181193f | 2010-04-30 11:32:44 +0100 | [diff] [blame] | 69 | |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 70 | struct arm_pmu { |
Will Deacon | 181193f | 2010-04-30 11:32:44 +0100 | [diff] [blame] | 71 | enum arm_perf_pmu_ids id; |
Will Deacon | 6299483 | 2010-11-13 18:45:27 +0000 | [diff] [blame] | 72 | const char *name; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 73 | irqreturn_t (*handle_irq)(int irq_num, void *dev); |
| 74 | void (*enable)(struct hw_perf_event *evt, int idx); |
| 75 | void (*disable)(struct hw_perf_event *evt, int idx); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 76 | int (*get_event_idx)(struct cpu_hw_events *cpuc, |
| 77 | struct hw_perf_event *hwc); |
| 78 | u32 (*read_counter)(int idx); |
| 79 | void (*write_counter)(int idx, u32 val); |
| 80 | void (*start)(void); |
| 81 | void (*stop)(void); |
Will Deacon | 84fee97 | 2010-11-13 17:13:56 +0000 | [diff] [blame] | 82 | const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX] |
| 83 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 84 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; |
| 85 | const unsigned (*event_map)[PERF_COUNT_HW_MAX]; |
| 86 | u32 raw_event_mask; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 87 | int num_events; |
| 88 | u64 max_period; |
| 89 | }; |
| 90 | |
| 91 | /* Set at runtime when we know what CPU type we are. */ |
| 92 | static const struct arm_pmu *armpmu; |
| 93 | |
Will Deacon | 181193f | 2010-04-30 11:32:44 +0100 | [diff] [blame] | 94 | enum arm_perf_pmu_ids |
| 95 | armpmu_get_pmu_id(void) |
| 96 | { |
| 97 | int id = -ENODEV; |
| 98 | |
| 99 | if (armpmu != NULL) |
| 100 | id = armpmu->id; |
| 101 | |
| 102 | return id; |
| 103 | } |
| 104 | EXPORT_SYMBOL_GPL(armpmu_get_pmu_id); |
| 105 | |
Will Deacon | 929f519 | 2010-04-30 11:34:26 +0100 | [diff] [blame] | 106 | int |
| 107 | armpmu_get_max_events(void) |
| 108 | { |
| 109 | int max_events = 0; |
| 110 | |
| 111 | if (armpmu != NULL) |
| 112 | max_events = armpmu->num_events; |
| 113 | |
| 114 | return max_events; |
| 115 | } |
| 116 | EXPORT_SYMBOL_GPL(armpmu_get_max_events); |
| 117 | |
Matt Fleming | 3bf101b | 2010-09-27 20:22:24 +0100 | [diff] [blame] | 118 | int perf_num_counters(void) |
| 119 | { |
| 120 | return armpmu_get_max_events(); |
| 121 | } |
| 122 | EXPORT_SYMBOL_GPL(perf_num_counters); |
| 123 | |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 124 | #define HW_OP_UNSUPPORTED 0xFFFF |
| 125 | |
| 126 | #define C(_x) \ |
| 127 | PERF_COUNT_HW_CACHE_##_x |
| 128 | |
| 129 | #define CACHE_OP_UNSUPPORTED 0xFFFF |
| 130 | |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 131 | static int |
| 132 | armpmu_map_cache_event(u64 config) |
| 133 | { |
| 134 | unsigned int cache_type, cache_op, cache_result, ret; |
| 135 | |
| 136 | cache_type = (config >> 0) & 0xff; |
| 137 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) |
| 138 | return -EINVAL; |
| 139 | |
| 140 | cache_op = (config >> 8) & 0xff; |
| 141 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) |
| 142 | return -EINVAL; |
| 143 | |
| 144 | cache_result = (config >> 16) & 0xff; |
| 145 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) |
| 146 | return -EINVAL; |
| 147 | |
Will Deacon | 84fee97 | 2010-11-13 17:13:56 +0000 | [diff] [blame] | 148 | ret = (int)(*armpmu->cache_map)[cache_type][cache_op][cache_result]; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 149 | |
| 150 | if (ret == CACHE_OP_UNSUPPORTED) |
| 151 | return -ENOENT; |
| 152 | |
| 153 | return ret; |
| 154 | } |
| 155 | |
| 156 | static int |
Will Deacon | 84fee97 | 2010-11-13 17:13:56 +0000 | [diff] [blame] | 157 | armpmu_map_event(u64 config) |
| 158 | { |
| 159 | int mapping = (*armpmu->event_map)[config]; |
| 160 | return mapping == HW_OP_UNSUPPORTED ? -EOPNOTSUPP : mapping; |
| 161 | } |
| 162 | |
| 163 | static int |
| 164 | armpmu_map_raw_event(u64 config) |
| 165 | { |
| 166 | return (int)(config & armpmu->raw_event_mask); |
| 167 | } |
| 168 | |
| 169 | static int |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 170 | armpmu_event_set_period(struct perf_event *event, |
| 171 | struct hw_perf_event *hwc, |
| 172 | int idx) |
| 173 | { |
Peter Zijlstra | e785059 | 2010-05-21 14:43:08 +0200 | [diff] [blame] | 174 | s64 left = local64_read(&hwc->period_left); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 175 | s64 period = hwc->sample_period; |
| 176 | int ret = 0; |
| 177 | |
| 178 | if (unlikely(left <= -period)) { |
| 179 | left = period; |
Peter Zijlstra | e785059 | 2010-05-21 14:43:08 +0200 | [diff] [blame] | 180 | local64_set(&hwc->period_left, left); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 181 | hwc->last_period = period; |
| 182 | ret = 1; |
| 183 | } |
| 184 | |
| 185 | if (unlikely(left <= 0)) { |
| 186 | left += period; |
Peter Zijlstra | e785059 | 2010-05-21 14:43:08 +0200 | [diff] [blame] | 187 | local64_set(&hwc->period_left, left); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 188 | hwc->last_period = period; |
| 189 | ret = 1; |
| 190 | } |
| 191 | |
| 192 | if (left > (s64)armpmu->max_period) |
| 193 | left = armpmu->max_period; |
| 194 | |
Peter Zijlstra | e785059 | 2010-05-21 14:43:08 +0200 | [diff] [blame] | 195 | local64_set(&hwc->prev_count, (u64)-left); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 196 | |
| 197 | armpmu->write_counter(idx, (u64)(-left) & 0xffffffff); |
| 198 | |
| 199 | perf_event_update_userpage(event); |
| 200 | |
| 201 | return ret; |
| 202 | } |
| 203 | |
| 204 | static u64 |
| 205 | armpmu_event_update(struct perf_event *event, |
| 206 | struct hw_perf_event *hwc, |
| 207 | int idx) |
| 208 | { |
| 209 | int shift = 64 - 32; |
| 210 | s64 prev_raw_count, new_raw_count; |
Will Deacon | 446a5a8 | 2010-07-02 16:41:52 +0100 | [diff] [blame] | 211 | u64 delta; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 212 | |
| 213 | again: |
Peter Zijlstra | e785059 | 2010-05-21 14:43:08 +0200 | [diff] [blame] | 214 | prev_raw_count = local64_read(&hwc->prev_count); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 215 | new_raw_count = armpmu->read_counter(idx); |
| 216 | |
Peter Zijlstra | e785059 | 2010-05-21 14:43:08 +0200 | [diff] [blame] | 217 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 218 | new_raw_count) != prev_raw_count) |
| 219 | goto again; |
| 220 | |
| 221 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
| 222 | delta >>= shift; |
| 223 | |
Peter Zijlstra | e785059 | 2010-05-21 14:43:08 +0200 | [diff] [blame] | 224 | local64_add(delta, &event->count); |
| 225 | local64_sub(delta, &hwc->period_left); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 226 | |
| 227 | return new_raw_count; |
| 228 | } |
| 229 | |
| 230 | static void |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 231 | armpmu_read(struct perf_event *event) |
| 232 | { |
| 233 | struct hw_perf_event *hwc = &event->hw; |
| 234 | |
| 235 | /* Don't read disabled counters! */ |
| 236 | if (hwc->idx < 0) |
| 237 | return; |
| 238 | |
| 239 | armpmu_event_update(event, hwc, hwc->idx); |
| 240 | } |
| 241 | |
| 242 | static void |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 243 | armpmu_stop(struct perf_event *event, int flags) |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 244 | { |
| 245 | struct hw_perf_event *hwc = &event->hw; |
| 246 | |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 247 | if (!armpmu) |
| 248 | return; |
| 249 | |
| 250 | /* |
| 251 | * ARM pmu always has to update the counter, so ignore |
| 252 | * PERF_EF_UPDATE, see comments in armpmu_start(). |
| 253 | */ |
| 254 | if (!(hwc->state & PERF_HES_STOPPED)) { |
| 255 | armpmu->disable(hwc, hwc->idx); |
| 256 | barrier(); /* why? */ |
| 257 | armpmu_event_update(event, hwc, hwc->idx); |
| 258 | hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
| 259 | } |
| 260 | } |
| 261 | |
| 262 | static void |
| 263 | armpmu_start(struct perf_event *event, int flags) |
| 264 | { |
| 265 | struct hw_perf_event *hwc = &event->hw; |
| 266 | |
| 267 | if (!armpmu) |
| 268 | return; |
| 269 | |
| 270 | /* |
| 271 | * ARM pmu always has to reprogram the period, so ignore |
| 272 | * PERF_EF_RELOAD, see the comment below. |
| 273 | */ |
| 274 | if (flags & PERF_EF_RELOAD) |
| 275 | WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); |
| 276 | |
| 277 | hwc->state = 0; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 278 | /* |
| 279 | * Set the period again. Some counters can't be stopped, so when we |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 280 | * were stopped we simply disabled the IRQ source and the counter |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 281 | * may have been left counting. If we don't do this step then we may |
| 282 | * get an interrupt too soon or *way* too late if the overflow has |
| 283 | * happened since disabling. |
| 284 | */ |
| 285 | armpmu_event_set_period(event, hwc, hwc->idx); |
| 286 | armpmu->enable(hwc, hwc->idx); |
| 287 | } |
| 288 | |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 289 | static void |
| 290 | armpmu_del(struct perf_event *event, int flags) |
| 291 | { |
| 292 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 293 | struct hw_perf_event *hwc = &event->hw; |
| 294 | int idx = hwc->idx; |
| 295 | |
| 296 | WARN_ON(idx < 0); |
| 297 | |
| 298 | clear_bit(idx, cpuc->active_mask); |
| 299 | armpmu_stop(event, PERF_EF_UPDATE); |
| 300 | cpuc->events[idx] = NULL; |
| 301 | clear_bit(idx, cpuc->used_mask); |
| 302 | |
| 303 | perf_event_update_userpage(event); |
| 304 | } |
| 305 | |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 306 | static int |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 307 | armpmu_add(struct perf_event *event, int flags) |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 308 | { |
| 309 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 310 | struct hw_perf_event *hwc = &event->hw; |
| 311 | int idx; |
| 312 | int err = 0; |
| 313 | |
Peter Zijlstra | 33696fc | 2010-06-14 08:49:00 +0200 | [diff] [blame] | 314 | perf_pmu_disable(event->pmu); |
Peter Zijlstra | 24cd7f5 | 2010-06-11 17:32:03 +0200 | [diff] [blame] | 315 | |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 316 | /* If we don't have a space for the counter then finish early. */ |
| 317 | idx = armpmu->get_event_idx(cpuc, hwc); |
| 318 | if (idx < 0) { |
| 319 | err = idx; |
| 320 | goto out; |
| 321 | } |
| 322 | |
| 323 | /* |
| 324 | * If there is an event in the counter we are going to use then make |
| 325 | * sure it is disabled. |
| 326 | */ |
| 327 | event->hw.idx = idx; |
| 328 | armpmu->disable(hwc, idx); |
| 329 | cpuc->events[idx] = event; |
| 330 | set_bit(idx, cpuc->active_mask); |
| 331 | |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 332 | hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; |
| 333 | if (flags & PERF_EF_START) |
| 334 | armpmu_start(event, PERF_EF_RELOAD); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 335 | |
| 336 | /* Propagate our changes to the userspace mapping. */ |
| 337 | perf_event_update_userpage(event); |
| 338 | |
| 339 | out: |
Peter Zijlstra | 33696fc | 2010-06-14 08:49:00 +0200 | [diff] [blame] | 340 | perf_pmu_enable(event->pmu); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 341 | return err; |
| 342 | } |
| 343 | |
Peter Zijlstra | b0a873e | 2010-06-11 13:35:08 +0200 | [diff] [blame] | 344 | static struct pmu pmu; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 345 | |
| 346 | static int |
| 347 | validate_event(struct cpu_hw_events *cpuc, |
| 348 | struct perf_event *event) |
| 349 | { |
| 350 | struct hw_perf_event fake_event = event->hw; |
| 351 | |
Will Deacon | 65b4711 | 2010-09-02 09:32:08 +0100 | [diff] [blame] | 352 | if (event->pmu != &pmu || event->state <= PERF_EVENT_STATE_OFF) |
| 353 | return 1; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 354 | |
| 355 | return armpmu->get_event_idx(cpuc, &fake_event) >= 0; |
| 356 | } |
| 357 | |
| 358 | static int |
| 359 | validate_group(struct perf_event *event) |
| 360 | { |
| 361 | struct perf_event *sibling, *leader = event->group_leader; |
| 362 | struct cpu_hw_events fake_pmu; |
| 363 | |
| 364 | memset(&fake_pmu, 0, sizeof(fake_pmu)); |
| 365 | |
| 366 | if (!validate_event(&fake_pmu, leader)) |
| 367 | return -ENOSPC; |
| 368 | |
| 369 | list_for_each_entry(sibling, &leader->sibling_list, group_entry) { |
| 370 | if (!validate_event(&fake_pmu, sibling)) |
| 371 | return -ENOSPC; |
| 372 | } |
| 373 | |
| 374 | if (!validate_event(&fake_pmu, event)) |
| 375 | return -ENOSPC; |
| 376 | |
| 377 | return 0; |
| 378 | } |
| 379 | |
Rabin Vincent | 0e25a5c | 2011-02-08 09:24:36 +0530 | [diff] [blame^] | 380 | static irqreturn_t armpmu_platform_irq(int irq, void *dev) |
| 381 | { |
| 382 | struct arm_pmu_platdata *plat = dev_get_platdata(&pmu_device->dev); |
| 383 | |
| 384 | return plat->handle_irq(irq, dev, armpmu->handle_irq); |
| 385 | } |
| 386 | |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 387 | static int |
| 388 | armpmu_reserve_hardware(void) |
| 389 | { |
Rabin Vincent | 0e25a5c | 2011-02-08 09:24:36 +0530 | [diff] [blame^] | 390 | struct arm_pmu_platdata *plat; |
| 391 | irq_handler_t handle_irq; |
Will Deacon | 49c006b | 2010-04-29 17:13:24 +0100 | [diff] [blame] | 392 | int i, err = -ENODEV, irq; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 393 | |
Will Deacon | 49c006b | 2010-04-29 17:13:24 +0100 | [diff] [blame] | 394 | pmu_device = reserve_pmu(ARM_PMU_DEVICE_CPU); |
| 395 | if (IS_ERR(pmu_device)) { |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 396 | pr_warning("unable to reserve pmu\n"); |
Will Deacon | 49c006b | 2010-04-29 17:13:24 +0100 | [diff] [blame] | 397 | return PTR_ERR(pmu_device); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 398 | } |
| 399 | |
Will Deacon | 49c006b | 2010-04-29 17:13:24 +0100 | [diff] [blame] | 400 | init_pmu(ARM_PMU_DEVICE_CPU); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 401 | |
Rabin Vincent | 0e25a5c | 2011-02-08 09:24:36 +0530 | [diff] [blame^] | 402 | plat = dev_get_platdata(&pmu_device->dev); |
| 403 | if (plat && plat->handle_irq) |
| 404 | handle_irq = armpmu_platform_irq; |
| 405 | else |
| 406 | handle_irq = armpmu->handle_irq; |
| 407 | |
Will Deacon | 49c006b | 2010-04-29 17:13:24 +0100 | [diff] [blame] | 408 | if (pmu_device->num_resources < 1) { |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 409 | pr_err("no irqs for PMUs defined\n"); |
| 410 | return -ENODEV; |
| 411 | } |
| 412 | |
Will Deacon | 49c006b | 2010-04-29 17:13:24 +0100 | [diff] [blame] | 413 | for (i = 0; i < pmu_device->num_resources; ++i) { |
| 414 | irq = platform_get_irq(pmu_device, i); |
| 415 | if (irq < 0) |
| 416 | continue; |
| 417 | |
Rabin Vincent | 0e25a5c | 2011-02-08 09:24:36 +0530 | [diff] [blame^] | 418 | err = request_irq(irq, handle_irq, |
Will Deacon | ddee87f | 2010-02-25 15:04:14 +0100 | [diff] [blame] | 419 | IRQF_DISABLED | IRQF_NOBALANCING, |
| 420 | "armpmu", NULL); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 421 | if (err) { |
Will Deacon | 49c006b | 2010-04-29 17:13:24 +0100 | [diff] [blame] | 422 | pr_warning("unable to request IRQ%d for ARM perf " |
| 423 | "counters\n", irq); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 424 | break; |
| 425 | } |
| 426 | } |
| 427 | |
| 428 | if (err) { |
Will Deacon | 49c006b | 2010-04-29 17:13:24 +0100 | [diff] [blame] | 429 | for (i = i - 1; i >= 0; --i) { |
| 430 | irq = platform_get_irq(pmu_device, i); |
| 431 | if (irq >= 0) |
| 432 | free_irq(irq, NULL); |
| 433 | } |
| 434 | release_pmu(pmu_device); |
| 435 | pmu_device = NULL; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 436 | } |
| 437 | |
| 438 | return err; |
| 439 | } |
| 440 | |
| 441 | static void |
| 442 | armpmu_release_hardware(void) |
| 443 | { |
Will Deacon | 49c006b | 2010-04-29 17:13:24 +0100 | [diff] [blame] | 444 | int i, irq; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 445 | |
Will Deacon | 49c006b | 2010-04-29 17:13:24 +0100 | [diff] [blame] | 446 | for (i = pmu_device->num_resources - 1; i >= 0; --i) { |
| 447 | irq = platform_get_irq(pmu_device, i); |
| 448 | if (irq >= 0) |
| 449 | free_irq(irq, NULL); |
| 450 | } |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 451 | armpmu->stop(); |
| 452 | |
Will Deacon | 49c006b | 2010-04-29 17:13:24 +0100 | [diff] [blame] | 453 | release_pmu(pmu_device); |
| 454 | pmu_device = NULL; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 455 | } |
| 456 | |
| 457 | static atomic_t active_events = ATOMIC_INIT(0); |
| 458 | static DEFINE_MUTEX(pmu_reserve_mutex); |
| 459 | |
| 460 | static void |
| 461 | hw_perf_event_destroy(struct perf_event *event) |
| 462 | { |
| 463 | if (atomic_dec_and_mutex_lock(&active_events, &pmu_reserve_mutex)) { |
| 464 | armpmu_release_hardware(); |
| 465 | mutex_unlock(&pmu_reserve_mutex); |
| 466 | } |
| 467 | } |
| 468 | |
| 469 | static int |
| 470 | __hw_perf_event_init(struct perf_event *event) |
| 471 | { |
| 472 | struct hw_perf_event *hwc = &event->hw; |
| 473 | int mapping, err; |
| 474 | |
| 475 | /* Decode the generic type into an ARM event identifier. */ |
| 476 | if (PERF_TYPE_HARDWARE == event->attr.type) { |
Will Deacon | 84fee97 | 2010-11-13 17:13:56 +0000 | [diff] [blame] | 477 | mapping = armpmu_map_event(event->attr.config); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 478 | } else if (PERF_TYPE_HW_CACHE == event->attr.type) { |
| 479 | mapping = armpmu_map_cache_event(event->attr.config); |
| 480 | } else if (PERF_TYPE_RAW == event->attr.type) { |
Will Deacon | 84fee97 | 2010-11-13 17:13:56 +0000 | [diff] [blame] | 481 | mapping = armpmu_map_raw_event(event->attr.config); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 482 | } else { |
| 483 | pr_debug("event type %x not supported\n", event->attr.type); |
| 484 | return -EOPNOTSUPP; |
| 485 | } |
| 486 | |
| 487 | if (mapping < 0) { |
| 488 | pr_debug("event %x:%llx not supported\n", event->attr.type, |
| 489 | event->attr.config); |
| 490 | return mapping; |
| 491 | } |
| 492 | |
| 493 | /* |
| 494 | * Check whether we need to exclude the counter from certain modes. |
| 495 | * The ARM performance counters are on all of the time so if someone |
| 496 | * has asked us for some excludes then we have to fail. |
| 497 | */ |
| 498 | if (event->attr.exclude_kernel || event->attr.exclude_user || |
| 499 | event->attr.exclude_hv || event->attr.exclude_idle) { |
| 500 | pr_debug("ARM performance counters do not support " |
| 501 | "mode exclusion\n"); |
| 502 | return -EPERM; |
| 503 | } |
| 504 | |
| 505 | /* |
| 506 | * We don't assign an index until we actually place the event onto |
| 507 | * hardware. Use -1 to signify that we haven't decided where to put it |
| 508 | * yet. For SMP systems, each core has it's own PMU so we can't do any |
| 509 | * clever allocation or constraints checking at this point. |
| 510 | */ |
| 511 | hwc->idx = -1; |
| 512 | |
| 513 | /* |
| 514 | * Store the event encoding into the config_base field. config and |
| 515 | * event_base are unused as the only 2 things we need to know are |
| 516 | * the event mapping and the counter to use. The counter to use is |
| 517 | * also the indx and the config_base is the event type. |
| 518 | */ |
| 519 | hwc->config_base = (unsigned long)mapping; |
| 520 | hwc->config = 0; |
| 521 | hwc->event_base = 0; |
| 522 | |
| 523 | if (!hwc->sample_period) { |
| 524 | hwc->sample_period = armpmu->max_period; |
| 525 | hwc->last_period = hwc->sample_period; |
Peter Zijlstra | e785059 | 2010-05-21 14:43:08 +0200 | [diff] [blame] | 526 | local64_set(&hwc->period_left, hwc->sample_period); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 527 | } |
| 528 | |
| 529 | err = 0; |
| 530 | if (event->group_leader != event) { |
| 531 | err = validate_group(event); |
| 532 | if (err) |
| 533 | return -EINVAL; |
| 534 | } |
| 535 | |
| 536 | return err; |
| 537 | } |
| 538 | |
Peter Zijlstra | b0a873e | 2010-06-11 13:35:08 +0200 | [diff] [blame] | 539 | static int armpmu_event_init(struct perf_event *event) |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 540 | { |
| 541 | int err = 0; |
| 542 | |
Peter Zijlstra | b0a873e | 2010-06-11 13:35:08 +0200 | [diff] [blame] | 543 | switch (event->attr.type) { |
| 544 | case PERF_TYPE_RAW: |
| 545 | case PERF_TYPE_HARDWARE: |
| 546 | case PERF_TYPE_HW_CACHE: |
| 547 | break; |
| 548 | |
| 549 | default: |
| 550 | return -ENOENT; |
| 551 | } |
| 552 | |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 553 | if (!armpmu) |
Peter Zijlstra | b0a873e | 2010-06-11 13:35:08 +0200 | [diff] [blame] | 554 | return -ENODEV; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 555 | |
| 556 | event->destroy = hw_perf_event_destroy; |
| 557 | |
| 558 | if (!atomic_inc_not_zero(&active_events)) { |
Ingo Molnar | 1efeb08 | 2010-10-14 08:09:42 +0200 | [diff] [blame] | 559 | if (atomic_read(&active_events) > armpmu->num_events) { |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 560 | atomic_dec(&active_events); |
Peter Zijlstra | b0a873e | 2010-06-11 13:35:08 +0200 | [diff] [blame] | 561 | return -ENOSPC; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 562 | } |
| 563 | |
| 564 | mutex_lock(&pmu_reserve_mutex); |
| 565 | if (atomic_read(&active_events) == 0) { |
| 566 | err = armpmu_reserve_hardware(); |
| 567 | } |
| 568 | |
| 569 | if (!err) |
| 570 | atomic_inc(&active_events); |
| 571 | mutex_unlock(&pmu_reserve_mutex); |
| 572 | } |
| 573 | |
| 574 | if (err) |
Peter Zijlstra | b0a873e | 2010-06-11 13:35:08 +0200 | [diff] [blame] | 575 | return err; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 576 | |
| 577 | err = __hw_perf_event_init(event); |
| 578 | if (err) |
| 579 | hw_perf_event_destroy(event); |
| 580 | |
Peter Zijlstra | b0a873e | 2010-06-11 13:35:08 +0200 | [diff] [blame] | 581 | return err; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 582 | } |
| 583 | |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 584 | static void armpmu_enable(struct pmu *pmu) |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 585 | { |
| 586 | /* Enable all of the perf events on hardware. */ |
| 587 | int idx; |
| 588 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 589 | |
| 590 | if (!armpmu) |
| 591 | return; |
| 592 | |
| 593 | for (idx = 0; idx <= armpmu->num_events; ++idx) { |
| 594 | struct perf_event *event = cpuc->events[idx]; |
| 595 | |
| 596 | if (!event) |
| 597 | continue; |
| 598 | |
| 599 | armpmu->enable(&event->hw, idx); |
| 600 | } |
| 601 | |
| 602 | armpmu->start(); |
| 603 | } |
| 604 | |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 605 | static void armpmu_disable(struct pmu *pmu) |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 606 | { |
| 607 | if (armpmu) |
| 608 | armpmu->stop(); |
| 609 | } |
| 610 | |
Peter Zijlstra | 33696fc | 2010-06-14 08:49:00 +0200 | [diff] [blame] | 611 | static struct pmu pmu = { |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 612 | .pmu_enable = armpmu_enable, |
| 613 | .pmu_disable = armpmu_disable, |
| 614 | .event_init = armpmu_event_init, |
| 615 | .add = armpmu_add, |
| 616 | .del = armpmu_del, |
| 617 | .start = armpmu_start, |
| 618 | .stop = armpmu_stop, |
| 619 | .read = armpmu_read, |
Peter Zijlstra | 33696fc | 2010-06-14 08:49:00 +0200 | [diff] [blame] | 620 | }; |
| 621 | |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 622 | /* Include the PMU-specific implementations. */ |
| 623 | #include "perf_event_xscale.c" |
| 624 | #include "perf_event_v6.c" |
| 625 | #include "perf_event_v7.c" |
Will Deacon | 49e6a32 | 2010-04-30 11:33:33 +0100 | [diff] [blame] | 626 | |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 627 | static int __init |
| 628 | init_hw_perf_events(void) |
| 629 | { |
| 630 | unsigned long cpuid = read_cpuid_id(); |
| 631 | unsigned long implementor = (cpuid & 0xFF000000) >> 24; |
| 632 | unsigned long part_number = (cpuid & 0xFFF0); |
| 633 | |
Will Deacon | 49e6a32 | 2010-04-30 11:33:33 +0100 | [diff] [blame] | 634 | /* ARM Ltd CPUs. */ |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 635 | if (0x41 == implementor) { |
| 636 | switch (part_number) { |
| 637 | case 0xB360: /* ARM1136 */ |
| 638 | case 0xB560: /* ARM1156 */ |
| 639 | case 0xB760: /* ARM1176 */ |
Will Deacon | 3cb314b | 2010-11-13 17:37:46 +0000 | [diff] [blame] | 640 | armpmu = armv6pmu_init(); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 641 | break; |
| 642 | case 0xB020: /* ARM11mpcore */ |
Will Deacon | 3cb314b | 2010-11-13 17:37:46 +0000 | [diff] [blame] | 643 | armpmu = armv6mpcore_pmu_init(); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 644 | break; |
Jean PIHET | 796d129 | 2010-01-26 18:51:05 +0100 | [diff] [blame] | 645 | case 0xC080: /* Cortex-A8 */ |
Will Deacon | 3cb314b | 2010-11-13 17:37:46 +0000 | [diff] [blame] | 646 | armpmu = armv7_a8_pmu_init(); |
Jean PIHET | 796d129 | 2010-01-26 18:51:05 +0100 | [diff] [blame] | 647 | break; |
| 648 | case 0xC090: /* Cortex-A9 */ |
Will Deacon | 3cb314b | 2010-11-13 17:37:46 +0000 | [diff] [blame] | 649 | armpmu = armv7_a9_pmu_init(); |
Jean PIHET | 796d129 | 2010-01-26 18:51:05 +0100 | [diff] [blame] | 650 | break; |
Will Deacon | 49e6a32 | 2010-04-30 11:33:33 +0100 | [diff] [blame] | 651 | } |
| 652 | /* Intel CPUs [xscale]. */ |
| 653 | } else if (0x69 == implementor) { |
| 654 | part_number = (cpuid >> 13) & 0x7; |
| 655 | switch (part_number) { |
| 656 | case 1: |
Will Deacon | 3cb314b | 2010-11-13 17:37:46 +0000 | [diff] [blame] | 657 | armpmu = xscale1pmu_init(); |
Will Deacon | 49e6a32 | 2010-04-30 11:33:33 +0100 | [diff] [blame] | 658 | break; |
| 659 | case 2: |
Will Deacon | 3cb314b | 2010-11-13 17:37:46 +0000 | [diff] [blame] | 660 | armpmu = xscale2pmu_init(); |
Will Deacon | 49e6a32 | 2010-04-30 11:33:33 +0100 | [diff] [blame] | 661 | break; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 662 | } |
| 663 | } |
| 664 | |
Will Deacon | 49e6a32 | 2010-04-30 11:33:33 +0100 | [diff] [blame] | 665 | if (armpmu) { |
Jean PIHET | 796d129 | 2010-01-26 18:51:05 +0100 | [diff] [blame] | 666 | pr_info("enabled with %s PMU driver, %d counters available\n", |
Will Deacon | 6299483 | 2010-11-13 18:45:27 +0000 | [diff] [blame] | 667 | armpmu->name, armpmu->num_events); |
Will Deacon | 49e6a32 | 2010-04-30 11:33:33 +0100 | [diff] [blame] | 668 | } else { |
| 669 | pr_info("no hardware support available\n"); |
Will Deacon | 49e6a32 | 2010-04-30 11:33:33 +0100 | [diff] [blame] | 670 | } |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 671 | |
Peter Zijlstra | 2e80a82 | 2010-11-17 23:17:36 +0100 | [diff] [blame] | 672 | perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); |
Peter Zijlstra | b0a873e | 2010-06-11 13:35:08 +0200 | [diff] [blame] | 673 | |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 674 | return 0; |
| 675 | } |
Peter Zijlstra | 004417a | 2010-11-25 18:38:29 +0100 | [diff] [blame] | 676 | early_initcall(init_hw_perf_events); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 677 | |
| 678 | /* |
| 679 | * Callchain handling code. |
| 680 | */ |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 681 | |
| 682 | /* |
| 683 | * The registers we're interested in are at the end of the variable |
| 684 | * length saved register structure. The fp points at the end of this |
| 685 | * structure so the address of this struct is: |
| 686 | * (struct frame_tail *)(xxx->fp)-1 |
| 687 | * |
| 688 | * This code has been adapted from the ARM OProfile support. |
| 689 | */ |
| 690 | struct frame_tail { |
Will Deacon | 4d6b7a7 | 2010-11-30 18:15:53 +0100 | [diff] [blame] | 691 | struct frame_tail __user *fp; |
| 692 | unsigned long sp; |
| 693 | unsigned long lr; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 694 | } __attribute__((packed)); |
| 695 | |
| 696 | /* |
| 697 | * Get the return address for a single stackframe and return a pointer to the |
| 698 | * next frame tail. |
| 699 | */ |
Will Deacon | 4d6b7a7 | 2010-11-30 18:15:53 +0100 | [diff] [blame] | 700 | static struct frame_tail __user * |
| 701 | user_backtrace(struct frame_tail __user *tail, |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 702 | struct perf_callchain_entry *entry) |
| 703 | { |
| 704 | struct frame_tail buftail; |
| 705 | |
| 706 | /* Also check accessibility of one struct frame_tail beyond */ |
| 707 | if (!access_ok(VERIFY_READ, tail, sizeof(buftail))) |
| 708 | return NULL; |
| 709 | if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail))) |
| 710 | return NULL; |
| 711 | |
Frederic Weisbecker | 70791ce | 2010-06-29 19:34:05 +0200 | [diff] [blame] | 712 | perf_callchain_store(entry, buftail.lr); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 713 | |
| 714 | /* |
| 715 | * Frame pointers should strictly progress back up the stack |
| 716 | * (towards higher addresses). |
| 717 | */ |
| 718 | if (tail >= buftail.fp) |
| 719 | return NULL; |
| 720 | |
| 721 | return buftail.fp - 1; |
| 722 | } |
| 723 | |
Frederic Weisbecker | 56962b4 | 2010-06-30 23:03:51 +0200 | [diff] [blame] | 724 | void |
| 725 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 726 | { |
Will Deacon | 4d6b7a7 | 2010-11-30 18:15:53 +0100 | [diff] [blame] | 727 | struct frame_tail __user *tail; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 728 | |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 729 | |
Will Deacon | 4d6b7a7 | 2010-11-30 18:15:53 +0100 | [diff] [blame] | 730 | tail = (struct frame_tail __user *)regs->ARM_fp - 1; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 731 | |
| 732 | while (tail && !((unsigned long)tail & 0x3)) |
| 733 | tail = user_backtrace(tail, entry); |
| 734 | } |
| 735 | |
| 736 | /* |
| 737 | * Gets called by walk_stackframe() for every stackframe. This will be called |
| 738 | * whist unwinding the stackframe and is like a subroutine return so we use |
| 739 | * the PC. |
| 740 | */ |
| 741 | static int |
| 742 | callchain_trace(struct stackframe *fr, |
| 743 | void *data) |
| 744 | { |
| 745 | struct perf_callchain_entry *entry = data; |
Frederic Weisbecker | 70791ce | 2010-06-29 19:34:05 +0200 | [diff] [blame] | 746 | perf_callchain_store(entry, fr->pc); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 747 | return 0; |
| 748 | } |
| 749 | |
Frederic Weisbecker | 56962b4 | 2010-06-30 23:03:51 +0200 | [diff] [blame] | 750 | void |
| 751 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 752 | { |
| 753 | struct stackframe fr; |
| 754 | |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 755 | fr.fp = regs->ARM_fp; |
| 756 | fr.sp = regs->ARM_sp; |
| 757 | fr.lr = regs->ARM_lr; |
| 758 | fr.pc = regs->ARM_pc; |
| 759 | walk_stackframe(&fr, callchain_trace, entry); |
| 760 | } |