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Brett Russ20f733e2005-09-01 18:26:17 -04001/*
2 * sata_mv.c - Marvell SATA support
3 *
Mark Lord40f21b12009-03-10 18:51:04 -04004 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
Jeff Garzik8b260242005-11-12 12:32:50 -05005 * Copyright 2005: EMC Corporation, all rights reserved.
Jeff Garzike2b1be52005-11-18 14:04:23 -05006 * Copyright 2005 Red Hat, Inc. All rights reserved.
Brett Russ20f733e2005-09-01 18:26:17 -04007 *
Mark Lord40f21b12009-03-10 18:51:04 -04008 * Originally written by Brett Russ.
9 * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>.
10 *
Brett Russ20f733e2005-09-01 18:26:17 -040011 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; version 2 of the License.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 */
27
Jeff Garzik4a05e202007-05-24 23:40:15 -040028/*
Mark Lord85afb932008-04-19 14:54:41 -040029 * sata_mv TODO list:
30 *
Mark Lord85afb932008-04-19 14:54:41 -040031 * --> Develop a low-power-consumption strategy, and implement it.
32 *
Mark Lord2b748a02009-03-10 22:01:17 -040033 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
Mark Lord85afb932008-04-19 14:54:41 -040034 *
35 * --> [Experiment, Marvell value added] Is it possible to use target
36 * mode to cross-connect two Linux boxes with Marvell cards? If so,
37 * creating LibATA target mode support would be very interesting.
38 *
39 * Target mode, for those without docs, is the ability to directly
40 * connect two SATA ports.
41 */
Jeff Garzik4a05e202007-05-24 23:40:15 -040042
Mark Lord65ad7fef2009-04-06 15:24:14 -040043/*
44 * 80x1-B2 errata PCI#11:
45 *
46 * Users of the 6041/6081 Rev.B2 chips (current is C0)
47 * should be careful to insert those cards only onto PCI-X bus #0,
48 * and only in device slots 0..7, not higher. The chips may not
49 * work correctly otherwise (note: this is a pretty rare condition).
50 */
51
Brett Russ20f733e2005-09-01 18:26:17 -040052#include <linux/kernel.h>
53#include <linux/module.h>
54#include <linux/pci.h>
55#include <linux/init.h>
56#include <linux/blkdev.h>
57#include <linux/delay.h>
58#include <linux/interrupt.h>
Andrew Morton8d8b6002008-02-04 23:43:44 -080059#include <linux/dmapool.h>
Brett Russ20f733e2005-09-01 18:26:17 -040060#include <linux/dma-mapping.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050061#include <linux/device.h>
Saeed Bisharac77a2f42009-12-06 18:26:18 +020062#include <linux/clk.h>
Saeed Bisharaf351b2d2008-02-01 18:08:03 -050063#include <linux/platform_device.h>
64#include <linux/ata_platform.h>
Lennert Buytenhek15a32632008-03-27 14:51:39 -040065#include <linux/mbus.h>
Mark Lordc46938c2008-05-02 14:02:28 -040066#include <linux/bitops.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090067#include <linux/gfp.h>
Andrew Lunn97b414e2012-06-10 16:45:37 +020068#include <linux/of.h>
69#include <linux/of_irq.h>
Brett Russ20f733e2005-09-01 18:26:17 -040070#include <scsi/scsi_host.h>
Jeff Garzik193515d2005-11-07 00:59:37 -050071#include <scsi/scsi_cmnd.h>
Jeff Garzik6c087722007-10-12 00:16:23 -040072#include <scsi/scsi_device.h>
Brett Russ20f733e2005-09-01 18:26:17 -040073#include <linux/libata.h>
Brett Russ20f733e2005-09-01 18:26:17 -040074
75#define DRV_NAME "sata_mv"
Mark Lordcae5a292009-04-06 16:43:45 -040076#define DRV_VERSION "1.28"
Brett Russ20f733e2005-09-01 18:26:17 -040077
Mark Lord40f21b12009-03-10 18:51:04 -040078/*
79 * module options
80 */
81
Mark Lord40f21b12009-03-10 18:51:04 -040082#ifdef CONFIG_PCI
Andrew Lunn13b74082012-09-28 17:04:10 +020083static int msi;
Mark Lord40f21b12009-03-10 18:51:04 -040084module_param(msi, int, S_IRUGO);
85MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
86#endif
87
Mark Lord2b748a02009-03-10 22:01:17 -040088static int irq_coalescing_io_count;
89module_param(irq_coalescing_io_count, int, S_IRUGO);
90MODULE_PARM_DESC(irq_coalescing_io_count,
91 "IRQ coalescing I/O count threshold (0..255)");
92
93static int irq_coalescing_usecs;
94module_param(irq_coalescing_usecs, int, S_IRUGO);
95MODULE_PARM_DESC(irq_coalescing_usecs,
96 "IRQ coalescing time threshold in usecs");
97
Brett Russ20f733e2005-09-01 18:26:17 -040098enum {
99 /* BAR's are enumerated in terms of pci_resource_start() terms */
100 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
101 MV_IO_BAR = 2, /* offset 0x18: IO space */
102 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
103
104 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
105 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
106
Mark Lord2b748a02009-03-10 22:01:17 -0400107 /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */
108 COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */
109 MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */
110 MAX_COAL_IO_COUNT = 255, /* completed I/O count */
111
Brett Russ20f733e2005-09-01 18:26:17 -0400112 MV_PCI_REG_BASE = 0,
Mark Lord615ab952006-05-19 16:24:56 -0400113
Mark Lord2b748a02009-03-10 22:01:17 -0400114 /*
115 * Per-chip ("all ports") interrupt coalescing feature.
116 * This is only for GEN_II / GEN_IIE hardware.
117 *
118 * Coalescing defers the interrupt until either the IO_THRESHOLD
119 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
120 */
Mark Lordcae5a292009-04-06 16:43:45 -0400121 COAL_REG_BASE = 0x18000,
122 IRQ_COAL_CAUSE = (COAL_REG_BASE + 0x08),
Mark Lord2b748a02009-03-10 22:01:17 -0400123 ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */
124
Mark Lordcae5a292009-04-06 16:43:45 -0400125 IRQ_COAL_IO_THRESHOLD = (COAL_REG_BASE + 0xcc),
126 IRQ_COAL_TIME_THRESHOLD = (COAL_REG_BASE + 0xd0),
Mark Lord2b748a02009-03-10 22:01:17 -0400127
128 /*
129 * Registers for the (unused here) transaction coalescing feature:
130 */
Mark Lordcae5a292009-04-06 16:43:45 -0400131 TRAN_COAL_CAUSE_LO = (COAL_REG_BASE + 0x88),
132 TRAN_COAL_CAUSE_HI = (COAL_REG_BASE + 0x8c),
Mark Lord2b748a02009-03-10 22:01:17 -0400133
Mark Lordcae5a292009-04-06 16:43:45 -0400134 SATAHC0_REG_BASE = 0x20000,
135 FLASH_CTL = 0x1046c,
136 GPIO_PORT_CTL = 0x104f0,
137 RESET_CFG = 0x180d8,
Brett Russ20f733e2005-09-01 18:26:17 -0400138
139 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
140 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
141 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
142 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
143
Brett Russ31961942005-09-30 01:36:00 -0400144 MV_MAX_Q_DEPTH = 32,
145 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
146
147 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
148 * CRPB needs alignment on a 256B boundary. Size == 256B
Brett Russ31961942005-09-30 01:36:00 -0400149 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
150 */
151 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
152 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
Mark Lordda2fa9b2008-01-26 18:32:45 -0500153 MV_MAX_SG_CT = 256,
Brett Russ31961942005-09-30 01:36:00 -0400154 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
Brett Russ31961942005-09-30 01:36:00 -0400155
Mark Lord352fab72008-04-19 14:43:42 -0400156 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
Brett Russ20f733e2005-09-01 18:26:17 -0400157 MV_PORT_HC_SHIFT = 2,
Mark Lord352fab72008-04-19 14:43:42 -0400158 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
159 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
160 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
Brett Russ20f733e2005-09-01 18:26:17 -0400161
162 /* Host Flags */
163 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
Saeed Bishara7bb3c522008-01-30 11:50:45 -1100164
Sergei Shtylyov9cbe0562011-02-04 22:05:48 +0300165 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_PIO_POLLING,
Mark Lordad3aef52008-05-14 09:21:43 -0400166
Mark Lord91b1a842009-01-30 18:46:39 -0500167 MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI,
Brett Russ20f733e2005-09-01 18:26:17 -0400168
Mark Lord40f21b12009-03-10 18:51:04 -0400169 MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ |
170 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA,
Mark Lord91b1a842009-01-30 18:46:39 -0500171
172 MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN,
Mark Lordad3aef52008-05-14 09:21:43 -0400173
Brett Russ31961942005-09-30 01:36:00 -0400174 CRQB_FLAG_READ = (1 << 0),
175 CRQB_TAG_SHIFT = 1,
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400176 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
Mark Lorde12bef52008-03-31 19:33:56 -0400177 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400178 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
Brett Russ31961942005-09-30 01:36:00 -0400179 CRQB_CMD_ADDR_SHIFT = 8,
180 CRQB_CMD_CS = (0x2 << 11),
181 CRQB_CMD_LAST = (1 << 15),
182
183 CRPB_FLAG_STATUS_SHIFT = 8,
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400184 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
185 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
Brett Russ31961942005-09-30 01:36:00 -0400186
187 EPRD_FLAG_END_OF_TBL = (1 << 31),
188
Brett Russ20f733e2005-09-01 18:26:17 -0400189 /* PCI interface registers */
190
Mark Lordcae5a292009-04-06 16:43:45 -0400191 MV_PCI_COMMAND = 0xc00,
192 MV_PCI_COMMAND_MWRCOM = (1 << 4), /* PCI Master Write Combining */
193 MV_PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
Brett Russ31961942005-09-30 01:36:00 -0400194
Mark Lordcae5a292009-04-06 16:43:45 -0400195 PCI_MAIN_CMD_STS = 0xd30,
Brett Russ20f733e2005-09-01 18:26:17 -0400196 STOP_PCI_MASTER = (1 << 2),
197 PCI_MASTER_EMPTY = (1 << 3),
198 GLOB_SFT_RST = (1 << 4),
199
Mark Lordcae5a292009-04-06 16:43:45 -0400200 MV_PCI_MODE = 0xd00,
Mark Lord8e7decd2008-05-02 02:07:51 -0400201 MV_PCI_MODE_MASK = 0x30,
202
Jeff Garzik522479f2005-11-12 22:14:02 -0500203 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
204 MV_PCI_DISC_TIMER = 0xd04,
205 MV_PCI_MSI_TRIGGER = 0xc38,
206 MV_PCI_SERR_MASK = 0xc28,
Mark Lordcae5a292009-04-06 16:43:45 -0400207 MV_PCI_XBAR_TMOUT = 0x1d04,
Jeff Garzik522479f2005-11-12 22:14:02 -0500208 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
209 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
210 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
211 MV_PCI_ERR_COMMAND = 0x1d50,
212
Mark Lordcae5a292009-04-06 16:43:45 -0400213 PCI_IRQ_CAUSE = 0x1d58,
214 PCI_IRQ_MASK = 0x1d5c,
Brett Russ20f733e2005-09-01 18:26:17 -0400215 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
216
Mark Lordcae5a292009-04-06 16:43:45 -0400217 PCIE_IRQ_CAUSE = 0x1900,
218 PCIE_IRQ_MASK = 0x1910,
Mark Lord646a4da2008-01-26 18:30:37 -0500219 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
Mark Lord02a121d2007-12-01 13:07:22 -0500220
Mark Lord7368f912008-04-25 11:24:24 -0400221 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
Mark Lordcae5a292009-04-06 16:43:45 -0400222 PCI_HC_MAIN_IRQ_CAUSE = 0x1d60,
223 PCI_HC_MAIN_IRQ_MASK = 0x1d64,
224 SOC_HC_MAIN_IRQ_CAUSE = 0x20020,
225 SOC_HC_MAIN_IRQ_MASK = 0x20024,
Mark Lord40f21b12009-03-10 18:51:04 -0400226 ERR_IRQ = (1 << 0), /* shift by (2 * port #) */
227 DONE_IRQ = (1 << 1), /* shift by (2 * port #) */
Brett Russ20f733e2005-09-01 18:26:17 -0400228 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
229 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
Mark Lord2b748a02009-03-10 22:01:17 -0400230 DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */
231 DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */
Brett Russ20f733e2005-09-01 18:26:17 -0400232 PCI_ERR = (1 << 18),
Mark Lord40f21b12009-03-10 18:51:04 -0400233 TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */
234 TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */
235 PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */
236 PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */
237 ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */
Brett Russ20f733e2005-09-01 18:26:17 -0400238 GPIO_INT = (1 << 22),
239 SELF_INT = (1 << 23),
240 TWSI_INT = (1 << 24),
241 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
Jeff Garzikfb621e22007-02-25 04:19:45 -0500242 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
Mark Lorde12bef52008-03-31 19:33:56 -0400243 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
Brett Russ20f733e2005-09-01 18:26:17 -0400244
245 /* SATAHC registers */
Mark Lordcae5a292009-04-06 16:43:45 -0400246 HC_CFG = 0x00,
Brett Russ20f733e2005-09-01 18:26:17 -0400247
Mark Lordcae5a292009-04-06 16:43:45 -0400248 HC_IRQ_CAUSE = 0x14,
Mark Lord352fab72008-04-19 14:43:42 -0400249 DMA_IRQ = (1 << 0), /* shift by port # */
250 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
Brett Russ20f733e2005-09-01 18:26:17 -0400251 DEV_IRQ = (1 << 8), /* shift by port # */
252
Mark Lord2b748a02009-03-10 22:01:17 -0400253 /*
254 * Per-HC (Host-Controller) interrupt coalescing feature.
255 * This is present on all chip generations.
256 *
257 * Coalescing defers the interrupt until either the IO_THRESHOLD
258 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
259 */
Mark Lordcae5a292009-04-06 16:43:45 -0400260 HC_IRQ_COAL_IO_THRESHOLD = 0x000c,
261 HC_IRQ_COAL_TIME_THRESHOLD = 0x0010,
Mark Lord2b748a02009-03-10 22:01:17 -0400262
Mark Lordcae5a292009-04-06 16:43:45 -0400263 SOC_LED_CTRL = 0x2c,
Mark Lord000b3442009-03-15 11:33:19 -0400264 SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */
265 SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */
266 /* with dev activity LED */
267
Brett Russ20f733e2005-09-01 18:26:17 -0400268 /* Shadow block registers */
Mark Lordcae5a292009-04-06 16:43:45 -0400269 SHD_BLK = 0x100,
270 SHD_CTL_AST = 0x20, /* ofs from SHD_BLK */
Brett Russ20f733e2005-09-01 18:26:17 -0400271
272 /* SATA registers */
Mark Lordcae5a292009-04-06 16:43:45 -0400273 SATA_STATUS = 0x300, /* ctrl, err regs follow status */
274 SATA_ACTIVE = 0x350,
275 FIS_IRQ_CAUSE = 0x364,
276 FIS_IRQ_CAUSE_AN = (1 << 9), /* async notification */
Mark Lord17c5aab2008-04-16 14:56:51 -0400277
Mark Lordcae5a292009-04-06 16:43:45 -0400278 LTMODE = 0x30c, /* requires read-after-write */
Mark Lord17c5aab2008-04-16 14:56:51 -0400279 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
280
Mark Lordcae5a292009-04-06 16:43:45 -0400281 PHY_MODE2 = 0x330,
Jeff Garzik47c2b672005-11-12 21:13:17 -0500282 PHY_MODE3 = 0x310,
Mark Lordcae5a292009-04-06 16:43:45 -0400283
284 PHY_MODE4 = 0x314, /* requires read-after-write */
Mark Lordba069e32008-05-31 16:46:34 -0400285 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
286 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
287 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
288 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
289
Mark Lordcae5a292009-04-06 16:43:45 -0400290 SATA_IFCTL = 0x344,
291 SATA_TESTCTL = 0x348,
292 SATA_IFSTAT = 0x34c,
293 VENDOR_UNIQUE_FIS = 0x35c,
Mark Lord17c5aab2008-04-16 14:56:51 -0400294
Mark Lordcae5a292009-04-06 16:43:45 -0400295 FISCFG = 0x360,
Mark Lord8e7decd2008-05-02 02:07:51 -0400296 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
297 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
Mark Lord17c5aab2008-04-16 14:56:51 -0400298
Martin Michlmayr29b7e432009-05-04 20:58:50 +0200299 PHY_MODE9_GEN2 = 0x398,
300 PHY_MODE9_GEN1 = 0x39c,
301 PHYCFG_OFS = 0x3a0, /* only in 65n devices */
302
Jeff Garzikc9d39132005-11-13 17:47:51 -0500303 MV5_PHY_MODE = 0x74,
Mark Lordcae5a292009-04-06 16:43:45 -0400304 MV5_LTMODE = 0x30,
305 MV5_PHY_CTL = 0x0C,
306 SATA_IFCFG = 0x050,
Jeff Garzikbca1c4e2005-11-12 12:48:15 -0500307
308 MV_M2_PREAMP_MASK = 0x7e0,
Brett Russ20f733e2005-09-01 18:26:17 -0400309
310 /* Port registers */
Mark Lordcae5a292009-04-06 16:43:45 -0400311 EDMA_CFG = 0,
Mark Lord0c589122008-01-26 18:31:16 -0500312 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
313 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
314 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
315 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
316 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
Mark Lorde12bef52008-03-31 19:33:56 -0400317 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
318 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
Brett Russ20f733e2005-09-01 18:26:17 -0400319
Mark Lordcae5a292009-04-06 16:43:45 -0400320 EDMA_ERR_IRQ_CAUSE = 0x8,
321 EDMA_ERR_IRQ_MASK = 0xc,
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400322 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
323 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
324 EDMA_ERR_DEV = (1 << 2), /* device error */
325 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
326 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
327 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400328 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
329 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400330 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400331 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400332 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
333 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
334 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
335 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
Mark Lord646a4da2008-01-26 18:30:37 -0500336
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400337 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
Mark Lord646a4da2008-01-26 18:30:37 -0500338 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
339 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
340 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
341 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
342
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400343 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
Mark Lord646a4da2008-01-26 18:30:37 -0500344
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400345 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
Mark Lord646a4da2008-01-26 18:30:37 -0500346 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
347 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
348 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
349 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
350 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
351
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400352 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
Mark Lord646a4da2008-01-26 18:30:37 -0500353
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400354 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400355 EDMA_ERR_OVERRUN_5 = (1 << 5),
356 EDMA_ERR_UNDERRUN_5 = (1 << 6),
Mark Lord646a4da2008-01-26 18:30:37 -0500357
358 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
359 EDMA_ERR_LNK_CTRL_RX_1 |
360 EDMA_ERR_LNK_CTRL_RX_3 |
Mark Lord85afb932008-04-19 14:54:41 -0400361 EDMA_ERR_LNK_CTRL_TX,
Mark Lord646a4da2008-01-26 18:30:37 -0500362
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400363 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
364 EDMA_ERR_PRD_PAR |
365 EDMA_ERR_DEV_DCON |
366 EDMA_ERR_DEV_CON |
367 EDMA_ERR_SERR |
368 EDMA_ERR_SELF_DIS |
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400369 EDMA_ERR_CRQB_PAR |
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400370 EDMA_ERR_CRPB_PAR |
371 EDMA_ERR_INTRL_PAR |
372 EDMA_ERR_IORDY |
373 EDMA_ERR_LNK_CTRL_RX_2 |
374 EDMA_ERR_LNK_DATA_RX |
375 EDMA_ERR_LNK_DATA_TX |
376 EDMA_ERR_TRANS_PROTO,
Mark Lorde12bef52008-03-31 19:33:56 -0400377
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400378 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
379 EDMA_ERR_PRD_PAR |
380 EDMA_ERR_DEV_DCON |
381 EDMA_ERR_DEV_CON |
382 EDMA_ERR_OVERRUN_5 |
383 EDMA_ERR_UNDERRUN_5 |
384 EDMA_ERR_SELF_DIS_5 |
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400385 EDMA_ERR_CRQB_PAR |
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400386 EDMA_ERR_CRPB_PAR |
387 EDMA_ERR_INTRL_PAR |
388 EDMA_ERR_IORDY,
Brett Russ20f733e2005-09-01 18:26:17 -0400389
Mark Lordcae5a292009-04-06 16:43:45 -0400390 EDMA_REQ_Q_BASE_HI = 0x10,
391 EDMA_REQ_Q_IN_PTR = 0x14, /* also contains BASE_LO */
Brett Russ31961942005-09-30 01:36:00 -0400392
Mark Lordcae5a292009-04-06 16:43:45 -0400393 EDMA_REQ_Q_OUT_PTR = 0x18,
Brett Russ31961942005-09-30 01:36:00 -0400394 EDMA_REQ_Q_PTR_SHIFT = 5,
395
Mark Lordcae5a292009-04-06 16:43:45 -0400396 EDMA_RSP_Q_BASE_HI = 0x1c,
397 EDMA_RSP_Q_IN_PTR = 0x20,
398 EDMA_RSP_Q_OUT_PTR = 0x24, /* also contains BASE_LO */
Brett Russ31961942005-09-30 01:36:00 -0400399 EDMA_RSP_Q_PTR_SHIFT = 3,
400
Mark Lordcae5a292009-04-06 16:43:45 -0400401 EDMA_CMD = 0x28, /* EDMA command register */
Jeff Garzik0ea9e172007-07-13 17:06:45 -0400402 EDMA_EN = (1 << 0), /* enable EDMA */
403 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
Mark Lord8e7decd2008-05-02 02:07:51 -0400404 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
Brett Russ20f733e2005-09-01 18:26:17 -0400405
Mark Lordcae5a292009-04-06 16:43:45 -0400406 EDMA_STATUS = 0x30, /* EDMA engine status */
Mark Lord8e7decd2008-05-02 02:07:51 -0400407 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
408 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
409
Mark Lordcae5a292009-04-06 16:43:45 -0400410 EDMA_IORDY_TMOUT = 0x34,
411 EDMA_ARB_CFG = 0x38,
Mark Lord8e7decd2008-05-02 02:07:51 -0400412
Mark Lordcae5a292009-04-06 16:43:45 -0400413 EDMA_HALTCOND = 0x60, /* GenIIe halt conditions */
414 EDMA_UNKNOWN_RSVD = 0x6C, /* GenIIe unknown/reserved */
Mark Lordda142652009-01-30 18:51:54 -0500415
Mark Lordcae5a292009-04-06 16:43:45 -0400416 BMDMA_CMD = 0x224, /* bmdma command register */
417 BMDMA_STATUS = 0x228, /* bmdma status register */
418 BMDMA_PRD_LOW = 0x22c, /* bmdma PRD addr 31:0 */
419 BMDMA_PRD_HIGH = 0x230, /* bmdma PRD addr 63:32 */
Mark Lordda142652009-01-30 18:51:54 -0500420
Brett Russ31961942005-09-30 01:36:00 -0400421 /* Host private flags (hp_flags) */
422 MV_HP_FLAG_MSI = (1 << 0),
Jeff Garzik47c2b672005-11-12 21:13:17 -0500423 MV_HP_ERRATA_50XXB0 = (1 << 1),
424 MV_HP_ERRATA_50XXB2 = (1 << 2),
425 MV_HP_ERRATA_60X1B2 = (1 << 3),
426 MV_HP_ERRATA_60X1C0 = (1 << 4),
Jeff Garzik0ea9e172007-07-13 17:06:45 -0400427 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
428 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
429 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
Mark Lord02a121d2007-12-01 13:07:22 -0500430 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
Mark Lord616d4a92008-05-02 02:08:32 -0400431 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
Mark Lord1f398472008-05-27 17:54:48 -0400432 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
Mark Lord000b3442009-03-15 11:33:19 -0400433 MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */
Brett Russ20f733e2005-09-01 18:26:17 -0400434
Brett Russ31961942005-09-30 01:36:00 -0400435 /* Port private flags (pp_flags) */
Jeff Garzik0ea9e172007-07-13 17:06:45 -0400436 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
Mark Lord72109162008-01-26 18:31:33 -0500437 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
Mark Lord00f42ea2008-05-02 02:11:45 -0400438 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
Mark Lord29d187b2008-05-02 02:15:37 -0400439 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
Mark Lordd16ab3f2009-02-25 15:17:43 -0500440 MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */
Brett Russ31961942005-09-30 01:36:00 -0400441};
442
Jeff Garzikee9ccdf2007-07-12 15:51:22 -0400443#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
444#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
Jeff Garzike4e7b892006-01-31 12:18:41 -0500445#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
Mark Lord8e7decd2008-05-02 02:07:51 -0400446#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
Mark Lord1f398472008-05-27 17:54:48 -0400447#define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
Jeff Garzikbca1c4e2005-11-12 12:48:15 -0500448
Lennert Buytenhek15a32632008-03-27 14:51:39 -0400449#define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
450#define WINDOW_BASE(i) (0x20034 + ((i) << 4))
451
Jeff Garzik095fec82005-11-12 09:50:49 -0500452enum {
Jeff Garzikbaf14aa2007-10-09 13:51:57 -0400453 /* DMA boundary 0xffff is required by the s/g splitting
454 * we need on /length/ in mv_fill-sg().
455 */
456 MV_DMA_BOUNDARY = 0xffffU,
Jeff Garzik095fec82005-11-12 09:50:49 -0500457
Jeff Garzik0ea9e172007-07-13 17:06:45 -0400458 /* mask of register bits containing lower 32 bits
459 * of EDMA request queue DMA address
460 */
Jeff Garzik095fec82005-11-12 09:50:49 -0500461 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
462
Jeff Garzik0ea9e172007-07-13 17:06:45 -0400463 /* ditto, for response queue */
Jeff Garzik095fec82005-11-12 09:50:49 -0500464 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
465};
466
Jeff Garzik522479f2005-11-12 22:14:02 -0500467enum chip_type {
468 chip_504x,
469 chip_508x,
470 chip_5080,
471 chip_604x,
472 chip_608x,
Jeff Garzike4e7b892006-01-31 12:18:41 -0500473 chip_6042,
474 chip_7042,
Saeed Bisharaf351b2d2008-02-01 18:08:03 -0500475 chip_soc,
Jeff Garzik522479f2005-11-12 22:14:02 -0500476};
477
Brett Russ31961942005-09-30 01:36:00 -0400478/* Command ReQuest Block: 32B */
479struct mv_crqb {
Mark Lorde1469872006-05-22 19:02:03 -0400480 __le32 sg_addr;
481 __le32 sg_addr_hi;
482 __le16 ctrl_flags;
483 __le16 ata_cmd[11];
Brett Russ31961942005-09-30 01:36:00 -0400484};
485
Jeff Garzike4e7b892006-01-31 12:18:41 -0500486struct mv_crqb_iie {
Mark Lorde1469872006-05-22 19:02:03 -0400487 __le32 addr;
488 __le32 addr_hi;
489 __le32 flags;
490 __le32 len;
491 __le32 ata_cmd[4];
Jeff Garzike4e7b892006-01-31 12:18:41 -0500492};
493
Brett Russ31961942005-09-30 01:36:00 -0400494/* Command ResPonse Block: 8B */
495struct mv_crpb {
Mark Lorde1469872006-05-22 19:02:03 -0400496 __le16 id;
497 __le16 flags;
498 __le32 tmstmp;
Brett Russ31961942005-09-30 01:36:00 -0400499};
500
501/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
502struct mv_sg {
Mark Lorde1469872006-05-22 19:02:03 -0400503 __le32 addr;
504 __le32 flags_size;
505 __le32 addr_hi;
506 __le32 reserved;
Brett Russ20f733e2005-09-01 18:26:17 -0400507};
508
Mark Lord08da1752009-02-25 15:13:03 -0500509/*
510 * We keep a local cache of a few frequently accessed port
511 * registers here, to avoid having to read them (very slow)
512 * when switching between EDMA and non-EDMA modes.
513 */
514struct mv_cached_regs {
515 u32 fiscfg;
516 u32 ltmode;
517 u32 haltcond;
Mark Lordc01e8a22009-02-25 15:14:48 -0500518 u32 unknown_rsvd;
Mark Lord08da1752009-02-25 15:13:03 -0500519};
520
Brett Russ20f733e2005-09-01 18:26:17 -0400521struct mv_port_priv {
Brett Russ31961942005-09-30 01:36:00 -0400522 struct mv_crqb *crqb;
523 dma_addr_t crqb_dma;
524 struct mv_crpb *crpb;
525 dma_addr_t crpb_dma;
Mark Lordeb73d552008-01-29 13:24:00 -0500526 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
527 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400528
529 unsigned int req_idx;
530 unsigned int resp_idx;
531
Brett Russ31961942005-09-30 01:36:00 -0400532 u32 pp_flags;
Mark Lord08da1752009-02-25 15:13:03 -0500533 struct mv_cached_regs cached;
Mark Lord29d187b2008-05-02 02:15:37 -0400534 unsigned int delayed_eh_pmp_map;
Brett Russ20f733e2005-09-01 18:26:17 -0400535};
536
Jeff Garzikbca1c4e2005-11-12 12:48:15 -0500537struct mv_port_signal {
538 u32 amps;
539 u32 pre;
540};
541
Mark Lord02a121d2007-12-01 13:07:22 -0500542struct mv_host_priv {
543 u32 hp_flags;
Saeed Bishara1bfeff02009-12-17 01:05:00 -0500544 unsigned int board_idx;
Mark Lord96e2c4872008-05-17 13:38:00 -0400545 u32 main_irq_mask;
Mark Lord02a121d2007-12-01 13:07:22 -0500546 struct mv_port_signal signal[8];
547 const struct mv_hw_ops *ops;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -0500548 int n_ports;
549 void __iomem *base;
Mark Lord7368f912008-04-25 11:24:24 -0400550 void __iomem *main_irq_cause_addr;
551 void __iomem *main_irq_mask_addr;
Mark Lordcae5a292009-04-06 16:43:45 -0400552 u32 irq_cause_offset;
553 u32 irq_mask_offset;
Mark Lord02a121d2007-12-01 13:07:22 -0500554 u32 unmask_all_irqs;
Saeed Bisharac77a2f42009-12-06 18:26:18 +0200555
556#if defined(CONFIG_HAVE_CLK)
557 struct clk *clk;
Andrew Lunneee98992012-02-18 22:26:42 +0100558 struct clk **port_clks;
Saeed Bisharac77a2f42009-12-06 18:26:18 +0200559#endif
Mark Lordda2fa9b2008-01-26 18:32:45 -0500560 /*
561 * These consistent DMA memory pools give us guaranteed
562 * alignment for hardware-accessed data structures,
563 * and less memory waste in accomplishing the alignment.
564 */
565 struct dma_pool *crqb_pool;
566 struct dma_pool *crpb_pool;
567 struct dma_pool *sg_tbl_pool;
Mark Lord02a121d2007-12-01 13:07:22 -0500568};
569
Jeff Garzik47c2b672005-11-12 21:13:17 -0500570struct mv_hw_ops {
Jeff Garzik2a47ce02005-11-12 23:05:14 -0500571 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
572 unsigned int port);
Jeff Garzik47c2b672005-11-12 21:13:17 -0500573 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
574 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
575 void __iomem *mmio);
Jeff Garzikc9d39132005-11-13 17:47:51 -0500576 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
577 unsigned int n_hc);
Jeff Garzik522479f2005-11-12 22:14:02 -0500578 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
Saeed Bishara7bb3c522008-01-30 11:50:45 -1100579 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
Jeff Garzik47c2b672005-11-12 21:13:17 -0500580};
581
Tejun Heo82ef04f2008-07-31 17:02:40 +0900582static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
583static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
584static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
585static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
Brett Russ31961942005-09-30 01:36:00 -0400586static int mv_port_start(struct ata_port *ap);
587static void mv_port_stop(struct ata_port *ap);
Mark Lord3e4a1392008-05-02 02:10:02 -0400588static int mv_qc_defer(struct ata_queued_cmd *qc);
Brett Russ31961942005-09-30 01:36:00 -0400589static void mv_qc_prep(struct ata_queued_cmd *qc);
Jeff Garzike4e7b892006-01-31 12:18:41 -0500590static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
Tejun Heo9a3d9eb2006-01-23 13:09:36 +0900591static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
Tejun Heoa1efdab2008-03-25 12:22:50 +0900592static int mv_hardreset(struct ata_link *link, unsigned int *class,
593 unsigned long deadline);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400594static void mv_eh_freeze(struct ata_port *ap);
595static void mv_eh_thaw(struct ata_port *ap);
Mark Lordf2738272008-01-26 18:32:29 -0500596static void mv6_dev_config(struct ata_device *dev);
Brett Russ20f733e2005-09-01 18:26:17 -0400597
Jeff Garzik2a47ce02005-11-12 23:05:14 -0500598static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
599 unsigned int port);
Jeff Garzik47c2b672005-11-12 21:13:17 -0500600static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
601static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
602 void __iomem *mmio);
Jeff Garzikc9d39132005-11-13 17:47:51 -0500603static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
604 unsigned int n_hc);
Jeff Garzik522479f2005-11-12 22:14:02 -0500605static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
Saeed Bishara7bb3c522008-01-30 11:50:45 -1100606static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
Jeff Garzik47c2b672005-11-12 21:13:17 -0500607
Jeff Garzik2a47ce02005-11-12 23:05:14 -0500608static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
609 unsigned int port);
Jeff Garzik47c2b672005-11-12 21:13:17 -0500610static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
611static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
612 void __iomem *mmio);
Jeff Garzikc9d39132005-11-13 17:47:51 -0500613static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
614 unsigned int n_hc);
Jeff Garzik522479f2005-11-12 22:14:02 -0500615static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
Saeed Bisharaf351b2d2008-02-01 18:08:03 -0500616static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
617 void __iomem *mmio);
618static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
619 void __iomem *mmio);
620static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
621 void __iomem *mmio, unsigned int n_hc);
622static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
623 void __iomem *mmio);
624static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
Martin Michlmayr29b7e432009-05-04 20:58:50 +0200625static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
626 void __iomem *mmio, unsigned int port);
Saeed Bishara7bb3c522008-01-30 11:50:45 -1100627static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
Mark Lorde12bef52008-03-31 19:33:56 -0400628static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
Jeff Garzikc9d39132005-11-13 17:47:51 -0500629 unsigned int port_no);
Mark Lorde12bef52008-03-31 19:33:56 -0400630static int mv_stop_edma(struct ata_port *ap);
Mark Lordb5624682008-03-31 19:34:40 -0400631static int mv_stop_edma_engine(void __iomem *port_mmio);
Mark Lord00b81232009-01-30 18:47:51 -0500632static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma);
Jeff Garzik47c2b672005-11-12 21:13:17 -0500633
Mark Lorde49856d2008-04-16 14:59:07 -0400634static void mv_pmp_select(struct ata_port *ap, int pmp);
635static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
636 unsigned long deadline);
637static int mv_softreset(struct ata_link *link, unsigned int *class,
638 unsigned long deadline);
Mark Lord29d187b2008-05-02 02:15:37 -0400639static void mv_pmp_error_handler(struct ata_port *ap);
Mark Lord4c299ca2008-05-02 02:16:20 -0400640static void mv_process_crpb_entries(struct ata_port *ap,
641 struct mv_port_priv *pp);
Brett Russ20f733e2005-09-01 18:26:17 -0400642
Mark Lordda142652009-01-30 18:51:54 -0500643static void mv_sff_irq_clear(struct ata_port *ap);
644static int mv_check_atapi_dma(struct ata_queued_cmd *qc);
645static void mv_bmdma_setup(struct ata_queued_cmd *qc);
646static void mv_bmdma_start(struct ata_queued_cmd *qc);
647static void mv_bmdma_stop(struct ata_queued_cmd *qc);
648static u8 mv_bmdma_status(struct ata_port *ap);
Mark Lordd16ab3f2009-02-25 15:17:43 -0500649static u8 mv_sff_check_status(struct ata_port *ap);
Mark Lordda142652009-01-30 18:51:54 -0500650
Mark Lordeb73d552008-01-29 13:24:00 -0500651/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
652 * because we have to allow room for worst case splitting of
653 * PRDs for 64K boundaries in mv_fill_sg().
654 */
Andrew Lunn13b74082012-09-28 17:04:10 +0200655#ifdef CONFIG_PCI
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400656static struct scsi_host_template mv5_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900657 ATA_BASE_SHT(DRV_NAME),
Jeff Garzikbaf14aa2007-10-09 13:51:57 -0400658 .sg_tablesize = MV_MAX_SG_CT / 2,
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400659 .dma_boundary = MV_DMA_BOUNDARY,
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400660};
Andrew Lunn13b74082012-09-28 17:04:10 +0200661#endif
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400662static struct scsi_host_template mv6_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900663 ATA_NCQ_SHT(DRV_NAME),
Mark Lord138bfdd2008-01-26 18:33:18 -0500664 .can_queue = MV_MAX_Q_DEPTH - 1,
Jeff Garzikbaf14aa2007-10-09 13:51:57 -0400665 .sg_tablesize = MV_MAX_SG_CT / 2,
Brett Russ20f733e2005-09-01 18:26:17 -0400666 .dma_boundary = MV_DMA_BOUNDARY,
Brett Russ20f733e2005-09-01 18:26:17 -0400667};
668
Tejun Heo029cfd62008-03-25 12:22:49 +0900669static struct ata_port_operations mv5_ops = {
670 .inherits = &ata_sff_port_ops,
Jeff Garzikc9d39132005-11-13 17:47:51 -0500671
Alan Coxc96f1732009-03-24 10:23:46 +0000672 .lost_interrupt = ATA_OP_NULL,
673
Mark Lord3e4a1392008-05-02 02:10:02 -0400674 .qc_defer = mv_qc_defer,
Jeff Garzikc9d39132005-11-13 17:47:51 -0500675 .qc_prep = mv_qc_prep,
676 .qc_issue = mv_qc_issue,
677
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400678 .freeze = mv_eh_freeze,
679 .thaw = mv_eh_thaw,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900680 .hardreset = mv_hardreset,
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400681
Jeff Garzikc9d39132005-11-13 17:47:51 -0500682 .scr_read = mv5_scr_read,
683 .scr_write = mv5_scr_write,
684
685 .port_start = mv_port_start,
686 .port_stop = mv_port_stop,
Jeff Garzikc9d39132005-11-13 17:47:51 -0500687};
688
Tejun Heo029cfd62008-03-25 12:22:49 +0900689static struct ata_port_operations mv6_ops = {
Tejun Heo8930ff22010-05-10 21:41:33 +0200690 .inherits = &ata_bmdma_port_ops,
Brett Russ20f733e2005-09-01 18:26:17 -0400691
Tejun Heo8930ff22010-05-10 21:41:33 +0200692 .lost_interrupt = ATA_OP_NULL,
693
694 .qc_defer = mv_qc_defer,
695 .qc_prep = mv_qc_prep,
696 .qc_issue = mv_qc_issue,
697
698 .dev_config = mv6_dev_config,
699
700 .freeze = mv_eh_freeze,
701 .thaw = mv_eh_thaw,
702 .hardreset = mv_hardreset,
703 .softreset = mv_softreset,
Mark Lorde49856d2008-04-16 14:59:07 -0400704 .pmp_hardreset = mv_pmp_hardreset,
705 .pmp_softreset = mv_softreset,
Mark Lord29d187b2008-05-02 02:15:37 -0400706 .error_handler = mv_pmp_error_handler,
Mark Lordda142652009-01-30 18:51:54 -0500707
Tejun Heo8930ff22010-05-10 21:41:33 +0200708 .scr_read = mv_scr_read,
709 .scr_write = mv_scr_write,
710
Mark Lord40f21b12009-03-10 18:51:04 -0400711 .sff_check_status = mv_sff_check_status,
Mark Lordda142652009-01-30 18:51:54 -0500712 .sff_irq_clear = mv_sff_irq_clear,
713 .check_atapi_dma = mv_check_atapi_dma,
714 .bmdma_setup = mv_bmdma_setup,
715 .bmdma_start = mv_bmdma_start,
716 .bmdma_stop = mv_bmdma_stop,
717 .bmdma_status = mv_bmdma_status,
Tejun Heo8930ff22010-05-10 21:41:33 +0200718
719 .port_start = mv_port_start,
720 .port_stop = mv_port_stop,
Brett Russ20f733e2005-09-01 18:26:17 -0400721};
722
Tejun Heo029cfd62008-03-25 12:22:49 +0900723static struct ata_port_operations mv_iie_ops = {
724 .inherits = &mv6_ops,
725 .dev_config = ATA_OP_NULL,
Jeff Garzike4e7b892006-01-31 12:18:41 -0500726 .qc_prep = mv_qc_prep_iie,
Jeff Garzike4e7b892006-01-31 12:18:41 -0500727};
728
Arjan van de Ven98ac62d2005-11-28 10:06:23 +0100729static const struct ata_port_info mv_port_info[] = {
Brett Russ20f733e2005-09-01 18:26:17 -0400730 { /* chip_504x */
Mark Lord91b1a842009-01-30 18:46:39 -0500731 .flags = MV_GEN_I_FLAGS,
Mark Lordc361acb2009-04-06 15:22:21 -0400732 .pio_mask = ATA_PIO4,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400733 .udma_mask = ATA_UDMA6,
Jeff Garzikc9d39132005-11-13 17:47:51 -0500734 .port_ops = &mv5_ops,
Brett Russ20f733e2005-09-01 18:26:17 -0400735 },
736 { /* chip_508x */
Mark Lord91b1a842009-01-30 18:46:39 -0500737 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
Mark Lordc361acb2009-04-06 15:22:21 -0400738 .pio_mask = ATA_PIO4,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400739 .udma_mask = ATA_UDMA6,
Jeff Garzikc9d39132005-11-13 17:47:51 -0500740 .port_ops = &mv5_ops,
Brett Russ20f733e2005-09-01 18:26:17 -0400741 },
Jeff Garzik47c2b672005-11-12 21:13:17 -0500742 { /* chip_5080 */
Mark Lord91b1a842009-01-30 18:46:39 -0500743 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
Mark Lordc361acb2009-04-06 15:22:21 -0400744 .pio_mask = ATA_PIO4,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400745 .udma_mask = ATA_UDMA6,
Jeff Garzikc9d39132005-11-13 17:47:51 -0500746 .port_ops = &mv5_ops,
Jeff Garzik47c2b672005-11-12 21:13:17 -0500747 },
Brett Russ20f733e2005-09-01 18:26:17 -0400748 { /* chip_604x */
Mark Lord91b1a842009-01-30 18:46:39 -0500749 .flags = MV_GEN_II_FLAGS,
Mark Lordc361acb2009-04-06 15:22:21 -0400750 .pio_mask = ATA_PIO4,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400751 .udma_mask = ATA_UDMA6,
Jeff Garzikc9d39132005-11-13 17:47:51 -0500752 .port_ops = &mv6_ops,
Brett Russ20f733e2005-09-01 18:26:17 -0400753 },
754 { /* chip_608x */
Mark Lord91b1a842009-01-30 18:46:39 -0500755 .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC,
Mark Lordc361acb2009-04-06 15:22:21 -0400756 .pio_mask = ATA_PIO4,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400757 .udma_mask = ATA_UDMA6,
Jeff Garzikc9d39132005-11-13 17:47:51 -0500758 .port_ops = &mv6_ops,
Brett Russ20f733e2005-09-01 18:26:17 -0400759 },
Jeff Garzike4e7b892006-01-31 12:18:41 -0500760 { /* chip_6042 */
Mark Lord91b1a842009-01-30 18:46:39 -0500761 .flags = MV_GEN_IIE_FLAGS,
Mark Lordc361acb2009-04-06 15:22:21 -0400762 .pio_mask = ATA_PIO4,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400763 .udma_mask = ATA_UDMA6,
Jeff Garzike4e7b892006-01-31 12:18:41 -0500764 .port_ops = &mv_iie_ops,
765 },
766 { /* chip_7042 */
Mark Lord91b1a842009-01-30 18:46:39 -0500767 .flags = MV_GEN_IIE_FLAGS,
Mark Lordc361acb2009-04-06 15:22:21 -0400768 .pio_mask = ATA_PIO4,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400769 .udma_mask = ATA_UDMA6,
Jeff Garzike4e7b892006-01-31 12:18:41 -0500770 .port_ops = &mv_iie_ops,
771 },
Saeed Bisharaf351b2d2008-02-01 18:08:03 -0500772 { /* chip_soc */
Mark Lord91b1a842009-01-30 18:46:39 -0500773 .flags = MV_GEN_IIE_FLAGS,
Mark Lordc361acb2009-04-06 15:22:21 -0400774 .pio_mask = ATA_PIO4,
Mark Lord17c5aab2008-04-16 14:56:51 -0400775 .udma_mask = ATA_UDMA6,
776 .port_ops = &mv_iie_ops,
Saeed Bisharaf351b2d2008-02-01 18:08:03 -0500777 },
Brett Russ20f733e2005-09-01 18:26:17 -0400778};
779
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500780static const struct pci_device_id mv_pci_tbl[] = {
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400781 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
782 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
783 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
784 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
Mark Lord46c57842008-09-04 18:21:07 -0400785 /* RocketRAID 1720/174x have different identifiers */
786 { PCI_VDEVICE(TTI, 0x1720), chip_6042 },
Mark Lord44622542009-01-27 16:33:13 -0500787 { PCI_VDEVICE(TTI, 0x1740), chip_6042 },
788 { PCI_VDEVICE(TTI, 0x1742), chip_6042 },
Brett Russ20f733e2005-09-01 18:26:17 -0400789
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400790 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
791 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
792 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
793 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
794 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
Jeff Garzik29179532005-11-11 08:08:03 -0500795
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400796 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
797
Florian Attenbergerd9f9c6b2007-07-02 17:09:29 +0200798 /* Adaptec 1430SA */
799 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
800
Mark Lord02a121d2007-12-01 13:07:22 -0500801 /* Marvell 7042 support */
Morrison, Tom6a3d5862007-03-06 02:38:10 -0800802 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
803
Mark Lord02a121d2007-12-01 13:07:22 -0500804 /* Highpoint RocketRAID PCIe series */
805 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
806 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
807
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400808 { } /* terminate list */
Brett Russ20f733e2005-09-01 18:26:17 -0400809};
810
Jeff Garzik47c2b672005-11-12 21:13:17 -0500811static const struct mv_hw_ops mv5xxx_ops = {
812 .phy_errata = mv5_phy_errata,
813 .enable_leds = mv5_enable_leds,
814 .read_preamp = mv5_read_preamp,
815 .reset_hc = mv5_reset_hc,
Jeff Garzik522479f2005-11-12 22:14:02 -0500816 .reset_flash = mv5_reset_flash,
817 .reset_bus = mv5_reset_bus,
Jeff Garzik47c2b672005-11-12 21:13:17 -0500818};
819
820static const struct mv_hw_ops mv6xxx_ops = {
821 .phy_errata = mv6_phy_errata,
822 .enable_leds = mv6_enable_leds,
823 .read_preamp = mv6_read_preamp,
824 .reset_hc = mv6_reset_hc,
Jeff Garzik522479f2005-11-12 22:14:02 -0500825 .reset_flash = mv6_reset_flash,
826 .reset_bus = mv_reset_pci_bus,
Jeff Garzik47c2b672005-11-12 21:13:17 -0500827};
828
Saeed Bisharaf351b2d2008-02-01 18:08:03 -0500829static const struct mv_hw_ops mv_soc_ops = {
830 .phy_errata = mv6_phy_errata,
831 .enable_leds = mv_soc_enable_leds,
832 .read_preamp = mv_soc_read_preamp,
833 .reset_hc = mv_soc_reset_hc,
834 .reset_flash = mv_soc_reset_flash,
835 .reset_bus = mv_soc_reset_bus,
836};
837
Martin Michlmayr29b7e432009-05-04 20:58:50 +0200838static const struct mv_hw_ops mv_soc_65n_ops = {
839 .phy_errata = mv_soc_65n_phy_errata,
840 .enable_leds = mv_soc_enable_leds,
841 .reset_hc = mv_soc_reset_hc,
842 .reset_flash = mv_soc_reset_flash,
843 .reset_bus = mv_soc_reset_bus,
844};
845
Brett Russ20f733e2005-09-01 18:26:17 -0400846/*
847 * Functions
848 */
849
850static inline void writelfl(unsigned long data, void __iomem *addr)
851{
852 writel(data, addr);
853 (void) readl(addr); /* flush to avoid PCI posted write */
854}
855
Jeff Garzikc9d39132005-11-13 17:47:51 -0500856static inline unsigned int mv_hc_from_port(unsigned int port)
857{
858 return port >> MV_PORT_HC_SHIFT;
859}
860
861static inline unsigned int mv_hardport_from_port(unsigned int port)
862{
863 return port & MV_PORT_MASK;
864}
865
Mark Lord1cfd19a2008-04-19 15:05:50 -0400866/*
867 * Consolidate some rather tricky bit shift calculations.
868 * This is hot-path stuff, so not a function.
869 * Simple code, with two return values, so macro rather than inline.
870 *
871 * port is the sole input, in range 0..7.
Mark Lord7368f912008-04-25 11:24:24 -0400872 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
873 * hardport is the other output, in range 0..3.
Mark Lord1cfd19a2008-04-19 15:05:50 -0400874 *
875 * Note that port and hardport may be the same variable in some cases.
876 */
877#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
878{ \
879 shift = mv_hc_from_port(port) * HC_SHIFT; \
880 hardport = mv_hardport_from_port(port); \
881 shift += hardport * 2; \
882}
883
Mark Lord352fab72008-04-19 14:43:42 -0400884static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
885{
Mark Lordcae5a292009-04-06 16:43:45 -0400886 return (base + SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
Mark Lord352fab72008-04-19 14:43:42 -0400887}
888
Jeff Garzikc9d39132005-11-13 17:47:51 -0500889static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
890 unsigned int port)
891{
892 return mv_hc_base(base, mv_hc_from_port(port));
893}
894
Brett Russ20f733e2005-09-01 18:26:17 -0400895static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
896{
Jeff Garzikc9d39132005-11-13 17:47:51 -0500897 return mv_hc_base_from_port(base, port) +
Jeff Garzik8b260242005-11-12 12:32:50 -0500898 MV_SATAHC_ARBTR_REG_SZ +
Jeff Garzikc9d39132005-11-13 17:47:51 -0500899 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
Brett Russ20f733e2005-09-01 18:26:17 -0400900}
901
Mark Lorde12bef52008-03-31 19:33:56 -0400902static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
903{
904 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
905 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
906
907 return hc_mmio + ofs;
908}
909
Saeed Bisharaf351b2d2008-02-01 18:08:03 -0500910static inline void __iomem *mv_host_base(struct ata_host *host)
911{
912 struct mv_host_priv *hpriv = host->private_data;
913 return hpriv->base;
914}
915
Brett Russ20f733e2005-09-01 18:26:17 -0400916static inline void __iomem *mv_ap_base(struct ata_port *ap)
917{
Saeed Bisharaf351b2d2008-02-01 18:08:03 -0500918 return mv_port_base(mv_host_base(ap->host), ap->port_no);
Brett Russ20f733e2005-09-01 18:26:17 -0400919}
920
Jeff Garzikcca39742006-08-24 03:19:22 -0400921static inline int mv_get_hc_count(unsigned long port_flags)
Brett Russ20f733e2005-09-01 18:26:17 -0400922{
Jeff Garzikcca39742006-08-24 03:19:22 -0400923 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
Brett Russ20f733e2005-09-01 18:26:17 -0400924}
925
Mark Lord08da1752009-02-25 15:13:03 -0500926/**
927 * mv_save_cached_regs - (re-)initialize cached port registers
928 * @ap: the port whose registers we are caching
929 *
930 * Initialize the local cache of port registers,
931 * so that reading them over and over again can
932 * be avoided on the hotter paths of this driver.
933 * This saves a few microseconds each time we switch
934 * to/from EDMA mode to perform (eg.) a drive cache flush.
935 */
936static void mv_save_cached_regs(struct ata_port *ap)
937{
938 void __iomem *port_mmio = mv_ap_base(ap);
939 struct mv_port_priv *pp = ap->private_data;
940
Mark Lordcae5a292009-04-06 16:43:45 -0400941 pp->cached.fiscfg = readl(port_mmio + FISCFG);
942 pp->cached.ltmode = readl(port_mmio + LTMODE);
943 pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND);
944 pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD);
Mark Lord08da1752009-02-25 15:13:03 -0500945}
946
947/**
948 * mv_write_cached_reg - write to a cached port register
949 * @addr: hardware address of the register
950 * @old: pointer to cached value of the register
951 * @new: new value for the register
952 *
953 * Write a new value to a cached register,
954 * but only if the value is different from before.
955 */
956static inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new)
957{
958 if (new != *old) {
Mark Lord12f3b6d2009-04-06 15:26:24 -0400959 unsigned long laddr;
Mark Lord08da1752009-02-25 15:13:03 -0500960 *old = new;
Mark Lord12f3b6d2009-04-06 15:26:24 -0400961 /*
962 * Workaround for 88SX60x1-B2 FEr SATA#13:
963 * Read-after-write is needed to prevent generating 64-bit
964 * write cycles on the PCI bus for SATA interface registers
965 * at offsets ending in 0x4 or 0xc.
966 *
967 * Looks like a lot of fuss, but it avoids an unnecessary
968 * +1 usec read-after-write delay for unaffected registers.
969 */
970 laddr = (long)addr & 0xffff;
971 if (laddr >= 0x300 && laddr <= 0x33c) {
972 laddr &= 0x000f;
973 if (laddr == 0x4 || laddr == 0xc) {
974 writelfl(new, addr); /* read after write */
975 return;
976 }
977 }
978 writel(new, addr); /* unaffected by the errata */
Mark Lord08da1752009-02-25 15:13:03 -0500979 }
980}
981
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400982static void mv_set_edma_ptrs(void __iomem *port_mmio,
983 struct mv_host_priv *hpriv,
984 struct mv_port_priv *pp)
985{
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400986 u32 index;
987
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400988 /*
989 * initialize request queue
990 */
Mark Lordfcfb1f72008-04-19 15:06:40 -0400991 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
992 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400993
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400994 WARN_ON(pp->crqb_dma & 0x3ff);
Mark Lordcae5a292009-04-06 16:43:45 -0400995 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400996 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
Mark Lordcae5a292009-04-06 16:43:45 -0400997 port_mmio + EDMA_REQ_Q_IN_PTR);
998 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR);
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400999
1000 /*
1001 * initialize response queue
1002 */
Mark Lordfcfb1f72008-04-19 15:06:40 -04001003 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
1004 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001005
Jeff Garzikc5d3e452007-07-11 18:30:50 -04001006 WARN_ON(pp->crpb_dma & 0xff);
Mark Lordcae5a292009-04-06 16:43:45 -04001007 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI);
1008 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001009 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
Mark Lordcae5a292009-04-06 16:43:45 -04001010 port_mmio + EDMA_RSP_Q_OUT_PTR);
Jeff Garzikc5d3e452007-07-11 18:30:50 -04001011}
1012
Mark Lord2b748a02009-03-10 22:01:17 -04001013static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv)
1014{
1015 /*
1016 * When writing to the main_irq_mask in hardware,
1017 * we must ensure exclusivity between the interrupt coalescing bits
1018 * and the corresponding individual port DONE_IRQ bits.
1019 *
1020 * Note that this register is really an "IRQ enable" register,
1021 * not an "IRQ mask" register as Marvell's naming might suggest.
1022 */
1023 if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE))
1024 mask &= ~DONE_IRQ_0_3;
1025 if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE))
1026 mask &= ~DONE_IRQ_4_7;
1027 writelfl(mask, hpriv->main_irq_mask_addr);
1028}
1029
Mark Lordc4de5732008-05-17 13:35:21 -04001030static void mv_set_main_irq_mask(struct ata_host *host,
1031 u32 disable_bits, u32 enable_bits)
1032{
1033 struct mv_host_priv *hpriv = host->private_data;
1034 u32 old_mask, new_mask;
1035
Mark Lord96e2c4872008-05-17 13:38:00 -04001036 old_mask = hpriv->main_irq_mask;
Mark Lordc4de5732008-05-17 13:35:21 -04001037 new_mask = (old_mask & ~disable_bits) | enable_bits;
Mark Lord96e2c4872008-05-17 13:38:00 -04001038 if (new_mask != old_mask) {
1039 hpriv->main_irq_mask = new_mask;
Mark Lord2b748a02009-03-10 22:01:17 -04001040 mv_write_main_irq_mask(new_mask, hpriv);
Mark Lord96e2c4872008-05-17 13:38:00 -04001041 }
Mark Lordc4de5732008-05-17 13:35:21 -04001042}
1043
1044static void mv_enable_port_irqs(struct ata_port *ap,
1045 unsigned int port_bits)
1046{
1047 unsigned int shift, hardport, port = ap->port_no;
1048 u32 disable_bits, enable_bits;
1049
1050 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
1051
1052 disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
1053 enable_bits = port_bits << shift;
1054 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
1055}
1056
Mark Lord00b81232009-01-30 18:47:51 -05001057static void mv_clear_and_enable_port_irqs(struct ata_port *ap,
1058 void __iomem *port_mmio,
1059 unsigned int port_irqs)
1060{
1061 struct mv_host_priv *hpriv = ap->host->private_data;
1062 int hardport = mv_hardport_from_port(ap->port_no);
1063 void __iomem *hc_mmio = mv_hc_base_from_port(
1064 mv_host_base(ap->host), ap->port_no);
1065 u32 hc_irq_cause;
1066
1067 /* clear EDMA event indicators, if any */
Mark Lordcae5a292009-04-06 16:43:45 -04001068 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
Mark Lord00b81232009-01-30 18:47:51 -05001069
1070 /* clear pending irq events */
1071 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
Mark Lordcae5a292009-04-06 16:43:45 -04001072 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
Mark Lord00b81232009-01-30 18:47:51 -05001073
1074 /* clear FIS IRQ Cause */
1075 if (IS_GEN_IIE(hpriv))
Mark Lordcae5a292009-04-06 16:43:45 -04001076 writelfl(0, port_mmio + FIS_IRQ_CAUSE);
Mark Lord00b81232009-01-30 18:47:51 -05001077
1078 mv_enable_port_irqs(ap, port_irqs);
1079}
1080
Mark Lord2b748a02009-03-10 22:01:17 -04001081static void mv_set_irq_coalescing(struct ata_host *host,
1082 unsigned int count, unsigned int usecs)
1083{
1084 struct mv_host_priv *hpriv = host->private_data;
1085 void __iomem *mmio = hpriv->base, *hc_mmio;
1086 u32 coal_enable = 0;
1087 unsigned long flags;
Mark Lord6abf4672009-03-11 00:56:00 -04001088 unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC;
Mark Lord2b748a02009-03-10 22:01:17 -04001089 const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
1090 ALL_PORTS_COAL_DONE;
1091
1092 /* Disable IRQ coalescing if either threshold is zero */
1093 if (!usecs || !count) {
1094 clks = count = 0;
1095 } else {
1096 /* Respect maximum limits of the hardware */
1097 clks = usecs * COAL_CLOCKS_PER_USEC;
1098 if (clks > MAX_COAL_TIME_THRESHOLD)
1099 clks = MAX_COAL_TIME_THRESHOLD;
1100 if (count > MAX_COAL_IO_COUNT)
1101 count = MAX_COAL_IO_COUNT;
1102 }
1103
1104 spin_lock_irqsave(&host->lock, flags);
Mark Lord6abf4672009-03-11 00:56:00 -04001105 mv_set_main_irq_mask(host, coal_disable, 0);
Mark Lord2b748a02009-03-10 22:01:17 -04001106
Mark Lord6abf4672009-03-11 00:56:00 -04001107 if (is_dual_hc && !IS_GEN_I(hpriv)) {
Mark Lord2b748a02009-03-10 22:01:17 -04001108 /*
Mark Lord6abf4672009-03-11 00:56:00 -04001109 * GEN_II/GEN_IIE with dual host controllers:
1110 * one set of global thresholds for the entire chip.
Mark Lord2b748a02009-03-10 22:01:17 -04001111 */
Mark Lordcae5a292009-04-06 16:43:45 -04001112 writel(clks, mmio + IRQ_COAL_TIME_THRESHOLD);
1113 writel(count, mmio + IRQ_COAL_IO_THRESHOLD);
Mark Lord2b748a02009-03-10 22:01:17 -04001114 /* clear leftover coal IRQ bit */
Mark Lordcae5a292009-04-06 16:43:45 -04001115 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
Mark Lord6abf4672009-03-11 00:56:00 -04001116 if (count)
1117 coal_enable = ALL_PORTS_COAL_DONE;
1118 clks = count = 0; /* force clearing of regular regs below */
Mark Lord2b748a02009-03-10 22:01:17 -04001119 }
Mark Lord6abf4672009-03-11 00:56:00 -04001120
Mark Lord2b748a02009-03-10 22:01:17 -04001121 /*
1122 * All chips: independent thresholds for each HC on the chip.
1123 */
1124 hc_mmio = mv_hc_base_from_port(mmio, 0);
Mark Lordcae5a292009-04-06 16:43:45 -04001125 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
1126 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
1127 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
Mark Lord6abf4672009-03-11 00:56:00 -04001128 if (count)
1129 coal_enable |= PORTS_0_3_COAL_DONE;
1130 if (is_dual_hc) {
Mark Lord2b748a02009-03-10 22:01:17 -04001131 hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC);
Mark Lordcae5a292009-04-06 16:43:45 -04001132 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
1133 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
1134 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
Mark Lord6abf4672009-03-11 00:56:00 -04001135 if (count)
1136 coal_enable |= PORTS_4_7_COAL_DONE;
Mark Lord2b748a02009-03-10 22:01:17 -04001137 }
Mark Lord2b748a02009-03-10 22:01:17 -04001138
Mark Lord6abf4672009-03-11 00:56:00 -04001139 mv_set_main_irq_mask(host, 0, coal_enable);
Mark Lord2b748a02009-03-10 22:01:17 -04001140 spin_unlock_irqrestore(&host->lock, flags);
1141}
1142
Brett Russ05b308e2005-10-05 17:08:53 -04001143/**
Mark Lord00b81232009-01-30 18:47:51 -05001144 * mv_start_edma - Enable eDMA engine
Brett Russ05b308e2005-10-05 17:08:53 -04001145 * @base: port base address
1146 * @pp: port private data
1147 *
Tejun Heobeec7db2006-02-11 19:11:13 +09001148 * Verify the local cache of the eDMA state is accurate with a
1149 * WARN_ON.
Brett Russ05b308e2005-10-05 17:08:53 -04001150 *
1151 * LOCKING:
1152 * Inherited from caller.
1153 */
Mark Lord00b81232009-01-30 18:47:51 -05001154static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio,
Mark Lord72109162008-01-26 18:31:33 -05001155 struct mv_port_priv *pp, u8 protocol)
Brett Russ31961942005-09-30 01:36:00 -04001156{
Mark Lord72109162008-01-26 18:31:33 -05001157 int want_ncq = (protocol == ATA_PROT_NCQ);
1158
1159 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1160 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
1161 if (want_ncq != using_ncq)
Mark Lordb5624682008-03-31 19:34:40 -04001162 mv_stop_edma(ap);
Mark Lord72109162008-01-26 18:31:33 -05001163 }
Jeff Garzikc5d3e452007-07-11 18:30:50 -04001164 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
Mark Lord0c589122008-01-26 18:31:16 -05001165 struct mv_host_priv *hpriv = ap->host->private_data;
Mark Lord0c589122008-01-26 18:31:16 -05001166
Mark Lord00b81232009-01-30 18:47:51 -05001167 mv_edma_cfg(ap, want_ncq, 1);
Mark Lord0c589122008-01-26 18:31:16 -05001168
Mark Lordf630d562008-01-26 18:31:00 -05001169 mv_set_edma_ptrs(port_mmio, hpriv, pp);
Mark Lord00b81232009-01-30 18:47:51 -05001170 mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001171
Mark Lordcae5a292009-04-06 16:43:45 -04001172 writelfl(EDMA_EN, port_mmio + EDMA_CMD);
Brett Russafb0edd2005-10-05 17:08:42 -04001173 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
1174 }
Brett Russ31961942005-09-30 01:36:00 -04001175}
1176
Mark Lord9b2c4e02008-05-02 02:09:14 -04001177static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
1178{
1179 void __iomem *port_mmio = mv_ap_base(ap);
1180 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
1181 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
1182 int i;
1183
1184 /*
1185 * Wait for the EDMA engine to finish transactions in progress.
Mark Lordc46938c2008-05-02 14:02:28 -04001186 * No idea what a good "timeout" value might be, but measurements
1187 * indicate that it often requires hundreds of microseconds
1188 * with two drives in-use. So we use the 15msec value above
1189 * as a rough guess at what even more drives might require.
Mark Lord9b2c4e02008-05-02 02:09:14 -04001190 */
1191 for (i = 0; i < timeout; ++i) {
Mark Lordcae5a292009-04-06 16:43:45 -04001192 u32 edma_stat = readl(port_mmio + EDMA_STATUS);
Mark Lord9b2c4e02008-05-02 02:09:14 -04001193 if ((edma_stat & empty_idle) == empty_idle)
1194 break;
1195 udelay(per_loop);
1196 }
Joe Perchesa9a79df2011-04-15 15:51:59 -07001197 /* ata_port_info(ap, "%s: %u+ usecs\n", __func__, i); */
Mark Lord9b2c4e02008-05-02 02:09:14 -04001198}
1199
Brett Russ05b308e2005-10-05 17:08:53 -04001200/**
Mark Lorde12bef52008-03-31 19:33:56 -04001201 * mv_stop_edma_engine - Disable eDMA engine
Mark Lordb5624682008-03-31 19:34:40 -04001202 * @port_mmio: io base address
Brett Russ05b308e2005-10-05 17:08:53 -04001203 *
1204 * LOCKING:
1205 * Inherited from caller.
1206 */
Mark Lordb5624682008-03-31 19:34:40 -04001207static int mv_stop_edma_engine(void __iomem *port_mmio)
Brett Russ31961942005-09-30 01:36:00 -04001208{
Mark Lordb5624682008-03-31 19:34:40 -04001209 int i;
Brett Russ31961942005-09-30 01:36:00 -04001210
Mark Lordb5624682008-03-31 19:34:40 -04001211 /* Disable eDMA. The disable bit auto clears. */
Mark Lordcae5a292009-04-06 16:43:45 -04001212 writelfl(EDMA_DS, port_mmio + EDMA_CMD);
Jeff Garzik8b260242005-11-12 12:32:50 -05001213
Mark Lordb5624682008-03-31 19:34:40 -04001214 /* Wait for the chip to confirm eDMA is off. */
1215 for (i = 10000; i > 0; i--) {
Mark Lordcae5a292009-04-06 16:43:45 -04001216 u32 reg = readl(port_mmio + EDMA_CMD);
Jeff Garzik4537deb2007-07-12 14:30:19 -04001217 if (!(reg & EDMA_EN))
Mark Lordb5624682008-03-31 19:34:40 -04001218 return 0;
1219 udelay(10);
Brett Russ31961942005-09-30 01:36:00 -04001220 }
Mark Lordb5624682008-03-31 19:34:40 -04001221 return -EIO;
Brett Russ31961942005-09-30 01:36:00 -04001222}
1223
Mark Lorde12bef52008-03-31 19:33:56 -04001224static int mv_stop_edma(struct ata_port *ap)
Jeff Garzik0ea9e172007-07-13 17:06:45 -04001225{
Mark Lordb5624682008-03-31 19:34:40 -04001226 void __iomem *port_mmio = mv_ap_base(ap);
1227 struct mv_port_priv *pp = ap->private_data;
Mark Lord66e57a22009-01-30 18:52:58 -05001228 int err = 0;
Jeff Garzik0ea9e172007-07-13 17:06:45 -04001229
Mark Lordb5624682008-03-31 19:34:40 -04001230 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1231 return 0;
1232 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
Mark Lord9b2c4e02008-05-02 02:09:14 -04001233 mv_wait_for_edma_empty_idle(ap);
Mark Lordb5624682008-03-31 19:34:40 -04001234 if (mv_stop_edma_engine(port_mmio)) {
Joe Perchesa9a79df2011-04-15 15:51:59 -07001235 ata_port_err(ap, "Unable to stop eDMA\n");
Mark Lord66e57a22009-01-30 18:52:58 -05001236 err = -EIO;
Mark Lordb5624682008-03-31 19:34:40 -04001237 }
Mark Lord66e57a22009-01-30 18:52:58 -05001238 mv_edma_cfg(ap, 0, 0);
1239 return err;
Jeff Garzik0ea9e172007-07-13 17:06:45 -04001240}
1241
Jeff Garzik8a70f8d2005-10-05 17:19:47 -04001242#ifdef ATA_DEBUG
Brett Russ31961942005-09-30 01:36:00 -04001243static void mv_dump_mem(void __iomem *start, unsigned bytes)
1244{
Brett Russ31961942005-09-30 01:36:00 -04001245 int b, w;
1246 for (b = 0; b < bytes; ) {
1247 DPRINTK("%p: ", start + b);
1248 for (w = 0; b < bytes && w < 4; w++) {
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001249 printk("%08x ", readl(start + b));
Brett Russ31961942005-09-30 01:36:00 -04001250 b += sizeof(u32);
1251 }
1252 printk("\n");
1253 }
Brett Russ31961942005-09-30 01:36:00 -04001254}
Jeff Garzik8a70f8d2005-10-05 17:19:47 -04001255#endif
Andrew Lunn13b74082012-09-28 17:04:10 +02001256#if defined(ATA_DEBUG) || defined(CONFIG_PCI)
Brett Russ31961942005-09-30 01:36:00 -04001257static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
1258{
1259#ifdef ATA_DEBUG
1260 int b, w;
1261 u32 dw;
1262 for (b = 0; b < bytes; ) {
1263 DPRINTK("%02x: ", b);
1264 for (w = 0; b < bytes && w < 4; w++) {
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001265 (void) pci_read_config_dword(pdev, b, &dw);
1266 printk("%08x ", dw);
Brett Russ31961942005-09-30 01:36:00 -04001267 b += sizeof(u32);
1268 }
1269 printk("\n");
1270 }
1271#endif
1272}
Andrew Lunn13b74082012-09-28 17:04:10 +02001273#endif
Brett Russ31961942005-09-30 01:36:00 -04001274static void mv_dump_all_regs(void __iomem *mmio_base, int port,
1275 struct pci_dev *pdev)
1276{
1277#ifdef ATA_DEBUG
Jeff Garzik8b260242005-11-12 12:32:50 -05001278 void __iomem *hc_base = mv_hc_base(mmio_base,
Brett Russ31961942005-09-30 01:36:00 -04001279 port >> MV_PORT_HC_SHIFT);
1280 void __iomem *port_base;
1281 int start_port, num_ports, p, start_hc, num_hcs, hc;
1282
1283 if (0 > port) {
1284 start_hc = start_port = 0;
1285 num_ports = 8; /* shld be benign for 4 port devs */
1286 num_hcs = 2;
1287 } else {
1288 start_hc = port >> MV_PORT_HC_SHIFT;
1289 start_port = port;
1290 num_ports = num_hcs = 1;
1291 }
Jeff Garzik8b260242005-11-12 12:32:50 -05001292 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
Brett Russ31961942005-09-30 01:36:00 -04001293 num_ports > 1 ? num_ports - 1 : start_port);
1294
1295 if (NULL != pdev) {
1296 DPRINTK("PCI config space regs:\n");
1297 mv_dump_pci_cfg(pdev, 0x68);
1298 }
1299 DPRINTK("PCI regs:\n");
1300 mv_dump_mem(mmio_base+0xc00, 0x3c);
1301 mv_dump_mem(mmio_base+0xd00, 0x34);
1302 mv_dump_mem(mmio_base+0xf00, 0x4);
1303 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1304 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
Dan Alonid220c372006-04-10 23:20:22 -07001305 hc_base = mv_hc_base(mmio_base, hc);
Brett Russ31961942005-09-30 01:36:00 -04001306 DPRINTK("HC regs (HC %i):\n", hc);
1307 mv_dump_mem(hc_base, 0x1c);
1308 }
1309 for (p = start_port; p < start_port + num_ports; p++) {
1310 port_base = mv_port_base(mmio_base, p);
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001311 DPRINTK("EDMA regs (port %i):\n", p);
Brett Russ31961942005-09-30 01:36:00 -04001312 mv_dump_mem(port_base, 0x54);
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001313 DPRINTK("SATA regs (port %i):\n", p);
Brett Russ31961942005-09-30 01:36:00 -04001314 mv_dump_mem(port_base+0x300, 0x60);
1315 }
1316#endif
1317}
1318
Brett Russ20f733e2005-09-01 18:26:17 -04001319static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1320{
1321 unsigned int ofs;
1322
1323 switch (sc_reg_in) {
1324 case SCR_STATUS:
1325 case SCR_CONTROL:
1326 case SCR_ERROR:
Mark Lordcae5a292009-04-06 16:43:45 -04001327 ofs = SATA_STATUS + (sc_reg_in * sizeof(u32));
Brett Russ20f733e2005-09-01 18:26:17 -04001328 break;
1329 case SCR_ACTIVE:
Mark Lordcae5a292009-04-06 16:43:45 -04001330 ofs = SATA_ACTIVE; /* active is not with the others */
Brett Russ20f733e2005-09-01 18:26:17 -04001331 break;
1332 default:
1333 ofs = 0xffffffffU;
1334 break;
1335 }
1336 return ofs;
1337}
1338
Tejun Heo82ef04f2008-07-31 17:02:40 +09001339static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
Brett Russ20f733e2005-09-01 18:26:17 -04001340{
1341 unsigned int ofs = mv_scr_offset(sc_reg_in);
1342
Tejun Heoda3dbb12007-07-16 14:29:40 +09001343 if (ofs != 0xffffffffU) {
Tejun Heo82ef04f2008-07-31 17:02:40 +09001344 *val = readl(mv_ap_base(link->ap) + ofs);
Tejun Heoda3dbb12007-07-16 14:29:40 +09001345 return 0;
1346 } else
1347 return -EINVAL;
Brett Russ20f733e2005-09-01 18:26:17 -04001348}
1349
Tejun Heo82ef04f2008-07-31 17:02:40 +09001350static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
Brett Russ20f733e2005-09-01 18:26:17 -04001351{
1352 unsigned int ofs = mv_scr_offset(sc_reg_in);
1353
Tejun Heoda3dbb12007-07-16 14:29:40 +09001354 if (ofs != 0xffffffffU) {
Mark Lord20091772009-04-06 15:24:57 -04001355 void __iomem *addr = mv_ap_base(link->ap) + ofs;
1356 if (sc_reg_in == SCR_CONTROL) {
1357 /*
1358 * Workaround for 88SX60x1 FEr SATA#26:
1359 *
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001360 * COMRESETs have to take care not to accidentally
Mark Lord20091772009-04-06 15:24:57 -04001361 * put the drive to sleep when writing SCR_CONTROL.
1362 * Setting bits 12..15 prevents this problem.
1363 *
1364 * So if we see an outbound COMMRESET, set those bits.
1365 * Ditto for the followup write that clears the reset.
1366 *
1367 * The proprietary driver does this for
1368 * all chip versions, and so do we.
1369 */
1370 if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1)
1371 val |= 0xf000;
1372 }
1373 writelfl(val, addr);
Tejun Heoda3dbb12007-07-16 14:29:40 +09001374 return 0;
1375 } else
1376 return -EINVAL;
Brett Russ20f733e2005-09-01 18:26:17 -04001377}
1378
Mark Lordf2738272008-01-26 18:32:29 -05001379static void mv6_dev_config(struct ata_device *adev)
1380{
1381 /*
Mark Lorde49856d2008-04-16 14:59:07 -04001382 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1383 *
1384 * Gen-II does not support NCQ over a port multiplier
1385 * (no FIS-based switching).
Mark Lordf2738272008-01-26 18:32:29 -05001386 */
Mark Lorde49856d2008-04-16 14:59:07 -04001387 if (adev->flags & ATA_DFLAG_NCQ) {
Mark Lord352fab72008-04-19 14:43:42 -04001388 if (sata_pmp_attached(adev->link->ap)) {
Mark Lorde49856d2008-04-16 14:59:07 -04001389 adev->flags &= ~ATA_DFLAG_NCQ;
Joe Perchesa9a79df2011-04-15 15:51:59 -07001390 ata_dev_info(adev,
Mark Lord352fab72008-04-19 14:43:42 -04001391 "NCQ disabled for command-based switching\n");
Mark Lord352fab72008-04-19 14:43:42 -04001392 }
Mark Lorde49856d2008-04-16 14:59:07 -04001393 }
Mark Lordf2738272008-01-26 18:32:29 -05001394}
1395
Mark Lord3e4a1392008-05-02 02:10:02 -04001396static int mv_qc_defer(struct ata_queued_cmd *qc)
1397{
1398 struct ata_link *link = qc->dev->link;
1399 struct ata_port *ap = link->ap;
1400 struct mv_port_priv *pp = ap->private_data;
1401
1402 /*
Mark Lord29d187b2008-05-02 02:15:37 -04001403 * Don't allow new commands if we're in a delayed EH state
1404 * for NCQ and/or FIS-based switching.
1405 */
1406 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1407 return ATA_DEFER_PORT;
Gwendal Grignou159a7ff2009-10-12 15:44:00 -07001408
1409 /* PIO commands need exclusive link: no other commands [DMA or PIO]
1410 * can run concurrently.
1411 * set excl_link when we want to send a PIO command in DMA mode
1412 * or a non-NCQ command in NCQ mode.
1413 * When we receive a command from that link, and there are no
1414 * outstanding commands, mark a flag to clear excl_link and let
1415 * the command go through.
1416 */
1417 if (unlikely(ap->excl_link)) {
1418 if (link == ap->excl_link) {
1419 if (ap->nr_active_links)
1420 return ATA_DEFER_PORT;
1421 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
1422 return 0;
1423 } else
1424 return ATA_DEFER_PORT;
1425 }
1426
Mark Lord29d187b2008-05-02 02:15:37 -04001427 /*
Mark Lord3e4a1392008-05-02 02:10:02 -04001428 * If the port is completely idle, then allow the new qc.
1429 */
1430 if (ap->nr_active_links == 0)
1431 return 0;
1432
Tejun Heo4bdee6c2008-08-13 20:24:16 +09001433 /*
1434 * The port is operating in host queuing mode (EDMA) with NCQ
1435 * enabled, allow multiple NCQ commands. EDMA also allows
1436 * queueing multiple DMA commands but libata core currently
1437 * doesn't allow it.
1438 */
1439 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) &&
Gwendal Grignou159a7ff2009-10-12 15:44:00 -07001440 (pp->pp_flags & MV_PP_FLAG_NCQ_EN)) {
1441 if (ata_is_ncq(qc->tf.protocol))
1442 return 0;
1443 else {
1444 ap->excl_link = link;
1445 return ATA_DEFER_PORT;
1446 }
1447 }
Tejun Heo4bdee6c2008-08-13 20:24:16 +09001448
Mark Lord3e4a1392008-05-02 02:10:02 -04001449 return ATA_DEFER_PORT;
1450}
1451
Mark Lord08da1752009-02-25 15:13:03 -05001452static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs)
Mark Lorde49856d2008-04-16 14:59:07 -04001453{
Mark Lord08da1752009-02-25 15:13:03 -05001454 struct mv_port_priv *pp = ap->private_data;
1455 void __iomem *port_mmio;
Mark Lord00f42ea2008-05-02 02:11:45 -04001456
Mark Lord08da1752009-02-25 15:13:03 -05001457 u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg;
1458 u32 ltmode, *old_ltmode = &pp->cached.ltmode;
1459 u32 haltcond, *old_haltcond = &pp->cached.haltcond;
Mark Lord00f42ea2008-05-02 02:11:45 -04001460
Mark Lord08da1752009-02-25 15:13:03 -05001461 ltmode = *old_ltmode & ~LTMODE_BIT8;
1462 haltcond = *old_haltcond | EDMA_ERR_DEV;
Mark Lord00f42ea2008-05-02 02:11:45 -04001463
1464 if (want_fbs) {
Mark Lord08da1752009-02-25 15:13:03 -05001465 fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC;
1466 ltmode = *old_ltmode | LTMODE_BIT8;
Mark Lord4c299ca2008-05-02 02:16:20 -04001467 if (want_ncq)
Mark Lord08da1752009-02-25 15:13:03 -05001468 haltcond &= ~EDMA_ERR_DEV;
Mark Lord4c299ca2008-05-02 02:16:20 -04001469 else
Mark Lord08da1752009-02-25 15:13:03 -05001470 fiscfg |= FISCFG_WAIT_DEV_ERR;
1471 } else {
1472 fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
Mark Lorde49856d2008-04-16 14:59:07 -04001473 }
Mark Lord00f42ea2008-05-02 02:11:45 -04001474
Mark Lord08da1752009-02-25 15:13:03 -05001475 port_mmio = mv_ap_base(ap);
Mark Lordcae5a292009-04-06 16:43:45 -04001476 mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg);
1477 mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode);
1478 mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond);
Mark Lord0c589122008-01-26 18:31:16 -05001479}
Jeff Garzike4e7b892006-01-31 12:18:41 -05001480
Mark Lorddd2890f2008-05-02 02:10:56 -04001481static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1482{
1483 struct mv_host_priv *hpriv = ap->host->private_data;
1484 u32 old, new;
1485
1486 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
Mark Lordcae5a292009-04-06 16:43:45 -04001487 old = readl(hpriv->base + GPIO_PORT_CTL);
Mark Lorddd2890f2008-05-02 02:10:56 -04001488 if (want_ncq)
1489 new = old | (1 << 22);
1490 else
1491 new = old & ~(1 << 22);
1492 if (new != old)
Mark Lordcae5a292009-04-06 16:43:45 -04001493 writel(new, hpriv->base + GPIO_PORT_CTL);
Mark Lorddd2890f2008-05-02 02:10:56 -04001494}
1495
Mark Lordc01e8a22009-02-25 15:14:48 -05001496/**
Mark Lord40f21b12009-03-10 18:51:04 -04001497 * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
1498 * @ap: Port being initialized
Mark Lordc01e8a22009-02-25 15:14:48 -05001499 *
1500 * There are two DMA modes on these chips: basic DMA, and EDMA.
1501 *
1502 * Bit-0 of the "EDMA RESERVED" register enables/disables use
1503 * of basic DMA on the GEN_IIE versions of the chips.
1504 *
1505 * This bit survives EDMA resets, and must be set for basic DMA
1506 * to function, and should be cleared when EDMA is active.
1507 */
1508static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma)
1509{
1510 struct mv_port_priv *pp = ap->private_data;
1511 u32 new, *old = &pp->cached.unknown_rsvd;
1512
1513 if (enable_bmdma)
1514 new = *old | 1;
1515 else
1516 new = *old & ~1;
Mark Lordcae5a292009-04-06 16:43:45 -04001517 mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD, old, new);
Mark Lordc01e8a22009-02-25 15:14:48 -05001518}
1519
Mark Lord000b3442009-03-15 11:33:19 -04001520/*
1521 * SOC chips have an issue whereby the HDD LEDs don't always blink
1522 * during I/O when NCQ is enabled. Enabling a special "LED blink" mode
1523 * of the SOC takes care of it, generating a steady blink rate when
1524 * any drive on the chip is active.
1525 *
1526 * Unfortunately, the blink mode is a global hardware setting for the SOC,
1527 * so we must use it whenever at least one port on the SOC has NCQ enabled.
1528 *
1529 * We turn "LED blink" off when NCQ is not in use anywhere, because the normal
1530 * LED operation works then, and provides better (more accurate) feedback.
1531 *
1532 * Note that this code assumes that an SOC never has more than one HC onboard.
1533 */
1534static void mv_soc_led_blink_enable(struct ata_port *ap)
1535{
1536 struct ata_host *host = ap->host;
1537 struct mv_host_priv *hpriv = host->private_data;
1538 void __iomem *hc_mmio;
1539 u32 led_ctrl;
1540
1541 if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)
1542 return;
1543 hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN;
1544 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
Mark Lordcae5a292009-04-06 16:43:45 -04001545 led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
1546 writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
Mark Lord000b3442009-03-15 11:33:19 -04001547}
1548
1549static void mv_soc_led_blink_disable(struct ata_port *ap)
1550{
1551 struct ata_host *host = ap->host;
1552 struct mv_host_priv *hpriv = host->private_data;
1553 void __iomem *hc_mmio;
1554 u32 led_ctrl;
1555 unsigned int port;
1556
1557 if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN))
1558 return;
1559
1560 /* disable led-blink only if no ports are using NCQ */
1561 for (port = 0; port < hpriv->n_ports; port++) {
1562 struct ata_port *this_ap = host->ports[port];
1563 struct mv_port_priv *pp = this_ap->private_data;
1564
1565 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1566 return;
1567 }
1568
1569 hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN;
1570 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
Mark Lordcae5a292009-04-06 16:43:45 -04001571 led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
1572 writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
Mark Lord000b3442009-03-15 11:33:19 -04001573}
1574
Mark Lord00b81232009-01-30 18:47:51 -05001575static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma)
Jeff Garzike4e7b892006-01-31 12:18:41 -05001576{
1577 u32 cfg;
Mark Lorde12bef52008-03-31 19:33:56 -04001578 struct mv_port_priv *pp = ap->private_data;
1579 struct mv_host_priv *hpriv = ap->host->private_data;
1580 void __iomem *port_mmio = mv_ap_base(ap);
Jeff Garzike4e7b892006-01-31 12:18:41 -05001581
1582 /* set up non-NCQ EDMA configuration */
1583 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
Mark Lordd16ab3f2009-02-25 15:17:43 -05001584 pp->pp_flags &=
1585 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
Jeff Garzike4e7b892006-01-31 12:18:41 -05001586
1587 if (IS_GEN_I(hpriv))
1588 cfg |= (1 << 8); /* enab config burst size mask */
1589
Mark Lorddd2890f2008-05-02 02:10:56 -04001590 else if (IS_GEN_II(hpriv)) {
Jeff Garzike4e7b892006-01-31 12:18:41 -05001591 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
Mark Lorddd2890f2008-05-02 02:10:56 -04001592 mv_60x1_errata_sata25(ap, want_ncq);
Jeff Garzike4e7b892006-01-31 12:18:41 -05001593
Mark Lorddd2890f2008-05-02 02:10:56 -04001594 } else if (IS_GEN_IIE(hpriv)) {
Mark Lord00f42ea2008-05-02 02:11:45 -04001595 int want_fbs = sata_pmp_attached(ap);
1596 /*
1597 * Possible future enhancement:
1598 *
1599 * The chip can use FBS with non-NCQ, if we allow it,
1600 * But first we need to have the error handling in place
1601 * for this mode (datasheet section 7.3.15.4.2.3).
1602 * So disallow non-NCQ FBS for now.
1603 */
1604 want_fbs &= want_ncq;
1605
Mark Lord08da1752009-02-25 15:13:03 -05001606 mv_config_fbs(ap, want_ncq, want_fbs);
Mark Lord00f42ea2008-05-02 02:11:45 -04001607
1608 if (want_fbs) {
1609 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1610 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1611 }
1612
Jeff Garzike728eab2007-02-25 02:53:41 -05001613 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
Mark Lord00b81232009-01-30 18:47:51 -05001614 if (want_edma) {
1615 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1616 if (!IS_SOC(hpriv))
1617 cfg |= (1 << 18); /* enab early completion */
1618 }
Mark Lord616d4a92008-05-02 02:08:32 -04001619 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1620 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
Mark Lordc01e8a22009-02-25 15:14:48 -05001621 mv_bmdma_enable_iie(ap, !want_edma);
Mark Lord000b3442009-03-15 11:33:19 -04001622
1623 if (IS_SOC(hpriv)) {
1624 if (want_ncq)
1625 mv_soc_led_blink_enable(ap);
1626 else
1627 mv_soc_led_blink_disable(ap);
1628 }
Jeff Garzike4e7b892006-01-31 12:18:41 -05001629 }
1630
Mark Lord72109162008-01-26 18:31:33 -05001631 if (want_ncq) {
1632 cfg |= EDMA_CFG_NCQ;
1633 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
Mark Lord00b81232009-01-30 18:47:51 -05001634 }
Mark Lord72109162008-01-26 18:31:33 -05001635
Mark Lordcae5a292009-04-06 16:43:45 -04001636 writelfl(cfg, port_mmio + EDMA_CFG);
Jeff Garzike4e7b892006-01-31 12:18:41 -05001637}
1638
Mark Lordda2fa9b2008-01-26 18:32:45 -05001639static void mv_port_free_dma_mem(struct ata_port *ap)
1640{
1641 struct mv_host_priv *hpriv = ap->host->private_data;
1642 struct mv_port_priv *pp = ap->private_data;
Mark Lordeb73d552008-01-29 13:24:00 -05001643 int tag;
Mark Lordda2fa9b2008-01-26 18:32:45 -05001644
1645 if (pp->crqb) {
1646 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1647 pp->crqb = NULL;
1648 }
1649 if (pp->crpb) {
1650 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1651 pp->crpb = NULL;
1652 }
Mark Lordeb73d552008-01-29 13:24:00 -05001653 /*
1654 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1655 * For later hardware, we have one unique sg_tbl per NCQ tag.
1656 */
1657 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1658 if (pp->sg_tbl[tag]) {
1659 if (tag == 0 || !IS_GEN_I(hpriv))
1660 dma_pool_free(hpriv->sg_tbl_pool,
1661 pp->sg_tbl[tag],
1662 pp->sg_tbl_dma[tag]);
1663 pp->sg_tbl[tag] = NULL;
1664 }
Mark Lordda2fa9b2008-01-26 18:32:45 -05001665 }
1666}
1667
Brett Russ05b308e2005-10-05 17:08:53 -04001668/**
1669 * mv_port_start - Port specific init/start routine.
1670 * @ap: ATA channel to manipulate
1671 *
1672 * Allocate and point to DMA memory, init port private memory,
1673 * zero indices.
1674 *
1675 * LOCKING:
1676 * Inherited from caller.
1677 */
Brett Russ31961942005-09-30 01:36:00 -04001678static int mv_port_start(struct ata_port *ap)
1679{
Jeff Garzikcca39742006-08-24 03:19:22 -04001680 struct device *dev = ap->host->dev;
1681 struct mv_host_priv *hpriv = ap->host->private_data;
Brett Russ31961942005-09-30 01:36:00 -04001682 struct mv_port_priv *pp;
Mark Lord933cb8e2009-04-06 12:30:43 -04001683 unsigned long flags;
James Bottomleydde20202008-02-19 11:36:56 +01001684 int tag;
Brett Russ31961942005-09-30 01:36:00 -04001685
Tejun Heo24dc5f32007-01-20 16:00:28 +09001686 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
Jeff Garzik6037d6b2005-11-04 22:08:00 -05001687 if (!pp)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001688 return -ENOMEM;
Mark Lordda2fa9b2008-01-26 18:32:45 -05001689 ap->private_data = pp;
Brett Russ31961942005-09-30 01:36:00 -04001690
Mark Lordda2fa9b2008-01-26 18:32:45 -05001691 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1692 if (!pp->crqb)
1693 return -ENOMEM;
1694 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
Brett Russ31961942005-09-30 01:36:00 -04001695
Mark Lordda2fa9b2008-01-26 18:32:45 -05001696 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1697 if (!pp->crpb)
1698 goto out_port_free_dma_mem;
1699 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
Brett Russ31961942005-09-30 01:36:00 -04001700
Mark Lord3bd0a702008-06-18 12:11:16 -04001701 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
1702 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
1703 ap->flags |= ATA_FLAG_AN;
Mark Lordeb73d552008-01-29 13:24:00 -05001704 /*
1705 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1706 * For later hardware, we need one unique sg_tbl per NCQ tag.
1707 */
1708 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1709 if (tag == 0 || !IS_GEN_I(hpriv)) {
1710 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1711 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1712 if (!pp->sg_tbl[tag])
1713 goto out_port_free_dma_mem;
1714 } else {
1715 pp->sg_tbl[tag] = pp->sg_tbl[0];
1716 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1717 }
1718 }
Mark Lord933cb8e2009-04-06 12:30:43 -04001719
1720 spin_lock_irqsave(ap->lock, flags);
Mark Lord08da1752009-02-25 15:13:03 -05001721 mv_save_cached_regs(ap);
Mark Lord66e57a22009-01-30 18:52:58 -05001722 mv_edma_cfg(ap, 0, 0);
Mark Lord933cb8e2009-04-06 12:30:43 -04001723 spin_unlock_irqrestore(ap->lock, flags);
1724
Brett Russ31961942005-09-30 01:36:00 -04001725 return 0;
Mark Lordda2fa9b2008-01-26 18:32:45 -05001726
1727out_port_free_dma_mem:
1728 mv_port_free_dma_mem(ap);
1729 return -ENOMEM;
Brett Russ31961942005-09-30 01:36:00 -04001730}
1731
Brett Russ05b308e2005-10-05 17:08:53 -04001732/**
1733 * mv_port_stop - Port specific cleanup/stop routine.
1734 * @ap: ATA channel to manipulate
1735 *
1736 * Stop DMA, cleanup port memory.
1737 *
1738 * LOCKING:
Jeff Garzikcca39742006-08-24 03:19:22 -04001739 * This routine uses the host lock to protect the DMA stop.
Brett Russ05b308e2005-10-05 17:08:53 -04001740 */
Brett Russ31961942005-09-30 01:36:00 -04001741static void mv_port_stop(struct ata_port *ap)
1742{
Mark Lord933cb8e2009-04-06 12:30:43 -04001743 unsigned long flags;
1744
1745 spin_lock_irqsave(ap->lock, flags);
Mark Lorde12bef52008-03-31 19:33:56 -04001746 mv_stop_edma(ap);
Mark Lord88e675e2008-05-17 13:36:30 -04001747 mv_enable_port_irqs(ap, 0);
Mark Lord933cb8e2009-04-06 12:30:43 -04001748 spin_unlock_irqrestore(ap->lock, flags);
Mark Lordda2fa9b2008-01-26 18:32:45 -05001749 mv_port_free_dma_mem(ap);
Brett Russ31961942005-09-30 01:36:00 -04001750}
1751
Brett Russ05b308e2005-10-05 17:08:53 -04001752/**
1753 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1754 * @qc: queued command whose SG list to source from
1755 *
1756 * Populate the SG list and mark the last entry.
1757 *
1758 * LOCKING:
1759 * Inherited from caller.
1760 */
Jeff Garzik6c087722007-10-12 00:16:23 -04001761static void mv_fill_sg(struct ata_queued_cmd *qc)
Brett Russ31961942005-09-30 01:36:00 -04001762{
1763 struct mv_port_priv *pp = qc->ap->private_data;
Jeff Garzik972c26b2005-10-18 22:14:54 -04001764 struct scatterlist *sg;
Jeff Garzik3be6cbd2007-10-18 16:21:18 -04001765 struct mv_sg *mv_sg, *last_sg = NULL;
Tejun Heoff2aeb12007-12-05 16:43:11 +09001766 unsigned int si;
Brett Russ31961942005-09-30 01:36:00 -04001767
Mark Lordeb73d552008-01-29 13:24:00 -05001768 mv_sg = pp->sg_tbl[qc->tag];
Tejun Heoff2aeb12007-12-05 16:43:11 +09001769 for_each_sg(qc->sg, sg, qc->n_elem, si) {
Jeff Garzikd88184f2007-02-26 01:26:06 -05001770 dma_addr_t addr = sg_dma_address(sg);
1771 u32 sg_len = sg_dma_len(sg);
Brett Russ31961942005-09-30 01:36:00 -04001772
Olof Johansson4007b492007-10-02 20:45:27 -05001773 while (sg_len) {
1774 u32 offset = addr & 0xffff;
1775 u32 len = sg_len;
Brett Russ31961942005-09-30 01:36:00 -04001776
Mark Lord32cd11a2009-02-01 16:50:32 -05001777 if (offset + len > 0x10000)
Olof Johansson4007b492007-10-02 20:45:27 -05001778 len = 0x10000 - offset;
Jeff Garzik972c26b2005-10-18 22:14:54 -04001779
Olof Johansson4007b492007-10-02 20:45:27 -05001780 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1781 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
Jeff Garzik6c087722007-10-12 00:16:23 -04001782 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
Mark Lord32cd11a2009-02-01 16:50:32 -05001783 mv_sg->reserved = 0;
Olof Johansson4007b492007-10-02 20:45:27 -05001784
1785 sg_len -= len;
1786 addr += len;
1787
Jeff Garzik3be6cbd2007-10-18 16:21:18 -04001788 last_sg = mv_sg;
Olof Johansson4007b492007-10-02 20:45:27 -05001789 mv_sg++;
Olof Johansson4007b492007-10-02 20:45:27 -05001790 }
Brett Russ31961942005-09-30 01:36:00 -04001791 }
Jeff Garzik3be6cbd2007-10-18 16:21:18 -04001792
1793 if (likely(last_sg))
1794 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
Mark Lord32cd11a2009-02-01 16:50:32 -05001795 mb(); /* ensure data structure is visible to the chipset */
Brett Russ31961942005-09-30 01:36:00 -04001796}
1797
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001798static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
Brett Russ31961942005-09-30 01:36:00 -04001799{
Mark Lord559eeda2006-05-19 16:40:15 -04001800 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
Brett Russ31961942005-09-30 01:36:00 -04001801 (last ? CRQB_CMD_LAST : 0);
Mark Lord559eeda2006-05-19 16:40:15 -04001802 *cmdw = cpu_to_le16(tmp);
Brett Russ31961942005-09-30 01:36:00 -04001803}
1804
Brett Russ05b308e2005-10-05 17:08:53 -04001805/**
Mark Lordda142652009-01-30 18:51:54 -05001806 * mv_sff_irq_clear - Clear hardware interrupt after DMA.
1807 * @ap: Port associated with this ATA transaction.
1808 *
1809 * We need this only for ATAPI bmdma transactions,
1810 * as otherwise we experience spurious interrupts
1811 * after libata-sff handles the bmdma interrupts.
1812 */
1813static void mv_sff_irq_clear(struct ata_port *ap)
1814{
1815 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ);
1816}
1817
1818/**
1819 * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
1820 * @qc: queued command to check for chipset/DMA compatibility.
1821 *
1822 * The bmdma engines cannot handle speculative data sizes
1823 * (bytecount under/over flow). So only allow DMA for
1824 * data transfer commands with known data sizes.
1825 *
1826 * LOCKING:
1827 * Inherited from caller.
1828 */
1829static int mv_check_atapi_dma(struct ata_queued_cmd *qc)
1830{
1831 struct scsi_cmnd *scmd = qc->scsicmd;
1832
1833 if (scmd) {
1834 switch (scmd->cmnd[0]) {
1835 case READ_6:
1836 case READ_10:
1837 case READ_12:
1838 case WRITE_6:
1839 case WRITE_10:
1840 case WRITE_12:
1841 case GPCMD_READ_CD:
1842 case GPCMD_SEND_DVD_STRUCTURE:
1843 case GPCMD_SEND_CUE_SHEET:
1844 return 0; /* DMA is safe */
1845 }
1846 }
1847 return -EOPNOTSUPP; /* use PIO instead */
1848}
1849
1850/**
1851 * mv_bmdma_setup - Set up BMDMA transaction
1852 * @qc: queued command to prepare DMA for.
1853 *
1854 * LOCKING:
1855 * Inherited from caller.
1856 */
1857static void mv_bmdma_setup(struct ata_queued_cmd *qc)
1858{
1859 struct ata_port *ap = qc->ap;
1860 void __iomem *port_mmio = mv_ap_base(ap);
1861 struct mv_port_priv *pp = ap->private_data;
1862
1863 mv_fill_sg(qc);
1864
1865 /* clear all DMA cmd bits */
Mark Lordcae5a292009-04-06 16:43:45 -04001866 writel(0, port_mmio + BMDMA_CMD);
Mark Lordda142652009-01-30 18:51:54 -05001867
1868 /* load PRD table addr. */
1869 writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16,
Mark Lordcae5a292009-04-06 16:43:45 -04001870 port_mmio + BMDMA_PRD_HIGH);
Mark Lordda142652009-01-30 18:51:54 -05001871 writelfl(pp->sg_tbl_dma[qc->tag],
Mark Lordcae5a292009-04-06 16:43:45 -04001872 port_mmio + BMDMA_PRD_LOW);
Mark Lordda142652009-01-30 18:51:54 -05001873
1874 /* issue r/w command */
1875 ap->ops->sff_exec_command(ap, &qc->tf);
1876}
1877
1878/**
1879 * mv_bmdma_start - Start a BMDMA transaction
1880 * @qc: queued command to start DMA on.
1881 *
1882 * LOCKING:
1883 * Inherited from caller.
1884 */
1885static void mv_bmdma_start(struct ata_queued_cmd *qc)
1886{
1887 struct ata_port *ap = qc->ap;
1888 void __iomem *port_mmio = mv_ap_base(ap);
1889 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
1890 u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START;
1891
1892 /* start host DMA transaction */
Mark Lordcae5a292009-04-06 16:43:45 -04001893 writelfl(cmd, port_mmio + BMDMA_CMD);
Mark Lordda142652009-01-30 18:51:54 -05001894}
1895
1896/**
1897 * mv_bmdma_stop - Stop BMDMA transfer
1898 * @qc: queued command to stop DMA on.
1899 *
1900 * Clears the ATA_DMA_START flag in the bmdma control register
1901 *
1902 * LOCKING:
1903 * Inherited from caller.
1904 */
Mark Lord44b73382010-08-19 21:40:44 -04001905static void mv_bmdma_stop_ap(struct ata_port *ap)
Mark Lordda142652009-01-30 18:51:54 -05001906{
Mark Lordda142652009-01-30 18:51:54 -05001907 void __iomem *port_mmio = mv_ap_base(ap);
1908 u32 cmd;
1909
1910 /* clear start/stop bit */
Mark Lordcae5a292009-04-06 16:43:45 -04001911 cmd = readl(port_mmio + BMDMA_CMD);
Mark Lord44b73382010-08-19 21:40:44 -04001912 if (cmd & ATA_DMA_START) {
1913 cmd &= ~ATA_DMA_START;
1914 writelfl(cmd, port_mmio + BMDMA_CMD);
Mark Lordda142652009-01-30 18:51:54 -05001915
Mark Lord44b73382010-08-19 21:40:44 -04001916 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
1917 ata_sff_dma_pause(ap);
1918 }
1919}
1920
1921static void mv_bmdma_stop(struct ata_queued_cmd *qc)
1922{
1923 mv_bmdma_stop_ap(qc->ap);
Mark Lordda142652009-01-30 18:51:54 -05001924}
1925
1926/**
1927 * mv_bmdma_status - Read BMDMA status
1928 * @ap: port for which to retrieve DMA status.
1929 *
1930 * Read and return equivalent of the sff BMDMA status register.
1931 *
1932 * LOCKING:
1933 * Inherited from caller.
1934 */
1935static u8 mv_bmdma_status(struct ata_port *ap)
1936{
1937 void __iomem *port_mmio = mv_ap_base(ap);
1938 u32 reg, status;
1939
1940 /*
1941 * Other bits are valid only if ATA_DMA_ACTIVE==0,
1942 * and the ATA_DMA_INTR bit doesn't exist.
1943 */
Mark Lordcae5a292009-04-06 16:43:45 -04001944 reg = readl(port_mmio + BMDMA_STATUS);
Mark Lordda142652009-01-30 18:51:54 -05001945 if (reg & ATA_DMA_ACTIVE)
1946 status = ATA_DMA_ACTIVE;
Mark Lord44b73382010-08-19 21:40:44 -04001947 else if (reg & ATA_DMA_ERR)
Mark Lordda142652009-01-30 18:51:54 -05001948 status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR;
Mark Lord44b73382010-08-19 21:40:44 -04001949 else {
1950 /*
1951 * Just because DMA_ACTIVE is 0 (DMA completed),
1952 * this does _not_ mean the device is "done".
1953 * So we should not yet be signalling ATA_DMA_INTR
1954 * in some cases. Eg. DSM/TRIM, and perhaps others.
1955 */
1956 mv_bmdma_stop_ap(ap);
1957 if (ioread8(ap->ioaddr.altstatus_addr) & ATA_BUSY)
1958 status = 0;
1959 else
1960 status = ATA_DMA_INTR;
1961 }
Mark Lordda142652009-01-30 18:51:54 -05001962 return status;
1963}
1964
Mark Lord299b3f82009-04-13 11:29:34 -04001965static void mv_rw_multi_errata_sata24(struct ata_queued_cmd *qc)
1966{
1967 struct ata_taskfile *tf = &qc->tf;
1968 /*
1969 * Workaround for 88SX60x1 FEr SATA#24.
1970 *
1971 * Chip may corrupt WRITEs if multi_count >= 4kB.
1972 * Note that READs are unaffected.
1973 *
1974 * It's not clear if this errata really means "4K bytes",
1975 * or if it always happens for multi_count > 7
1976 * regardless of device sector_size.
1977 *
1978 * So, for safety, any write with multi_count > 7
1979 * gets converted here into a regular PIO write instead:
1980 */
1981 if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) {
1982 if (qc->dev->multi_count > 7) {
1983 switch (tf->command) {
1984 case ATA_CMD_WRITE_MULTI:
1985 tf->command = ATA_CMD_PIO_WRITE;
1986 break;
1987 case ATA_CMD_WRITE_MULTI_FUA_EXT:
1988 tf->flags &= ~ATA_TFLAG_FUA; /* ugh */
1989 /* fall through */
1990 case ATA_CMD_WRITE_MULTI_EXT:
1991 tf->command = ATA_CMD_PIO_WRITE_EXT;
1992 break;
1993 }
1994 }
1995 }
1996}
1997
Mark Lordda142652009-01-30 18:51:54 -05001998/**
Brett Russ05b308e2005-10-05 17:08:53 -04001999 * mv_qc_prep - Host specific command preparation.
2000 * @qc: queued command to prepare
2001 *
2002 * This routine simply redirects to the general purpose routine
2003 * if command is not DMA. Else, it handles prep of the CRQB
2004 * (command request block), does some sanity checking, and calls
2005 * the SG load routine.
2006 *
2007 * LOCKING:
2008 * Inherited from caller.
2009 */
Brett Russ31961942005-09-30 01:36:00 -04002010static void mv_qc_prep(struct ata_queued_cmd *qc)
2011{
2012 struct ata_port *ap = qc->ap;
2013 struct mv_port_priv *pp = ap->private_data;
Mark Lorde1469872006-05-22 19:02:03 -04002014 __le16 *cw;
Mark Lord8d2b4502009-04-13 11:27:18 -04002015 struct ata_taskfile *tf = &qc->tf;
Brett Russ31961942005-09-30 01:36:00 -04002016 u16 flags = 0;
Mark Lorda6432432006-05-19 16:36:36 -04002017 unsigned in_index;
Brett Russ31961942005-09-30 01:36:00 -04002018
Mark Lord299b3f82009-04-13 11:29:34 -04002019 switch (tf->protocol) {
2020 case ATA_PROT_DMA:
Mark Lord44b73382010-08-19 21:40:44 -04002021 if (tf->command == ATA_CMD_DSM)
2022 return;
2023 /* fall-thru */
Mark Lord299b3f82009-04-13 11:29:34 -04002024 case ATA_PROT_NCQ:
2025 break; /* continue below */
2026 case ATA_PROT_PIO:
2027 mv_rw_multi_errata_sata24(qc);
Brett Russ31961942005-09-30 01:36:00 -04002028 return;
Mark Lord299b3f82009-04-13 11:29:34 -04002029 default:
2030 return;
2031 }
Brett Russ20f733e2005-09-01 18:26:17 -04002032
Brett Russ31961942005-09-30 01:36:00 -04002033 /* Fill in command request block
2034 */
Mark Lord8d2b4502009-04-13 11:27:18 -04002035 if (!(tf->flags & ATA_TFLAG_WRITE))
Brett Russ31961942005-09-30 01:36:00 -04002036 flags |= CRQB_FLAG_READ;
Tejun Heobeec7db2006-02-11 19:11:13 +09002037 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
Brett Russ31961942005-09-30 01:36:00 -04002038 flags |= qc->tag << CRQB_TAG_SHIFT;
Mark Lorde49856d2008-04-16 14:59:07 -04002039 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
Brett Russ31961942005-09-30 01:36:00 -04002040
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002041 /* get current queue index from software */
Mark Lordfcfb1f72008-04-19 15:06:40 -04002042 in_index = pp->req_idx;
Brett Russ31961942005-09-30 01:36:00 -04002043
Mark Lorda6432432006-05-19 16:36:36 -04002044 pp->crqb[in_index].sg_addr =
Mark Lordeb73d552008-01-29 13:24:00 -05002045 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
Mark Lorda6432432006-05-19 16:36:36 -04002046 pp->crqb[in_index].sg_addr_hi =
Mark Lordeb73d552008-01-29 13:24:00 -05002047 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
Mark Lorda6432432006-05-19 16:36:36 -04002048 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
2049
2050 cw = &pp->crqb[in_index].ata_cmd[0];
Brett Russ31961942005-09-30 01:36:00 -04002051
Lucas De Marchi25985ed2011-03-30 22:57:33 -03002052 /* Sadly, the CRQB cannot accommodate all registers--there are
Brett Russ31961942005-09-30 01:36:00 -04002053 * only 11 bytes...so we must pick and choose required
2054 * registers based on the command. So, we drop feature and
2055 * hob_feature for [RW] DMA commands, but they are needed for
Mark Lordcd12e1f2009-01-19 18:06:28 -05002056 * NCQ. NCQ will drop hob_nsect, which is not needed there
2057 * (nsect is used only for the tag; feat/hob_feat hold true nsect).
Brett Russ31961942005-09-30 01:36:00 -04002058 */
2059 switch (tf->command) {
2060 case ATA_CMD_READ:
2061 case ATA_CMD_READ_EXT:
2062 case ATA_CMD_WRITE:
2063 case ATA_CMD_WRITE_EXT:
Jens Axboec15d85c2006-02-15 15:59:25 +01002064 case ATA_CMD_WRITE_FUA_EXT:
Brett Russ31961942005-09-30 01:36:00 -04002065 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
2066 break;
Brett Russ31961942005-09-30 01:36:00 -04002067 case ATA_CMD_FPDMA_READ:
2068 case ATA_CMD_FPDMA_WRITE:
Jeff Garzik8b260242005-11-12 12:32:50 -05002069 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
Brett Russ31961942005-09-30 01:36:00 -04002070 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
2071 break;
Brett Russ31961942005-09-30 01:36:00 -04002072 default:
2073 /* The only other commands EDMA supports in non-queued and
2074 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
2075 * of which are defined/used by Linux. If we get here, this
2076 * driver needs work.
2077 *
2078 * FIXME: modify libata to give qc_prep a return value and
2079 * return error here.
2080 */
2081 BUG_ON(tf->command);
2082 break;
2083 }
2084 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
2085 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
2086 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
2087 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
2088 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
2089 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
2090 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
2091 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
2092 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
2093
Jeff Garzike4e7b892006-01-31 12:18:41 -05002094 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
Brett Russ31961942005-09-30 01:36:00 -04002095 return;
Jeff Garzike4e7b892006-01-31 12:18:41 -05002096 mv_fill_sg(qc);
2097}
2098
2099/**
2100 * mv_qc_prep_iie - Host specific command preparation.
2101 * @qc: queued command to prepare
2102 *
2103 * This routine simply redirects to the general purpose routine
2104 * if command is not DMA. Else, it handles prep of the CRQB
2105 * (command request block), does some sanity checking, and calls
2106 * the SG load routine.
2107 *
2108 * LOCKING:
2109 * Inherited from caller.
2110 */
2111static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
2112{
2113 struct ata_port *ap = qc->ap;
2114 struct mv_port_priv *pp = ap->private_data;
2115 struct mv_crqb_iie *crqb;
Mark Lord8d2b4502009-04-13 11:27:18 -04002116 struct ata_taskfile *tf = &qc->tf;
Mark Lorda6432432006-05-19 16:36:36 -04002117 unsigned in_index;
Jeff Garzike4e7b892006-01-31 12:18:41 -05002118 u32 flags = 0;
2119
Mark Lord8d2b4502009-04-13 11:27:18 -04002120 if ((tf->protocol != ATA_PROT_DMA) &&
2121 (tf->protocol != ATA_PROT_NCQ))
Jeff Garzike4e7b892006-01-31 12:18:41 -05002122 return;
Mark Lord44b73382010-08-19 21:40:44 -04002123 if (tf->command == ATA_CMD_DSM)
2124 return; /* use bmdma for this */
Jeff Garzike4e7b892006-01-31 12:18:41 -05002125
Mark Lorde12bef52008-03-31 19:33:56 -04002126 /* Fill in Gen IIE command request block */
Mark Lord8d2b4502009-04-13 11:27:18 -04002127 if (!(tf->flags & ATA_TFLAG_WRITE))
Jeff Garzike4e7b892006-01-31 12:18:41 -05002128 flags |= CRQB_FLAG_READ;
2129
Tejun Heobeec7db2006-02-11 19:11:13 +09002130 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
Jeff Garzike4e7b892006-01-31 12:18:41 -05002131 flags |= qc->tag << CRQB_TAG_SHIFT;
Mark Lord8c0aeb42008-01-26 18:31:48 -05002132 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
Mark Lorde49856d2008-04-16 14:59:07 -04002133 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
Jeff Garzike4e7b892006-01-31 12:18:41 -05002134
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002135 /* get current queue index from software */
Mark Lordfcfb1f72008-04-19 15:06:40 -04002136 in_index = pp->req_idx;
Mark Lorda6432432006-05-19 16:36:36 -04002137
2138 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
Mark Lordeb73d552008-01-29 13:24:00 -05002139 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
2140 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
Jeff Garzike4e7b892006-01-31 12:18:41 -05002141 crqb->flags = cpu_to_le32(flags);
2142
Jeff Garzike4e7b892006-01-31 12:18:41 -05002143 crqb->ata_cmd[0] = cpu_to_le32(
2144 (tf->command << 16) |
2145 (tf->feature << 24)
2146 );
2147 crqb->ata_cmd[1] = cpu_to_le32(
2148 (tf->lbal << 0) |
2149 (tf->lbam << 8) |
2150 (tf->lbah << 16) |
2151 (tf->device << 24)
2152 );
2153 crqb->ata_cmd[2] = cpu_to_le32(
2154 (tf->hob_lbal << 0) |
2155 (tf->hob_lbam << 8) |
2156 (tf->hob_lbah << 16) |
2157 (tf->hob_feature << 24)
2158 );
2159 crqb->ata_cmd[3] = cpu_to_le32(
2160 (tf->nsect << 0) |
2161 (tf->hob_nsect << 8)
2162 );
2163
2164 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2165 return;
Brett Russ31961942005-09-30 01:36:00 -04002166 mv_fill_sg(qc);
2167}
2168
Brett Russ05b308e2005-10-05 17:08:53 -04002169/**
Mark Lordd16ab3f2009-02-25 15:17:43 -05002170 * mv_sff_check_status - fetch device status, if valid
2171 * @ap: ATA port to fetch status from
2172 *
2173 * When using command issue via mv_qc_issue_fis(),
2174 * the initial ATA_BUSY state does not show up in the
2175 * ATA status (shadow) register. This can confuse libata!
2176 *
2177 * So we have a hook here to fake ATA_BUSY for that situation,
2178 * until the first time a BUSY, DRQ, or ERR bit is seen.
2179 *
2180 * The rest of the time, it simply returns the ATA status register.
2181 */
2182static u8 mv_sff_check_status(struct ata_port *ap)
2183{
2184 u8 stat = ioread8(ap->ioaddr.status_addr);
2185 struct mv_port_priv *pp = ap->private_data;
2186
2187 if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) {
2188 if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR))
2189 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY;
2190 else
2191 stat = ATA_BUSY;
2192 }
2193 return stat;
2194}
2195
2196/**
Mark Lord70f8b792009-02-25 15:19:20 -05002197 * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register
2198 * @fis: fis to be sent
2199 * @nwords: number of 32-bit words in the fis
2200 */
2201static unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords)
2202{
2203 void __iomem *port_mmio = mv_ap_base(ap);
2204 u32 ifctl, old_ifctl, ifstat;
2205 int i, timeout = 200, final_word = nwords - 1;
2206
2207 /* Initiate FIS transmission mode */
Mark Lordcae5a292009-04-06 16:43:45 -04002208 old_ifctl = readl(port_mmio + SATA_IFCTL);
Mark Lord70f8b792009-02-25 15:19:20 -05002209 ifctl = 0x100 | (old_ifctl & 0xf);
Mark Lordcae5a292009-04-06 16:43:45 -04002210 writelfl(ifctl, port_mmio + SATA_IFCTL);
Mark Lord70f8b792009-02-25 15:19:20 -05002211
2212 /* Send all words of the FIS except for the final word */
2213 for (i = 0; i < final_word; ++i)
Mark Lordcae5a292009-04-06 16:43:45 -04002214 writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS);
Mark Lord70f8b792009-02-25 15:19:20 -05002215
2216 /* Flag end-of-transmission, and then send the final word */
Mark Lordcae5a292009-04-06 16:43:45 -04002217 writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL);
2218 writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS);
Mark Lord70f8b792009-02-25 15:19:20 -05002219
2220 /*
2221 * Wait for FIS transmission to complete.
2222 * This typically takes just a single iteration.
2223 */
2224 do {
Mark Lordcae5a292009-04-06 16:43:45 -04002225 ifstat = readl(port_mmio + SATA_IFSTAT);
Mark Lord70f8b792009-02-25 15:19:20 -05002226 } while (!(ifstat & 0x1000) && --timeout);
2227
2228 /* Restore original port configuration */
Mark Lordcae5a292009-04-06 16:43:45 -04002229 writelfl(old_ifctl, port_mmio + SATA_IFCTL);
Mark Lord70f8b792009-02-25 15:19:20 -05002230
2231 /* See if it worked */
2232 if ((ifstat & 0x3000) != 0x1000) {
Joe Perchesa9a79df2011-04-15 15:51:59 -07002233 ata_port_warn(ap, "%s transmission error, ifstat=%08x\n",
2234 __func__, ifstat);
Mark Lord70f8b792009-02-25 15:19:20 -05002235 return AC_ERR_OTHER;
2236 }
2237 return 0;
2238}
2239
2240/**
2241 * mv_qc_issue_fis - Issue a command directly as a FIS
2242 * @qc: queued command to start
2243 *
2244 * Note that the ATA shadow registers are not updated
2245 * after command issue, so the device will appear "READY"
2246 * if polled, even while it is BUSY processing the command.
2247 *
2248 * So we use a status hook to fake ATA_BUSY until the drive changes state.
2249 *
2250 * Note: we don't get updated shadow regs on *completion*
2251 * of non-data commands. So avoid sending them via this function,
2252 * as they will appear to have completed immediately.
2253 *
2254 * GEN_IIE has special registers that we could get the result tf from,
2255 * but earlier chipsets do not. For now, we ignore those registers.
2256 */
2257static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc)
2258{
2259 struct ata_port *ap = qc->ap;
2260 struct mv_port_priv *pp = ap->private_data;
2261 struct ata_link *link = qc->dev->link;
2262 u32 fis[5];
2263 int err = 0;
2264
2265 ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis);
Thiago Farina4c4a90f2009-11-08 14:30:57 -05002266 err = mv_send_fis(ap, fis, ARRAY_SIZE(fis));
Mark Lord70f8b792009-02-25 15:19:20 -05002267 if (err)
2268 return err;
2269
2270 switch (qc->tf.protocol) {
2271 case ATAPI_PROT_PIO:
2272 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2273 /* fall through */
2274 case ATAPI_PROT_NODATA:
2275 ap->hsm_task_state = HSM_ST_FIRST;
2276 break;
2277 case ATA_PROT_PIO:
2278 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2279 if (qc->tf.flags & ATA_TFLAG_WRITE)
2280 ap->hsm_task_state = HSM_ST_FIRST;
2281 else
2282 ap->hsm_task_state = HSM_ST;
2283 break;
2284 default:
2285 ap->hsm_task_state = HSM_ST_LAST;
2286 break;
2287 }
2288
2289 if (qc->tf.flags & ATA_TFLAG_POLLING)
Gwendal Grignouea3c6452010-08-31 16:20:36 -07002290 ata_sff_queue_pio_task(link, 0);
Mark Lord70f8b792009-02-25 15:19:20 -05002291 return 0;
2292}
2293
2294/**
Brett Russ05b308e2005-10-05 17:08:53 -04002295 * mv_qc_issue - Initiate a command to the host
2296 * @qc: queued command to start
2297 *
2298 * This routine simply redirects to the general purpose routine
2299 * if command is not DMA. Else, it sanity checks our local
2300 * caches of the request producer/consumer indices then enables
2301 * DMA and bumps the request producer index.
2302 *
2303 * LOCKING:
2304 * Inherited from caller.
2305 */
Tejun Heo9a3d9eb2006-01-23 13:09:36 +09002306static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
Brett Russ31961942005-09-30 01:36:00 -04002307{
Mark Lordf48765c2009-01-30 18:48:41 -05002308 static int limit_warnings = 10;
Jeff Garzikc5d3e452007-07-11 18:30:50 -04002309 struct ata_port *ap = qc->ap;
2310 void __iomem *port_mmio = mv_ap_base(ap);
2311 struct mv_port_priv *pp = ap->private_data;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002312 u32 in_index;
Mark Lord42ed8932009-02-25 15:15:39 -05002313 unsigned int port_irqs;
Brett Russ31961942005-09-30 01:36:00 -04002314
Mark Lordd16ab3f2009-02-25 15:17:43 -05002315 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */
2316
Mark Lordf48765c2009-01-30 18:48:41 -05002317 switch (qc->tf.protocol) {
2318 case ATA_PROT_DMA:
Mark Lord44b73382010-08-19 21:40:44 -04002319 if (qc->tf.command == ATA_CMD_DSM) {
2320 if (!ap->ops->bmdma_setup) /* no bmdma on GEN_I */
2321 return AC_ERR_OTHER;
2322 break; /* use bmdma for this */
2323 }
2324 /* fall thru */
Mark Lordf48765c2009-01-30 18:48:41 -05002325 case ATA_PROT_NCQ:
2326 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);
2327 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2328 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
2329
2330 /* Write the request in pointer to kick the EDMA to life */
2331 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
Mark Lordcae5a292009-04-06 16:43:45 -04002332 port_mmio + EDMA_REQ_Q_IN_PTR);
Mark Lordf48765c2009-01-30 18:48:41 -05002333 return 0;
2334
2335 case ATA_PROT_PIO:
Mark Lordc6112bd2008-06-18 12:13:02 -04002336 /*
2337 * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
2338 *
2339 * Someday, we might implement special polling workarounds
2340 * for these, but it all seems rather unnecessary since we
2341 * normally use only DMA for commands which transfer more
2342 * than a single block of data.
2343 *
2344 * Much of the time, this could just work regardless.
2345 * So for now, just log the incident, and allow the attempt.
2346 */
Mark Lordc7843e82008-06-18 21:57:42 -04002347 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {
Mark Lordc6112bd2008-06-18 12:13:02 -04002348 --limit_warnings;
Joe Perchesa9a79df2011-04-15 15:51:59 -07002349 ata_link_warn(qc->dev->link, DRV_NAME
2350 ": attempting PIO w/multiple DRQ: "
2351 "this may fail due to h/w errata\n");
Mark Lordc6112bd2008-06-18 12:13:02 -04002352 }
Mark Lordf48765c2009-01-30 18:48:41 -05002353 /* drop through */
Mark Lord42ed8932009-02-25 15:15:39 -05002354 case ATA_PROT_NODATA:
Mark Lordf48765c2009-01-30 18:48:41 -05002355 case ATAPI_PROT_PIO:
Mark Lord42ed8932009-02-25 15:15:39 -05002356 case ATAPI_PROT_NODATA:
2357 if (ap->flags & ATA_FLAG_PIO_POLLING)
2358 qc->tf.flags |= ATA_TFLAG_POLLING;
2359 break;
Brett Russ31961942005-09-30 01:36:00 -04002360 }
Mark Lord42ed8932009-02-25 15:15:39 -05002361
2362 if (qc->tf.flags & ATA_TFLAG_POLLING)
2363 port_irqs = ERR_IRQ; /* mask device interrupt when polling */
2364 else
2365 port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */
2366
2367 /*
2368 * We're about to send a non-EDMA capable command to the
2369 * port. Turn off EDMA so there won't be problems accessing
2370 * shadow block, etc registers.
2371 */
2372 mv_stop_edma(ap);
2373 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs);
2374 mv_pmp_select(ap, qc->dev->link->pmp);
Mark Lord70f8b792009-02-25 15:19:20 -05002375
2376 if (qc->tf.command == ATA_CMD_READ_LOG_EXT) {
2377 struct mv_host_priv *hpriv = ap->host->private_data;
2378 /*
2379 * Workaround for 88SX60x1 FEr SATA#25 (part 2).
Mark Lord40f21b12009-03-10 18:51:04 -04002380 *
Mark Lord70f8b792009-02-25 15:19:20 -05002381 * After any NCQ error, the READ_LOG_EXT command
2382 * from libata-eh *must* use mv_qc_issue_fis().
2383 * Otherwise it might fail, due to chip errata.
2384 *
2385 * Rather than special-case it, we'll just *always*
2386 * use this method here for READ_LOG_EXT, making for
2387 * easier testing.
2388 */
2389 if (IS_GEN_II(hpriv))
2390 return mv_qc_issue_fis(qc);
2391 }
Tejun Heo360ff782010-05-10 21:41:42 +02002392 return ata_bmdma_qc_issue(qc);
Brett Russ31961942005-09-30 01:36:00 -04002393}
2394
Mark Lord8f767f82008-04-19 14:53:07 -04002395static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
2396{
2397 struct mv_port_priv *pp = ap->private_data;
2398 struct ata_queued_cmd *qc;
2399
2400 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
2401 return NULL;
2402 qc = ata_qc_from_tag(ap, ap->link.active_tag);
Tejun Heo3e4ec342010-05-10 21:41:30 +02002403 if (qc && !(qc->tf.flags & ATA_TFLAG_POLLING))
2404 return qc;
2405 return NULL;
Mark Lord8f767f82008-04-19 14:53:07 -04002406}
2407
Mark Lord29d187b2008-05-02 02:15:37 -04002408static void mv_pmp_error_handler(struct ata_port *ap)
2409{
2410 unsigned int pmp, pmp_map;
2411 struct mv_port_priv *pp = ap->private_data;
2412
2413 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
2414 /*
2415 * Perform NCQ error analysis on failed PMPs
2416 * before we freeze the port entirely.
2417 *
2418 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
2419 */
2420 pmp_map = pp->delayed_eh_pmp_map;
2421 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
2422 for (pmp = 0; pmp_map != 0; pmp++) {
2423 unsigned int this_pmp = (1 << pmp);
2424 if (pmp_map & this_pmp) {
2425 struct ata_link *link = &ap->pmp_link[pmp];
2426 pmp_map &= ~this_pmp;
2427 ata_eh_analyze_ncq_error(link);
2428 }
2429 }
2430 ata_port_freeze(ap);
2431 }
2432 sata_pmp_error_handler(ap);
2433}
2434
Mark Lord4c299ca2008-05-02 02:16:20 -04002435static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
2436{
2437 void __iomem *port_mmio = mv_ap_base(ap);
2438
Mark Lordcae5a292009-04-06 16:43:45 -04002439 return readl(port_mmio + SATA_TESTCTL) >> 16;
Mark Lord4c299ca2008-05-02 02:16:20 -04002440}
2441
Mark Lord4c299ca2008-05-02 02:16:20 -04002442static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
2443{
2444 struct ata_eh_info *ehi;
2445 unsigned int pmp;
2446
2447 /*
2448 * Initialize EH info for PMPs which saw device errors
2449 */
2450 ehi = &ap->link.eh_info;
2451 for (pmp = 0; pmp_map != 0; pmp++) {
2452 unsigned int this_pmp = (1 << pmp);
2453 if (pmp_map & this_pmp) {
2454 struct ata_link *link = &ap->pmp_link[pmp];
2455
2456 pmp_map &= ~this_pmp;
2457 ehi = &link->eh_info;
2458 ata_ehi_clear_desc(ehi);
2459 ata_ehi_push_desc(ehi, "dev err");
2460 ehi->err_mask |= AC_ERR_DEV;
2461 ehi->action |= ATA_EH_RESET;
2462 ata_link_abort(link);
2463 }
2464 }
2465}
2466
Mark Lord06aaca32008-05-19 09:01:24 -04002467static int mv_req_q_empty(struct ata_port *ap)
2468{
2469 void __iomem *port_mmio = mv_ap_base(ap);
2470 u32 in_ptr, out_ptr;
2471
Mark Lordcae5a292009-04-06 16:43:45 -04002472 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR)
Mark Lord06aaca32008-05-19 09:01:24 -04002473 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
Mark Lordcae5a292009-04-06 16:43:45 -04002474 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR)
Mark Lord06aaca32008-05-19 09:01:24 -04002475 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2476 return (in_ptr == out_ptr); /* 1 == queue_is_empty */
2477}
2478
Mark Lord4c299ca2008-05-02 02:16:20 -04002479static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
2480{
2481 struct mv_port_priv *pp = ap->private_data;
2482 int failed_links;
2483 unsigned int old_map, new_map;
2484
2485 /*
2486 * Device error during FBS+NCQ operation:
2487 *
2488 * Set a port flag to prevent further I/O being enqueued.
2489 * Leave the EDMA running to drain outstanding commands from this port.
2490 * Perform the post-mortem/EH only when all responses are complete.
2491 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
2492 */
2493 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
2494 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
2495 pp->delayed_eh_pmp_map = 0;
2496 }
2497 old_map = pp->delayed_eh_pmp_map;
2498 new_map = old_map | mv_get_err_pmp_map(ap);
2499
2500 if (old_map != new_map) {
2501 pp->delayed_eh_pmp_map = new_map;
2502 mv_pmp_eh_prep(ap, new_map & ~old_map);
2503 }
Mark Lordc46938c2008-05-02 14:02:28 -04002504 failed_links = hweight16(new_map);
Mark Lord4c299ca2008-05-02 02:16:20 -04002505
Joe Perchesa9a79df2011-04-15 15:51:59 -07002506 ata_port_info(ap,
2507 "%s: pmp_map=%04x qc_map=%04x failed_links=%d nr_active_links=%d\n",
2508 __func__, pp->delayed_eh_pmp_map,
2509 ap->qc_active, failed_links,
2510 ap->nr_active_links);
Mark Lord4c299ca2008-05-02 02:16:20 -04002511
Mark Lord06aaca32008-05-19 09:01:24 -04002512 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
Mark Lord4c299ca2008-05-02 02:16:20 -04002513 mv_process_crpb_entries(ap, pp);
2514 mv_stop_edma(ap);
2515 mv_eh_freeze(ap);
Joe Perchesa9a79df2011-04-15 15:51:59 -07002516 ata_port_info(ap, "%s: done\n", __func__);
Mark Lord4c299ca2008-05-02 02:16:20 -04002517 return 1; /* handled */
2518 }
Joe Perchesa9a79df2011-04-15 15:51:59 -07002519 ata_port_info(ap, "%s: waiting\n", __func__);
Mark Lord4c299ca2008-05-02 02:16:20 -04002520 return 1; /* handled */
2521}
2522
2523static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
2524{
2525 /*
2526 * Possible future enhancement:
2527 *
2528 * FBS+non-NCQ operation is not yet implemented.
2529 * See related notes in mv_edma_cfg().
2530 *
2531 * Device error during FBS+non-NCQ operation:
2532 *
2533 * We need to snapshot the shadow registers for each failed command.
2534 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
2535 */
2536 return 0; /* not handled */
2537}
2538
2539static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
2540{
2541 struct mv_port_priv *pp = ap->private_data;
2542
2543 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
2544 return 0; /* EDMA was not active: not handled */
2545 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
2546 return 0; /* FBS was not active: not handled */
2547
2548 if (!(edma_err_cause & EDMA_ERR_DEV))
2549 return 0; /* non DEV error: not handled */
2550 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
2551 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
2552 return 0; /* other problems: not handled */
2553
2554 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
2555 /*
2556 * EDMA should NOT have self-disabled for this case.
2557 * If it did, then something is wrong elsewhere,
2558 * and we cannot handle it here.
2559 */
2560 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
Joe Perchesa9a79df2011-04-15 15:51:59 -07002561 ata_port_warn(ap, "%s: err_cause=0x%x pp_flags=0x%x\n",
2562 __func__, edma_err_cause, pp->pp_flags);
Mark Lord4c299ca2008-05-02 02:16:20 -04002563 return 0; /* not handled */
2564 }
2565 return mv_handle_fbs_ncq_dev_err(ap);
2566 } else {
2567 /*
2568 * EDMA should have self-disabled for this case.
2569 * If it did not, then something is wrong elsewhere,
2570 * and we cannot handle it here.
2571 */
2572 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
Joe Perchesa9a79df2011-04-15 15:51:59 -07002573 ata_port_warn(ap, "%s: err_cause=0x%x pp_flags=0x%x\n",
2574 __func__, edma_err_cause, pp->pp_flags);
Mark Lord4c299ca2008-05-02 02:16:20 -04002575 return 0; /* not handled */
2576 }
2577 return mv_handle_fbs_non_ncq_dev_err(ap);
2578 }
2579 return 0; /* not handled */
2580}
2581
Mark Lorda9010322008-05-02 02:14:02 -04002582static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
Mark Lord8f767f82008-04-19 14:53:07 -04002583{
Mark Lord8f767f82008-04-19 14:53:07 -04002584 struct ata_eh_info *ehi = &ap->link.eh_info;
Mark Lorda9010322008-05-02 02:14:02 -04002585 char *when = "idle";
Mark Lord8f767f82008-04-19 14:53:07 -04002586
Mark Lord8f767f82008-04-19 14:53:07 -04002587 ata_ehi_clear_desc(ehi);
Tejun Heo3e4ec342010-05-10 21:41:30 +02002588 if (edma_was_enabled) {
Mark Lorda9010322008-05-02 02:14:02 -04002589 when = "EDMA enabled";
Mark Lord8f767f82008-04-19 14:53:07 -04002590 } else {
2591 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
2592 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
Mark Lorda9010322008-05-02 02:14:02 -04002593 when = "polling";
Mark Lord8f767f82008-04-19 14:53:07 -04002594 }
Mark Lorda9010322008-05-02 02:14:02 -04002595 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
Mark Lord8f767f82008-04-19 14:53:07 -04002596 ehi->err_mask |= AC_ERR_OTHER;
2597 ehi->action |= ATA_EH_RESET;
2598 ata_port_freeze(ap);
2599}
2600
Brett Russ05b308e2005-10-05 17:08:53 -04002601/**
Brett Russ05b308e2005-10-05 17:08:53 -04002602 * mv_err_intr - Handle error interrupts on the port
2603 * @ap: ATA channel to manipulate
2604 *
Mark Lord8d073792008-04-19 15:07:49 -04002605 * Most cases require a full reset of the chip's state machine,
2606 * which also performs a COMRESET.
2607 * Also, if the port disabled DMA, update our cached copy to match.
Brett Russ05b308e2005-10-05 17:08:53 -04002608 *
2609 * LOCKING:
2610 * Inherited from caller.
2611 */
Mark Lord37b90462008-05-02 02:12:34 -04002612static void mv_err_intr(struct ata_port *ap)
Brett Russ20f733e2005-09-01 18:26:17 -04002613{
Brett Russ31961942005-09-30 01:36:00 -04002614 void __iomem *port_mmio = mv_ap_base(ap);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002615 u32 edma_err_cause, eh_freeze_mask, serr = 0;
Mark Lorde4006072008-05-14 09:19:30 -04002616 u32 fis_cause = 0;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002617 struct mv_port_priv *pp = ap->private_data;
2618 struct mv_host_priv *hpriv = ap->host->private_data;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002619 unsigned int action = 0, err_mask = 0;
Tejun Heo9af5c9c2007-08-06 18:36:22 +09002620 struct ata_eh_info *ehi = &ap->link.eh_info;
Mark Lord37b90462008-05-02 02:12:34 -04002621 struct ata_queued_cmd *qc;
2622 int abort = 0;
Brett Russ20f733e2005-09-01 18:26:17 -04002623
Mark Lord8d073792008-04-19 15:07:49 -04002624 /*
Mark Lord37b90462008-05-02 02:12:34 -04002625 * Read and clear the SError and err_cause bits.
Mark Lorde4006072008-05-14 09:19:30 -04002626 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
2627 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
Mark Lord8d073792008-04-19 15:07:49 -04002628 */
Mark Lord37b90462008-05-02 02:12:34 -04002629 sata_scr_read(&ap->link, SCR_ERROR, &serr);
2630 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
2631
Mark Lordcae5a292009-04-06 16:43:45 -04002632 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE);
Mark Lorde4006072008-05-14 09:19:30 -04002633 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
Mark Lordcae5a292009-04-06 16:43:45 -04002634 fis_cause = readl(port_mmio + FIS_IRQ_CAUSE);
2635 writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE);
Mark Lorde4006072008-05-14 09:19:30 -04002636 }
Mark Lordcae5a292009-04-06 16:43:45 -04002637 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002638
Mark Lord4c299ca2008-05-02 02:16:20 -04002639 if (edma_err_cause & EDMA_ERR_DEV) {
2640 /*
2641 * Device errors during FIS-based switching operation
2642 * require special handling.
2643 */
2644 if (mv_handle_dev_err(ap, edma_err_cause))
2645 return;
2646 }
2647
Mark Lord37b90462008-05-02 02:12:34 -04002648 qc = mv_get_active_qc(ap);
2649 ata_ehi_clear_desc(ehi);
2650 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
2651 edma_err_cause, pp->pp_flags);
Mark Lorde4006072008-05-14 09:19:30 -04002652
Mark Lordc443c502008-05-14 09:24:39 -04002653 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
Mark Lorde4006072008-05-14 09:19:30 -04002654 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
Mark Lordcae5a292009-04-06 16:43:45 -04002655 if (fis_cause & FIS_IRQ_CAUSE_AN) {
Mark Lordc443c502008-05-14 09:24:39 -04002656 u32 ec = edma_err_cause &
2657 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
2658 sata_async_notification(ap);
2659 if (!ec)
2660 return; /* Just an AN; no need for the nukes */
2661 ata_ehi_push_desc(ehi, "SDB notify");
2662 }
2663 }
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002664 /*
Mark Lord352fab72008-04-19 14:43:42 -04002665 * All generations share these EDMA error cause bits:
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002666 */
Mark Lord37b90462008-05-02 02:12:34 -04002667 if (edma_err_cause & EDMA_ERR_DEV) {
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002668 err_mask |= AC_ERR_DEV;
Mark Lord37b90462008-05-02 02:12:34 -04002669 action |= ATA_EH_RESET;
2670 ata_ehi_push_desc(ehi, "dev error");
2671 }
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002672 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
Jeff Garzik6c1153e2007-07-13 15:20:15 -04002673 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002674 EDMA_ERR_INTRL_PAR)) {
2675 err_mask |= AC_ERR_ATA_BUS;
Tejun Heocf480622008-01-24 00:05:14 +09002676 action |= ATA_EH_RESET;
Tejun Heob64bbc32007-07-16 14:29:39 +09002677 ata_ehi_push_desc(ehi, "parity error");
Brett Russafb0edd2005-10-05 17:08:42 -04002678 }
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002679 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
2680 ata_ehi_hotplugged(ehi);
2681 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
Tejun Heob64bbc32007-07-16 14:29:39 +09002682 "dev disconnect" : "dev connect");
Tejun Heocf480622008-01-24 00:05:14 +09002683 action |= ATA_EH_RESET;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002684 }
2685
Mark Lord352fab72008-04-19 14:43:42 -04002686 /*
2687 * Gen-I has a different SELF_DIS bit,
2688 * different FREEZE bits, and no SERR bit:
2689 */
Jeff Garzikee9ccdf2007-07-12 15:51:22 -04002690 if (IS_GEN_I(hpriv)) {
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002691 eh_freeze_mask = EDMA_EH_FREEZE_5;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002692 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002693 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
Tejun Heob64bbc32007-07-16 14:29:39 +09002694 ata_ehi_push_desc(ehi, "EDMA self-disable");
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002695 }
2696 } else {
2697 eh_freeze_mask = EDMA_EH_FREEZE;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002698 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002699 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
Tejun Heob64bbc32007-07-16 14:29:39 +09002700 ata_ehi_push_desc(ehi, "EDMA self-disable");
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002701 }
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002702 if (edma_err_cause & EDMA_ERR_SERR) {
Mark Lord8d073792008-04-19 15:07:49 -04002703 ata_ehi_push_desc(ehi, "SError=%08x", serr);
2704 err_mask |= AC_ERR_ATA_BUS;
Tejun Heocf480622008-01-24 00:05:14 +09002705 action |= ATA_EH_RESET;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002706 }
2707 }
Brett Russ20f733e2005-09-01 18:26:17 -04002708
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002709 if (!err_mask) {
2710 err_mask = AC_ERR_OTHER;
Tejun Heocf480622008-01-24 00:05:14 +09002711 action |= ATA_EH_RESET;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002712 }
2713
2714 ehi->serror |= serr;
2715 ehi->action |= action;
2716
2717 if (qc)
2718 qc->err_mask |= err_mask;
2719 else
2720 ehi->err_mask |= err_mask;
2721
Mark Lord37b90462008-05-02 02:12:34 -04002722 if (err_mask == AC_ERR_DEV) {
2723 /*
2724 * Cannot do ata_port_freeze() here,
2725 * because it would kill PIO access,
2726 * which is needed for further diagnosis.
2727 */
2728 mv_eh_freeze(ap);
2729 abort = 1;
2730 } else if (edma_err_cause & eh_freeze_mask) {
2731 /*
2732 * Note to self: ata_port_freeze() calls ata_port_abort()
2733 */
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002734 ata_port_freeze(ap);
Mark Lord37b90462008-05-02 02:12:34 -04002735 } else {
2736 abort = 1;
2737 }
2738
2739 if (abort) {
2740 if (qc)
2741 ata_link_abort(qc->dev->link);
2742 else
2743 ata_port_abort(ap);
2744 }
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002745}
2746
Tejun Heo1aadf5c2010-06-25 15:03:34 +02002747static bool mv_process_crpb_response(struct ata_port *ap,
Mark Lordfcfb1f72008-04-19 15:06:40 -04002748 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
2749{
Tejun Heo752e3862010-06-25 15:02:59 +02002750 u8 ata_status;
2751 u16 edma_status = le16_to_cpu(response->flags);
Tejun Heo752e3862010-06-25 15:02:59 +02002752
2753 /*
2754 * edma_status from a response queue entry:
2755 * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only).
2756 * MSB is saved ATA status from command completion.
2757 */
2758 if (!ncq_enabled) {
2759 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
2760 if (err_cause) {
2761 /*
2762 * Error will be seen/handled by
2763 * mv_err_intr(). So do nothing at all here.
2764 */
Tejun Heo1aadf5c2010-06-25 15:03:34 +02002765 return false;
Tejun Heo752e3862010-06-25 15:02:59 +02002766 }
2767 }
2768 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
2769 if (!ac_err_mask(ata_status))
Tejun Heo1aadf5c2010-06-25 15:03:34 +02002770 return true;
Tejun Heo752e3862010-06-25 15:02:59 +02002771 /* else: leave it for mv_err_intr() */
Tejun Heo1aadf5c2010-06-25 15:03:34 +02002772 return false;
Mark Lordfcfb1f72008-04-19 15:06:40 -04002773}
2774
2775static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002776{
2777 void __iomem *port_mmio = mv_ap_base(ap);
2778 struct mv_host_priv *hpriv = ap->host->private_data;
Mark Lordfcfb1f72008-04-19 15:06:40 -04002779 u32 in_index;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002780 bool work_done = false;
Tejun Heo1aadf5c2010-06-25 15:03:34 +02002781 u32 done_mask = 0;
Mark Lordfcfb1f72008-04-19 15:06:40 -04002782 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002783
Mark Lordfcfb1f72008-04-19 15:06:40 -04002784 /* Get the hardware queue position index */
Mark Lordcae5a292009-04-06 16:43:45 -04002785 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR)
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002786 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2787
Mark Lordfcfb1f72008-04-19 15:06:40 -04002788 /* Process new responses from since the last time we looked */
2789 while (in_index != pp->resp_idx) {
Jeff Garzik6c1153e2007-07-13 15:20:15 -04002790 unsigned int tag;
Mark Lordfcfb1f72008-04-19 15:06:40 -04002791 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002792
Mark Lordfcfb1f72008-04-19 15:06:40 -04002793 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002794
Mark Lordfcfb1f72008-04-19 15:06:40 -04002795 if (IS_GEN_I(hpriv)) {
2796 /* 50xx: no NCQ, only one command active at a time */
Tejun Heo9af5c9c2007-08-06 18:36:22 +09002797 tag = ap->link.active_tag;
Mark Lordfcfb1f72008-04-19 15:06:40 -04002798 } else {
2799 /* Gen II/IIE: get command tag from CRPB entry */
2800 tag = le16_to_cpu(response->id) & 0x1f;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002801 }
Tejun Heo1aadf5c2010-06-25 15:03:34 +02002802 if (mv_process_crpb_response(ap, response, tag, ncq_enabled))
2803 done_mask |= 1 << tag;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002804 work_done = true;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002805 }
2806
Tejun Heo1aadf5c2010-06-25 15:03:34 +02002807 if (work_done) {
2808 ata_qc_complete_multiple(ap, ap->qc_active ^ done_mask);
2809
2810 /* Update the software queue position index in hardware */
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002811 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
Mark Lordfcfb1f72008-04-19 15:06:40 -04002812 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
Mark Lordcae5a292009-04-06 16:43:45 -04002813 port_mmio + EDMA_RSP_Q_OUT_PTR);
Tejun Heo1aadf5c2010-06-25 15:03:34 +02002814 }
Brett Russ20f733e2005-09-01 18:26:17 -04002815}
2816
Mark Lorda9010322008-05-02 02:14:02 -04002817static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2818{
2819 struct mv_port_priv *pp;
2820 int edma_was_enabled;
2821
Mark Lorda9010322008-05-02 02:14:02 -04002822 /*
2823 * Grab a snapshot of the EDMA_EN flag setting,
2824 * so that we have a consistent view for this port,
2825 * even if something we call of our routines changes it.
2826 */
2827 pp = ap->private_data;
2828 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2829 /*
2830 * Process completed CRPB response(s) before other events.
2831 */
2832 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2833 mv_process_crpb_entries(ap, pp);
Mark Lord4c299ca2008-05-02 02:16:20 -04002834 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2835 mv_handle_fbs_ncq_dev_err(ap);
Mark Lorda9010322008-05-02 02:14:02 -04002836 }
2837 /*
2838 * Handle chip-reported errors, or continue on to handle PIO.
2839 */
2840 if (unlikely(port_cause & ERR_IRQ)) {
2841 mv_err_intr(ap);
2842 } else if (!edma_was_enabled) {
2843 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2844 if (qc)
Tejun Heoc3b28892010-05-19 22:10:21 +02002845 ata_bmdma_port_intr(ap, qc);
Mark Lorda9010322008-05-02 02:14:02 -04002846 else
2847 mv_unexpected_intr(ap, edma_was_enabled);
2848 }
2849}
2850
Brett Russ05b308e2005-10-05 17:08:53 -04002851/**
2852 * mv_host_intr - Handle all interrupts on the given host controller
Jeff Garzikcca39742006-08-24 03:19:22 -04002853 * @host: host specific structure
Mark Lord7368f912008-04-25 11:24:24 -04002854 * @main_irq_cause: Main interrupt cause register for the chip.
Brett Russ05b308e2005-10-05 17:08:53 -04002855 *
2856 * LOCKING:
2857 * Inherited from caller.
2858 */
Mark Lord7368f912008-04-25 11:24:24 -04002859static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
Brett Russ20f733e2005-09-01 18:26:17 -04002860{
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05002861 struct mv_host_priv *hpriv = host->private_data;
Mark Lordeabd5eb2008-05-02 02:13:27 -04002862 void __iomem *mmio = hpriv->base, *hc_mmio;
Mark Lorda3718c12008-04-19 15:07:18 -04002863 unsigned int handled = 0, port;
Brett Russ20f733e2005-09-01 18:26:17 -04002864
Mark Lord2b748a02009-03-10 22:01:17 -04002865 /* If asserted, clear the "all ports" IRQ coalescing bit */
2866 if (main_irq_cause & ALL_PORTS_COAL_DONE)
Mark Lordcae5a292009-04-06 16:43:45 -04002867 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
Mark Lord2b748a02009-03-10 22:01:17 -04002868
Mark Lorda3718c12008-04-19 15:07:18 -04002869 for (port = 0; port < hpriv->n_ports; port++) {
Jeff Garzikcca39742006-08-24 03:19:22 -04002870 struct ata_port *ap = host->ports[port];
Mark Lordeabd5eb2008-05-02 02:13:27 -04002871 unsigned int p, shift, hardport, port_cause;
2872
Mark Lorda3718c12008-04-19 15:07:18 -04002873 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
Mark Lorda3718c12008-04-19 15:07:18 -04002874 /*
Mark Lordeabd5eb2008-05-02 02:13:27 -04002875 * Each hc within the host has its own hc_irq_cause register,
2876 * where the interrupting ports bits get ack'd.
Mark Lorda3718c12008-04-19 15:07:18 -04002877 */
Mark Lordeabd5eb2008-05-02 02:13:27 -04002878 if (hardport == 0) { /* first port on this hc ? */
2879 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2880 u32 port_mask, ack_irqs;
2881 /*
2882 * Skip this entire hc if nothing pending for any ports
2883 */
2884 if (!hc_cause) {
2885 port += MV_PORTS_PER_HC - 1;
2886 continue;
2887 }
2888 /*
2889 * We don't need/want to read the hc_irq_cause register,
2890 * because doing so hurts performance, and
2891 * main_irq_cause already gives us everything we need.
2892 *
2893 * But we do have to *write* to the hc_irq_cause to ack
2894 * the ports that we are handling this time through.
2895 *
2896 * This requires that we create a bitmap for those
2897 * ports which interrupted us, and use that bitmap
2898 * to ack (only) those ports via hc_irq_cause.
2899 */
2900 ack_irqs = 0;
Mark Lord2b748a02009-03-10 22:01:17 -04002901 if (hc_cause & PORTS_0_3_COAL_DONE)
2902 ack_irqs = HC_COAL_IRQ;
Mark Lordeabd5eb2008-05-02 02:13:27 -04002903 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2904 if ((port + p) >= hpriv->n_ports)
2905 break;
2906 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2907 if (hc_cause & port_mask)
2908 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2909 }
Mark Lorda3718c12008-04-19 15:07:18 -04002910 hc_mmio = mv_hc_base_from_port(mmio, port);
Mark Lordcae5a292009-04-06 16:43:45 -04002911 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE);
Mark Lorda3718c12008-04-19 15:07:18 -04002912 handled = 1;
2913 }
Mark Lorda9010322008-05-02 02:14:02 -04002914 /*
2915 * Handle interrupts signalled for this port:
2916 */
Mark Lordeabd5eb2008-05-02 02:13:27 -04002917 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
Mark Lorda9010322008-05-02 02:14:02 -04002918 if (port_cause)
2919 mv_port_intr(ap, port_cause);
Brett Russ20f733e2005-09-01 18:26:17 -04002920 }
Mark Lorda3718c12008-04-19 15:07:18 -04002921 return handled;
Brett Russ20f733e2005-09-01 18:26:17 -04002922}
2923
Mark Lorda3718c12008-04-19 15:07:18 -04002924static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002925{
Mark Lord02a121d2007-12-01 13:07:22 -05002926 struct mv_host_priv *hpriv = host->private_data;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002927 struct ata_port *ap;
2928 struct ata_queued_cmd *qc;
2929 struct ata_eh_info *ehi;
2930 unsigned int i, err_mask, printed = 0;
2931 u32 err_cause;
2932
Mark Lordcae5a292009-04-06 16:43:45 -04002933 err_cause = readl(mmio + hpriv->irq_cause_offset);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002934
Joe Perchesa44fec12011-04-15 15:51:58 -07002935 dev_err(host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", err_cause);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002936
2937 DPRINTK("All regs @ PCI error\n");
2938 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2939
Mark Lordcae5a292009-04-06 16:43:45 -04002940 writelfl(0, mmio + hpriv->irq_cause_offset);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002941
2942 for (i = 0; i < host->n_ports; i++) {
2943 ap = host->ports[i];
Tejun Heo936fd732007-08-06 18:36:23 +09002944 if (!ata_link_offline(&ap->link)) {
Tejun Heo9af5c9c2007-08-06 18:36:22 +09002945 ehi = &ap->link.eh_info;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002946 ata_ehi_clear_desc(ehi);
2947 if (!printed++)
2948 ata_ehi_push_desc(ehi,
2949 "PCI err cause 0x%08x", err_cause);
2950 err_mask = AC_ERR_HOST_BUS;
Tejun Heocf480622008-01-24 00:05:14 +09002951 ehi->action = ATA_EH_RESET;
Tejun Heo9af5c9c2007-08-06 18:36:22 +09002952 qc = ata_qc_from_tag(ap, ap->link.active_tag);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002953 if (qc)
2954 qc->err_mask |= err_mask;
2955 else
2956 ehi->err_mask |= err_mask;
2957
2958 ata_port_freeze(ap);
2959 }
2960 }
Mark Lorda3718c12008-04-19 15:07:18 -04002961 return 1; /* handled */
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002962}
2963
Brett Russ05b308e2005-10-05 17:08:53 -04002964/**
Jeff Garzikc5d3e452007-07-11 18:30:50 -04002965 * mv_interrupt - Main interrupt event handler
Brett Russ05b308e2005-10-05 17:08:53 -04002966 * @irq: unused
2967 * @dev_instance: private data; in this case the host structure
Brett Russ05b308e2005-10-05 17:08:53 -04002968 *
2969 * Read the read only register to determine if any host
2970 * controllers have pending interrupts. If so, call lower level
2971 * routine to handle. Also check for PCI errors which are only
2972 * reported here.
2973 *
Jeff Garzik8b260242005-11-12 12:32:50 -05002974 * LOCKING:
Jeff Garzikcca39742006-08-24 03:19:22 -04002975 * This routine holds the host lock while processing pending
Brett Russ05b308e2005-10-05 17:08:53 -04002976 * interrupts.
2977 */
David Howells7d12e782006-10-05 14:55:46 +01002978static irqreturn_t mv_interrupt(int irq, void *dev_instance)
Brett Russ20f733e2005-09-01 18:26:17 -04002979{
Jeff Garzikcca39742006-08-24 03:19:22 -04002980 struct ata_host *host = dev_instance;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05002981 struct mv_host_priv *hpriv = host->private_data;
Mark Lorda3718c12008-04-19 15:07:18 -04002982 unsigned int handled = 0;
Mark Lord6d3c30e2009-01-21 10:31:29 -05002983 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;
Mark Lord96e2c4872008-05-17 13:38:00 -04002984 u32 main_irq_cause, pending_irqs;
Brett Russ20f733e2005-09-01 18:26:17 -04002985
Mark Lord646a4da2008-01-26 18:30:37 -05002986 spin_lock(&host->lock);
Mark Lord6d3c30e2009-01-21 10:31:29 -05002987
2988 /* for MSI: block new interrupts while in here */
2989 if (using_msi)
Mark Lord2b748a02009-03-10 22:01:17 -04002990 mv_write_main_irq_mask(0, hpriv);
Mark Lord6d3c30e2009-01-21 10:31:29 -05002991
Mark Lord7368f912008-04-25 11:24:24 -04002992 main_irq_cause = readl(hpriv->main_irq_cause_addr);
Mark Lord96e2c4872008-05-17 13:38:00 -04002993 pending_irqs = main_irq_cause & hpriv->main_irq_mask;
Mark Lord352fab72008-04-19 14:43:42 -04002994 /*
2995 * Deal with cases where we either have nothing pending, or have read
2996 * a bogus register value which can indicate HW removal or PCI fault.
Brett Russ20f733e2005-09-01 18:26:17 -04002997 */
Mark Lorda44253d2008-05-17 13:37:07 -04002998 if (pending_irqs && main_irq_cause != 0xffffffffU) {
Mark Lord1f398472008-05-27 17:54:48 -04002999 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
Mark Lorda3718c12008-04-19 15:07:18 -04003000 handled = mv_pci_error(host, hpriv->base);
3001 else
Mark Lorda44253d2008-05-17 13:37:07 -04003002 handled = mv_host_intr(host, pending_irqs);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003003 }
Mark Lord6d3c30e2009-01-21 10:31:29 -05003004
3005 /* for MSI: unmask; interrupt cause bits will retrigger now */
3006 if (using_msi)
Mark Lord2b748a02009-03-10 22:01:17 -04003007 mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv);
Mark Lord6d3c30e2009-01-21 10:31:29 -05003008
Mark Lord9d51af72009-03-10 16:28:51 -04003009 spin_unlock(&host->lock);
3010
Brett Russ20f733e2005-09-01 18:26:17 -04003011 return IRQ_RETVAL(handled);
3012}
3013
Jeff Garzikc9d39132005-11-13 17:47:51 -05003014static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
3015{
3016 unsigned int ofs;
3017
3018 switch (sc_reg_in) {
3019 case SCR_STATUS:
3020 case SCR_ERROR:
3021 case SCR_CONTROL:
3022 ofs = sc_reg_in * sizeof(u32);
3023 break;
3024 default:
3025 ofs = 0xffffffffU;
3026 break;
3027 }
3028 return ofs;
3029}
3030
Tejun Heo82ef04f2008-07-31 17:02:40 +09003031static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
Jeff Garzikc9d39132005-11-13 17:47:51 -05003032{
Tejun Heo82ef04f2008-07-31 17:02:40 +09003033 struct mv_host_priv *hpriv = link->ap->host->private_data;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003034 void __iomem *mmio = hpriv->base;
Tejun Heo82ef04f2008-07-31 17:02:40 +09003035 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
Jeff Garzikc9d39132005-11-13 17:47:51 -05003036 unsigned int ofs = mv5_scr_offset(sc_reg_in);
3037
Tejun Heoda3dbb12007-07-16 14:29:40 +09003038 if (ofs != 0xffffffffU) {
3039 *val = readl(addr + ofs);
3040 return 0;
3041 } else
3042 return -EINVAL;
Jeff Garzikc9d39132005-11-13 17:47:51 -05003043}
3044
Tejun Heo82ef04f2008-07-31 17:02:40 +09003045static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
Jeff Garzikc9d39132005-11-13 17:47:51 -05003046{
Tejun Heo82ef04f2008-07-31 17:02:40 +09003047 struct mv_host_priv *hpriv = link->ap->host->private_data;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003048 void __iomem *mmio = hpriv->base;
Tejun Heo82ef04f2008-07-31 17:02:40 +09003049 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
Jeff Garzikc9d39132005-11-13 17:47:51 -05003050 unsigned int ofs = mv5_scr_offset(sc_reg_in);
3051
Tejun Heoda3dbb12007-07-16 14:29:40 +09003052 if (ofs != 0xffffffffU) {
Tejun Heo0d5ff562007-02-01 15:06:36 +09003053 writelfl(val, addr + ofs);
Tejun Heoda3dbb12007-07-16 14:29:40 +09003054 return 0;
3055 } else
3056 return -EINVAL;
Jeff Garzikc9d39132005-11-13 17:47:51 -05003057}
3058
Saeed Bishara7bb3c522008-01-30 11:50:45 -11003059static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
Jeff Garzik522479f2005-11-12 22:14:02 -05003060{
Saeed Bishara7bb3c522008-01-30 11:50:45 -11003061 struct pci_dev *pdev = to_pci_dev(host->dev);
Jeff Garzik522479f2005-11-12 22:14:02 -05003062 int early_5080;
3063
Auke Kok44c10132007-06-08 15:46:36 -07003064 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
Jeff Garzik522479f2005-11-12 22:14:02 -05003065
3066 if (!early_5080) {
3067 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3068 tmp |= (1 << 0);
3069 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
3070 }
3071
Saeed Bishara7bb3c522008-01-30 11:50:45 -11003072 mv_reset_pci_bus(host, mmio);
Jeff Garzik522479f2005-11-12 22:14:02 -05003073}
3074
3075static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3076{
Mark Lordcae5a292009-04-06 16:43:45 -04003077 writel(0x0fcfffff, mmio + FLASH_CTL);
Jeff Garzik522479f2005-11-12 22:14:02 -05003078}
3079
Jeff Garzik47c2b672005-11-12 21:13:17 -05003080static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
Jeff Garzikba3fe8f2005-11-12 19:08:48 -05003081 void __iomem *mmio)
3082{
Jeff Garzikc9d39132005-11-13 17:47:51 -05003083 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
3084 u32 tmp;
3085
3086 tmp = readl(phy_mmio + MV5_PHY_MODE);
3087
3088 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
3089 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
Jeff Garzikba3fe8f2005-11-12 19:08:48 -05003090}
3091
Jeff Garzik47c2b672005-11-12 21:13:17 -05003092static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
Jeff Garzikba3fe8f2005-11-12 19:08:48 -05003093{
Jeff Garzik522479f2005-11-12 22:14:02 -05003094 u32 tmp;
3095
Mark Lordcae5a292009-04-06 16:43:45 -04003096 writel(0, mmio + GPIO_PORT_CTL);
Jeff Garzik522479f2005-11-12 22:14:02 -05003097
3098 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
3099
3100 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3101 tmp |= ~(1 << 0);
3102 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
Jeff Garzikba3fe8f2005-11-12 19:08:48 -05003103}
3104
Jeff Garzik2a47ce02005-11-12 23:05:14 -05003105static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3106 unsigned int port)
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003107{
Jeff Garzikc9d39132005-11-13 17:47:51 -05003108 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
3109 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
3110 u32 tmp;
3111 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
3112
3113 if (fix_apm_sq) {
Mark Lordcae5a292009-04-06 16:43:45 -04003114 tmp = readl(phy_mmio + MV5_LTMODE);
Jeff Garzikc9d39132005-11-13 17:47:51 -05003115 tmp |= (1 << 19);
Mark Lordcae5a292009-04-06 16:43:45 -04003116 writel(tmp, phy_mmio + MV5_LTMODE);
Jeff Garzikc9d39132005-11-13 17:47:51 -05003117
Mark Lordcae5a292009-04-06 16:43:45 -04003118 tmp = readl(phy_mmio + MV5_PHY_CTL);
Jeff Garzikc9d39132005-11-13 17:47:51 -05003119 tmp &= ~0x3;
3120 tmp |= 0x1;
Mark Lordcae5a292009-04-06 16:43:45 -04003121 writel(tmp, phy_mmio + MV5_PHY_CTL);
Jeff Garzikc9d39132005-11-13 17:47:51 -05003122 }
3123
3124 tmp = readl(phy_mmio + MV5_PHY_MODE);
3125 tmp &= ~mask;
3126 tmp |= hpriv->signal[port].pre;
3127 tmp |= hpriv->signal[port].amps;
3128 writel(tmp, phy_mmio + MV5_PHY_MODE);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003129}
3130
Jeff Garzikc9d39132005-11-13 17:47:51 -05003131
3132#undef ZERO
3133#define ZERO(reg) writel(0, port_mmio + (reg))
3134static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
3135 unsigned int port)
Jeff Garzik47c2b672005-11-12 21:13:17 -05003136{
Jeff Garzikc9d39132005-11-13 17:47:51 -05003137 void __iomem *port_mmio = mv_port_base(mmio, port);
3138
Mark Lorde12bef52008-03-31 19:33:56 -04003139 mv_reset_channel(hpriv, mmio, port);
Jeff Garzikc9d39132005-11-13 17:47:51 -05003140
3141 ZERO(0x028); /* command */
Mark Lordcae5a292009-04-06 16:43:45 -04003142 writel(0x11f, port_mmio + EDMA_CFG);
Jeff Garzikc9d39132005-11-13 17:47:51 -05003143 ZERO(0x004); /* timer */
3144 ZERO(0x008); /* irq err cause */
3145 ZERO(0x00c); /* irq err mask */
3146 ZERO(0x010); /* rq bah */
3147 ZERO(0x014); /* rq inp */
3148 ZERO(0x018); /* rq outp */
3149 ZERO(0x01c); /* respq bah */
3150 ZERO(0x024); /* respq outp */
3151 ZERO(0x020); /* respq inp */
3152 ZERO(0x02c); /* test control */
Mark Lordcae5a292009-04-06 16:43:45 -04003153 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
Jeff Garzikc9d39132005-11-13 17:47:51 -05003154}
3155#undef ZERO
3156
3157#define ZERO(reg) writel(0, hc_mmio + (reg))
3158static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3159 unsigned int hc)
3160{
3161 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3162 u32 tmp;
3163
3164 ZERO(0x00c);
3165 ZERO(0x010);
3166 ZERO(0x014);
3167 ZERO(0x018);
3168
3169 tmp = readl(hc_mmio + 0x20);
3170 tmp &= 0x1c1c1c1c;
3171 tmp |= 0x03030303;
3172 writel(tmp, hc_mmio + 0x20);
3173}
3174#undef ZERO
3175
3176static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3177 unsigned int n_hc)
3178{
3179 unsigned int hc, port;
3180
3181 for (hc = 0; hc < n_hc; hc++) {
3182 for (port = 0; port < MV_PORTS_PER_HC; port++)
3183 mv5_reset_hc_port(hpriv, mmio,
3184 (hc * MV_PORTS_PER_HC) + port);
3185
3186 mv5_reset_one_hc(hpriv, mmio, hc);
3187 }
3188
3189 return 0;
Jeff Garzik47c2b672005-11-12 21:13:17 -05003190}
3191
Jeff Garzik101ffae2005-11-12 22:17:49 -05003192#undef ZERO
3193#define ZERO(reg) writel(0, mmio + (reg))
Saeed Bishara7bb3c522008-01-30 11:50:45 -11003194static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
Jeff Garzik101ffae2005-11-12 22:17:49 -05003195{
Mark Lord02a121d2007-12-01 13:07:22 -05003196 struct mv_host_priv *hpriv = host->private_data;
Jeff Garzik101ffae2005-11-12 22:17:49 -05003197 u32 tmp;
3198
Mark Lordcae5a292009-04-06 16:43:45 -04003199 tmp = readl(mmio + MV_PCI_MODE);
Jeff Garzik101ffae2005-11-12 22:17:49 -05003200 tmp &= 0xff00ffff;
Mark Lordcae5a292009-04-06 16:43:45 -04003201 writel(tmp, mmio + MV_PCI_MODE);
Jeff Garzik101ffae2005-11-12 22:17:49 -05003202
3203 ZERO(MV_PCI_DISC_TIMER);
3204 ZERO(MV_PCI_MSI_TRIGGER);
Mark Lordcae5a292009-04-06 16:43:45 -04003205 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
Jeff Garzik101ffae2005-11-12 22:17:49 -05003206 ZERO(MV_PCI_SERR_MASK);
Mark Lordcae5a292009-04-06 16:43:45 -04003207 ZERO(hpriv->irq_cause_offset);
3208 ZERO(hpriv->irq_mask_offset);
Jeff Garzik101ffae2005-11-12 22:17:49 -05003209 ZERO(MV_PCI_ERR_LOW_ADDRESS);
3210 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
3211 ZERO(MV_PCI_ERR_ATTRIBUTE);
3212 ZERO(MV_PCI_ERR_COMMAND);
3213}
3214#undef ZERO
3215
3216static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3217{
3218 u32 tmp;
3219
3220 mv5_reset_flash(hpriv, mmio);
3221
Mark Lordcae5a292009-04-06 16:43:45 -04003222 tmp = readl(mmio + GPIO_PORT_CTL);
Jeff Garzik101ffae2005-11-12 22:17:49 -05003223 tmp &= 0x3;
3224 tmp |= (1 << 5) | (1 << 6);
Mark Lordcae5a292009-04-06 16:43:45 -04003225 writel(tmp, mmio + GPIO_PORT_CTL);
Jeff Garzik101ffae2005-11-12 22:17:49 -05003226}
3227
3228/**
3229 * mv6_reset_hc - Perform the 6xxx global soft reset
3230 * @mmio: base address of the HBA
3231 *
3232 * This routine only applies to 6xxx parts.
3233 *
3234 * LOCKING:
3235 * Inherited from caller.
3236 */
Jeff Garzikc9d39132005-11-13 17:47:51 -05003237static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3238 unsigned int n_hc)
Jeff Garzik101ffae2005-11-12 22:17:49 -05003239{
Mark Lordcae5a292009-04-06 16:43:45 -04003240 void __iomem *reg = mmio + PCI_MAIN_CMD_STS;
Jeff Garzik101ffae2005-11-12 22:17:49 -05003241 int i, rc = 0;
3242 u32 t;
3243
3244 /* Following procedure defined in PCI "main command and status
3245 * register" table.
3246 */
3247 t = readl(reg);
3248 writel(t | STOP_PCI_MASTER, reg);
3249
3250 for (i = 0; i < 1000; i++) {
3251 udelay(1);
3252 t = readl(reg);
Jeff Garzik2dcb4072007-10-19 06:42:56 -04003253 if (PCI_MASTER_EMPTY & t)
Jeff Garzik101ffae2005-11-12 22:17:49 -05003254 break;
Jeff Garzik101ffae2005-11-12 22:17:49 -05003255 }
3256 if (!(PCI_MASTER_EMPTY & t)) {
3257 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
3258 rc = 1;
3259 goto done;
3260 }
3261
3262 /* set reset */
3263 i = 5;
3264 do {
3265 writel(t | GLOB_SFT_RST, reg);
3266 t = readl(reg);
3267 udelay(1);
3268 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
3269
3270 if (!(GLOB_SFT_RST & t)) {
3271 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
3272 rc = 1;
3273 goto done;
3274 }
3275
3276 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
3277 i = 5;
3278 do {
3279 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
3280 t = readl(reg);
3281 udelay(1);
3282 } while ((GLOB_SFT_RST & t) && (i-- > 0));
3283
3284 if (GLOB_SFT_RST & t) {
3285 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
3286 rc = 1;
3287 }
3288done:
3289 return rc;
3290}
3291
Jeff Garzik47c2b672005-11-12 21:13:17 -05003292static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
Jeff Garzikba3fe8f2005-11-12 19:08:48 -05003293 void __iomem *mmio)
3294{
3295 void __iomem *port_mmio;
3296 u32 tmp;
3297
Mark Lordcae5a292009-04-06 16:43:45 -04003298 tmp = readl(mmio + RESET_CFG);
Jeff Garzikba3fe8f2005-11-12 19:08:48 -05003299 if ((tmp & (1 << 0)) == 0) {
Jeff Garzik47c2b672005-11-12 21:13:17 -05003300 hpriv->signal[idx].amps = 0x7 << 8;
Jeff Garzikba3fe8f2005-11-12 19:08:48 -05003301 hpriv->signal[idx].pre = 0x1 << 5;
3302 return;
3303 }
3304
3305 port_mmio = mv_port_base(mmio, idx);
3306 tmp = readl(port_mmio + PHY_MODE2);
3307
3308 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3309 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3310}
3311
Jeff Garzik47c2b672005-11-12 21:13:17 -05003312static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
Jeff Garzikba3fe8f2005-11-12 19:08:48 -05003313{
Mark Lordcae5a292009-04-06 16:43:45 -04003314 writel(0x00000060, mmio + GPIO_PORT_CTL);
Jeff Garzikba3fe8f2005-11-12 19:08:48 -05003315}
3316
Jeff Garzikc9d39132005-11-13 17:47:51 -05003317static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
Jeff Garzik2a47ce02005-11-12 23:05:14 -05003318 unsigned int port)
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003319{
Jeff Garzikc9d39132005-11-13 17:47:51 -05003320 void __iomem *port_mmio = mv_port_base(mmio, port);
3321
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003322 u32 hp_flags = hpriv->hp_flags;
Jeff Garzik47c2b672005-11-12 21:13:17 -05003323 int fix_phy_mode2 =
3324 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003325 int fix_phy_mode4 =
Jeff Garzik47c2b672005-11-12 21:13:17 -05003326 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
Mark Lord8c30a8b2008-05-27 17:56:31 -04003327 u32 m2, m3;
Jeff Garzik47c2b672005-11-12 21:13:17 -05003328
3329 if (fix_phy_mode2) {
3330 m2 = readl(port_mmio + PHY_MODE2);
3331 m2 &= ~(1 << 16);
3332 m2 |= (1 << 31);
3333 writel(m2, port_mmio + PHY_MODE2);
3334
3335 udelay(200);
3336
3337 m2 = readl(port_mmio + PHY_MODE2);
3338 m2 &= ~((1 << 16) | (1 << 31));
3339 writel(m2, port_mmio + PHY_MODE2);
3340
3341 udelay(200);
3342 }
3343
Mark Lord8c30a8b2008-05-27 17:56:31 -04003344 /*
3345 * Gen-II/IIe PHY_MODE3 errata RM#2:
3346 * Achieves better receiver noise performance than the h/w default:
3347 */
3348 m3 = readl(port_mmio + PHY_MODE3);
3349 m3 = (m3 & 0x1f) | (0x5555601 << 5);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003350
Mark Lord0388a8c2008-05-28 13:41:52 -04003351 /* Guideline 88F5182 (GL# SATA-S11) */
3352 if (IS_SOC(hpriv))
3353 m3 &= ~0x1c;
3354
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003355 if (fix_phy_mode4) {
Mark Lordba069e32008-05-31 16:46:34 -04003356 u32 m4 = readl(port_mmio + PHY_MODE4);
3357 /*
3358 * Enforce reserved-bit restrictions on GenIIe devices only.
3359 * For earlier chipsets, force only the internal config field
3360 * (workaround for errata FEr SATA#10 part 1).
3361 */
Mark Lord8c30a8b2008-05-27 17:56:31 -04003362 if (IS_GEN_IIE(hpriv))
Mark Lordba069e32008-05-31 16:46:34 -04003363 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
3364 else
3365 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
Mark Lord8c30a8b2008-05-27 17:56:31 -04003366 writel(m4, port_mmio + PHY_MODE4);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003367 }
Mark Lordb406c7a2008-05-28 12:01:12 -04003368 /*
3369 * Workaround for 60x1-B2 errata SATA#13:
3370 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
3371 * so we must always rewrite PHY_MODE3 after PHY_MODE4.
Mark Lordba684602009-04-06 15:25:39 -04003372 * Or ensure we use writelfl() when writing PHY_MODE4.
Mark Lordb406c7a2008-05-28 12:01:12 -04003373 */
3374 writel(m3, port_mmio + PHY_MODE3);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003375
3376 /* Revert values of pre-emphasis and signal amps to the saved ones */
3377 m2 = readl(port_mmio + PHY_MODE2);
3378
3379 m2 &= ~MV_M2_PREAMP_MASK;
Jeff Garzik2a47ce02005-11-12 23:05:14 -05003380 m2 |= hpriv->signal[port].amps;
3381 m2 |= hpriv->signal[port].pre;
Jeff Garzik47c2b672005-11-12 21:13:17 -05003382 m2 &= ~(1 << 16);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003383
Jeff Garzike4e7b892006-01-31 12:18:41 -05003384 /* according to mvSata 3.6.1, some IIE values are fixed */
3385 if (IS_GEN_IIE(hpriv)) {
3386 m2 &= ~0xC30FF01F;
3387 m2 |= 0x0000900F;
3388 }
3389
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003390 writel(m2, port_mmio + PHY_MODE2);
3391}
3392
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003393/* TODO: use the generic LED interface to configure the SATA Presence */
3394/* & Acitivy LEDs on the board */
3395static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
3396 void __iomem *mmio)
3397{
3398 return;
3399}
3400
3401static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
3402 void __iomem *mmio)
3403{
3404 void __iomem *port_mmio;
3405 u32 tmp;
3406
3407 port_mmio = mv_port_base(mmio, idx);
3408 tmp = readl(port_mmio + PHY_MODE2);
3409
3410 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3411 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3412}
3413
3414#undef ZERO
3415#define ZERO(reg) writel(0, port_mmio + (reg))
3416static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
3417 void __iomem *mmio, unsigned int port)
3418{
3419 void __iomem *port_mmio = mv_port_base(mmio, port);
3420
Mark Lorde12bef52008-03-31 19:33:56 -04003421 mv_reset_channel(hpriv, mmio, port);
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003422
3423 ZERO(0x028); /* command */
Mark Lordcae5a292009-04-06 16:43:45 -04003424 writel(0x101f, port_mmio + EDMA_CFG);
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003425 ZERO(0x004); /* timer */
3426 ZERO(0x008); /* irq err cause */
3427 ZERO(0x00c); /* irq err mask */
3428 ZERO(0x010); /* rq bah */
3429 ZERO(0x014); /* rq inp */
3430 ZERO(0x018); /* rq outp */
3431 ZERO(0x01c); /* respq bah */
3432 ZERO(0x024); /* respq outp */
3433 ZERO(0x020); /* respq inp */
3434 ZERO(0x02c); /* test control */
Saeed Bisharad7b0c142009-12-06 18:26:17 +02003435 writel(0x800, port_mmio + EDMA_IORDY_TMOUT);
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003436}
3437
3438#undef ZERO
3439
3440#define ZERO(reg) writel(0, hc_mmio + (reg))
3441static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
3442 void __iomem *mmio)
3443{
3444 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
3445
3446 ZERO(0x00c);
3447 ZERO(0x010);
3448 ZERO(0x014);
3449
3450}
3451
3452#undef ZERO
3453
3454static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
3455 void __iomem *mmio, unsigned int n_hc)
3456{
3457 unsigned int port;
3458
3459 for (port = 0; port < hpriv->n_ports; port++)
3460 mv_soc_reset_hc_port(hpriv, mmio, port);
3461
3462 mv_soc_reset_one_hc(hpriv, mmio);
3463
3464 return 0;
3465}
3466
3467static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
3468 void __iomem *mmio)
3469{
3470 return;
3471}
3472
3473static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
3474{
3475 return;
3476}
3477
Martin Michlmayr29b7e432009-05-04 20:58:50 +02003478static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
3479 void __iomem *mmio, unsigned int port)
3480{
3481 void __iomem *port_mmio = mv_port_base(mmio, port);
3482 u32 reg;
3483
3484 reg = readl(port_mmio + PHY_MODE3);
3485 reg &= ~(0x3 << 27); /* SELMUPF (bits 28:27) to 1 */
3486 reg |= (0x1 << 27);
3487 reg &= ~(0x3 << 29); /* SELMUPI (bits 30:29) to 1 */
3488 reg |= (0x1 << 29);
3489 writel(reg, port_mmio + PHY_MODE3);
3490
3491 reg = readl(port_mmio + PHY_MODE4);
3492 reg &= ~0x1; /* SATU_OD8 (bit 0) to 0, reserved bit 16 must be set */
3493 reg |= (0x1 << 16);
3494 writel(reg, port_mmio + PHY_MODE4);
3495
3496 reg = readl(port_mmio + PHY_MODE9_GEN2);
3497 reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
3498 reg |= 0x8;
3499 reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
3500 writel(reg, port_mmio + PHY_MODE9_GEN2);
3501
3502 reg = readl(port_mmio + PHY_MODE9_GEN1);
3503 reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
3504 reg |= 0x8;
3505 reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
3506 writel(reg, port_mmio + PHY_MODE9_GEN1);
3507}
3508
3509/**
3510 * soc_is_65 - check if the soc is 65 nano device
3511 *
3512 * Detect the type of the SoC, this is done by reading the PHYCFG_OFS
3513 * register, this register should contain non-zero value and it exists only
3514 * in the 65 nano devices, when reading it from older devices we get 0.
3515 */
3516static bool soc_is_65n(struct mv_host_priv *hpriv)
3517{
3518 void __iomem *port0_mmio = mv_port_base(hpriv->base, 0);
3519
3520 if (readl(port0_mmio + PHYCFG_OFS))
3521 return true;
3522 return false;
3523}
3524
Mark Lord8e7decd2008-05-02 02:07:51 -04003525static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
Mark Lordb67a1062008-03-31 19:35:13 -04003526{
Mark Lordcae5a292009-04-06 16:43:45 -04003527 u32 ifcfg = readl(port_mmio + SATA_IFCFG);
Mark Lordb67a1062008-03-31 19:35:13 -04003528
Mark Lord8e7decd2008-05-02 02:07:51 -04003529 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
Mark Lordb67a1062008-03-31 19:35:13 -04003530 if (want_gen2i)
Mark Lord8e7decd2008-05-02 02:07:51 -04003531 ifcfg |= (1 << 7); /* enable gen2i speed */
Mark Lordcae5a292009-04-06 16:43:45 -04003532 writelfl(ifcfg, port_mmio + SATA_IFCFG);
Mark Lordb67a1062008-03-31 19:35:13 -04003533}
3534
Mark Lorde12bef52008-03-31 19:33:56 -04003535static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
Jeff Garzikc9d39132005-11-13 17:47:51 -05003536 unsigned int port_no)
Brett Russ20f733e2005-09-01 18:26:17 -04003537{
Jeff Garzikc9d39132005-11-13 17:47:51 -05003538 void __iomem *port_mmio = mv_port_base(mmio, port_no);
Brett Russ20f733e2005-09-01 18:26:17 -04003539
Mark Lord8e7decd2008-05-02 02:07:51 -04003540 /*
3541 * The datasheet warns against setting EDMA_RESET when EDMA is active
3542 * (but doesn't say what the problem might be). So we first try
3543 * to disable the EDMA engine before doing the EDMA_RESET operation.
3544 */
Mark Lord0d8be5c2008-04-16 14:56:12 -04003545 mv_stop_edma_engine(port_mmio);
Mark Lordcae5a292009-04-06 16:43:45 -04003546 writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003547
Mark Lordb67a1062008-03-31 19:35:13 -04003548 if (!IS_GEN_I(hpriv)) {
Mark Lord8e7decd2008-05-02 02:07:51 -04003549 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
3550 mv_setup_ifcfg(port_mmio, 1);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003551 }
Mark Lordb67a1062008-03-31 19:35:13 -04003552 /*
Mark Lord8e7decd2008-05-02 02:07:51 -04003553 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
Mark Lordb67a1062008-03-31 19:35:13 -04003554 * link, and physical layers. It resets all SATA interface registers
Mark Lordcae5a292009-04-06 16:43:45 -04003555 * (except for SATA_IFCFG), and issues a COMRESET to the dev.
Brett Russ20f733e2005-09-01 18:26:17 -04003556 */
Mark Lordcae5a292009-04-06 16:43:45 -04003557 writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
Mark Lordb67a1062008-03-31 19:35:13 -04003558 udelay(25); /* allow reset propagation */
Mark Lordcae5a292009-04-06 16:43:45 -04003559 writelfl(0, port_mmio + EDMA_CMD);
Brett Russ20f733e2005-09-01 18:26:17 -04003560
Jeff Garzikc9d39132005-11-13 17:47:51 -05003561 hpriv->ops->phy_errata(hpriv, mmio, port_no);
3562
Jeff Garzikee9ccdf2007-07-12 15:51:22 -04003563 if (IS_GEN_I(hpriv))
Jeff Garzikc9d39132005-11-13 17:47:51 -05003564 mdelay(1);
3565}
3566
Mark Lorde49856d2008-04-16 14:59:07 -04003567static void mv_pmp_select(struct ata_port *ap, int pmp)
Jeff Garzikc9d39132005-11-13 17:47:51 -05003568{
Mark Lorde49856d2008-04-16 14:59:07 -04003569 if (sata_pmp_supported(ap)) {
3570 void __iomem *port_mmio = mv_ap_base(ap);
Mark Lordcae5a292009-04-06 16:43:45 -04003571 u32 reg = readl(port_mmio + SATA_IFCTL);
Mark Lorde49856d2008-04-16 14:59:07 -04003572 int old = reg & 0xf;
Jeff Garzikc9d39132005-11-13 17:47:51 -05003573
Mark Lorde49856d2008-04-16 14:59:07 -04003574 if (old != pmp) {
3575 reg = (reg & ~0xf) | pmp;
Mark Lordcae5a292009-04-06 16:43:45 -04003576 writelfl(reg, port_mmio + SATA_IFCTL);
Mark Lorde49856d2008-04-16 14:59:07 -04003577 }
Tejun Heoda3dbb12007-07-16 14:29:40 +09003578 }
Brett Russ20f733e2005-09-01 18:26:17 -04003579}
3580
Mark Lorde49856d2008-04-16 14:59:07 -04003581static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
3582 unsigned long deadline)
Jeff Garzik22374672005-11-17 10:59:48 -05003583{
Mark Lorde49856d2008-04-16 14:59:07 -04003584 mv_pmp_select(link->ap, sata_srst_pmp(link));
3585 return sata_std_hardreset(link, class, deadline);
3586}
Jeff Garzik0ea9e172007-07-13 17:06:45 -04003587
Mark Lorde49856d2008-04-16 14:59:07 -04003588static int mv_softreset(struct ata_link *link, unsigned int *class,
3589 unsigned long deadline)
3590{
3591 mv_pmp_select(link->ap, sata_srst_pmp(link));
3592 return ata_sff_softreset(link, class, deadline);
Jeff Garzik22374672005-11-17 10:59:48 -05003593}
3594
Tejun Heocc0680a2007-08-06 18:36:23 +09003595static int mv_hardreset(struct ata_link *link, unsigned int *class,
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003596 unsigned long deadline)
3597{
Tejun Heocc0680a2007-08-06 18:36:23 +09003598 struct ata_port *ap = link->ap;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003599 struct mv_host_priv *hpriv = ap->host->private_data;
Mark Lordb5624682008-03-31 19:34:40 -04003600 struct mv_port_priv *pp = ap->private_data;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003601 void __iomem *mmio = hpriv->base;
Mark Lord0d8be5c2008-04-16 14:56:12 -04003602 int rc, attempts = 0, extra = 0;
3603 u32 sstatus;
3604 bool online;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003605
Mark Lorde12bef52008-03-31 19:33:56 -04003606 mv_reset_channel(hpriv, mmio, ap->port_no);
Mark Lordb5624682008-03-31 19:34:40 -04003607 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
Mark Lordd16ab3f2009-02-25 15:17:43 -05003608 pp->pp_flags &=
3609 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003610
Mark Lord0d8be5c2008-04-16 14:56:12 -04003611 /* Workaround for errata FEr SATA#10 (part 2) */
3612 do {
Mark Lord17c5aab2008-04-16 14:56:51 -04003613 const unsigned long *timing =
3614 sata_ehc_deb_timing(&link->eh_context);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003615
Mark Lord17c5aab2008-04-16 14:56:51 -04003616 rc = sata_link_hardreset(link, timing, deadline + extra,
3617 &online, NULL);
Mark Lord9dcffd92008-05-14 09:18:12 -04003618 rc = online ? -EAGAIN : rc;
Mark Lord17c5aab2008-04-16 14:56:51 -04003619 if (rc)
Mark Lord0d8be5c2008-04-16 14:56:12 -04003620 return rc;
Mark Lord0d8be5c2008-04-16 14:56:12 -04003621 sata_scr_read(link, SCR_STATUS, &sstatus);
3622 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
3623 /* Force 1.5gb/s link speed and try again */
Mark Lord8e7decd2008-05-02 02:07:51 -04003624 mv_setup_ifcfg(mv_ap_base(ap), 0);
Mark Lord0d8be5c2008-04-16 14:56:12 -04003625 if (time_after(jiffies + HZ, deadline))
3626 extra = HZ; /* only extend it once, max */
3627 }
3628 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
Mark Lord08da1752009-02-25 15:13:03 -05003629 mv_save_cached_regs(ap);
Mark Lord66e57a22009-01-30 18:52:58 -05003630 mv_edma_cfg(ap, 0, 0);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003631
Mark Lord17c5aab2008-04-16 14:56:51 -04003632 return rc;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003633}
3634
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003635static void mv_eh_freeze(struct ata_port *ap)
Brett Russ20f733e2005-09-01 18:26:17 -04003636{
Mark Lord1cfd19a2008-04-19 15:05:50 -04003637 mv_stop_edma(ap);
Mark Lordc4de5732008-05-17 13:35:21 -04003638 mv_enable_port_irqs(ap, 0);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003639}
3640
3641static void mv_eh_thaw(struct ata_port *ap)
3642{
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003643 struct mv_host_priv *hpriv = ap->host->private_data;
Mark Lordc4de5732008-05-17 13:35:21 -04003644 unsigned int port = ap->port_no;
3645 unsigned int hardport = mv_hardport_from_port(port);
Mark Lord1cfd19a2008-04-19 15:05:50 -04003646 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003647 void __iomem *port_mmio = mv_ap_base(ap);
Mark Lordc4de5732008-05-17 13:35:21 -04003648 u32 hc_irq_cause;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003649
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003650 /* clear EDMA errors on this port */
Mark Lordcae5a292009-04-06 16:43:45 -04003651 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003652
3653 /* clear pending irq events */
Mark Lordcae6edc2009-01-19 18:05:42 -05003654 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
Mark Lordcae5a292009-04-06 16:43:45 -04003655 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003656
Mark Lord88e675e2008-05-17 13:36:30 -04003657 mv_enable_port_irqs(ap, ERR_IRQ);
Brett Russ31961942005-09-30 01:36:00 -04003658}
3659
Brett Russ05b308e2005-10-05 17:08:53 -04003660/**
3661 * mv_port_init - Perform some early initialization on a single port.
3662 * @port: libata data structure storing shadow register addresses
3663 * @port_mmio: base address of the port
3664 *
3665 * Initialize shadow register mmio addresses, clear outstanding
3666 * interrupts on the port, and unmask interrupts for the future
3667 * start of the port.
3668 *
3669 * LOCKING:
3670 * Inherited from caller.
3671 */
Brett Russ31961942005-09-30 01:36:00 -04003672static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
3673{
Mark Lordcae5a292009-04-06 16:43:45 -04003674 void __iomem *serr, *shd_base = port_mmio + SHD_BLK;
Brett Russ31961942005-09-30 01:36:00 -04003675
Jeff Garzik8b260242005-11-12 12:32:50 -05003676 /* PIO related setup
Brett Russ31961942005-09-30 01:36:00 -04003677 */
3678 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
Jeff Garzik8b260242005-11-12 12:32:50 -05003679 port->error_addr =
Brett Russ31961942005-09-30 01:36:00 -04003680 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
3681 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
3682 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
3683 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
3684 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
3685 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
Jeff Garzik8b260242005-11-12 12:32:50 -05003686 port->status_addr =
Brett Russ31961942005-09-30 01:36:00 -04003687 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
3688 /* special case: control/altstatus doesn't have ATA_REG_ address */
Mark Lordcae5a292009-04-06 16:43:45 -04003689 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST;
Brett Russ31961942005-09-30 01:36:00 -04003690
Brett Russ31961942005-09-30 01:36:00 -04003691 /* Clear any currently outstanding port interrupt conditions */
Mark Lordcae5a292009-04-06 16:43:45 -04003692 serr = port_mmio + mv_scr_offset(SCR_ERROR);
3693 writelfl(readl(serr), serr);
3694 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
Brett Russ31961942005-09-30 01:36:00 -04003695
Mark Lord646a4da2008-01-26 18:30:37 -05003696 /* unmask all non-transient EDMA error interrupts */
Mark Lordcae5a292009-04-06 16:43:45 -04003697 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK);
Brett Russ20f733e2005-09-01 18:26:17 -04003698
Jeff Garzik8b260242005-11-12 12:32:50 -05003699 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
Mark Lordcae5a292009-04-06 16:43:45 -04003700 readl(port_mmio + EDMA_CFG),
3701 readl(port_mmio + EDMA_ERR_IRQ_CAUSE),
3702 readl(port_mmio + EDMA_ERR_IRQ_MASK));
Brett Russ20f733e2005-09-01 18:26:17 -04003703}
3704
Mark Lord616d4a92008-05-02 02:08:32 -04003705static unsigned int mv_in_pcix_mode(struct ata_host *host)
3706{
3707 struct mv_host_priv *hpriv = host->private_data;
3708 void __iomem *mmio = hpriv->base;
3709 u32 reg;
3710
Mark Lord1f398472008-05-27 17:54:48 -04003711 if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
Mark Lord616d4a92008-05-02 02:08:32 -04003712 return 0; /* not PCI-X capable */
Mark Lordcae5a292009-04-06 16:43:45 -04003713 reg = readl(mmio + MV_PCI_MODE);
Mark Lord616d4a92008-05-02 02:08:32 -04003714 if ((reg & MV_PCI_MODE_MASK) == 0)
3715 return 0; /* conventional PCI mode */
3716 return 1; /* chip is in PCI-X mode */
3717}
3718
3719static int mv_pci_cut_through_okay(struct ata_host *host)
3720{
3721 struct mv_host_priv *hpriv = host->private_data;
3722 void __iomem *mmio = hpriv->base;
3723 u32 reg;
3724
3725 if (!mv_in_pcix_mode(host)) {
Mark Lordcae5a292009-04-06 16:43:45 -04003726 reg = readl(mmio + MV_PCI_COMMAND);
3727 if (reg & MV_PCI_COMMAND_MRDTRIG)
Mark Lord616d4a92008-05-02 02:08:32 -04003728 return 0; /* not okay */
3729 }
3730 return 1; /* okay */
3731}
3732
Mark Lord65ad7fef2009-04-06 15:24:14 -04003733static void mv_60x1b2_errata_pci7(struct ata_host *host)
3734{
3735 struct mv_host_priv *hpriv = host->private_data;
3736 void __iomem *mmio = hpriv->base;
3737
3738 /* workaround for 60x1-B2 errata PCI#7 */
3739 if (mv_in_pcix_mode(host)) {
Mark Lordcae5a292009-04-06 16:43:45 -04003740 u32 reg = readl(mmio + MV_PCI_COMMAND);
3741 writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND);
Mark Lord65ad7fef2009-04-06 15:24:14 -04003742 }
3743}
3744
Tejun Heo4447d352007-04-17 23:44:08 +09003745static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003746{
Tejun Heo4447d352007-04-17 23:44:08 +09003747 struct pci_dev *pdev = to_pci_dev(host->dev);
3748 struct mv_host_priv *hpriv = host->private_data;
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003749 u32 hp_flags = hpriv->hp_flags;
3750
Jeff Garzik5796d1c2007-10-26 00:03:37 -04003751 switch (board_idx) {
Jeff Garzik47c2b672005-11-12 21:13:17 -05003752 case chip_5080:
3753 hpriv->ops = &mv5xxx_ops;
Jeff Garzikee9ccdf2007-07-12 15:51:22 -04003754 hp_flags |= MV_HP_GEN_I;
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003755
Auke Kok44c10132007-06-08 15:46:36 -07003756 switch (pdev->revision) {
Jeff Garzik47c2b672005-11-12 21:13:17 -05003757 case 0x1:
3758 hp_flags |= MV_HP_ERRATA_50XXB0;
3759 break;
3760 case 0x3:
3761 hp_flags |= MV_HP_ERRATA_50XXB2;
3762 break;
3763 default:
Joe Perchesa44fec12011-04-15 15:51:58 -07003764 dev_warn(&pdev->dev,
3765 "Applying 50XXB2 workarounds to unknown rev\n");
Jeff Garzik47c2b672005-11-12 21:13:17 -05003766 hp_flags |= MV_HP_ERRATA_50XXB2;
3767 break;
3768 }
3769 break;
3770
3771 case chip_504x:
3772 case chip_508x:
3773 hpriv->ops = &mv5xxx_ops;
Jeff Garzikee9ccdf2007-07-12 15:51:22 -04003774 hp_flags |= MV_HP_GEN_I;
Jeff Garzik47c2b672005-11-12 21:13:17 -05003775
Auke Kok44c10132007-06-08 15:46:36 -07003776 switch (pdev->revision) {
Jeff Garzik47c2b672005-11-12 21:13:17 -05003777 case 0x0:
3778 hp_flags |= MV_HP_ERRATA_50XXB0;
3779 break;
3780 case 0x3:
3781 hp_flags |= MV_HP_ERRATA_50XXB2;
3782 break;
3783 default:
Joe Perchesa44fec12011-04-15 15:51:58 -07003784 dev_warn(&pdev->dev,
3785 "Applying B2 workarounds to unknown rev\n");
Jeff Garzik47c2b672005-11-12 21:13:17 -05003786 hp_flags |= MV_HP_ERRATA_50XXB2;
3787 break;
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003788 }
3789 break;
3790
3791 case chip_604x:
3792 case chip_608x:
Jeff Garzik47c2b672005-11-12 21:13:17 -05003793 hpriv->ops = &mv6xxx_ops;
Jeff Garzikee9ccdf2007-07-12 15:51:22 -04003794 hp_flags |= MV_HP_GEN_II;
Jeff Garzik47c2b672005-11-12 21:13:17 -05003795
Auke Kok44c10132007-06-08 15:46:36 -07003796 switch (pdev->revision) {
Jeff Garzik47c2b672005-11-12 21:13:17 -05003797 case 0x7:
Mark Lord65ad7fef2009-04-06 15:24:14 -04003798 mv_60x1b2_errata_pci7(host);
Jeff Garzik47c2b672005-11-12 21:13:17 -05003799 hp_flags |= MV_HP_ERRATA_60X1B2;
3800 break;
3801 case 0x9:
3802 hp_flags |= MV_HP_ERRATA_60X1C0;
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003803 break;
3804 default:
Joe Perchesa44fec12011-04-15 15:51:58 -07003805 dev_warn(&pdev->dev,
3806 "Applying B2 workarounds to unknown rev\n");
Jeff Garzik47c2b672005-11-12 21:13:17 -05003807 hp_flags |= MV_HP_ERRATA_60X1B2;
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003808 break;
3809 }
3810 break;
3811
Jeff Garzike4e7b892006-01-31 12:18:41 -05003812 case chip_7042:
Mark Lord616d4a92008-05-02 02:08:32 -04003813 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
Mark Lord306b30f2007-12-04 14:07:52 -05003814 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
3815 (pdev->device == 0x2300 || pdev->device == 0x2310))
3816 {
Mark Lord4e520032007-12-11 12:58:05 -05003817 /*
3818 * Highpoint RocketRAID PCIe 23xx series cards:
3819 *
3820 * Unconfigured drives are treated as "Legacy"
3821 * by the BIOS, and it overwrites sector 8 with
3822 * a "Lgcy" metadata block prior to Linux boot.
3823 *
3824 * Configured drives (RAID or JBOD) leave sector 8
3825 * alone, but instead overwrite a high numbered
3826 * sector for the RAID metadata. This sector can
3827 * be determined exactly, by truncating the physical
3828 * drive capacity to a nice even GB value.
3829 *
3830 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
3831 *
3832 * Warn the user, lest they think we're just buggy.
3833 */
3834 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
3835 " BIOS CORRUPTS DATA on all attached drives,"
3836 " regardless of if/how they are configured."
3837 " BEWARE!\n");
3838 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
3839 " use sectors 8-9 on \"Legacy\" drives,"
3840 " and avoid the final two gigabytes on"
3841 " all RocketRAID BIOS initialized drives.\n");
Mark Lord306b30f2007-12-04 14:07:52 -05003842 }
Mark Lord8e7decd2008-05-02 02:07:51 -04003843 /* drop through */
Jeff Garzike4e7b892006-01-31 12:18:41 -05003844 case chip_6042:
3845 hpriv->ops = &mv6xxx_ops;
Jeff Garzike4e7b892006-01-31 12:18:41 -05003846 hp_flags |= MV_HP_GEN_IIE;
Mark Lord616d4a92008-05-02 02:08:32 -04003847 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
3848 hp_flags |= MV_HP_CUT_THROUGH;
Jeff Garzike4e7b892006-01-31 12:18:41 -05003849
Auke Kok44c10132007-06-08 15:46:36 -07003850 switch (pdev->revision) {
Mark Lord5cf73bf2008-05-27 17:58:56 -04003851 case 0x2: /* Rev.B0: the first/only public release */
Jeff Garzike4e7b892006-01-31 12:18:41 -05003852 hp_flags |= MV_HP_ERRATA_60X1C0;
3853 break;
3854 default:
Joe Perchesa44fec12011-04-15 15:51:58 -07003855 dev_warn(&pdev->dev,
3856 "Applying 60X1C0 workarounds to unknown rev\n");
Jeff Garzike4e7b892006-01-31 12:18:41 -05003857 hp_flags |= MV_HP_ERRATA_60X1C0;
3858 break;
3859 }
3860 break;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003861 case chip_soc:
Martin Michlmayr29b7e432009-05-04 20:58:50 +02003862 if (soc_is_65n(hpriv))
3863 hpriv->ops = &mv_soc_65n_ops;
3864 else
3865 hpriv->ops = &mv_soc_ops;
Saeed Bisharaeb3a55a2008-08-04 00:52:55 -11003866 hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
3867 MV_HP_ERRATA_60X1C0;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003868 break;
Jeff Garzike4e7b892006-01-31 12:18:41 -05003869
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003870 default:
Joe Perchesa44fec12011-04-15 15:51:58 -07003871 dev_err(host->dev, "BUG: invalid board index %u\n", board_idx);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003872 return 1;
3873 }
3874
3875 hpriv->hp_flags = hp_flags;
Mark Lord02a121d2007-12-01 13:07:22 -05003876 if (hp_flags & MV_HP_PCIE) {
Mark Lordcae5a292009-04-06 16:43:45 -04003877 hpriv->irq_cause_offset = PCIE_IRQ_CAUSE;
3878 hpriv->irq_mask_offset = PCIE_IRQ_MASK;
Mark Lord02a121d2007-12-01 13:07:22 -05003879 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3880 } else {
Mark Lordcae5a292009-04-06 16:43:45 -04003881 hpriv->irq_cause_offset = PCI_IRQ_CAUSE;
3882 hpriv->irq_mask_offset = PCI_IRQ_MASK;
Mark Lord02a121d2007-12-01 13:07:22 -05003883 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3884 }
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003885
3886 return 0;
3887}
3888
Brett Russ05b308e2005-10-05 17:08:53 -04003889/**
Jeff Garzik47c2b672005-11-12 21:13:17 -05003890 * mv_init_host - Perform some early initialization of the host.
Tejun Heo4447d352007-04-17 23:44:08 +09003891 * @host: ATA host to initialize
Brett Russ05b308e2005-10-05 17:08:53 -04003892 *
3893 * If possible, do an early global reset of the host. Then do
3894 * our port init and clear/unmask all/relevant host interrupts.
3895 *
3896 * LOCKING:
3897 * Inherited from caller.
3898 */
Saeed Bishara1bfeff02009-12-17 01:05:00 -05003899static int mv_init_host(struct ata_host *host)
Brett Russ20f733e2005-09-01 18:26:17 -04003900{
3901 int rc = 0, n_hc, port, hc;
Tejun Heo4447d352007-04-17 23:44:08 +09003902 struct mv_host_priv *hpriv = host->private_data;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003903 void __iomem *mmio = hpriv->base;
Jeff Garzik47c2b672005-11-12 21:13:17 -05003904
Saeed Bishara1bfeff02009-12-17 01:05:00 -05003905 rc = mv_chip_id(host, hpriv->board_idx);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003906 if (rc)
Mark Lord352fab72008-04-19 14:43:42 -04003907 goto done;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003908
Mark Lord1f398472008-05-27 17:54:48 -04003909 if (IS_SOC(hpriv)) {
Mark Lordcae5a292009-04-06 16:43:45 -04003910 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE;
3911 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK;
Mark Lord1f398472008-05-27 17:54:48 -04003912 } else {
Mark Lordcae5a292009-04-06 16:43:45 -04003913 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE;
3914 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003915 }
Mark Lord352fab72008-04-19 14:43:42 -04003916
Thomas Reitmayr5d0fb2e2009-01-24 20:24:58 +01003917 /* initialize shadow irq mask with register's value */
3918 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
3919
Mark Lord352fab72008-04-19 14:43:42 -04003920 /* global interrupt mask: 0 == mask everything */
Mark Lordc4de5732008-05-17 13:35:21 -04003921 mv_set_main_irq_mask(host, ~0, 0);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003922
Tejun Heo4447d352007-04-17 23:44:08 +09003923 n_hc = mv_get_hc_count(host->ports[0]->flags);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003924
Tejun Heo4447d352007-04-17 23:44:08 +09003925 for (port = 0; port < host->n_ports; port++)
Martin Michlmayr29b7e432009-05-04 20:58:50 +02003926 if (hpriv->ops->read_preamp)
3927 hpriv->ops->read_preamp(hpriv, port, mmio);
Brett Russ20f733e2005-09-01 18:26:17 -04003928
Jeff Garzikc9d39132005-11-13 17:47:51 -05003929 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
Jeff Garzik47c2b672005-11-12 21:13:17 -05003930 if (rc)
Brett Russ20f733e2005-09-01 18:26:17 -04003931 goto done;
Brett Russ20f733e2005-09-01 18:26:17 -04003932
Jeff Garzik522479f2005-11-12 22:14:02 -05003933 hpriv->ops->reset_flash(hpriv, mmio);
Saeed Bishara7bb3c522008-01-30 11:50:45 -11003934 hpriv->ops->reset_bus(host, mmio);
Jeff Garzik47c2b672005-11-12 21:13:17 -05003935 hpriv->ops->enable_leds(hpriv, mmio);
Brett Russ20f733e2005-09-01 18:26:17 -04003936
Tejun Heo4447d352007-04-17 23:44:08 +09003937 for (port = 0; port < host->n_ports; port++) {
Tejun Heocbcdd872007-08-18 13:14:55 +09003938 struct ata_port *ap = host->ports[port];
Jeff Garzik2a47ce02005-11-12 23:05:14 -05003939 void __iomem *port_mmio = mv_port_base(mmio, port);
Tejun Heocbcdd872007-08-18 13:14:55 +09003940
3941 mv_port_init(&ap->ioaddr, port_mmio);
Brett Russ20f733e2005-09-01 18:26:17 -04003942 }
3943
3944 for (hc = 0; hc < n_hc; hc++) {
Brett Russ31961942005-09-30 01:36:00 -04003945 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3946
3947 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3948 "(before clear)=0x%08x\n", hc,
Mark Lordcae5a292009-04-06 16:43:45 -04003949 readl(hc_mmio + HC_CFG),
3950 readl(hc_mmio + HC_IRQ_CAUSE));
Brett Russ31961942005-09-30 01:36:00 -04003951
3952 /* Clear any currently outstanding hc interrupt conditions */
Mark Lordcae5a292009-04-06 16:43:45 -04003953 writelfl(0, hc_mmio + HC_IRQ_CAUSE);
Brett Russ20f733e2005-09-01 18:26:17 -04003954 }
3955
Mark Lord44c65d12009-04-06 12:29:49 -04003956 if (!IS_SOC(hpriv)) {
3957 /* Clear any currently outstanding host interrupt conditions */
Mark Lordcae5a292009-04-06 16:43:45 -04003958 writelfl(0, mmio + hpriv->irq_cause_offset);
Brett Russ31961942005-09-30 01:36:00 -04003959
Mark Lord44c65d12009-04-06 12:29:49 -04003960 /* and unmask interrupt generation for host regs */
Mark Lordcae5a292009-04-06 16:43:45 -04003961 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset);
Mark Lord44c65d12009-04-06 12:29:49 -04003962 }
Jeff Garzikfb621e22007-02-25 04:19:45 -05003963
Mark Lord6be96ac2009-02-19 10:38:04 -05003964 /*
3965 * enable only global host interrupts for now.
3966 * The per-port interrupts get done later as ports are set up.
3967 */
3968 mv_set_main_irq_mask(host, 0, PCI_ERR);
Mark Lord2b748a02009-03-10 22:01:17 -04003969 mv_set_irq_coalescing(host, irq_coalescing_io_count,
3970 irq_coalescing_usecs);
Brett Russ31961942005-09-30 01:36:00 -04003971done:
Brett Russ20f733e2005-09-01 18:26:17 -04003972 return rc;
3973}
3974
Byron Bradleyfbf14e22008-02-10 21:17:30 +00003975static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3976{
3977 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3978 MV_CRQB_Q_SZ, 0);
3979 if (!hpriv->crqb_pool)
3980 return -ENOMEM;
3981
3982 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3983 MV_CRPB_Q_SZ, 0);
3984 if (!hpriv->crpb_pool)
3985 return -ENOMEM;
3986
3987 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3988 MV_SG_TBL_SZ, 0);
3989 if (!hpriv->sg_tbl_pool)
3990 return -ENOMEM;
3991
3992 return 0;
3993}
3994
Lennert Buytenhek15a32632008-03-27 14:51:39 -04003995static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
Andrew Lunn63a93322011-12-07 21:48:07 +01003996 const struct mbus_dram_target_info *dram)
Lennert Buytenhek15a32632008-03-27 14:51:39 -04003997{
3998 int i;
3999
4000 for (i = 0; i < 4; i++) {
4001 writel(0, hpriv->base + WINDOW_CTRL(i));
4002 writel(0, hpriv->base + WINDOW_BASE(i));
4003 }
4004
4005 for (i = 0; i < dram->num_cs; i++) {
Andrew Lunn63a93322011-12-07 21:48:07 +01004006 const struct mbus_dram_window *cs = dram->cs + i;
Lennert Buytenhek15a32632008-03-27 14:51:39 -04004007
4008 writel(((cs->size - 1) & 0xffff0000) |
4009 (cs->mbus_attr << 8) |
4010 (dram->mbus_dram_target_id << 4) | 1,
4011 hpriv->base + WINDOW_CTRL(i));
4012 writel(cs->base, hpriv->base + WINDOW_BASE(i));
4013 }
4014}
4015
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004016/**
4017 * mv_platform_probe - handle a positive probe of an soc Marvell
4018 * host
4019 * @pdev: platform device found
4020 *
4021 * LOCKING:
4022 * Inherited from caller.
4023 */
4024static int mv_platform_probe(struct platform_device *pdev)
4025{
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004026 const struct mv_sata_platform_data *mv_platform_data;
Andrew Lunn63a93322011-12-07 21:48:07 +01004027 const struct mbus_dram_target_info *dram;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004028 const struct ata_port_info *ppi[] =
4029 { &mv_port_info[chip_soc], NULL };
4030 struct ata_host *host;
4031 struct mv_host_priv *hpriv;
4032 struct resource *res;
Andrew Lunn97b414e2012-06-10 16:45:37 +02004033 int n_ports = 0, irq = 0;
Dan Carpenter99b80e92012-03-10 12:00:05 +03004034 int rc;
Andrew Lunneee98992012-02-18 22:26:42 +01004035#if defined(CONFIG_HAVE_CLK)
4036 int port;
4037#endif
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004038
Joe Perches06296a12011-04-15 15:52:00 -07004039 ata_print_version_once(&pdev->dev, DRV_VERSION);
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004040
4041 /*
4042 * Simple resource validation ..
4043 */
4044 if (unlikely(pdev->num_resources != 2)) {
4045 dev_err(&pdev->dev, "invalid number of resources\n");
4046 return -EINVAL;
4047 }
4048
4049 /*
4050 * Get the register base first
4051 */
4052 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4053 if (res == NULL)
4054 return -EINVAL;
4055
4056 /* allocate host */
Andrew Lunn97b414e2012-06-10 16:45:37 +02004057 if (pdev->dev.of_node) {
4058 of_property_read_u32(pdev->dev.of_node, "nr-ports", &n_ports);
4059 irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
4060 } else {
4061 mv_platform_data = pdev->dev.platform_data;
4062 n_ports = mv_platform_data->n_ports;
4063 irq = platform_get_irq(pdev, 0);
4064 }
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004065
4066 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4067 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4068
4069 if (!host || !hpriv)
4070 return -ENOMEM;
Andrew Lunneee98992012-02-18 22:26:42 +01004071#if defined(CONFIG_HAVE_CLK)
4072 hpriv->port_clks = devm_kzalloc(&pdev->dev,
4073 sizeof(struct clk *) * n_ports,
4074 GFP_KERNEL);
4075 if (!hpriv->port_clks)
4076 return -ENOMEM;
4077#endif
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004078 host->private_data = hpriv;
4079 hpriv->n_ports = n_ports;
Saeed Bishara1bfeff02009-12-17 01:05:00 -05004080 hpriv->board_idx = chip_soc;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004081
4082 host->iomap = NULL;
Saeed Bisharaf1cb0ea2008-02-18 07:42:28 -11004083 hpriv->base = devm_ioremap(&pdev->dev, res->start,
Julia Lawall041b5ea2009-08-06 16:05:08 -07004084 resource_size(res));
Mark Lordcae5a292009-04-06 16:43:45 -04004085 hpriv->base -= SATAHC0_REG_BASE;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004086
Saeed Bisharac77a2f42009-12-06 18:26:18 +02004087#if defined(CONFIG_HAVE_CLK)
4088 hpriv->clk = clk_get(&pdev->dev, NULL);
4089 if (IS_ERR(hpriv->clk))
Andrew Lunneee98992012-02-18 22:26:42 +01004090 dev_notice(&pdev->dev, "cannot get optional clkdev\n");
Saeed Bisharac77a2f42009-12-06 18:26:18 +02004091 else
Andrew Lunneee98992012-02-18 22:26:42 +01004092 clk_prepare_enable(hpriv->clk);
4093
4094 for (port = 0; port < n_ports; port++) {
4095 char port_number[16];
4096 sprintf(port_number, "%d", port);
4097 hpriv->port_clks[port] = clk_get(&pdev->dev, port_number);
4098 if (!IS_ERR(hpriv->port_clks[port]))
4099 clk_prepare_enable(hpriv->port_clks[port]);
4100 }
Saeed Bisharac77a2f42009-12-06 18:26:18 +02004101#endif
4102
Lennert Buytenhek15a32632008-03-27 14:51:39 -04004103 /*
4104 * (Re-)program MBUS remapping windows if we are asked to.
4105 */
Andrew Lunn63a93322011-12-07 21:48:07 +01004106 dram = mv_mbus_dram_info();
4107 if (dram)
4108 mv_conf_mbus_windows(hpriv, dram);
Lennert Buytenhek15a32632008-03-27 14:51:39 -04004109
Byron Bradleyfbf14e22008-02-10 21:17:30 +00004110 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4111 if (rc)
Saeed Bisharac77a2f42009-12-06 18:26:18 +02004112 goto err;
Byron Bradleyfbf14e22008-02-10 21:17:30 +00004113
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004114 /* initialize adapter */
Saeed Bishara1bfeff02009-12-17 01:05:00 -05004115 rc = mv_init_host(host);
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004116 if (rc)
Saeed Bisharac77a2f42009-12-06 18:26:18 +02004117 goto err;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004118
Joe Perchesa44fec12011-04-15 15:51:58 -07004119 dev_info(&pdev->dev, "slots %u ports %d\n",
4120 (unsigned)MV_MAX_Q_DEPTH, host->n_ports);
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004121
Andrew Lunn97b414e2012-06-10 16:45:37 +02004122 rc = ata_host_activate(host, irq, mv_interrupt, IRQF_SHARED, &mv6_sht);
Sergei Shtylyovc00a4c92011-10-07 19:22:33 +04004123 if (!rc)
4124 return 0;
4125
Saeed Bisharac77a2f42009-12-06 18:26:18 +02004126err:
4127#if defined(CONFIG_HAVE_CLK)
4128 if (!IS_ERR(hpriv->clk)) {
Andrew Lunneee98992012-02-18 22:26:42 +01004129 clk_disable_unprepare(hpriv->clk);
Saeed Bisharac77a2f42009-12-06 18:26:18 +02004130 clk_put(hpriv->clk);
4131 }
Andrew Lunneee98992012-02-18 22:26:42 +01004132 for (port = 0; port < n_ports; port++) {
4133 if (!IS_ERR(hpriv->port_clks[port])) {
4134 clk_disable_unprepare(hpriv->port_clks[port]);
4135 clk_put(hpriv->port_clks[port]);
4136 }
4137 }
Saeed Bisharac77a2f42009-12-06 18:26:18 +02004138#endif
4139
4140 return rc;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004141}
4142
4143/*
4144 *
4145 * mv_platform_remove - unplug a platform interface
4146 * @pdev: platform device
4147 *
4148 * A platform bus SATA device has been unplugged. Perform the needed
4149 * cleanup. Also called on module unload for any active devices.
4150 */
Greg Kroah-Hartman0ec24912012-12-21 13:19:58 -08004151static int mv_platform_remove(struct platform_device *pdev)
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004152{
Sergei Shtylyovd8661922011-10-07 19:24:22 +04004153 struct ata_host *host = platform_get_drvdata(pdev);
Saeed Bisharac77a2f42009-12-06 18:26:18 +02004154#if defined(CONFIG_HAVE_CLK)
4155 struct mv_host_priv *hpriv = host->private_data;
Andrew Lunneee98992012-02-18 22:26:42 +01004156 int port;
Saeed Bisharac77a2f42009-12-06 18:26:18 +02004157#endif
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004158 ata_host_detach(host);
Saeed Bisharac77a2f42009-12-06 18:26:18 +02004159
4160#if defined(CONFIG_HAVE_CLK)
4161 if (!IS_ERR(hpriv->clk)) {
Andrew Lunneee98992012-02-18 22:26:42 +01004162 clk_disable_unprepare(hpriv->clk);
Saeed Bisharac77a2f42009-12-06 18:26:18 +02004163 clk_put(hpriv->clk);
4164 }
Andrew Lunneee98992012-02-18 22:26:42 +01004165 for (port = 0; port < host->n_ports; port++) {
4166 if (!IS_ERR(hpriv->port_clks[port])) {
4167 clk_disable_unprepare(hpriv->port_clks[port]);
4168 clk_put(hpriv->port_clks[port]);
4169 }
4170 }
Saeed Bisharac77a2f42009-12-06 18:26:18 +02004171#endif
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004172 return 0;
4173}
4174
Saeed Bishara6481f2b2009-12-06 18:26:19 +02004175#ifdef CONFIG_PM
4176static int mv_platform_suspend(struct platform_device *pdev, pm_message_t state)
4177{
Sergei Shtylyovd8661922011-10-07 19:24:22 +04004178 struct ata_host *host = platform_get_drvdata(pdev);
Saeed Bishara6481f2b2009-12-06 18:26:19 +02004179 if (host)
4180 return ata_host_suspend(host, state);
4181 else
4182 return 0;
4183}
4184
4185static int mv_platform_resume(struct platform_device *pdev)
4186{
Sergei Shtylyovd8661922011-10-07 19:24:22 +04004187 struct ata_host *host = platform_get_drvdata(pdev);
Andrew Lunn63a93322011-12-07 21:48:07 +01004188 const struct mbus_dram_target_info *dram;
Saeed Bishara6481f2b2009-12-06 18:26:19 +02004189 int ret;
4190
4191 if (host) {
4192 struct mv_host_priv *hpriv = host->private_data;
Andrew Lunn63a93322011-12-07 21:48:07 +01004193
Saeed Bishara6481f2b2009-12-06 18:26:19 +02004194 /*
4195 * (Re-)program MBUS remapping windows if we are asked to.
4196 */
Andrew Lunn63a93322011-12-07 21:48:07 +01004197 dram = mv_mbus_dram_info();
4198 if (dram)
4199 mv_conf_mbus_windows(hpriv, dram);
Saeed Bishara6481f2b2009-12-06 18:26:19 +02004200
4201 /* initialize adapter */
Saeed Bishara1bfeff02009-12-17 01:05:00 -05004202 ret = mv_init_host(host);
Saeed Bishara6481f2b2009-12-06 18:26:19 +02004203 if (ret) {
4204 printk(KERN_ERR DRV_NAME ": Error during HW init\n");
4205 return ret;
4206 }
4207 ata_host_resume(host);
4208 }
4209
4210 return 0;
4211}
4212#else
4213#define mv_platform_suspend NULL
4214#define mv_platform_resume NULL
4215#endif
4216
Andrew Lunn97b414e2012-06-10 16:45:37 +02004217#ifdef CONFIG_OF
Greg Kroah-Hartman0ec24912012-12-21 13:19:58 -08004218static struct of_device_id mv_sata_dt_ids[] = {
Andrew Lunn97b414e2012-06-10 16:45:37 +02004219 { .compatible = "marvell,orion-sata", },
4220 {},
4221};
4222MODULE_DEVICE_TABLE(of, mv_sata_dt_ids);
4223#endif
4224
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004225static struct platform_driver mv_platform_driver = {
Andrew Lunn97b414e2012-06-10 16:45:37 +02004226 .probe = mv_platform_probe,
Greg Kroah-Hartman0ec24912012-12-21 13:19:58 -08004227 .remove = mv_platform_remove,
Andrew Lunn97b414e2012-06-10 16:45:37 +02004228 .suspend = mv_platform_suspend,
4229 .resume = mv_platform_resume,
4230 .driver = {
4231 .name = DRV_NAME,
4232 .owner = THIS_MODULE,
4233 .of_match_table = of_match_ptr(mv_sata_dt_ids),
4234 },
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004235};
4236
4237
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004238#ifdef CONFIG_PCI
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004239static int mv_pci_init_one(struct pci_dev *pdev,
4240 const struct pci_device_id *ent);
Saeed Bisharab2dec482009-12-06 18:26:22 +02004241#ifdef CONFIG_PM
4242static int mv_pci_device_resume(struct pci_dev *pdev);
4243#endif
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004244
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004245
4246static struct pci_driver mv_pci_driver = {
4247 .name = DRV_NAME,
4248 .id_table = mv_pci_tbl,
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004249 .probe = mv_pci_init_one,
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004250 .remove = ata_pci_remove_one,
Saeed Bisharab2dec482009-12-06 18:26:22 +02004251#ifdef CONFIG_PM
4252 .suspend = ata_pci_device_suspend,
4253 .resume = mv_pci_device_resume,
4254#endif
4255
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004256};
4257
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004258/* move to PCI layer or libata core? */
4259static int pci_go_64(struct pci_dev *pdev)
4260{
4261 int rc;
4262
Yang Hongyang6a355282009-04-06 19:01:13 -07004263 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4264 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004265 if (rc) {
Yang Hongyang284901a2009-04-06 19:01:15 -07004266 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004267 if (rc) {
Joe Perchesa44fec12011-04-15 15:51:58 -07004268 dev_err(&pdev->dev,
4269 "64-bit DMA enable failed\n");
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004270 return rc;
4271 }
4272 }
4273 } else {
Yang Hongyang284901a2009-04-06 19:01:15 -07004274 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004275 if (rc) {
Joe Perchesa44fec12011-04-15 15:51:58 -07004276 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004277 return rc;
4278 }
Yang Hongyang284901a2009-04-06 19:01:15 -07004279 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004280 if (rc) {
Joe Perchesa44fec12011-04-15 15:51:58 -07004281 dev_err(&pdev->dev,
4282 "32-bit consistent DMA enable failed\n");
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004283 return rc;
4284 }
4285 }
4286
4287 return rc;
4288}
4289
Brett Russ05b308e2005-10-05 17:08:53 -04004290/**
4291 * mv_print_info - Dump key info to kernel log for perusal.
Tejun Heo4447d352007-04-17 23:44:08 +09004292 * @host: ATA host to print info about
Brett Russ05b308e2005-10-05 17:08:53 -04004293 *
4294 * FIXME: complete this.
4295 *
4296 * LOCKING:
4297 * Inherited from caller.
4298 */
Tejun Heo4447d352007-04-17 23:44:08 +09004299static void mv_print_info(struct ata_host *host)
Brett Russ31961942005-09-30 01:36:00 -04004300{
Tejun Heo4447d352007-04-17 23:44:08 +09004301 struct pci_dev *pdev = to_pci_dev(host->dev);
4302 struct mv_host_priv *hpriv = host->private_data;
Auke Kok44c10132007-06-08 15:46:36 -07004303 u8 scc;
Jeff Garzikc1e4fe72007-07-09 12:29:31 -04004304 const char *scc_s, *gen;
Brett Russ31961942005-09-30 01:36:00 -04004305
4306 /* Use this to determine the HW stepping of the chip so we know
4307 * what errata to workaround
4308 */
Brett Russ31961942005-09-30 01:36:00 -04004309 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
4310 if (scc == 0)
4311 scc_s = "SCSI";
4312 else if (scc == 0x01)
4313 scc_s = "RAID";
4314 else
Jeff Garzikc1e4fe72007-07-09 12:29:31 -04004315 scc_s = "?";
4316
4317 if (IS_GEN_I(hpriv))
4318 gen = "I";
4319 else if (IS_GEN_II(hpriv))
4320 gen = "II";
4321 else if (IS_GEN_IIE(hpriv))
4322 gen = "IIE";
4323 else
4324 gen = "?";
Brett Russ31961942005-09-30 01:36:00 -04004325
Joe Perchesa44fec12011-04-15 15:51:58 -07004326 dev_info(&pdev->dev, "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
4327 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
4328 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
Brett Russ31961942005-09-30 01:36:00 -04004329}
4330
Brett Russ05b308e2005-10-05 17:08:53 -04004331/**
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004332 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
Brett Russ05b308e2005-10-05 17:08:53 -04004333 * @pdev: PCI device found
4334 * @ent: PCI device ID entry for the matched host
4335 *
4336 * LOCKING:
4337 * Inherited from caller.
4338 */
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004339static int mv_pci_init_one(struct pci_dev *pdev,
4340 const struct pci_device_id *ent)
Brett Russ20f733e2005-09-01 18:26:17 -04004341{
Brett Russ20f733e2005-09-01 18:26:17 -04004342 unsigned int board_idx = (unsigned int)ent->driver_data;
Tejun Heo4447d352007-04-17 23:44:08 +09004343 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
4344 struct ata_host *host;
4345 struct mv_host_priv *hpriv;
Saeed Bisharac4bc7d72009-12-06 18:26:20 +02004346 int n_ports, port, rc;
Brett Russ20f733e2005-09-01 18:26:17 -04004347
Joe Perches06296a12011-04-15 15:52:00 -07004348 ata_print_version_once(&pdev->dev, DRV_VERSION);
Brett Russ20f733e2005-09-01 18:26:17 -04004349
Tejun Heo4447d352007-04-17 23:44:08 +09004350 /* allocate host */
4351 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
4352
4353 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4354 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4355 if (!host || !hpriv)
4356 return -ENOMEM;
4357 host->private_data = hpriv;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004358 hpriv->n_ports = n_ports;
Saeed Bishara1bfeff02009-12-17 01:05:00 -05004359 hpriv->board_idx = board_idx;
Tejun Heo4447d352007-04-17 23:44:08 +09004360
4361 /* acquire resources */
Tejun Heo24dc5f32007-01-20 16:00:28 +09004362 rc = pcim_enable_device(pdev);
4363 if (rc)
Brett Russ20f733e2005-09-01 18:26:17 -04004364 return rc;
Brett Russ20f733e2005-09-01 18:26:17 -04004365
Tejun Heo0d5ff562007-02-01 15:06:36 +09004366 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
4367 if (rc == -EBUSY)
Tejun Heo24dc5f32007-01-20 16:00:28 +09004368 pcim_pin_device(pdev);
Tejun Heo0d5ff562007-02-01 15:06:36 +09004369 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09004370 return rc;
Tejun Heo4447d352007-04-17 23:44:08 +09004371 host->iomap = pcim_iomap_table(pdev);
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004372 hpriv->base = host->iomap[MV_PRIMARY_BAR];
Brett Russ20f733e2005-09-01 18:26:17 -04004373
Jeff Garzikd88184f2007-02-26 01:26:06 -05004374 rc = pci_go_64(pdev);
4375 if (rc)
4376 return rc;
4377
Mark Lordda2fa9b2008-01-26 18:32:45 -05004378 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4379 if (rc)
4380 return rc;
4381
Saeed Bisharac4bc7d72009-12-06 18:26:20 +02004382 for (port = 0; port < host->n_ports; port++) {
4383 struct ata_port *ap = host->ports[port];
4384 void __iomem *port_mmio = mv_port_base(hpriv->base, port);
4385 unsigned int offset = port_mmio - hpriv->base;
4386
4387 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
4388 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
4389 }
4390
Brett Russ20f733e2005-09-01 18:26:17 -04004391 /* initialize adapter */
Saeed Bishara1bfeff02009-12-17 01:05:00 -05004392 rc = mv_init_host(host);
Tejun Heo24dc5f32007-01-20 16:00:28 +09004393 if (rc)
4394 return rc;
Brett Russ20f733e2005-09-01 18:26:17 -04004395
Mark Lord6d3c30e2009-01-21 10:31:29 -05004396 /* Enable message-switched interrupts, if requested */
4397 if (msi && pci_enable_msi(pdev) == 0)
4398 hpriv->hp_flags |= MV_HP_FLAG_MSI;
Brett Russ20f733e2005-09-01 18:26:17 -04004399
Brett Russ31961942005-09-30 01:36:00 -04004400 mv_dump_pci_cfg(pdev, 0x68);
Tejun Heo4447d352007-04-17 23:44:08 +09004401 mv_print_info(host);
Brett Russ20f733e2005-09-01 18:26:17 -04004402
Tejun Heo4447d352007-04-17 23:44:08 +09004403 pci_set_master(pdev);
Jeff Garzikea8b4db2007-07-17 02:21:50 -04004404 pci_try_set_mwi(pdev);
Tejun Heo4447d352007-04-17 23:44:08 +09004405 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
Jeff Garzikc5d3e452007-07-11 18:30:50 -04004406 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
Brett Russ20f733e2005-09-01 18:26:17 -04004407}
Saeed Bisharab2dec482009-12-06 18:26:22 +02004408
4409#ifdef CONFIG_PM
4410static int mv_pci_device_resume(struct pci_dev *pdev)
4411{
Sergei Shtylyovd8661922011-10-07 19:24:22 +04004412 struct ata_host *host = pci_get_drvdata(pdev);
Saeed Bisharab2dec482009-12-06 18:26:22 +02004413 int rc;
4414
4415 rc = ata_pci_device_do_resume(pdev);
4416 if (rc)
4417 return rc;
4418
4419 /* initialize adapter */
4420 rc = mv_init_host(host);
4421 if (rc)
4422 return rc;
4423
4424 ata_host_resume(host);
4425
4426 return 0;
4427}
4428#endif
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004429#endif
Brett Russ20f733e2005-09-01 18:26:17 -04004430
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004431static int mv_platform_probe(struct platform_device *pdev);
Greg Kroah-Hartman0ec24912012-12-21 13:19:58 -08004432static int mv_platform_remove(struct platform_device *pdev);
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004433
Brett Russ20f733e2005-09-01 18:26:17 -04004434static int __init mv_init(void)
4435{
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004436 int rc = -ENODEV;
4437#ifdef CONFIG_PCI
4438 rc = pci_register_driver(&mv_pci_driver);
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004439 if (rc < 0)
4440 return rc;
4441#endif
4442 rc = platform_driver_register(&mv_platform_driver);
4443
4444#ifdef CONFIG_PCI
4445 if (rc < 0)
4446 pci_unregister_driver(&mv_pci_driver);
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004447#endif
4448 return rc;
Brett Russ20f733e2005-09-01 18:26:17 -04004449}
4450
4451static void __exit mv_exit(void)
4452{
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004453#ifdef CONFIG_PCI
Brett Russ20f733e2005-09-01 18:26:17 -04004454 pci_unregister_driver(&mv_pci_driver);
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004455#endif
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004456 platform_driver_unregister(&mv_platform_driver);
Brett Russ20f733e2005-09-01 18:26:17 -04004457}
4458
4459MODULE_AUTHOR("Brett Russ");
4460MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
4461MODULE_LICENSE("GPL");
4462MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
4463MODULE_VERSION(DRV_VERSION);
Mark Lord17c5aab2008-04-16 14:56:51 -04004464MODULE_ALIAS("platform:" DRV_NAME);
Brett Russ20f733e2005-09-01 18:26:17 -04004465
Brett Russ20f733e2005-09-01 18:26:17 -04004466module_init(mv_init);
4467module_exit(mv_exit);