Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * offload engine driver for the Marvell XOR engine |
| 3 | * Copyright (C) 2007, 2008, Marvell International Ltd. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms and conditions of the GNU General Public License, |
| 7 | * version 2, as published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 12 | * more details. |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 13 | */ |
| 14 | |
| 15 | #include <linux/init.h> |
| 16 | #include <linux/module.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 17 | #include <linux/slab.h> |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 18 | #include <linux/delay.h> |
| 19 | #include <linux/dma-mapping.h> |
| 20 | #include <linux/spinlock.h> |
| 21 | #include <linux/interrupt.h> |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 22 | #include <linux/of_device.h> |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 23 | #include <linux/platform_device.h> |
| 24 | #include <linux/memory.h> |
Andrew Lunn | c510182 | 2012-02-19 13:30:26 +0100 | [diff] [blame] | 25 | #include <linux/clk.h> |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 26 | #include <linux/of.h> |
| 27 | #include <linux/of_irq.h> |
| 28 | #include <linux/irqdomain.h> |
Arnd Bergmann | c02cecb | 2012-08-24 15:21:54 +0200 | [diff] [blame] | 29 | #include <linux/platform_data/dma-mv_xor.h> |
Russell King - ARM Linux | d2ebfb3 | 2012-03-06 22:34:26 +0000 | [diff] [blame] | 30 | |
| 31 | #include "dmaengine.h" |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 32 | #include "mv_xor.h" |
| 33 | |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 34 | enum mv_xor_mode { |
| 35 | XOR_MODE_IN_REG, |
| 36 | XOR_MODE_IN_DESC, |
| 37 | }; |
| 38 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 39 | static void mv_xor_issue_pending(struct dma_chan *chan); |
| 40 | |
| 41 | #define to_mv_xor_chan(chan) \ |
Thomas Petazzoni | 98817b9 | 2012-11-15 14:57:44 +0100 | [diff] [blame] | 42 | container_of(chan, struct mv_xor_chan, dmachan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 43 | |
| 44 | #define to_mv_xor_slot(tx) \ |
| 45 | container_of(tx, struct mv_xor_desc_slot, async_tx) |
| 46 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 47 | #define mv_chan_to_devp(chan) \ |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 48 | ((chan)->dmadev.dev) |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 49 | |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 50 | static void mv_desc_init(struct mv_xor_desc_slot *desc, |
Lior Amsalem | ba87d13 | 2014-08-27 10:52:53 -0300 | [diff] [blame] | 51 | dma_addr_t addr, u32 byte_count, |
| 52 | enum dma_ctrl_flags flags) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 53 | { |
| 54 | struct mv_xor_desc *hw_desc = desc->hw_desc; |
| 55 | |
Ezequiel Garcia | 0e7488e | 2014-08-27 10:52:52 -0300 | [diff] [blame] | 56 | hw_desc->status = XOR_DESC_DMA_OWNED; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 57 | hw_desc->phy_next_desc = 0; |
Lior Amsalem | ba87d13 | 2014-08-27 10:52:53 -0300 | [diff] [blame] | 58 | /* Enable end-of-descriptor interrupts only for DMA_PREP_INTERRUPT */ |
| 59 | hw_desc->desc_command = (flags & DMA_PREP_INTERRUPT) ? |
| 60 | XOR_DESC_EOD_INT_EN : 0; |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 61 | hw_desc->phy_dest_addr = addr; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 62 | hw_desc->byte_count = byte_count; |
| 63 | } |
| 64 | |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 65 | static void mv_desc_set_mode(struct mv_xor_desc_slot *desc) |
| 66 | { |
| 67 | struct mv_xor_desc *hw_desc = desc->hw_desc; |
| 68 | |
| 69 | switch (desc->type) { |
| 70 | case DMA_XOR: |
| 71 | case DMA_INTERRUPT: |
| 72 | hw_desc->desc_command |= XOR_DESC_OPERATION_XOR; |
| 73 | break; |
| 74 | case DMA_MEMCPY: |
| 75 | hw_desc->desc_command |= XOR_DESC_OPERATION_MEMCPY; |
| 76 | break; |
| 77 | default: |
| 78 | BUG(); |
| 79 | return; |
| 80 | } |
| 81 | } |
| 82 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 83 | static void mv_desc_set_next_desc(struct mv_xor_desc_slot *desc, |
| 84 | u32 next_desc_addr) |
| 85 | { |
| 86 | struct mv_xor_desc *hw_desc = desc->hw_desc; |
| 87 | BUG_ON(hw_desc->phy_next_desc); |
| 88 | hw_desc->phy_next_desc = next_desc_addr; |
| 89 | } |
| 90 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 91 | static void mv_desc_set_src_addr(struct mv_xor_desc_slot *desc, |
| 92 | int index, dma_addr_t addr) |
| 93 | { |
| 94 | struct mv_xor_desc *hw_desc = desc->hw_desc; |
Thomas Petazzoni | e03bc65 | 2013-07-29 17:42:14 +0200 | [diff] [blame] | 95 | hw_desc->phy_src_addr[mv_phy_src_idx(index)] = addr; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 96 | if (desc->type == DMA_XOR) |
| 97 | hw_desc->desc_command |= (1 << index); |
| 98 | } |
| 99 | |
| 100 | static u32 mv_chan_get_current_desc(struct mv_xor_chan *chan) |
| 101 | { |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 102 | return readl_relaxed(XOR_CURR_DESC(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 103 | } |
| 104 | |
| 105 | static void mv_chan_set_next_descriptor(struct mv_xor_chan *chan, |
| 106 | u32 next_desc_addr) |
| 107 | { |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 108 | writel_relaxed(next_desc_addr, XOR_NEXT_DESC(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 109 | } |
| 110 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 111 | static void mv_chan_unmask_interrupts(struct mv_xor_chan *chan) |
| 112 | { |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 113 | u32 val = readl_relaxed(XOR_INTR_MASK(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 114 | val |= XOR_INTR_MASK_VALUE << (chan->idx * 16); |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 115 | writel_relaxed(val, XOR_INTR_MASK(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 116 | } |
| 117 | |
| 118 | static u32 mv_chan_get_intr_cause(struct mv_xor_chan *chan) |
| 119 | { |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 120 | u32 intr_cause = readl_relaxed(XOR_INTR_CAUSE(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 121 | intr_cause = (intr_cause >> (chan->idx * 16)) & 0xFFFF; |
| 122 | return intr_cause; |
| 123 | } |
| 124 | |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 125 | static void mv_chan_clear_eoc_cause(struct mv_xor_chan *chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 126 | { |
Lior Amsalem | ba87d13 | 2014-08-27 10:52:53 -0300 | [diff] [blame] | 127 | u32 val; |
| 128 | |
| 129 | val = XOR_INT_END_OF_DESC | XOR_INT_END_OF_CHAIN | XOR_INT_STOPPED; |
| 130 | val = ~(val << (chan->idx * 16)); |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 131 | dev_dbg(mv_chan_to_devp(chan), "%s, val 0x%08x\n", __func__, val); |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 132 | writel_relaxed(val, XOR_INTR_CAUSE(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 133 | } |
| 134 | |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 135 | static void mv_chan_clear_err_status(struct mv_xor_chan *chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 136 | { |
| 137 | u32 val = 0xFFFF0000 >> (chan->idx * 16); |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 138 | writel_relaxed(val, XOR_INTR_CAUSE(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 139 | } |
| 140 | |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 141 | static void mv_chan_set_mode(struct mv_xor_chan *chan, |
| 142 | enum dma_transaction_type type) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 143 | { |
| 144 | u32 op_mode; |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 145 | u32 config = readl_relaxed(XOR_CONFIG(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 146 | |
| 147 | switch (type) { |
| 148 | case DMA_XOR: |
| 149 | op_mode = XOR_OPERATION_MODE_XOR; |
| 150 | break; |
| 151 | case DMA_MEMCPY: |
| 152 | op_mode = XOR_OPERATION_MODE_MEMCPY; |
| 153 | break; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 154 | default: |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 155 | dev_err(mv_chan_to_devp(chan), |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 156 | "error: unsupported operation %d\n", |
Thomas Petazzoni | a3fc74b | 2012-11-15 12:50:27 +0100 | [diff] [blame] | 157 | type); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 158 | BUG(); |
| 159 | return; |
| 160 | } |
| 161 | |
| 162 | config &= ~0x7; |
| 163 | config |= op_mode; |
Thomas Petazzoni | e03bc65 | 2013-07-29 17:42:14 +0200 | [diff] [blame] | 164 | |
Thomas Petazzoni | 0ec9ebc | 2015-07-08 16:28:14 +0200 | [diff] [blame^] | 165 | #if defined(__BIG_ENDIAN) |
| 166 | config |= XOR_DESCRIPTOR_SWAP; |
| 167 | #else |
| 168 | config &= ~XOR_DESCRIPTOR_SWAP; |
| 169 | #endif |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 170 | |
| 171 | writel_relaxed(config, XOR_CONFIG(chan)); |
| 172 | chan->current_type = type; |
| 173 | } |
| 174 | |
| 175 | static void mv_chan_set_mode_to_desc(struct mv_xor_chan *chan) |
| 176 | { |
| 177 | u32 op_mode; |
| 178 | u32 config = readl_relaxed(XOR_CONFIG(chan)); |
| 179 | |
| 180 | op_mode = XOR_OPERATION_MODE_IN_DESC; |
| 181 | |
| 182 | config &= ~0x7; |
| 183 | config |= op_mode; |
| 184 | |
Thomas Petazzoni | e03bc65 | 2013-07-29 17:42:14 +0200 | [diff] [blame] | 185 | #if defined(__BIG_ENDIAN) |
| 186 | config |= XOR_DESCRIPTOR_SWAP; |
| 187 | #else |
| 188 | config &= ~XOR_DESCRIPTOR_SWAP; |
| 189 | #endif |
| 190 | |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 191 | writel_relaxed(config, XOR_CONFIG(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 192 | } |
| 193 | |
| 194 | static void mv_chan_activate(struct mv_xor_chan *chan) |
| 195 | { |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 196 | dev_dbg(mv_chan_to_devp(chan), " activate chan.\n"); |
Ezequiel Garcia | 5a9a55b | 2014-05-21 14:02:35 -0700 | [diff] [blame] | 197 | |
| 198 | /* writel ensures all descriptors are flushed before activation */ |
| 199 | writel(BIT(0), XOR_ACTIVATION(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 200 | } |
| 201 | |
| 202 | static char mv_chan_is_busy(struct mv_xor_chan *chan) |
| 203 | { |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 204 | u32 state = readl_relaxed(XOR_ACTIVATION(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 205 | |
| 206 | state = (state >> 4) & 0x3; |
| 207 | |
| 208 | return (state == 1) ? 1 : 0; |
| 209 | } |
| 210 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 211 | /* |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 212 | * mv_chan_start_new_chain - program the engine to operate on new |
| 213 | * chain headed by sw_desc |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 214 | * Caller must hold &mv_chan->lock while calling this function |
| 215 | */ |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 216 | static void mv_chan_start_new_chain(struct mv_xor_chan *mv_chan, |
| 217 | struct mv_xor_desc_slot *sw_desc) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 218 | { |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 219 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: sw_desc %p\n", |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 220 | __func__, __LINE__, sw_desc); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 221 | |
Bartlomiej Zolnierkiewicz | 48a9db4 | 2013-07-03 15:05:06 -0700 | [diff] [blame] | 222 | /* set the hardware chain */ |
| 223 | mv_chan_set_next_descriptor(mv_chan, sw_desc->async_tx.phys); |
| 224 | |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 225 | mv_chan->pending++; |
Thomas Petazzoni | 98817b9 | 2012-11-15 14:57:44 +0100 | [diff] [blame] | 226 | mv_xor_issue_pending(&mv_chan->dmachan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 227 | } |
| 228 | |
| 229 | static dma_cookie_t |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 230 | mv_desc_run_tx_complete_actions(struct mv_xor_desc_slot *desc, |
| 231 | struct mv_xor_chan *mv_chan, |
| 232 | dma_cookie_t cookie) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 233 | { |
| 234 | BUG_ON(desc->async_tx.cookie < 0); |
| 235 | |
| 236 | if (desc->async_tx.cookie > 0) { |
| 237 | cookie = desc->async_tx.cookie; |
| 238 | |
| 239 | /* call the callback (must not sleep or submit new |
| 240 | * operations to this channel) |
| 241 | */ |
| 242 | if (desc->async_tx.callback) |
| 243 | desc->async_tx.callback( |
| 244 | desc->async_tx.callback_param); |
| 245 | |
Dan Williams | d38a8c6 | 2013-10-18 19:35:23 +0200 | [diff] [blame] | 246 | dma_descriptor_unmap(&desc->async_tx); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 247 | } |
| 248 | |
| 249 | /* run dependent operations */ |
Dan Williams | 07f2211 | 2009-01-05 17:14:31 -0700 | [diff] [blame] | 250 | dma_run_dependencies(&desc->async_tx); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 251 | |
| 252 | return cookie; |
| 253 | } |
| 254 | |
| 255 | static int |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 256 | mv_chan_clean_completed_slots(struct mv_xor_chan *mv_chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 257 | { |
| 258 | struct mv_xor_desc_slot *iter, *_iter; |
| 259 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 260 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 261 | list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots, |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 262 | node) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 263 | |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 264 | if (async_tx_test_ack(&iter->async_tx)) |
| 265 | list_move_tail(&iter->node, &mv_chan->free_slots); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 266 | } |
| 267 | return 0; |
| 268 | } |
| 269 | |
| 270 | static int |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 271 | mv_desc_clean_slot(struct mv_xor_desc_slot *desc, |
| 272 | struct mv_xor_chan *mv_chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 273 | { |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 274 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: desc %p flags %d\n", |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 275 | __func__, __LINE__, desc, desc->async_tx.flags); |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 276 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 277 | /* the client is allowed to attach dependent operations |
| 278 | * until 'ack' is set |
| 279 | */ |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 280 | if (!async_tx_test_ack(&desc->async_tx)) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 281 | /* move this slot to the completed_slots */ |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 282 | list_move_tail(&desc->node, &mv_chan->completed_slots); |
| 283 | else |
| 284 | list_move_tail(&desc->node, &mv_chan->free_slots); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 285 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 286 | return 0; |
| 287 | } |
| 288 | |
Ezequiel Garcia | fbeec99 | 2014-03-07 16:46:47 -0300 | [diff] [blame] | 289 | /* This function must be called with the mv_xor_chan spinlock held */ |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 290 | static void mv_chan_slot_cleanup(struct mv_xor_chan *mv_chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 291 | { |
| 292 | struct mv_xor_desc_slot *iter, *_iter; |
| 293 | dma_cookie_t cookie = 0; |
| 294 | int busy = mv_chan_is_busy(mv_chan); |
| 295 | u32 current_desc = mv_chan_get_current_desc(mv_chan); |
Lior Amsalem | 9136291 | 2015-05-26 15:07:32 +0200 | [diff] [blame] | 296 | int current_cleaned = 0; |
| 297 | struct mv_xor_desc *hw_desc; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 298 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 299 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__); |
| 300 | dev_dbg(mv_chan_to_devp(mv_chan), "current_desc %x\n", current_desc); |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 301 | mv_chan_clean_completed_slots(mv_chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 302 | |
| 303 | /* free completed slots from the chain starting with |
| 304 | * the oldest descriptor |
| 305 | */ |
| 306 | |
| 307 | list_for_each_entry_safe(iter, _iter, &mv_chan->chain, |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 308 | node) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 309 | |
Lior Amsalem | 9136291 | 2015-05-26 15:07:32 +0200 | [diff] [blame] | 310 | /* clean finished descriptors */ |
| 311 | hw_desc = iter->hw_desc; |
| 312 | if (hw_desc->status & XOR_DESC_SUCCESS) { |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 313 | cookie = mv_desc_run_tx_complete_actions(iter, mv_chan, |
| 314 | cookie); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 315 | |
Lior Amsalem | 9136291 | 2015-05-26 15:07:32 +0200 | [diff] [blame] | 316 | /* done processing desc, clean slot */ |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 317 | mv_desc_clean_slot(iter, mv_chan); |
Lior Amsalem | 9136291 | 2015-05-26 15:07:32 +0200 | [diff] [blame] | 318 | |
| 319 | /* break if we did cleaned the current */ |
| 320 | if (iter->async_tx.phys == current_desc) { |
| 321 | current_cleaned = 1; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 322 | break; |
Lior Amsalem | 9136291 | 2015-05-26 15:07:32 +0200 | [diff] [blame] | 323 | } |
| 324 | } else { |
| 325 | if (iter->async_tx.phys == current_desc) { |
| 326 | current_cleaned = 0; |
| 327 | break; |
| 328 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 329 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 330 | } |
| 331 | |
| 332 | if ((busy == 0) && !list_empty(&mv_chan->chain)) { |
Lior Amsalem | 9136291 | 2015-05-26 15:07:32 +0200 | [diff] [blame] | 333 | if (current_cleaned) { |
| 334 | /* |
| 335 | * current descriptor cleaned and removed, run |
| 336 | * from list head |
| 337 | */ |
| 338 | iter = list_entry(mv_chan->chain.next, |
| 339 | struct mv_xor_desc_slot, |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 340 | node); |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 341 | mv_chan_start_new_chain(mv_chan, iter); |
Lior Amsalem | 9136291 | 2015-05-26 15:07:32 +0200 | [diff] [blame] | 342 | } else { |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 343 | if (!list_is_last(&iter->node, &mv_chan->chain)) { |
Lior Amsalem | 9136291 | 2015-05-26 15:07:32 +0200 | [diff] [blame] | 344 | /* |
| 345 | * descriptors are still waiting after |
| 346 | * current, trigger them |
| 347 | */ |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 348 | iter = list_entry(iter->node.next, |
Lior Amsalem | 9136291 | 2015-05-26 15:07:32 +0200 | [diff] [blame] | 349 | struct mv_xor_desc_slot, |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 350 | node); |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 351 | mv_chan_start_new_chain(mv_chan, iter); |
Lior Amsalem | 9136291 | 2015-05-26 15:07:32 +0200 | [diff] [blame] | 352 | } else { |
| 353 | /* |
| 354 | * some descriptors are still waiting |
| 355 | * to be cleaned |
| 356 | */ |
| 357 | tasklet_schedule(&mv_chan->irq_tasklet); |
| 358 | } |
| 359 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 360 | } |
| 361 | |
| 362 | if (cookie > 0) |
Thomas Petazzoni | 98817b9 | 2012-11-15 14:57:44 +0100 | [diff] [blame] | 363 | mv_chan->dmachan.completed_cookie = cookie; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 364 | } |
| 365 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 366 | static void mv_xor_tasklet(unsigned long data) |
| 367 | { |
| 368 | struct mv_xor_chan *chan = (struct mv_xor_chan *) data; |
Ezequiel Garcia | e43147a | 2014-03-07 16:46:46 -0300 | [diff] [blame] | 369 | |
| 370 | spin_lock_bh(&chan->lock); |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 371 | mv_chan_slot_cleanup(chan); |
Ezequiel Garcia | e43147a | 2014-03-07 16:46:46 -0300 | [diff] [blame] | 372 | spin_unlock_bh(&chan->lock); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 373 | } |
| 374 | |
| 375 | static struct mv_xor_desc_slot * |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 376 | mv_chan_alloc_slot(struct mv_xor_chan *mv_chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 377 | { |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 378 | struct mv_xor_desc_slot *iter; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 379 | |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 380 | spin_lock_bh(&mv_chan->lock); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 381 | |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 382 | if (!list_empty(&mv_chan->free_slots)) { |
| 383 | iter = list_first_entry(&mv_chan->free_slots, |
| 384 | struct mv_xor_desc_slot, |
| 385 | node); |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 386 | |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 387 | list_move_tail(&iter->node, &mv_chan->allocated_slots); |
| 388 | |
| 389 | spin_unlock_bh(&mv_chan->lock); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 390 | |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 391 | /* pre-ack descriptor */ |
| 392 | async_tx_ack(&iter->async_tx); |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 393 | iter->async_tx.cookie = -EBUSY; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 394 | |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 395 | return iter; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 396 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 397 | } |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 398 | |
| 399 | spin_unlock_bh(&mv_chan->lock); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 400 | |
| 401 | /* try to free some slots if the allocation fails */ |
| 402 | tasklet_schedule(&mv_chan->irq_tasklet); |
| 403 | |
| 404 | return NULL; |
| 405 | } |
| 406 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 407 | /************************ DMA engine API functions ****************************/ |
| 408 | static dma_cookie_t |
| 409 | mv_xor_tx_submit(struct dma_async_tx_descriptor *tx) |
| 410 | { |
| 411 | struct mv_xor_desc_slot *sw_desc = to_mv_xor_slot(tx); |
| 412 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(tx->chan); |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 413 | struct mv_xor_desc_slot *old_chain_tail; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 414 | dma_cookie_t cookie; |
| 415 | int new_hw_chain = 1; |
| 416 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 417 | dev_dbg(mv_chan_to_devp(mv_chan), |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 418 | "%s sw_desc %p: async_tx %p\n", |
| 419 | __func__, sw_desc, &sw_desc->async_tx); |
| 420 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 421 | spin_lock_bh(&mv_chan->lock); |
Russell King - ARM Linux | 884485e | 2012-03-06 22:34:46 +0000 | [diff] [blame] | 422 | cookie = dma_cookie_assign(tx); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 423 | |
| 424 | if (list_empty(&mv_chan->chain)) |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 425 | list_move_tail(&sw_desc->node, &mv_chan->chain); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 426 | else { |
| 427 | new_hw_chain = 0; |
| 428 | |
| 429 | old_chain_tail = list_entry(mv_chan->chain.prev, |
| 430 | struct mv_xor_desc_slot, |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 431 | node); |
| 432 | list_move_tail(&sw_desc->node, &mv_chan->chain); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 433 | |
Olof Johansson | 31fd8f5 | 2014-02-03 17:13:23 -0800 | [diff] [blame] | 434 | dev_dbg(mv_chan_to_devp(mv_chan), "Append to last desc %pa\n", |
| 435 | &old_chain_tail->async_tx.phys); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 436 | |
| 437 | /* fix up the hardware chain */ |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 438 | mv_desc_set_next_desc(old_chain_tail, sw_desc->async_tx.phys); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 439 | |
| 440 | /* if the channel is not busy */ |
| 441 | if (!mv_chan_is_busy(mv_chan)) { |
| 442 | u32 current_desc = mv_chan_get_current_desc(mv_chan); |
| 443 | /* |
| 444 | * and the curren desc is the end of the chain before |
| 445 | * the append, then we need to start the channel |
| 446 | */ |
| 447 | if (current_desc == old_chain_tail->async_tx.phys) |
| 448 | new_hw_chain = 1; |
| 449 | } |
| 450 | } |
| 451 | |
| 452 | if (new_hw_chain) |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 453 | mv_chan_start_new_chain(mv_chan, sw_desc); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 454 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 455 | spin_unlock_bh(&mv_chan->lock); |
| 456 | |
| 457 | return cookie; |
| 458 | } |
| 459 | |
| 460 | /* returns the number of allocated descriptors */ |
Dan Williams | aa1e6f1 | 2009-01-06 11:38:17 -0700 | [diff] [blame] | 461 | static int mv_xor_alloc_chan_resources(struct dma_chan *chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 462 | { |
Olof Johansson | 31fd8f5 | 2014-02-03 17:13:23 -0800 | [diff] [blame] | 463 | void *virt_desc; |
| 464 | dma_addr_t dma_desc; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 465 | int idx; |
| 466 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); |
| 467 | struct mv_xor_desc_slot *slot = NULL; |
Thomas Petazzoni | b503fa0 | 2012-11-15 15:55:30 +0100 | [diff] [blame] | 468 | int num_descs_in_pool = MV_XOR_POOL_SIZE/MV_XOR_SLOT_SIZE; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 469 | |
| 470 | /* Allocate descriptor slots */ |
| 471 | idx = mv_chan->slots_allocated; |
| 472 | while (idx < num_descs_in_pool) { |
| 473 | slot = kzalloc(sizeof(*slot), GFP_KERNEL); |
| 474 | if (!slot) { |
Ezequiel Garcia | b8291dd | 2014-08-27 10:52:49 -0300 | [diff] [blame] | 475 | dev_info(mv_chan_to_devp(mv_chan), |
| 476 | "channel only initialized %d descriptor slots", |
| 477 | idx); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 478 | break; |
| 479 | } |
Olof Johansson | 31fd8f5 | 2014-02-03 17:13:23 -0800 | [diff] [blame] | 480 | virt_desc = mv_chan->dma_desc_pool_virt; |
| 481 | slot->hw_desc = virt_desc + idx * MV_XOR_SLOT_SIZE; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 482 | |
| 483 | dma_async_tx_descriptor_init(&slot->async_tx, chan); |
| 484 | slot->async_tx.tx_submit = mv_xor_tx_submit; |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 485 | INIT_LIST_HEAD(&slot->node); |
Olof Johansson | 31fd8f5 | 2014-02-03 17:13:23 -0800 | [diff] [blame] | 486 | dma_desc = mv_chan->dma_desc_pool; |
| 487 | slot->async_tx.phys = dma_desc + idx * MV_XOR_SLOT_SIZE; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 488 | slot->idx = idx++; |
| 489 | |
| 490 | spin_lock_bh(&mv_chan->lock); |
| 491 | mv_chan->slots_allocated = idx; |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 492 | list_add_tail(&slot->node, &mv_chan->free_slots); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 493 | spin_unlock_bh(&mv_chan->lock); |
| 494 | } |
| 495 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 496 | dev_dbg(mv_chan_to_devp(mv_chan), |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 497 | "allocated %d descriptor slots\n", |
| 498 | mv_chan->slots_allocated); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 499 | |
| 500 | return mv_chan->slots_allocated ? : -ENOMEM; |
| 501 | } |
| 502 | |
| 503 | static struct dma_async_tx_descriptor * |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 504 | mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, |
| 505 | unsigned int src_cnt, size_t len, unsigned long flags) |
| 506 | { |
| 507 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 508 | struct mv_xor_desc_slot *sw_desc; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 509 | |
| 510 | if (unlikely(len < MV_XOR_MIN_BYTE_COUNT)) |
| 511 | return NULL; |
| 512 | |
Coly Li | 7912d30 | 2011-03-27 01:26:53 +0800 | [diff] [blame] | 513 | BUG_ON(len > MV_XOR_MAX_BYTE_COUNT); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 514 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 515 | dev_dbg(mv_chan_to_devp(mv_chan), |
Olof Johansson | 31fd8f5 | 2014-02-03 17:13:23 -0800 | [diff] [blame] | 516 | "%s src_cnt: %d len: %u dest %pad flags: %ld\n", |
| 517 | __func__, src_cnt, len, &dest, flags); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 518 | |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 519 | sw_desc = mv_chan_alloc_slot(mv_chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 520 | if (sw_desc) { |
| 521 | sw_desc->type = DMA_XOR; |
| 522 | sw_desc->async_tx.flags = flags; |
Lior Amsalem | ba87d13 | 2014-08-27 10:52:53 -0300 | [diff] [blame] | 523 | mv_desc_init(sw_desc, dest, len, flags); |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 524 | if (mv_chan->op_in_desc == XOR_MODE_IN_DESC) |
| 525 | mv_desc_set_mode(sw_desc); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 526 | while (src_cnt--) |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 527 | mv_desc_set_src_addr(sw_desc, src_cnt, src[src_cnt]); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 528 | } |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 529 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 530 | dev_dbg(mv_chan_to_devp(mv_chan), |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 531 | "%s sw_desc %p async_tx %p \n", |
| 532 | __func__, sw_desc, &sw_desc->async_tx); |
| 533 | return sw_desc ? &sw_desc->async_tx : NULL; |
| 534 | } |
| 535 | |
Lior Amsalem | 3e4f52e | 2014-08-27 10:52:50 -0300 | [diff] [blame] | 536 | static struct dma_async_tx_descriptor * |
| 537 | mv_xor_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, |
| 538 | size_t len, unsigned long flags) |
| 539 | { |
| 540 | /* |
| 541 | * A MEMCPY operation is identical to an XOR operation with only |
| 542 | * a single source address. |
| 543 | */ |
| 544 | return mv_xor_prep_dma_xor(chan, dest, &src, 1, len, flags); |
| 545 | } |
| 546 | |
Lior Amsalem | 2284354 | 2014-08-27 10:52:55 -0300 | [diff] [blame] | 547 | static struct dma_async_tx_descriptor * |
| 548 | mv_xor_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags) |
| 549 | { |
| 550 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); |
| 551 | dma_addr_t src, dest; |
| 552 | size_t len; |
| 553 | |
| 554 | src = mv_chan->dummy_src_addr; |
| 555 | dest = mv_chan->dummy_dst_addr; |
| 556 | len = MV_XOR_MIN_BYTE_COUNT; |
| 557 | |
| 558 | /* |
| 559 | * We implement the DMA_INTERRUPT operation as a minimum sized |
| 560 | * XOR operation with a single dummy source address. |
| 561 | */ |
| 562 | return mv_xor_prep_dma_xor(chan, dest, &src, 1, len, flags); |
| 563 | } |
| 564 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 565 | static void mv_xor_free_chan_resources(struct dma_chan *chan) |
| 566 | { |
| 567 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); |
| 568 | struct mv_xor_desc_slot *iter, *_iter; |
| 569 | int in_use_descs = 0; |
| 570 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 571 | spin_lock_bh(&mv_chan->lock); |
Ezequiel Garcia | e43147a | 2014-03-07 16:46:46 -0300 | [diff] [blame] | 572 | |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 573 | mv_chan_slot_cleanup(mv_chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 574 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 575 | list_for_each_entry_safe(iter, _iter, &mv_chan->chain, |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 576 | node) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 577 | in_use_descs++; |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 578 | list_move_tail(&iter->node, &mv_chan->free_slots); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 579 | } |
| 580 | list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots, |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 581 | node) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 582 | in_use_descs++; |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 583 | list_move_tail(&iter->node, &mv_chan->free_slots); |
| 584 | } |
| 585 | list_for_each_entry_safe(iter, _iter, &mv_chan->allocated_slots, |
| 586 | node) { |
| 587 | in_use_descs++; |
| 588 | list_move_tail(&iter->node, &mv_chan->free_slots); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 589 | } |
| 590 | list_for_each_entry_safe_reverse( |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 591 | iter, _iter, &mv_chan->free_slots, node) { |
| 592 | list_del(&iter->node); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 593 | kfree(iter); |
| 594 | mv_chan->slots_allocated--; |
| 595 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 596 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 597 | dev_dbg(mv_chan_to_devp(mv_chan), "%s slots_allocated %d\n", |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 598 | __func__, mv_chan->slots_allocated); |
| 599 | spin_unlock_bh(&mv_chan->lock); |
| 600 | |
| 601 | if (in_use_descs) |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 602 | dev_err(mv_chan_to_devp(mv_chan), |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 603 | "freeing %d in use descriptors!\n", in_use_descs); |
| 604 | } |
| 605 | |
| 606 | /** |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 607 | * mv_xor_status - poll the status of an XOR transaction |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 608 | * @chan: XOR channel handle |
| 609 | * @cookie: XOR transaction identifier |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 610 | * @txstate: XOR transactions state holder (or NULL) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 611 | */ |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 612 | static enum dma_status mv_xor_status(struct dma_chan *chan, |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 613 | dma_cookie_t cookie, |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 614 | struct dma_tx_state *txstate) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 615 | { |
| 616 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 617 | enum dma_status ret; |
| 618 | |
Russell King - ARM Linux | 96a2af4 | 2012-03-06 22:35:27 +0000 | [diff] [blame] | 619 | ret = dma_cookie_status(chan, cookie, txstate); |
Ezequiel Garcia | 890766d | 2014-03-07 16:46:45 -0300 | [diff] [blame] | 620 | if (ret == DMA_COMPLETE) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 621 | return ret; |
Ezequiel Garcia | e43147a | 2014-03-07 16:46:46 -0300 | [diff] [blame] | 622 | |
| 623 | spin_lock_bh(&mv_chan->lock); |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 624 | mv_chan_slot_cleanup(mv_chan); |
Ezequiel Garcia | e43147a | 2014-03-07 16:46:46 -0300 | [diff] [blame] | 625 | spin_unlock_bh(&mv_chan->lock); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 626 | |
Russell King - ARM Linux | 96a2af4 | 2012-03-06 22:35:27 +0000 | [diff] [blame] | 627 | return dma_cookie_status(chan, cookie, txstate); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 628 | } |
| 629 | |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 630 | static void mv_chan_dump_regs(struct mv_xor_chan *chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 631 | { |
| 632 | u32 val; |
| 633 | |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 634 | val = readl_relaxed(XOR_CONFIG(chan)); |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 635 | dev_err(mv_chan_to_devp(chan), "config 0x%08x\n", val); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 636 | |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 637 | val = readl_relaxed(XOR_ACTIVATION(chan)); |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 638 | dev_err(mv_chan_to_devp(chan), "activation 0x%08x\n", val); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 639 | |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 640 | val = readl_relaxed(XOR_INTR_CAUSE(chan)); |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 641 | dev_err(mv_chan_to_devp(chan), "intr cause 0x%08x\n", val); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 642 | |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 643 | val = readl_relaxed(XOR_INTR_MASK(chan)); |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 644 | dev_err(mv_chan_to_devp(chan), "intr mask 0x%08x\n", val); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 645 | |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 646 | val = readl_relaxed(XOR_ERROR_CAUSE(chan)); |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 647 | dev_err(mv_chan_to_devp(chan), "error cause 0x%08x\n", val); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 648 | |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 649 | val = readl_relaxed(XOR_ERROR_ADDR(chan)); |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 650 | dev_err(mv_chan_to_devp(chan), "error addr 0x%08x\n", val); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 651 | } |
| 652 | |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 653 | static void mv_chan_err_interrupt_handler(struct mv_xor_chan *chan, |
| 654 | u32 intr_cause) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 655 | { |
Ezequiel Garcia | 0e7488e | 2014-08-27 10:52:52 -0300 | [diff] [blame] | 656 | if (intr_cause & XOR_INT_ERR_DECODE) { |
| 657 | dev_dbg(mv_chan_to_devp(chan), "ignoring address decode error\n"); |
| 658 | return; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 659 | } |
| 660 | |
Ezequiel Garcia | 0e7488e | 2014-08-27 10:52:52 -0300 | [diff] [blame] | 661 | dev_err(mv_chan_to_devp(chan), "error on chan %d. intr cause 0x%08x\n", |
Thomas Petazzoni | a3fc74b | 2012-11-15 12:50:27 +0100 | [diff] [blame] | 662 | chan->idx, intr_cause); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 663 | |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 664 | mv_chan_dump_regs(chan); |
Ezequiel Garcia | 0e7488e | 2014-08-27 10:52:52 -0300 | [diff] [blame] | 665 | WARN_ON(1); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 666 | } |
| 667 | |
| 668 | static irqreturn_t mv_xor_interrupt_handler(int irq, void *data) |
| 669 | { |
| 670 | struct mv_xor_chan *chan = data; |
| 671 | u32 intr_cause = mv_chan_get_intr_cause(chan); |
| 672 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 673 | dev_dbg(mv_chan_to_devp(chan), "intr cause %x\n", intr_cause); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 674 | |
Ezequiel Garcia | 0e7488e | 2014-08-27 10:52:52 -0300 | [diff] [blame] | 675 | if (intr_cause & XOR_INTR_ERRORS) |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 676 | mv_chan_err_interrupt_handler(chan, intr_cause); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 677 | |
| 678 | tasklet_schedule(&chan->irq_tasklet); |
| 679 | |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 680 | mv_chan_clear_eoc_cause(chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 681 | |
| 682 | return IRQ_HANDLED; |
| 683 | } |
| 684 | |
| 685 | static void mv_xor_issue_pending(struct dma_chan *chan) |
| 686 | { |
| 687 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); |
| 688 | |
| 689 | if (mv_chan->pending >= MV_XOR_THRESHOLD) { |
| 690 | mv_chan->pending = 0; |
| 691 | mv_chan_activate(mv_chan); |
| 692 | } |
| 693 | } |
| 694 | |
| 695 | /* |
| 696 | * Perform a transaction to verify the HW works. |
| 697 | */ |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 698 | |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 699 | static int mv_chan_memcpy_self_test(struct mv_xor_chan *mv_chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 700 | { |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 701 | int i, ret; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 702 | void *src, *dest; |
| 703 | dma_addr_t src_dma, dest_dma; |
| 704 | struct dma_chan *dma_chan; |
| 705 | dma_cookie_t cookie; |
| 706 | struct dma_async_tx_descriptor *tx; |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 707 | struct dmaengine_unmap_data *unmap; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 708 | int err = 0; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 709 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 710 | src = kmalloc(sizeof(u8) * PAGE_SIZE, GFP_KERNEL); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 711 | if (!src) |
| 712 | return -ENOMEM; |
| 713 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 714 | dest = kzalloc(sizeof(u8) * PAGE_SIZE, GFP_KERNEL); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 715 | if (!dest) { |
| 716 | kfree(src); |
| 717 | return -ENOMEM; |
| 718 | } |
| 719 | |
| 720 | /* Fill in src buffer */ |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 721 | for (i = 0; i < PAGE_SIZE; i++) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 722 | ((u8 *) src)[i] = (u8)i; |
| 723 | |
Thomas Petazzoni | 275cc0c | 2012-11-15 15:09:42 +0100 | [diff] [blame] | 724 | dma_chan = &mv_chan->dmachan; |
Dan Williams | aa1e6f1 | 2009-01-06 11:38:17 -0700 | [diff] [blame] | 725 | if (mv_xor_alloc_chan_resources(dma_chan) < 1) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 726 | err = -ENODEV; |
| 727 | goto out; |
| 728 | } |
| 729 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 730 | unmap = dmaengine_get_unmap_data(dma_chan->device->dev, 2, GFP_KERNEL); |
| 731 | if (!unmap) { |
| 732 | err = -ENOMEM; |
| 733 | goto free_resources; |
| 734 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 735 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 736 | src_dma = dma_map_page(dma_chan->device->dev, virt_to_page(src), 0, |
| 737 | PAGE_SIZE, DMA_TO_DEVICE); |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 738 | unmap->addr[0] = src_dma; |
| 739 | |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 740 | ret = dma_mapping_error(dma_chan->device->dev, src_dma); |
| 741 | if (ret) { |
| 742 | err = -ENOMEM; |
| 743 | goto free_resources; |
| 744 | } |
| 745 | unmap->to_cnt = 1; |
| 746 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 747 | dest_dma = dma_map_page(dma_chan->device->dev, virt_to_page(dest), 0, |
| 748 | PAGE_SIZE, DMA_FROM_DEVICE); |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 749 | unmap->addr[1] = dest_dma; |
| 750 | |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 751 | ret = dma_mapping_error(dma_chan->device->dev, dest_dma); |
| 752 | if (ret) { |
| 753 | err = -ENOMEM; |
| 754 | goto free_resources; |
| 755 | } |
| 756 | unmap->from_cnt = 1; |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 757 | unmap->len = PAGE_SIZE; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 758 | |
| 759 | tx = mv_xor_prep_dma_memcpy(dma_chan, dest_dma, src_dma, |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 760 | PAGE_SIZE, 0); |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 761 | if (!tx) { |
| 762 | dev_err(dma_chan->device->dev, |
| 763 | "Self-test cannot prepare operation, disabling\n"); |
| 764 | err = -ENODEV; |
| 765 | goto free_resources; |
| 766 | } |
| 767 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 768 | cookie = mv_xor_tx_submit(tx); |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 769 | if (dma_submit_error(cookie)) { |
| 770 | dev_err(dma_chan->device->dev, |
| 771 | "Self-test submit error, disabling\n"); |
| 772 | err = -ENODEV; |
| 773 | goto free_resources; |
| 774 | } |
| 775 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 776 | mv_xor_issue_pending(dma_chan); |
| 777 | async_tx_ack(tx); |
| 778 | msleep(1); |
| 779 | |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 780 | if (mv_xor_status(dma_chan, cookie, NULL) != |
Vinod Koul | b3efb8f | 2013-10-16 20:51:04 +0530 | [diff] [blame] | 781 | DMA_COMPLETE) { |
Thomas Petazzoni | a3fc74b | 2012-11-15 12:50:27 +0100 | [diff] [blame] | 782 | dev_err(dma_chan->device->dev, |
| 783 | "Self-test copy timed out, disabling\n"); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 784 | err = -ENODEV; |
| 785 | goto free_resources; |
| 786 | } |
| 787 | |
Thomas Petazzoni | c35064c | 2012-11-15 13:01:59 +0100 | [diff] [blame] | 788 | dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma, |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 789 | PAGE_SIZE, DMA_FROM_DEVICE); |
| 790 | if (memcmp(src, dest, PAGE_SIZE)) { |
Thomas Petazzoni | a3fc74b | 2012-11-15 12:50:27 +0100 | [diff] [blame] | 791 | dev_err(dma_chan->device->dev, |
| 792 | "Self-test copy failed compare, disabling\n"); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 793 | err = -ENODEV; |
| 794 | goto free_resources; |
| 795 | } |
| 796 | |
| 797 | free_resources: |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 798 | dmaengine_unmap_put(unmap); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 799 | mv_xor_free_chan_resources(dma_chan); |
| 800 | out: |
| 801 | kfree(src); |
| 802 | kfree(dest); |
| 803 | return err; |
| 804 | } |
| 805 | |
| 806 | #define MV_XOR_NUM_SRC_TEST 4 /* must be <= 15 */ |
Bill Pemberton | 463a1f8 | 2012-11-19 13:22:55 -0500 | [diff] [blame] | 807 | static int |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 808 | mv_chan_xor_self_test(struct mv_xor_chan *mv_chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 809 | { |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 810 | int i, src_idx, ret; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 811 | struct page *dest; |
| 812 | struct page *xor_srcs[MV_XOR_NUM_SRC_TEST]; |
| 813 | dma_addr_t dma_srcs[MV_XOR_NUM_SRC_TEST]; |
| 814 | dma_addr_t dest_dma; |
| 815 | struct dma_async_tx_descriptor *tx; |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 816 | struct dmaengine_unmap_data *unmap; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 817 | struct dma_chan *dma_chan; |
| 818 | dma_cookie_t cookie; |
| 819 | u8 cmp_byte = 0; |
| 820 | u32 cmp_word; |
| 821 | int err = 0; |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 822 | int src_count = MV_XOR_NUM_SRC_TEST; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 823 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 824 | for (src_idx = 0; src_idx < src_count; src_idx++) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 825 | xor_srcs[src_idx] = alloc_page(GFP_KERNEL); |
Roel Kluin | a09b09a | 2009-02-25 13:56:21 +0100 | [diff] [blame] | 826 | if (!xor_srcs[src_idx]) { |
| 827 | while (src_idx--) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 828 | __free_page(xor_srcs[src_idx]); |
Roel Kluin | a09b09a | 2009-02-25 13:56:21 +0100 | [diff] [blame] | 829 | return -ENOMEM; |
| 830 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 831 | } |
| 832 | |
| 833 | dest = alloc_page(GFP_KERNEL); |
Roel Kluin | a09b09a | 2009-02-25 13:56:21 +0100 | [diff] [blame] | 834 | if (!dest) { |
| 835 | while (src_idx--) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 836 | __free_page(xor_srcs[src_idx]); |
Roel Kluin | a09b09a | 2009-02-25 13:56:21 +0100 | [diff] [blame] | 837 | return -ENOMEM; |
| 838 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 839 | |
| 840 | /* Fill in src buffers */ |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 841 | for (src_idx = 0; src_idx < src_count; src_idx++) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 842 | u8 *ptr = page_address(xor_srcs[src_idx]); |
| 843 | for (i = 0; i < PAGE_SIZE; i++) |
| 844 | ptr[i] = (1 << src_idx); |
| 845 | } |
| 846 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 847 | for (src_idx = 0; src_idx < src_count; src_idx++) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 848 | cmp_byte ^= (u8) (1 << src_idx); |
| 849 | |
| 850 | cmp_word = (cmp_byte << 24) | (cmp_byte << 16) | |
| 851 | (cmp_byte << 8) | cmp_byte; |
| 852 | |
| 853 | memset(page_address(dest), 0, PAGE_SIZE); |
| 854 | |
Thomas Petazzoni | 275cc0c | 2012-11-15 15:09:42 +0100 | [diff] [blame] | 855 | dma_chan = &mv_chan->dmachan; |
Dan Williams | aa1e6f1 | 2009-01-06 11:38:17 -0700 | [diff] [blame] | 856 | if (mv_xor_alloc_chan_resources(dma_chan) < 1) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 857 | err = -ENODEV; |
| 858 | goto out; |
| 859 | } |
| 860 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 861 | unmap = dmaengine_get_unmap_data(dma_chan->device->dev, src_count + 1, |
| 862 | GFP_KERNEL); |
| 863 | if (!unmap) { |
| 864 | err = -ENOMEM; |
| 865 | goto free_resources; |
| 866 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 867 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 868 | /* test xor */ |
| 869 | for (i = 0; i < src_count; i++) { |
| 870 | unmap->addr[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i], |
| 871 | 0, PAGE_SIZE, DMA_TO_DEVICE); |
| 872 | dma_srcs[i] = unmap->addr[i]; |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 873 | ret = dma_mapping_error(dma_chan->device->dev, unmap->addr[i]); |
| 874 | if (ret) { |
| 875 | err = -ENOMEM; |
| 876 | goto free_resources; |
| 877 | } |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 878 | unmap->to_cnt++; |
| 879 | } |
| 880 | |
| 881 | unmap->addr[src_count] = dma_map_page(dma_chan->device->dev, dest, 0, PAGE_SIZE, |
| 882 | DMA_FROM_DEVICE); |
| 883 | dest_dma = unmap->addr[src_count]; |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 884 | ret = dma_mapping_error(dma_chan->device->dev, unmap->addr[src_count]); |
| 885 | if (ret) { |
| 886 | err = -ENOMEM; |
| 887 | goto free_resources; |
| 888 | } |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 889 | unmap->from_cnt = 1; |
| 890 | unmap->len = PAGE_SIZE; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 891 | |
| 892 | tx = mv_xor_prep_dma_xor(dma_chan, dest_dma, dma_srcs, |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 893 | src_count, PAGE_SIZE, 0); |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 894 | if (!tx) { |
| 895 | dev_err(dma_chan->device->dev, |
| 896 | "Self-test cannot prepare operation, disabling\n"); |
| 897 | err = -ENODEV; |
| 898 | goto free_resources; |
| 899 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 900 | |
| 901 | cookie = mv_xor_tx_submit(tx); |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 902 | if (dma_submit_error(cookie)) { |
| 903 | dev_err(dma_chan->device->dev, |
| 904 | "Self-test submit error, disabling\n"); |
| 905 | err = -ENODEV; |
| 906 | goto free_resources; |
| 907 | } |
| 908 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 909 | mv_xor_issue_pending(dma_chan); |
| 910 | async_tx_ack(tx); |
| 911 | msleep(8); |
| 912 | |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 913 | if (mv_xor_status(dma_chan, cookie, NULL) != |
Vinod Koul | b3efb8f | 2013-10-16 20:51:04 +0530 | [diff] [blame] | 914 | DMA_COMPLETE) { |
Thomas Petazzoni | a3fc74b | 2012-11-15 12:50:27 +0100 | [diff] [blame] | 915 | dev_err(dma_chan->device->dev, |
| 916 | "Self-test xor timed out, disabling\n"); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 917 | err = -ENODEV; |
| 918 | goto free_resources; |
| 919 | } |
| 920 | |
Thomas Petazzoni | c35064c | 2012-11-15 13:01:59 +0100 | [diff] [blame] | 921 | dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma, |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 922 | PAGE_SIZE, DMA_FROM_DEVICE); |
| 923 | for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) { |
| 924 | u32 *ptr = page_address(dest); |
| 925 | if (ptr[i] != cmp_word) { |
Thomas Petazzoni | a3fc74b | 2012-11-15 12:50:27 +0100 | [diff] [blame] | 926 | dev_err(dma_chan->device->dev, |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 927 | "Self-test xor failed compare, disabling. index %d, data %x, expected %x\n", |
| 928 | i, ptr[i], cmp_word); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 929 | err = -ENODEV; |
| 930 | goto free_resources; |
| 931 | } |
| 932 | } |
| 933 | |
| 934 | free_resources: |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 935 | dmaengine_unmap_put(unmap); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 936 | mv_xor_free_chan_resources(dma_chan); |
| 937 | out: |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 938 | src_idx = src_count; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 939 | while (src_idx--) |
| 940 | __free_page(xor_srcs[src_idx]); |
| 941 | __free_page(dest); |
| 942 | return err; |
| 943 | } |
| 944 | |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 945 | static int mv_xor_channel_remove(struct mv_xor_chan *mv_chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 946 | { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 947 | struct dma_chan *chan, *_chan; |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 948 | struct device *dev = mv_chan->dmadev.dev; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 949 | |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 950 | dma_async_device_unregister(&mv_chan->dmadev); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 951 | |
Thomas Petazzoni | b503fa0 | 2012-11-15 15:55:30 +0100 | [diff] [blame] | 952 | dma_free_coherent(dev, MV_XOR_POOL_SIZE, |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 953 | mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool); |
Lior Amsalem | 2284354 | 2014-08-27 10:52:55 -0300 | [diff] [blame] | 954 | dma_unmap_single(dev, mv_chan->dummy_src_addr, |
| 955 | MV_XOR_MIN_BYTE_COUNT, DMA_FROM_DEVICE); |
| 956 | dma_unmap_single(dev, mv_chan->dummy_dst_addr, |
| 957 | MV_XOR_MIN_BYTE_COUNT, DMA_TO_DEVICE); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 958 | |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 959 | list_for_each_entry_safe(chan, _chan, &mv_chan->dmadev.channels, |
Thomas Petazzoni | a6b4a9d | 2012-10-29 16:45:46 +0100 | [diff] [blame] | 960 | device_node) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 961 | list_del(&chan->device_node); |
| 962 | } |
| 963 | |
Thomas Petazzoni | 88eb92c | 2012-11-15 16:11:18 +0100 | [diff] [blame] | 964 | free_irq(mv_chan->irq, mv_chan); |
| 965 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 966 | return 0; |
| 967 | } |
| 968 | |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 969 | static struct mv_xor_chan * |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 970 | mv_xor_channel_add(struct mv_xor_device *xordev, |
Thomas Petazzoni | a6b4a9d | 2012-10-29 16:45:46 +0100 | [diff] [blame] | 971 | struct platform_device *pdev, |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 972 | int idx, dma_cap_mask_t cap_mask, int irq, int op_in_desc) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 973 | { |
| 974 | int ret = 0; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 975 | struct mv_xor_chan *mv_chan; |
| 976 | struct dma_device *dma_dev; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 977 | |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 978 | mv_chan = devm_kzalloc(&pdev->dev, sizeof(*mv_chan), GFP_KERNEL); |
Sachin Kamat | a577659 | 2013-09-02 13:54:20 +0530 | [diff] [blame] | 979 | if (!mv_chan) |
| 980 | return ERR_PTR(-ENOMEM); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 981 | |
Thomas Petazzoni | 9aedbdb | 2012-11-15 15:36:37 +0100 | [diff] [blame] | 982 | mv_chan->idx = idx; |
Thomas Petazzoni | 88eb92c | 2012-11-15 16:11:18 +0100 | [diff] [blame] | 983 | mv_chan->irq = irq; |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 984 | mv_chan->op_in_desc = op_in_desc; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 985 | |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 986 | dma_dev = &mv_chan->dmadev; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 987 | |
Lior Amsalem | 2284354 | 2014-08-27 10:52:55 -0300 | [diff] [blame] | 988 | /* |
| 989 | * These source and destination dummy buffers are used to implement |
| 990 | * a DMA_INTERRUPT operation as a minimum-sized XOR operation. |
| 991 | * Hence, we only need to map the buffers at initialization-time. |
| 992 | */ |
| 993 | mv_chan->dummy_src_addr = dma_map_single(dma_dev->dev, |
| 994 | mv_chan->dummy_src, MV_XOR_MIN_BYTE_COUNT, DMA_FROM_DEVICE); |
| 995 | mv_chan->dummy_dst_addr = dma_map_single(dma_dev->dev, |
| 996 | mv_chan->dummy_dst, MV_XOR_MIN_BYTE_COUNT, DMA_TO_DEVICE); |
| 997 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 998 | /* allocate coherent memory for hardware descriptors |
| 999 | * note: writecombine gives slightly better performance, but |
| 1000 | * requires that we explicitly flush the writes |
| 1001 | */ |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 1002 | mv_chan->dma_desc_pool_virt = |
Thomas Petazzoni | b503fa0 | 2012-11-15 15:55:30 +0100 | [diff] [blame] | 1003 | dma_alloc_writecombine(&pdev->dev, MV_XOR_POOL_SIZE, |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 1004 | &mv_chan->dma_desc_pool, GFP_KERNEL); |
| 1005 | if (!mv_chan->dma_desc_pool_virt) |
Thomas Petazzoni | a6b4a9d | 2012-10-29 16:45:46 +0100 | [diff] [blame] | 1006 | return ERR_PTR(-ENOMEM); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1007 | |
| 1008 | /* discover transaction capabilites from the platform data */ |
Thomas Petazzoni | a6b4a9d | 2012-10-29 16:45:46 +0100 | [diff] [blame] | 1009 | dma_dev->cap_mask = cap_mask; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1010 | |
| 1011 | INIT_LIST_HEAD(&dma_dev->channels); |
| 1012 | |
| 1013 | /* set base routines */ |
| 1014 | dma_dev->device_alloc_chan_resources = mv_xor_alloc_chan_resources; |
| 1015 | dma_dev->device_free_chan_resources = mv_xor_free_chan_resources; |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 1016 | dma_dev->device_tx_status = mv_xor_status; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1017 | dma_dev->device_issue_pending = mv_xor_issue_pending; |
| 1018 | dma_dev->dev = &pdev->dev; |
| 1019 | |
| 1020 | /* set prep routines based on capability */ |
Lior Amsalem | 2284354 | 2014-08-27 10:52:55 -0300 | [diff] [blame] | 1021 | if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask)) |
| 1022 | dma_dev->device_prep_dma_interrupt = mv_xor_prep_dma_interrupt; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1023 | if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) |
| 1024 | dma_dev->device_prep_dma_memcpy = mv_xor_prep_dma_memcpy; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1025 | if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { |
Joe Perches | c019894 | 2009-06-28 09:26:21 -0700 | [diff] [blame] | 1026 | dma_dev->max_xor = 8; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1027 | dma_dev->device_prep_dma_xor = mv_xor_prep_dma_xor; |
| 1028 | } |
| 1029 | |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1030 | mv_chan->mmr_base = xordev->xor_base; |
Ezequiel Garcia | 82a1402 | 2013-10-30 12:01:43 -0300 | [diff] [blame] | 1031 | mv_chan->mmr_high_base = xordev->xor_high_base; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1032 | tasklet_init(&mv_chan->irq_tasklet, mv_xor_tasklet, (unsigned long) |
| 1033 | mv_chan); |
| 1034 | |
| 1035 | /* clear errors before enabling interrupts */ |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 1036 | mv_chan_clear_err_status(mv_chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1037 | |
Thomas Petazzoni | 2d0a074 | 2012-11-22 18:19:09 +0100 | [diff] [blame] | 1038 | ret = request_irq(mv_chan->irq, mv_xor_interrupt_handler, |
| 1039 | 0, dev_name(&pdev->dev), mv_chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1040 | if (ret) |
| 1041 | goto err_free_dma; |
| 1042 | |
| 1043 | mv_chan_unmask_interrupts(mv_chan); |
| 1044 | |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 1045 | if (mv_chan->op_in_desc == XOR_MODE_IN_DESC) |
| 1046 | mv_chan_set_mode_to_desc(mv_chan); |
| 1047 | else |
| 1048 | mv_chan_set_mode(mv_chan, DMA_XOR); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1049 | |
| 1050 | spin_lock_init(&mv_chan->lock); |
| 1051 | INIT_LIST_HEAD(&mv_chan->chain); |
| 1052 | INIT_LIST_HEAD(&mv_chan->completed_slots); |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 1053 | INIT_LIST_HEAD(&mv_chan->free_slots); |
| 1054 | INIT_LIST_HEAD(&mv_chan->allocated_slots); |
Thomas Petazzoni | 98817b9 | 2012-11-15 14:57:44 +0100 | [diff] [blame] | 1055 | mv_chan->dmachan.device = dma_dev; |
| 1056 | dma_cookie_init(&mv_chan->dmachan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1057 | |
Thomas Petazzoni | 98817b9 | 2012-11-15 14:57:44 +0100 | [diff] [blame] | 1058 | list_add_tail(&mv_chan->dmachan.device_node, &dma_dev->channels); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1059 | |
| 1060 | if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) { |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 1061 | ret = mv_chan_memcpy_self_test(mv_chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1062 | dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret); |
| 1063 | if (ret) |
Thomas Petazzoni | 2d0a074 | 2012-11-22 18:19:09 +0100 | [diff] [blame] | 1064 | goto err_free_irq; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1065 | } |
| 1066 | |
| 1067 | if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 1068 | ret = mv_chan_xor_self_test(mv_chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1069 | dev_dbg(&pdev->dev, "xor self test returned %d\n", ret); |
| 1070 | if (ret) |
Thomas Petazzoni | 2d0a074 | 2012-11-22 18:19:09 +0100 | [diff] [blame] | 1071 | goto err_free_irq; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1072 | } |
| 1073 | |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 1074 | dev_info(&pdev->dev, "Marvell XOR (%s): ( %s%s%s)\n", |
| 1075 | mv_chan->op_in_desc ? "Descriptor Mode" : "Registers Mode", |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 1076 | dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "", |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 1077 | dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "", |
| 1078 | dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : ""); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1079 | |
| 1080 | dma_async_device_register(dma_dev); |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 1081 | return mv_chan; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1082 | |
Thomas Petazzoni | 2d0a074 | 2012-11-22 18:19:09 +0100 | [diff] [blame] | 1083 | err_free_irq: |
| 1084 | free_irq(mv_chan->irq, mv_chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1085 | err_free_dma: |
Thomas Petazzoni | b503fa0 | 2012-11-15 15:55:30 +0100 | [diff] [blame] | 1086 | dma_free_coherent(&pdev->dev, MV_XOR_POOL_SIZE, |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 1087 | mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool); |
Thomas Petazzoni | a6b4a9d | 2012-10-29 16:45:46 +0100 | [diff] [blame] | 1088 | return ERR_PTR(ret); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1089 | } |
| 1090 | |
| 1091 | static void |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1092 | mv_xor_conf_mbus_windows(struct mv_xor_device *xordev, |
Andrew Lunn | 63a9332 | 2011-12-07 21:48:07 +0100 | [diff] [blame] | 1093 | const struct mbus_dram_target_info *dram) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1094 | { |
Ezequiel Garcia | 82a1402 | 2013-10-30 12:01:43 -0300 | [diff] [blame] | 1095 | void __iomem *base = xordev->xor_high_base; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1096 | u32 win_enable = 0; |
| 1097 | int i; |
| 1098 | |
| 1099 | for (i = 0; i < 8; i++) { |
| 1100 | writel(0, base + WINDOW_BASE(i)); |
| 1101 | writel(0, base + WINDOW_SIZE(i)); |
| 1102 | if (i < 4) |
| 1103 | writel(0, base + WINDOW_REMAP_HIGH(i)); |
| 1104 | } |
| 1105 | |
| 1106 | for (i = 0; i < dram->num_cs; i++) { |
Andrew Lunn | 63a9332 | 2011-12-07 21:48:07 +0100 | [diff] [blame] | 1107 | const struct mbus_dram_window *cs = dram->cs + i; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1108 | |
| 1109 | writel((cs->base & 0xffff0000) | |
| 1110 | (cs->mbus_attr << 8) | |
| 1111 | dram->mbus_dram_target_id, base + WINDOW_BASE(i)); |
| 1112 | writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); |
| 1113 | |
| 1114 | win_enable |= (1 << i); |
| 1115 | win_enable |= 3 << (16 + (2 * i)); |
| 1116 | } |
| 1117 | |
| 1118 | writel(win_enable, base + WINDOW_BAR_ENABLE(0)); |
| 1119 | writel(win_enable, base + WINDOW_BAR_ENABLE(1)); |
Thomas Petazzoni | c4b4b73 | 2012-11-22 18:16:37 +0100 | [diff] [blame] | 1120 | writel(0, base + WINDOW_OVERRIDE_CTRL(0)); |
| 1121 | writel(0, base + WINDOW_OVERRIDE_CTRL(1)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1122 | } |
| 1123 | |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 1124 | static const struct of_device_id mv_xor_dt_ids[] = { |
| 1125 | { .compatible = "marvell,orion-xor", .data = (void *)XOR_MODE_IN_REG }, |
| 1126 | { .compatible = "marvell,armada-380-xor", .data = (void *)XOR_MODE_IN_DESC }, |
| 1127 | {}, |
| 1128 | }; |
| 1129 | MODULE_DEVICE_TABLE(of, mv_xor_dt_ids); |
| 1130 | |
Linus Torvalds | c271433 | 2012-12-14 14:54:26 -0800 | [diff] [blame] | 1131 | static int mv_xor_probe(struct platform_device *pdev) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1132 | { |
Andrew Lunn | 63a9332 | 2011-12-07 21:48:07 +0100 | [diff] [blame] | 1133 | const struct mbus_dram_target_info *dram; |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1134 | struct mv_xor_device *xordev; |
Jingoo Han | d4adcc0 | 2013-07-30 17:09:11 +0900 | [diff] [blame] | 1135 | struct mv_xor_platform_data *pdata = dev_get_platdata(&pdev->dev); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1136 | struct resource *res; |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1137 | int i, ret; |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 1138 | int op_in_desc; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1139 | |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 1140 | dev_notice(&pdev->dev, "Marvell shared XOR driver\n"); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1141 | |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1142 | xordev = devm_kzalloc(&pdev->dev, sizeof(*xordev), GFP_KERNEL); |
| 1143 | if (!xordev) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1144 | return -ENOMEM; |
| 1145 | |
| 1146 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1147 | if (!res) |
| 1148 | return -ENODEV; |
| 1149 | |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1150 | xordev->xor_base = devm_ioremap(&pdev->dev, res->start, |
| 1151 | resource_size(res)); |
| 1152 | if (!xordev->xor_base) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1153 | return -EBUSY; |
| 1154 | |
| 1155 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
| 1156 | if (!res) |
| 1157 | return -ENODEV; |
| 1158 | |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1159 | xordev->xor_high_base = devm_ioremap(&pdev->dev, res->start, |
| 1160 | resource_size(res)); |
| 1161 | if (!xordev->xor_high_base) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1162 | return -EBUSY; |
| 1163 | |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1164 | platform_set_drvdata(pdev, xordev); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1165 | |
| 1166 | /* |
| 1167 | * (Re-)program MBUS remapping windows if we are asked to. |
| 1168 | */ |
Andrew Lunn | 63a9332 | 2011-12-07 21:48:07 +0100 | [diff] [blame] | 1169 | dram = mv_mbus_dram_info(); |
| 1170 | if (dram) |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1171 | mv_xor_conf_mbus_windows(xordev, dram); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1172 | |
Andrew Lunn | c510182 | 2012-02-19 13:30:26 +0100 | [diff] [blame] | 1173 | /* Not all platforms can gate the clock, so it is not |
| 1174 | * an error if the clock does not exists. |
| 1175 | */ |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1176 | xordev->clk = clk_get(&pdev->dev, NULL); |
| 1177 | if (!IS_ERR(xordev->clk)) |
| 1178 | clk_prepare_enable(xordev->clk); |
Andrew Lunn | c510182 | 2012-02-19 13:30:26 +0100 | [diff] [blame] | 1179 | |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1180 | if (pdev->dev.of_node) { |
| 1181 | struct device_node *np; |
| 1182 | int i = 0; |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 1183 | const struct of_device_id *of_id = |
| 1184 | of_match_device(mv_xor_dt_ids, |
| 1185 | &pdev->dev); |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1186 | |
| 1187 | for_each_child_of_node(pdev->dev.of_node, np) { |
Russell King | 0be8253 | 2013-12-12 23:59:08 +0000 | [diff] [blame] | 1188 | struct mv_xor_chan *chan; |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1189 | dma_cap_mask_t cap_mask; |
| 1190 | int irq; |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 1191 | op_in_desc = (int)of_id->data; |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1192 | |
| 1193 | dma_cap_zero(cap_mask); |
| 1194 | if (of_property_read_bool(np, "dmacap,memcpy")) |
| 1195 | dma_cap_set(DMA_MEMCPY, cap_mask); |
| 1196 | if (of_property_read_bool(np, "dmacap,xor")) |
| 1197 | dma_cap_set(DMA_XOR, cap_mask); |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1198 | if (of_property_read_bool(np, "dmacap,interrupt")) |
| 1199 | dma_cap_set(DMA_INTERRUPT, cap_mask); |
| 1200 | |
| 1201 | irq = irq_of_parse_and_map(np, 0); |
Thomas Petazzoni | f8eb9e7 | 2012-11-22 18:22:12 +0100 | [diff] [blame] | 1202 | if (!irq) { |
| 1203 | ret = -ENODEV; |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1204 | goto err_channel_add; |
| 1205 | } |
| 1206 | |
Russell King | 0be8253 | 2013-12-12 23:59:08 +0000 | [diff] [blame] | 1207 | chan = mv_xor_channel_add(xordev, pdev, i, |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 1208 | cap_mask, irq, op_in_desc); |
Russell King | 0be8253 | 2013-12-12 23:59:08 +0000 | [diff] [blame] | 1209 | if (IS_ERR(chan)) { |
| 1210 | ret = PTR_ERR(chan); |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1211 | irq_dispose_mapping(irq); |
| 1212 | goto err_channel_add; |
| 1213 | } |
| 1214 | |
Russell King | 0be8253 | 2013-12-12 23:59:08 +0000 | [diff] [blame] | 1215 | xordev->channels[i] = chan; |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1216 | i++; |
| 1217 | } |
| 1218 | } else if (pdata && pdata->channels) { |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1219 | for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) { |
Thomas Petazzoni | e39f6ec | 2012-10-30 11:56:26 +0100 | [diff] [blame] | 1220 | struct mv_xor_channel_data *cd; |
Russell King | 0be8253 | 2013-12-12 23:59:08 +0000 | [diff] [blame] | 1221 | struct mv_xor_chan *chan; |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1222 | int irq; |
| 1223 | |
| 1224 | cd = &pdata->channels[i]; |
| 1225 | if (!cd) { |
| 1226 | ret = -ENODEV; |
| 1227 | goto err_channel_add; |
| 1228 | } |
| 1229 | |
| 1230 | irq = platform_get_irq(pdev, i); |
| 1231 | if (irq < 0) { |
| 1232 | ret = irq; |
| 1233 | goto err_channel_add; |
| 1234 | } |
| 1235 | |
Russell King | 0be8253 | 2013-12-12 23:59:08 +0000 | [diff] [blame] | 1236 | chan = mv_xor_channel_add(xordev, pdev, i, |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 1237 | cd->cap_mask, irq, |
| 1238 | XOR_MODE_IN_REG); |
Russell King | 0be8253 | 2013-12-12 23:59:08 +0000 | [diff] [blame] | 1239 | if (IS_ERR(chan)) { |
| 1240 | ret = PTR_ERR(chan); |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1241 | goto err_channel_add; |
| 1242 | } |
Russell King | 0be8253 | 2013-12-12 23:59:08 +0000 | [diff] [blame] | 1243 | |
| 1244 | xordev->channels[i] = chan; |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1245 | } |
| 1246 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1247 | |
| 1248 | return 0; |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1249 | |
| 1250 | err_channel_add: |
| 1251 | for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1252 | if (xordev->channels[i]) { |
Thomas Petazzoni | ab6e439 | 2013-01-06 11:10:43 +0100 | [diff] [blame] | 1253 | mv_xor_channel_remove(xordev->channels[i]); |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1254 | if (pdev->dev.of_node) |
| 1255 | irq_dispose_mapping(xordev->channels[i]->irq); |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1256 | } |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1257 | |
Thomas Petazzoni | dab9206 | 2013-01-06 11:10:44 +0100 | [diff] [blame] | 1258 | if (!IS_ERR(xordev->clk)) { |
| 1259 | clk_disable_unprepare(xordev->clk); |
| 1260 | clk_put(xordev->clk); |
| 1261 | } |
| 1262 | |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1263 | return ret; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1264 | } |
| 1265 | |
Linus Torvalds | c271433 | 2012-12-14 14:54:26 -0800 | [diff] [blame] | 1266 | static int mv_xor_remove(struct platform_device *pdev) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1267 | { |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1268 | struct mv_xor_device *xordev = platform_get_drvdata(pdev); |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1269 | int i; |
Andrew Lunn | c510182 | 2012-02-19 13:30:26 +0100 | [diff] [blame] | 1270 | |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1271 | for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) { |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1272 | if (xordev->channels[i]) |
| 1273 | mv_xor_channel_remove(xordev->channels[i]); |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1274 | } |
Andrew Lunn | c510182 | 2012-02-19 13:30:26 +0100 | [diff] [blame] | 1275 | |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1276 | if (!IS_ERR(xordev->clk)) { |
| 1277 | clk_disable_unprepare(xordev->clk); |
| 1278 | clk_put(xordev->clk); |
Andrew Lunn | c510182 | 2012-02-19 13:30:26 +0100 | [diff] [blame] | 1279 | } |
| 1280 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1281 | return 0; |
| 1282 | } |
| 1283 | |
Thomas Petazzoni | 6197165 | 2012-10-30 12:05:40 +0100 | [diff] [blame] | 1284 | static struct platform_driver mv_xor_driver = { |
| 1285 | .probe = mv_xor_probe, |
Linus Torvalds | c271433 | 2012-12-14 14:54:26 -0800 | [diff] [blame] | 1286 | .remove = mv_xor_remove, |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1287 | .driver = { |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1288 | .name = MV_XOR_NAME, |
| 1289 | .of_match_table = of_match_ptr(mv_xor_dt_ids), |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1290 | }, |
| 1291 | }; |
| 1292 | |
| 1293 | |
| 1294 | static int __init mv_xor_init(void) |
| 1295 | { |
Thomas Petazzoni | 6197165 | 2012-10-30 12:05:40 +0100 | [diff] [blame] | 1296 | return platform_driver_register(&mv_xor_driver); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1297 | } |
| 1298 | module_init(mv_xor_init); |
| 1299 | |
| 1300 | /* it's currently unsafe to unload this module */ |
| 1301 | #if 0 |
| 1302 | static void __exit mv_xor_exit(void) |
| 1303 | { |
| 1304 | platform_driver_unregister(&mv_xor_driver); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1305 | return; |
| 1306 | } |
| 1307 | |
| 1308 | module_exit(mv_xor_exit); |
| 1309 | #endif |
| 1310 | |
| 1311 | MODULE_AUTHOR("Saeed Bishara <saeed@marvell.com>"); |
| 1312 | MODULE_DESCRIPTION("DMA engine driver for Marvell's XOR engine"); |
| 1313 | MODULE_LICENSE("GPL"); |