Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1 | /******************************************************************************* |
| 2 | |
| 3 | Intel 10 Gigabit PCI Express Linux driver |
Peter P Waskiewicz Jr | 3efac5a | 2009-02-01 01:19:20 -0800 | [diff] [blame] | 4 | Copyright(c) 1999 - 2009 Intel Corporation. |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 5 | |
| 6 | This program is free software; you can redistribute it and/or modify it |
| 7 | under the terms and conditions of the GNU General Public License, |
| 8 | version 2, as published by the Free Software Foundation. |
| 9 | |
| 10 | This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License along with |
| 16 | this program; if not, write to the Free Software Foundation, Inc., |
| 17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 18 | |
| 19 | The full GNU General Public License is included in this distribution in |
| 20 | the file called "COPYING". |
| 21 | |
| 22 | Contact Information: |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 25 | |
| 26 | *******************************************************************************/ |
| 27 | |
| 28 | #include <linux/pci.h> |
| 29 | #include <linux/delay.h> |
| 30 | #include <linux/sched.h> |
| 31 | |
| 32 | #include "ixgbe_common.h" |
| 33 | #include "ixgbe_phy.h" |
| 34 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 35 | static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw); |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 36 | static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 37 | static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); |
| 38 | static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 39 | static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); |
| 40 | static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); |
| 41 | static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, |
| 42 | u16 count); |
| 43 | static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); |
| 44 | static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); |
| 45 | static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); |
| 46 | static void ixgbe_release_eeprom(struct ixgbe_hw *hw); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 47 | static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw); |
| 48 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 49 | static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index); |
| 50 | static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 51 | static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); |
| 52 | static void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr); |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 53 | static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 54 | |
| 55 | /** |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 56 | * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 57 | * @hw: pointer to hardware structure |
| 58 | * |
| 59 | * Starts the hardware by filling the bus info structure and media type, clears |
| 60 | * all on chip counters, initializes receive address registers, multicast |
| 61 | * table, VLAN filter table, calls routine to set up link and flow control |
| 62 | * settings, and leaves transmit and receive units disabled and uninitialized |
| 63 | **/ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 64 | s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 65 | { |
| 66 | u32 ctrl_ext; |
| 67 | |
| 68 | /* Set the media type */ |
| 69 | hw->phy.media_type = hw->mac.ops.get_media_type(hw); |
| 70 | |
| 71 | /* Identify the PHY */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 72 | hw->phy.ops.identify(hw); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 73 | |
| 74 | /* |
| 75 | * Store MAC address from RAR0, clear receive address registers, and |
| 76 | * clear the multicast table |
| 77 | */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 78 | hw->mac.ops.init_rx_addrs(hw); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 79 | |
| 80 | /* Clear the VLAN filter table */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 81 | hw->mac.ops.clear_vfta(hw); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 82 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 83 | /* Clear statistics registers */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 84 | hw->mac.ops.clear_hw_cntrs(hw); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 85 | |
| 86 | /* Set No Snoop Disable */ |
| 87 | ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); |
| 88 | ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; |
| 89 | IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); |
Auke Kok | 3957d63 | 2007-10-31 15:22:10 -0700 | [diff] [blame] | 90 | IXGBE_WRITE_FLUSH(hw); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 91 | |
| 92 | /* Clear adapter stopped flag */ |
| 93 | hw->adapter_stopped = false; |
| 94 | |
| 95 | return 0; |
| 96 | } |
| 97 | |
| 98 | /** |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 99 | * ixgbe_init_hw_generic - Generic hardware initialization |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 100 | * @hw: pointer to hardware structure |
| 101 | * |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 102 | * Initialize the hardware by resetting the hardware, filling the bus info |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 103 | * structure and media type, clears all on chip counters, initializes receive |
| 104 | * address registers, multicast table, VLAN filter table, calls routine to set |
| 105 | * up link and flow control settings, and leaves transmit and receive units |
| 106 | * disabled and uninitialized |
| 107 | **/ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 108 | s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 109 | { |
| 110 | /* Reset the hardware */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 111 | hw->mac.ops.reset_hw(hw); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 112 | |
| 113 | /* Start the HW */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 114 | hw->mac.ops.start_hw(hw); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 115 | |
| 116 | return 0; |
| 117 | } |
| 118 | |
| 119 | /** |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 120 | * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 121 | * @hw: pointer to hardware structure |
| 122 | * |
| 123 | * Clears all hardware statistics counters by reading them from the hardware |
| 124 | * Statistics counters are clear on read. |
| 125 | **/ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 126 | s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 127 | { |
| 128 | u16 i = 0; |
| 129 | |
| 130 | IXGBE_READ_REG(hw, IXGBE_CRCERRS); |
| 131 | IXGBE_READ_REG(hw, IXGBE_ILLERRC); |
| 132 | IXGBE_READ_REG(hw, IXGBE_ERRBC); |
| 133 | IXGBE_READ_REG(hw, IXGBE_MSPDC); |
| 134 | for (i = 0; i < 8; i++) |
| 135 | IXGBE_READ_REG(hw, IXGBE_MPC(i)); |
| 136 | |
| 137 | IXGBE_READ_REG(hw, IXGBE_MLFC); |
| 138 | IXGBE_READ_REG(hw, IXGBE_MRFC); |
| 139 | IXGBE_READ_REG(hw, IXGBE_RLEC); |
| 140 | IXGBE_READ_REG(hw, IXGBE_LXONTXC); |
| 141 | IXGBE_READ_REG(hw, IXGBE_LXONRXC); |
| 142 | IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); |
| 143 | IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); |
| 144 | |
| 145 | for (i = 0; i < 8; i++) { |
| 146 | IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); |
| 147 | IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); |
| 148 | IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); |
| 149 | IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); |
| 150 | } |
| 151 | |
| 152 | IXGBE_READ_REG(hw, IXGBE_PRC64); |
| 153 | IXGBE_READ_REG(hw, IXGBE_PRC127); |
| 154 | IXGBE_READ_REG(hw, IXGBE_PRC255); |
| 155 | IXGBE_READ_REG(hw, IXGBE_PRC511); |
| 156 | IXGBE_READ_REG(hw, IXGBE_PRC1023); |
| 157 | IXGBE_READ_REG(hw, IXGBE_PRC1522); |
| 158 | IXGBE_READ_REG(hw, IXGBE_GPRC); |
| 159 | IXGBE_READ_REG(hw, IXGBE_BPRC); |
| 160 | IXGBE_READ_REG(hw, IXGBE_MPRC); |
| 161 | IXGBE_READ_REG(hw, IXGBE_GPTC); |
| 162 | IXGBE_READ_REG(hw, IXGBE_GORCL); |
| 163 | IXGBE_READ_REG(hw, IXGBE_GORCH); |
| 164 | IXGBE_READ_REG(hw, IXGBE_GOTCL); |
| 165 | IXGBE_READ_REG(hw, IXGBE_GOTCH); |
| 166 | for (i = 0; i < 8; i++) |
| 167 | IXGBE_READ_REG(hw, IXGBE_RNBC(i)); |
| 168 | IXGBE_READ_REG(hw, IXGBE_RUC); |
| 169 | IXGBE_READ_REG(hw, IXGBE_RFC); |
| 170 | IXGBE_READ_REG(hw, IXGBE_ROC); |
| 171 | IXGBE_READ_REG(hw, IXGBE_RJC); |
| 172 | IXGBE_READ_REG(hw, IXGBE_MNGPRC); |
| 173 | IXGBE_READ_REG(hw, IXGBE_MNGPDC); |
| 174 | IXGBE_READ_REG(hw, IXGBE_MNGPTC); |
| 175 | IXGBE_READ_REG(hw, IXGBE_TORL); |
| 176 | IXGBE_READ_REG(hw, IXGBE_TORH); |
| 177 | IXGBE_READ_REG(hw, IXGBE_TPR); |
| 178 | IXGBE_READ_REG(hw, IXGBE_TPT); |
| 179 | IXGBE_READ_REG(hw, IXGBE_PTC64); |
| 180 | IXGBE_READ_REG(hw, IXGBE_PTC127); |
| 181 | IXGBE_READ_REG(hw, IXGBE_PTC255); |
| 182 | IXGBE_READ_REG(hw, IXGBE_PTC511); |
| 183 | IXGBE_READ_REG(hw, IXGBE_PTC1023); |
| 184 | IXGBE_READ_REG(hw, IXGBE_PTC1522); |
| 185 | IXGBE_READ_REG(hw, IXGBE_MPTC); |
| 186 | IXGBE_READ_REG(hw, IXGBE_BPTC); |
| 187 | for (i = 0; i < 16; i++) { |
| 188 | IXGBE_READ_REG(hw, IXGBE_QPRC(i)); |
| 189 | IXGBE_READ_REG(hw, IXGBE_QBRC(i)); |
| 190 | IXGBE_READ_REG(hw, IXGBE_QPTC(i)); |
| 191 | IXGBE_READ_REG(hw, IXGBE_QBTC(i)); |
| 192 | } |
| 193 | |
| 194 | return 0; |
| 195 | } |
| 196 | |
| 197 | /** |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 198 | * ixgbe_read_pba_num_generic - Reads part number from EEPROM |
| 199 | * @hw: pointer to hardware structure |
| 200 | * @pba_num: stores the part number from the EEPROM |
| 201 | * |
| 202 | * Reads the part number from the EEPROM. |
| 203 | **/ |
| 204 | s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num) |
| 205 | { |
| 206 | s32 ret_val; |
| 207 | u16 data; |
| 208 | |
| 209 | ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); |
| 210 | if (ret_val) { |
| 211 | hw_dbg(hw, "NVM Read Error\n"); |
| 212 | return ret_val; |
| 213 | } |
| 214 | *pba_num = (u32)(data << 16); |
| 215 | |
| 216 | ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data); |
| 217 | if (ret_val) { |
| 218 | hw_dbg(hw, "NVM Read Error\n"); |
| 219 | return ret_val; |
| 220 | } |
| 221 | *pba_num |= data; |
| 222 | |
| 223 | return 0; |
| 224 | } |
| 225 | |
| 226 | /** |
| 227 | * ixgbe_get_mac_addr_generic - Generic get MAC address |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 228 | * @hw: pointer to hardware structure |
| 229 | * @mac_addr: Adapter MAC address |
| 230 | * |
| 231 | * Reads the adapter's MAC address from first Receive Address Register (RAR0) |
| 232 | * A reset of the adapter must be performed prior to calling this function |
| 233 | * in order for the MAC address to have been loaded from the EEPROM into RAR0 |
| 234 | **/ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 235 | s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 236 | { |
| 237 | u32 rar_high; |
| 238 | u32 rar_low; |
| 239 | u16 i; |
| 240 | |
| 241 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); |
| 242 | rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); |
| 243 | |
| 244 | for (i = 0; i < 4; i++) |
| 245 | mac_addr[i] = (u8)(rar_low >> (i*8)); |
| 246 | |
| 247 | for (i = 0; i < 2; i++) |
| 248 | mac_addr[i+4] = (u8)(rar_high >> (i*8)); |
| 249 | |
| 250 | return 0; |
| 251 | } |
| 252 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 253 | /** |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 254 | * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 255 | * @hw: pointer to hardware structure |
| 256 | * |
| 257 | * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, |
| 258 | * disables transmit and receive units. The adapter_stopped flag is used by |
| 259 | * the shared code and drivers to determine if the adapter is in a stopped |
| 260 | * state and should not touch the hardware. |
| 261 | **/ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 262 | s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 263 | { |
| 264 | u32 number_of_queues; |
| 265 | u32 reg_val; |
| 266 | u16 i; |
| 267 | |
| 268 | /* |
| 269 | * Set the adapter_stopped flag so other driver functions stop touching |
| 270 | * the hardware |
| 271 | */ |
| 272 | hw->adapter_stopped = true; |
| 273 | |
| 274 | /* Disable the receive unit */ |
| 275 | reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL); |
| 276 | reg_val &= ~(IXGBE_RXCTRL_RXEN); |
| 277 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val); |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 278 | IXGBE_WRITE_FLUSH(hw); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 279 | msleep(2); |
| 280 | |
| 281 | /* Clear interrupt mask to stop from interrupts being generated */ |
| 282 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); |
| 283 | |
| 284 | /* Clear any pending interrupts */ |
| 285 | IXGBE_READ_REG(hw, IXGBE_EICR); |
| 286 | |
| 287 | /* Disable the transmit unit. Each queue must be disabled. */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 288 | number_of_queues = hw->mac.max_tx_queues; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 289 | for (i = 0; i < number_of_queues; i++) { |
| 290 | reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); |
| 291 | if (reg_val & IXGBE_TXDCTL_ENABLE) { |
| 292 | reg_val &= ~IXGBE_TXDCTL_ENABLE; |
| 293 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val); |
| 294 | } |
| 295 | } |
| 296 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 297 | /* |
| 298 | * Prevent the PCI-E bus from from hanging by disabling PCI-E master |
| 299 | * access and verify no pending requests |
| 300 | */ |
| 301 | if (ixgbe_disable_pcie_master(hw) != 0) |
| 302 | hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); |
| 303 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 304 | return 0; |
| 305 | } |
| 306 | |
| 307 | /** |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 308 | * ixgbe_led_on_generic - Turns on the software controllable LEDs. |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 309 | * @hw: pointer to hardware structure |
| 310 | * @index: led number to turn on |
| 311 | **/ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 312 | s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 313 | { |
| 314 | u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); |
| 315 | |
| 316 | /* To turn on the LED, set mode to ON. */ |
| 317 | led_reg &= ~IXGBE_LED_MODE_MASK(index); |
| 318 | led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); |
| 319 | IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); |
Auke Kok | 3957d63 | 2007-10-31 15:22:10 -0700 | [diff] [blame] | 320 | IXGBE_WRITE_FLUSH(hw); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 321 | |
| 322 | return 0; |
| 323 | } |
| 324 | |
| 325 | /** |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 326 | * ixgbe_led_off_generic - Turns off the software controllable LEDs. |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 327 | * @hw: pointer to hardware structure |
| 328 | * @index: led number to turn off |
| 329 | **/ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 330 | s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 331 | { |
| 332 | u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); |
| 333 | |
| 334 | /* To turn off the LED, set mode to OFF. */ |
| 335 | led_reg &= ~IXGBE_LED_MODE_MASK(index); |
| 336 | led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); |
| 337 | IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); |
Auke Kok | 3957d63 | 2007-10-31 15:22:10 -0700 | [diff] [blame] | 338 | IXGBE_WRITE_FLUSH(hw); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 339 | |
| 340 | return 0; |
| 341 | } |
| 342 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 343 | /** |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 344 | * ixgbe_init_eeprom_params_generic - Initialize EEPROM params |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 345 | * @hw: pointer to hardware structure |
| 346 | * |
| 347 | * Initializes the EEPROM parameters ixgbe_eeprom_info within the |
| 348 | * ixgbe_hw struct in order to set up EEPROM access. |
| 349 | **/ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 350 | s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 351 | { |
| 352 | struct ixgbe_eeprom_info *eeprom = &hw->eeprom; |
| 353 | u32 eec; |
| 354 | u16 eeprom_size; |
| 355 | |
| 356 | if (eeprom->type == ixgbe_eeprom_uninitialized) { |
| 357 | eeprom->type = ixgbe_eeprom_none; |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 358 | /* Set default semaphore delay to 10ms which is a well |
| 359 | * tested value */ |
| 360 | eeprom->semaphore_delay = 10; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 361 | |
| 362 | /* |
| 363 | * Check for EEPROM present first. |
| 364 | * If not present leave as none |
| 365 | */ |
| 366 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); |
| 367 | if (eec & IXGBE_EEC_PRES) { |
| 368 | eeprom->type = ixgbe_eeprom_spi; |
| 369 | |
| 370 | /* |
| 371 | * SPI EEPROM is assumed here. This code would need to |
| 372 | * change if a future EEPROM is not SPI. |
| 373 | */ |
| 374 | eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> |
| 375 | IXGBE_EEC_SIZE_SHIFT); |
| 376 | eeprom->word_size = 1 << (eeprom_size + |
| 377 | IXGBE_EEPROM_WORD_SIZE_SHIFT); |
| 378 | } |
| 379 | |
| 380 | if (eec & IXGBE_EEC_ADDR_SIZE) |
| 381 | eeprom->address_bits = 16; |
| 382 | else |
| 383 | eeprom->address_bits = 8; |
| 384 | hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: " |
| 385 | "%d\n", eeprom->type, eeprom->word_size, |
| 386 | eeprom->address_bits); |
| 387 | } |
| 388 | |
| 389 | return 0; |
| 390 | } |
| 391 | |
| 392 | /** |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 393 | * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang |
| 394 | * @hw: pointer to hardware structure |
| 395 | * @offset: offset within the EEPROM to be read |
| 396 | * @data: read 16 bit value from EEPROM |
| 397 | * |
| 398 | * Reads 16 bit value from EEPROM through bit-bang method |
| 399 | **/ |
| 400 | s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, |
| 401 | u16 *data) |
| 402 | { |
| 403 | s32 status; |
| 404 | u16 word_in; |
| 405 | u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; |
| 406 | |
| 407 | hw->eeprom.ops.init_params(hw); |
| 408 | |
| 409 | if (offset >= hw->eeprom.word_size) { |
| 410 | status = IXGBE_ERR_EEPROM; |
| 411 | goto out; |
| 412 | } |
| 413 | |
| 414 | /* Prepare the EEPROM for reading */ |
| 415 | status = ixgbe_acquire_eeprom(hw); |
| 416 | |
| 417 | if (status == 0) { |
| 418 | if (ixgbe_ready_eeprom(hw) != 0) { |
| 419 | ixgbe_release_eeprom(hw); |
| 420 | status = IXGBE_ERR_EEPROM; |
| 421 | } |
| 422 | } |
| 423 | |
| 424 | if (status == 0) { |
| 425 | ixgbe_standby_eeprom(hw); |
| 426 | |
| 427 | /* |
| 428 | * Some SPI eeproms use the 8th address bit embedded in the |
| 429 | * opcode |
| 430 | */ |
| 431 | if ((hw->eeprom.address_bits == 8) && (offset >= 128)) |
| 432 | read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; |
| 433 | |
| 434 | /* Send the READ command (opcode + addr) */ |
| 435 | ixgbe_shift_out_eeprom_bits(hw, read_opcode, |
| 436 | IXGBE_EEPROM_OPCODE_BITS); |
| 437 | ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2), |
| 438 | hw->eeprom.address_bits); |
| 439 | |
| 440 | /* Read the data. */ |
| 441 | word_in = ixgbe_shift_in_eeprom_bits(hw, 16); |
| 442 | *data = (word_in >> 8) | (word_in << 8); |
| 443 | |
| 444 | /* End this read operation */ |
| 445 | ixgbe_release_eeprom(hw); |
| 446 | } |
| 447 | |
| 448 | out: |
| 449 | return status; |
| 450 | } |
| 451 | |
| 452 | /** |
| 453 | * ixgbe_read_eeprom_generic - Read EEPROM word using EERD |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 454 | * @hw: pointer to hardware structure |
| 455 | * @offset: offset of word in the EEPROM to read |
| 456 | * @data: word read from the EEPROM |
| 457 | * |
| 458 | * Reads a 16 bit word from the EEPROM using the EERD register. |
| 459 | **/ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 460 | s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 461 | { |
| 462 | u32 eerd; |
| 463 | s32 status; |
| 464 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 465 | hw->eeprom.ops.init_params(hw); |
| 466 | |
| 467 | if (offset >= hw->eeprom.word_size) { |
| 468 | status = IXGBE_ERR_EEPROM; |
| 469 | goto out; |
| 470 | } |
| 471 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 472 | eerd = (offset << IXGBE_EEPROM_READ_ADDR_SHIFT) + |
| 473 | IXGBE_EEPROM_READ_REG_START; |
| 474 | |
| 475 | IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); |
| 476 | status = ixgbe_poll_eeprom_eerd_done(hw); |
| 477 | |
| 478 | if (status == 0) |
| 479 | *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >> |
Peter P Waskiewicz | b461724 | 2008-09-11 20:04:46 -0700 | [diff] [blame] | 480 | IXGBE_EEPROM_READ_REG_DATA); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 481 | else |
| 482 | hw_dbg(hw, "Eeprom read timed out\n"); |
| 483 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 484 | out: |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 485 | return status; |
| 486 | } |
| 487 | |
| 488 | /** |
| 489 | * ixgbe_poll_eeprom_eerd_done - Poll EERD status |
| 490 | * @hw: pointer to hardware structure |
| 491 | * |
| 492 | * Polls the status bit (bit 1) of the EERD to determine when the read is done. |
| 493 | **/ |
| 494 | static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw) |
| 495 | { |
| 496 | u32 i; |
| 497 | u32 reg; |
| 498 | s32 status = IXGBE_ERR_EEPROM; |
| 499 | |
| 500 | for (i = 0; i < IXGBE_EERD_ATTEMPTS; i++) { |
| 501 | reg = IXGBE_READ_REG(hw, IXGBE_EERD); |
| 502 | if (reg & IXGBE_EEPROM_READ_REG_DONE) { |
| 503 | status = 0; |
| 504 | break; |
| 505 | } |
| 506 | udelay(5); |
| 507 | } |
| 508 | return status; |
| 509 | } |
| 510 | |
| 511 | /** |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 512 | * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang |
| 513 | * @hw: pointer to hardware structure |
| 514 | * |
| 515 | * Prepares EEPROM for access using bit-bang method. This function should |
| 516 | * be called before issuing a command to the EEPROM. |
| 517 | **/ |
| 518 | static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) |
| 519 | { |
| 520 | s32 status = 0; |
| 521 | u32 eec; |
| 522 | u32 i; |
| 523 | |
| 524 | if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0) |
| 525 | status = IXGBE_ERR_SWFW_SYNC; |
| 526 | |
| 527 | if (status == 0) { |
| 528 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); |
| 529 | |
| 530 | /* Request EEPROM Access */ |
| 531 | eec |= IXGBE_EEC_REQ; |
| 532 | IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); |
| 533 | |
| 534 | for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { |
| 535 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); |
| 536 | if (eec & IXGBE_EEC_GNT) |
| 537 | break; |
| 538 | udelay(5); |
| 539 | } |
| 540 | |
| 541 | /* Release if grant not acquired */ |
| 542 | if (!(eec & IXGBE_EEC_GNT)) { |
| 543 | eec &= ~IXGBE_EEC_REQ; |
| 544 | IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); |
| 545 | hw_dbg(hw, "Could not acquire EEPROM grant\n"); |
| 546 | |
| 547 | ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); |
| 548 | status = IXGBE_ERR_EEPROM; |
| 549 | } |
| 550 | } |
| 551 | |
| 552 | /* Setup EEPROM for Read/Write */ |
| 553 | if (status == 0) { |
| 554 | /* Clear CS and SK */ |
| 555 | eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); |
| 556 | IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); |
| 557 | IXGBE_WRITE_FLUSH(hw); |
| 558 | udelay(1); |
| 559 | } |
| 560 | return status; |
| 561 | } |
| 562 | |
| 563 | /** |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 564 | * ixgbe_get_eeprom_semaphore - Get hardware semaphore |
| 565 | * @hw: pointer to hardware structure |
| 566 | * |
| 567 | * Sets the hardware semaphores so EEPROM access can occur for bit-bang method |
| 568 | **/ |
| 569 | static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) |
| 570 | { |
| 571 | s32 status = IXGBE_ERR_EEPROM; |
| 572 | u32 timeout; |
| 573 | u32 i; |
| 574 | u32 swsm; |
| 575 | |
| 576 | /* Set timeout value based on size of EEPROM */ |
| 577 | timeout = hw->eeprom.word_size + 1; |
| 578 | |
| 579 | /* Get SMBI software semaphore between device drivers first */ |
| 580 | for (i = 0; i < timeout; i++) { |
| 581 | /* |
| 582 | * If the SMBI bit is 0 when we read it, then the bit will be |
| 583 | * set and we have the semaphore |
| 584 | */ |
| 585 | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); |
| 586 | if (!(swsm & IXGBE_SWSM_SMBI)) { |
| 587 | status = 0; |
| 588 | break; |
| 589 | } |
| 590 | msleep(1); |
| 591 | } |
| 592 | |
| 593 | /* Now get the semaphore between SW/FW through the SWESMBI bit */ |
| 594 | if (status == 0) { |
| 595 | for (i = 0; i < timeout; i++) { |
| 596 | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); |
| 597 | |
| 598 | /* Set the SW EEPROM semaphore bit to request access */ |
| 599 | swsm |= IXGBE_SWSM_SWESMBI; |
| 600 | IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); |
| 601 | |
| 602 | /* |
| 603 | * If we set the bit successfully then we got the |
| 604 | * semaphore. |
| 605 | */ |
| 606 | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); |
| 607 | if (swsm & IXGBE_SWSM_SWESMBI) |
| 608 | break; |
| 609 | |
| 610 | udelay(50); |
| 611 | } |
| 612 | |
| 613 | /* |
| 614 | * Release semaphores and return error if SW EEPROM semaphore |
| 615 | * was not granted because we don't have access to the EEPROM |
| 616 | */ |
| 617 | if (i >= timeout) { |
| 618 | hw_dbg(hw, "Driver can't access the Eeprom - Semaphore " |
Peter P Waskiewicz | b461724 | 2008-09-11 20:04:46 -0700 | [diff] [blame] | 619 | "not granted.\n"); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 620 | ixgbe_release_eeprom_semaphore(hw); |
| 621 | status = IXGBE_ERR_EEPROM; |
| 622 | } |
| 623 | } |
| 624 | |
| 625 | return status; |
| 626 | } |
| 627 | |
| 628 | /** |
| 629 | * ixgbe_release_eeprom_semaphore - Release hardware semaphore |
| 630 | * @hw: pointer to hardware structure |
| 631 | * |
| 632 | * This function clears hardware semaphore bits. |
| 633 | **/ |
| 634 | static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) |
| 635 | { |
| 636 | u32 swsm; |
| 637 | |
| 638 | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); |
| 639 | |
| 640 | /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ |
| 641 | swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); |
| 642 | IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); |
Auke Kok | 3957d63 | 2007-10-31 15:22:10 -0700 | [diff] [blame] | 643 | IXGBE_WRITE_FLUSH(hw); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 644 | } |
| 645 | |
| 646 | /** |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 647 | * ixgbe_ready_eeprom - Polls for EEPROM ready |
| 648 | * @hw: pointer to hardware structure |
| 649 | **/ |
| 650 | static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) |
| 651 | { |
| 652 | s32 status = 0; |
| 653 | u16 i; |
| 654 | u8 spi_stat_reg; |
| 655 | |
| 656 | /* |
| 657 | * Read "Status Register" repeatedly until the LSB is cleared. The |
| 658 | * EEPROM will signal that the command has been completed by clearing |
| 659 | * bit 0 of the internal status register. If it's not cleared within |
| 660 | * 5 milliseconds, then error out. |
| 661 | */ |
| 662 | for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { |
| 663 | ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, |
| 664 | IXGBE_EEPROM_OPCODE_BITS); |
| 665 | spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); |
| 666 | if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) |
| 667 | break; |
| 668 | |
| 669 | udelay(5); |
| 670 | ixgbe_standby_eeprom(hw); |
| 671 | }; |
| 672 | |
| 673 | /* |
| 674 | * On some parts, SPI write time could vary from 0-20mSec on 3.3V |
| 675 | * devices (and only 0-5mSec on 5V devices) |
| 676 | */ |
| 677 | if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { |
| 678 | hw_dbg(hw, "SPI EEPROM Status error\n"); |
| 679 | status = IXGBE_ERR_EEPROM; |
| 680 | } |
| 681 | |
| 682 | return status; |
| 683 | } |
| 684 | |
| 685 | /** |
| 686 | * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state |
| 687 | * @hw: pointer to hardware structure |
| 688 | **/ |
| 689 | static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) |
| 690 | { |
| 691 | u32 eec; |
| 692 | |
| 693 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); |
| 694 | |
| 695 | /* Toggle CS to flush commands */ |
| 696 | eec |= IXGBE_EEC_CS; |
| 697 | IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); |
| 698 | IXGBE_WRITE_FLUSH(hw); |
| 699 | udelay(1); |
| 700 | eec &= ~IXGBE_EEC_CS; |
| 701 | IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); |
| 702 | IXGBE_WRITE_FLUSH(hw); |
| 703 | udelay(1); |
| 704 | } |
| 705 | |
| 706 | /** |
| 707 | * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. |
| 708 | * @hw: pointer to hardware structure |
| 709 | * @data: data to send to the EEPROM |
| 710 | * @count: number of bits to shift out |
| 711 | **/ |
| 712 | static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, |
| 713 | u16 count) |
| 714 | { |
| 715 | u32 eec; |
| 716 | u32 mask; |
| 717 | u32 i; |
| 718 | |
| 719 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); |
| 720 | |
| 721 | /* |
| 722 | * Mask is used to shift "count" bits of "data" out to the EEPROM |
| 723 | * one bit at a time. Determine the starting bit based on count |
| 724 | */ |
| 725 | mask = 0x01 << (count - 1); |
| 726 | |
| 727 | for (i = 0; i < count; i++) { |
| 728 | /* |
| 729 | * A "1" is shifted out to the EEPROM by setting bit "DI" to a |
| 730 | * "1", and then raising and then lowering the clock (the SK |
| 731 | * bit controls the clock input to the EEPROM). A "0" is |
| 732 | * shifted out to the EEPROM by setting "DI" to "0" and then |
| 733 | * raising and then lowering the clock. |
| 734 | */ |
| 735 | if (data & mask) |
| 736 | eec |= IXGBE_EEC_DI; |
| 737 | else |
| 738 | eec &= ~IXGBE_EEC_DI; |
| 739 | |
| 740 | IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); |
| 741 | IXGBE_WRITE_FLUSH(hw); |
| 742 | |
| 743 | udelay(1); |
| 744 | |
| 745 | ixgbe_raise_eeprom_clk(hw, &eec); |
| 746 | ixgbe_lower_eeprom_clk(hw, &eec); |
| 747 | |
| 748 | /* |
| 749 | * Shift mask to signify next bit of data to shift in to the |
| 750 | * EEPROM |
| 751 | */ |
| 752 | mask = mask >> 1; |
| 753 | }; |
| 754 | |
| 755 | /* We leave the "DI" bit set to "0" when we leave this routine. */ |
| 756 | eec &= ~IXGBE_EEC_DI; |
| 757 | IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); |
| 758 | IXGBE_WRITE_FLUSH(hw); |
| 759 | } |
| 760 | |
| 761 | /** |
| 762 | * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM |
| 763 | * @hw: pointer to hardware structure |
| 764 | **/ |
| 765 | static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) |
| 766 | { |
| 767 | u32 eec; |
| 768 | u32 i; |
| 769 | u16 data = 0; |
| 770 | |
| 771 | /* |
| 772 | * In order to read a register from the EEPROM, we need to shift |
| 773 | * 'count' bits in from the EEPROM. Bits are "shifted in" by raising |
| 774 | * the clock input to the EEPROM (setting the SK bit), and then reading |
| 775 | * the value of the "DO" bit. During this "shifting in" process the |
| 776 | * "DI" bit should always be clear. |
| 777 | */ |
| 778 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); |
| 779 | |
| 780 | eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); |
| 781 | |
| 782 | for (i = 0; i < count; i++) { |
| 783 | data = data << 1; |
| 784 | ixgbe_raise_eeprom_clk(hw, &eec); |
| 785 | |
| 786 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); |
| 787 | |
| 788 | eec &= ~(IXGBE_EEC_DI); |
| 789 | if (eec & IXGBE_EEC_DO) |
| 790 | data |= 1; |
| 791 | |
| 792 | ixgbe_lower_eeprom_clk(hw, &eec); |
| 793 | } |
| 794 | |
| 795 | return data; |
| 796 | } |
| 797 | |
| 798 | /** |
| 799 | * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. |
| 800 | * @hw: pointer to hardware structure |
| 801 | * @eec: EEC register's current value |
| 802 | **/ |
| 803 | static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) |
| 804 | { |
| 805 | /* |
| 806 | * Raise the clock input to the EEPROM |
| 807 | * (setting the SK bit), then delay |
| 808 | */ |
| 809 | *eec = *eec | IXGBE_EEC_SK; |
| 810 | IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); |
| 811 | IXGBE_WRITE_FLUSH(hw); |
| 812 | udelay(1); |
| 813 | } |
| 814 | |
| 815 | /** |
| 816 | * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. |
| 817 | * @hw: pointer to hardware structure |
| 818 | * @eecd: EECD's current value |
| 819 | **/ |
| 820 | static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) |
| 821 | { |
| 822 | /* |
| 823 | * Lower the clock input to the EEPROM (clearing the SK bit), then |
| 824 | * delay |
| 825 | */ |
| 826 | *eec = *eec & ~IXGBE_EEC_SK; |
| 827 | IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); |
| 828 | IXGBE_WRITE_FLUSH(hw); |
| 829 | udelay(1); |
| 830 | } |
| 831 | |
| 832 | /** |
| 833 | * ixgbe_release_eeprom - Release EEPROM, release semaphores |
| 834 | * @hw: pointer to hardware structure |
| 835 | **/ |
| 836 | static void ixgbe_release_eeprom(struct ixgbe_hw *hw) |
| 837 | { |
| 838 | u32 eec; |
| 839 | |
| 840 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); |
| 841 | |
| 842 | eec |= IXGBE_EEC_CS; /* Pull CS high */ |
| 843 | eec &= ~IXGBE_EEC_SK; /* Lower SCK */ |
| 844 | |
| 845 | IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); |
| 846 | IXGBE_WRITE_FLUSH(hw); |
| 847 | |
| 848 | udelay(1); |
| 849 | |
| 850 | /* Stop requesting EEPROM access */ |
| 851 | eec &= ~IXGBE_EEC_REQ; |
| 852 | IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); |
| 853 | |
| 854 | ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); |
| 855 | } |
| 856 | |
| 857 | /** |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 858 | * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum |
| 859 | * @hw: pointer to hardware structure |
| 860 | **/ |
| 861 | static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw) |
| 862 | { |
| 863 | u16 i; |
| 864 | u16 j; |
| 865 | u16 checksum = 0; |
| 866 | u16 length = 0; |
| 867 | u16 pointer = 0; |
| 868 | u16 word = 0; |
| 869 | |
| 870 | /* Include 0x0-0x3F in the checksum */ |
| 871 | for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 872 | if (hw->eeprom.ops.read(hw, i, &word) != 0) { |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 873 | hw_dbg(hw, "EEPROM read failed\n"); |
| 874 | break; |
| 875 | } |
| 876 | checksum += word; |
| 877 | } |
| 878 | |
| 879 | /* Include all data from pointers except for the fw pointer */ |
| 880 | for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 881 | hw->eeprom.ops.read(hw, i, &pointer); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 882 | |
| 883 | /* Make sure the pointer seems valid */ |
| 884 | if (pointer != 0xFFFF && pointer != 0) { |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 885 | hw->eeprom.ops.read(hw, pointer, &length); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 886 | |
| 887 | if (length != 0xFFFF && length != 0) { |
| 888 | for (j = pointer+1; j <= pointer+length; j++) { |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 889 | hw->eeprom.ops.read(hw, j, &word); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 890 | checksum += word; |
| 891 | } |
| 892 | } |
| 893 | } |
| 894 | } |
| 895 | |
| 896 | checksum = (u16)IXGBE_EEPROM_SUM - checksum; |
| 897 | |
| 898 | return checksum; |
| 899 | } |
| 900 | |
| 901 | /** |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 902 | * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 903 | * @hw: pointer to hardware structure |
| 904 | * @checksum_val: calculated checksum |
| 905 | * |
| 906 | * Performs checksum calculation and validates the EEPROM checksum. If the |
| 907 | * caller does not need checksum_val, the value can be NULL. |
| 908 | **/ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 909 | s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, |
| 910 | u16 *checksum_val) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 911 | { |
| 912 | s32 status; |
| 913 | u16 checksum; |
| 914 | u16 read_checksum = 0; |
| 915 | |
| 916 | /* |
| 917 | * Read the first word from the EEPROM. If this times out or fails, do |
| 918 | * not continue or we could be in for a very long wait while every |
| 919 | * EEPROM read fails |
| 920 | */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 921 | status = hw->eeprom.ops.read(hw, 0, &checksum); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 922 | |
| 923 | if (status == 0) { |
| 924 | checksum = ixgbe_calc_eeprom_checksum(hw); |
| 925 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 926 | hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 927 | |
| 928 | /* |
| 929 | * Verify read checksum from EEPROM is the same as |
| 930 | * calculated checksum |
| 931 | */ |
| 932 | if (read_checksum != checksum) |
| 933 | status = IXGBE_ERR_EEPROM_CHECKSUM; |
| 934 | |
| 935 | /* If the user cares, return the calculated checksum */ |
| 936 | if (checksum_val) |
| 937 | *checksum_val = checksum; |
| 938 | } else { |
| 939 | hw_dbg(hw, "EEPROM read failed\n"); |
| 940 | } |
| 941 | |
| 942 | return status; |
| 943 | } |
| 944 | |
| 945 | /** |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 946 | * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum |
| 947 | * @hw: pointer to hardware structure |
| 948 | **/ |
| 949 | s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) |
| 950 | { |
| 951 | s32 status; |
| 952 | u16 checksum; |
| 953 | |
| 954 | /* |
| 955 | * Read the first word from the EEPROM. If this times out or fails, do |
| 956 | * not continue or we could be in for a very long wait while every |
| 957 | * EEPROM read fails |
| 958 | */ |
| 959 | status = hw->eeprom.ops.read(hw, 0, &checksum); |
| 960 | |
| 961 | if (status == 0) { |
| 962 | checksum = ixgbe_calc_eeprom_checksum(hw); |
| 963 | status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, |
| 964 | checksum); |
| 965 | } else { |
| 966 | hw_dbg(hw, "EEPROM read failed\n"); |
| 967 | } |
| 968 | |
| 969 | return status; |
| 970 | } |
| 971 | |
| 972 | /** |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 973 | * ixgbe_validate_mac_addr - Validate MAC address |
| 974 | * @mac_addr: pointer to MAC address. |
| 975 | * |
| 976 | * Tests a MAC address to ensure it is a valid Individual Address |
| 977 | **/ |
| 978 | s32 ixgbe_validate_mac_addr(u8 *mac_addr) |
| 979 | { |
| 980 | s32 status = 0; |
| 981 | |
| 982 | /* Make sure it is not a multicast address */ |
| 983 | if (IXGBE_IS_MULTICAST(mac_addr)) |
| 984 | status = IXGBE_ERR_INVALID_MAC_ADDR; |
| 985 | /* Not a broadcast address */ |
| 986 | else if (IXGBE_IS_BROADCAST(mac_addr)) |
| 987 | status = IXGBE_ERR_INVALID_MAC_ADDR; |
| 988 | /* Reject the zero address */ |
| 989 | else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 990 | mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 991 | status = IXGBE_ERR_INVALID_MAC_ADDR; |
| 992 | |
| 993 | return status; |
| 994 | } |
| 995 | |
| 996 | /** |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 997 | * ixgbe_set_rar_generic - Set Rx address register |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 998 | * @hw: pointer to hardware structure |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 999 | * @index: Receive address register to write |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1000 | * @addr: Address to put into receive address register |
| 1001 | * @vmdq: VMDq "set" or "pool" index |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1002 | * @enable_addr: set flag that address is active |
| 1003 | * |
| 1004 | * Puts an ethernet address into a receive address register. |
| 1005 | **/ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1006 | s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, |
| 1007 | u32 enable_addr) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1008 | { |
| 1009 | u32 rar_low, rar_high; |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1010 | u32 rar_entries = hw->mac.num_rar_entries; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1011 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1012 | /* setup VMDq pool selection before this RAR gets enabled */ |
| 1013 | hw->mac.ops.set_vmdq(hw, index, vmdq); |
| 1014 | |
| 1015 | /* Make sure we are using a valid rar index range */ |
| 1016 | if (index < rar_entries) { |
Peter P Waskiewicz | b461724 | 2008-09-11 20:04:46 -0700 | [diff] [blame] | 1017 | /* |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1018 | * HW expects these in little endian so we reverse the byte |
| 1019 | * order from network order (big endian) to little endian |
Peter P Waskiewicz | b461724 | 2008-09-11 20:04:46 -0700 | [diff] [blame] | 1020 | */ |
| 1021 | rar_low = ((u32)addr[0] | |
| 1022 | ((u32)addr[1] << 8) | |
| 1023 | ((u32)addr[2] << 16) | |
| 1024 | ((u32)addr[3] << 24)); |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1025 | /* |
| 1026 | * Some parts put the VMDq setting in the extra RAH bits, |
| 1027 | * so save everything except the lower 16 bits that hold part |
| 1028 | * of the address and the address valid bit. |
| 1029 | */ |
| 1030 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); |
| 1031 | rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); |
| 1032 | rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1033 | |
Peter P Waskiewicz | b461724 | 2008-09-11 20:04:46 -0700 | [diff] [blame] | 1034 | if (enable_addr != 0) |
| 1035 | rar_high |= IXGBE_RAH_AV; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1036 | |
Peter P Waskiewicz | b461724 | 2008-09-11 20:04:46 -0700 | [diff] [blame] | 1037 | IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); |
| 1038 | IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1039 | } else { |
| 1040 | hw_dbg(hw, "RAR index %d is out of range.\n", index); |
| 1041 | } |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1042 | |
| 1043 | return 0; |
| 1044 | } |
| 1045 | |
| 1046 | /** |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1047 | * ixgbe_clear_rar_generic - Remove Rx address register |
| 1048 | * @hw: pointer to hardware structure |
| 1049 | * @index: Receive address register to write |
| 1050 | * |
| 1051 | * Clears an ethernet address from a receive address register. |
| 1052 | **/ |
| 1053 | s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) |
| 1054 | { |
| 1055 | u32 rar_high; |
| 1056 | u32 rar_entries = hw->mac.num_rar_entries; |
| 1057 | |
| 1058 | /* Make sure we are using a valid rar index range */ |
| 1059 | if (index < rar_entries) { |
| 1060 | /* |
| 1061 | * Some parts put the VMDq setting in the extra RAH bits, |
| 1062 | * so save everything except the lower 16 bits that hold part |
| 1063 | * of the address and the address valid bit. |
| 1064 | */ |
| 1065 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); |
| 1066 | rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); |
| 1067 | |
| 1068 | IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); |
| 1069 | IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); |
| 1070 | } else { |
| 1071 | hw_dbg(hw, "RAR index %d is out of range.\n", index); |
| 1072 | } |
| 1073 | |
| 1074 | /* clear VMDq pool/queue selection for this RAR */ |
| 1075 | hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); |
| 1076 | |
| 1077 | return 0; |
| 1078 | } |
| 1079 | |
| 1080 | /** |
| 1081 | * ixgbe_enable_rar - Enable Rx address register |
| 1082 | * @hw: pointer to hardware structure |
| 1083 | * @index: index into the RAR table |
| 1084 | * |
| 1085 | * Enables the select receive address register. |
| 1086 | **/ |
| 1087 | static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index) |
| 1088 | { |
| 1089 | u32 rar_high; |
| 1090 | |
| 1091 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); |
| 1092 | rar_high |= IXGBE_RAH_AV; |
| 1093 | IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); |
| 1094 | } |
| 1095 | |
| 1096 | /** |
| 1097 | * ixgbe_disable_rar - Disable Rx address register |
| 1098 | * @hw: pointer to hardware structure |
| 1099 | * @index: index into the RAR table |
| 1100 | * |
| 1101 | * Disables the select receive address register. |
| 1102 | **/ |
| 1103 | static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index) |
| 1104 | { |
| 1105 | u32 rar_high; |
| 1106 | |
| 1107 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); |
| 1108 | rar_high &= (~IXGBE_RAH_AV); |
| 1109 | IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); |
| 1110 | } |
| 1111 | |
| 1112 | /** |
| 1113 | * ixgbe_init_rx_addrs_generic - Initializes receive address filters. |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1114 | * @hw: pointer to hardware structure |
| 1115 | * |
| 1116 | * Places the MAC address in receive address register 0 and clears the rest |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1117 | * of the receive address registers. Clears the multicast table. Assumes |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1118 | * the receiver is in reset when the routine is called. |
| 1119 | **/ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1120 | s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1121 | { |
| 1122 | u32 i; |
Christopher Leech | 2c5645c | 2008-08-26 04:27:02 -0700 | [diff] [blame] | 1123 | u32 rar_entries = hw->mac.num_rar_entries; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1124 | |
| 1125 | /* |
| 1126 | * If the current mac address is valid, assume it is a software override |
| 1127 | * to the permanent address. |
| 1128 | * Otherwise, use the permanent address from the eeprom. |
| 1129 | */ |
| 1130 | if (ixgbe_validate_mac_addr(hw->mac.addr) == |
| 1131 | IXGBE_ERR_INVALID_MAC_ADDR) { |
| 1132 | /* Get the MAC address from the RAR0 for later reference */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1133 | hw->mac.ops.get_mac_addr(hw, hw->mac.addr); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1134 | |
| 1135 | hw_dbg(hw, " Keeping Current RAR0 Addr =%.2X %.2X %.2X ", |
Peter P Waskiewicz | b461724 | 2008-09-11 20:04:46 -0700 | [diff] [blame] | 1136 | hw->mac.addr[0], hw->mac.addr[1], |
| 1137 | hw->mac.addr[2]); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1138 | hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3], |
Peter P Waskiewicz | b461724 | 2008-09-11 20:04:46 -0700 | [diff] [blame] | 1139 | hw->mac.addr[4], hw->mac.addr[5]); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1140 | } else { |
| 1141 | /* Setup the receive address. */ |
| 1142 | hw_dbg(hw, "Overriding MAC Address in RAR[0]\n"); |
| 1143 | hw_dbg(hw, " New MAC Addr =%.2X %.2X %.2X ", |
Peter P Waskiewicz | b461724 | 2008-09-11 20:04:46 -0700 | [diff] [blame] | 1144 | hw->mac.addr[0], hw->mac.addr[1], |
| 1145 | hw->mac.addr[2]); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1146 | hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3], |
Peter P Waskiewicz | b461724 | 2008-09-11 20:04:46 -0700 | [diff] [blame] | 1147 | hw->mac.addr[4], hw->mac.addr[5]); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1148 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1149 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1150 | } |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1151 | hw->addr_ctrl.overflow_promisc = 0; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1152 | |
| 1153 | hw->addr_ctrl.rar_used_count = 1; |
| 1154 | |
| 1155 | /* Zero out the other receive addresses. */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1156 | hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1157 | for (i = 1; i < rar_entries; i++) { |
| 1158 | IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); |
| 1159 | IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); |
| 1160 | } |
| 1161 | |
| 1162 | /* Clear the MTA */ |
| 1163 | hw->addr_ctrl.mc_addr_in_rar_count = 0; |
| 1164 | hw->addr_ctrl.mta_in_use = 0; |
| 1165 | IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); |
| 1166 | |
| 1167 | hw_dbg(hw, " Clearing MTA\n"); |
Christopher Leech | 2c5645c | 2008-08-26 04:27:02 -0700 | [diff] [blame] | 1168 | for (i = 0; i < hw->mac.mcft_size; i++) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1169 | IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); |
| 1170 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1171 | if (hw->mac.ops.init_uta_tables) |
| 1172 | hw->mac.ops.init_uta_tables(hw); |
| 1173 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1174 | return 0; |
| 1175 | } |
| 1176 | |
| 1177 | /** |
Christopher Leech | 2c5645c | 2008-08-26 04:27:02 -0700 | [diff] [blame] | 1178 | * ixgbe_add_uc_addr - Adds a secondary unicast address. |
| 1179 | * @hw: pointer to hardware structure |
| 1180 | * @addr: new address |
| 1181 | * |
| 1182 | * Adds it to unused receive address register or goes into promiscuous mode. |
| 1183 | **/ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1184 | static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) |
Christopher Leech | 2c5645c | 2008-08-26 04:27:02 -0700 | [diff] [blame] | 1185 | { |
| 1186 | u32 rar_entries = hw->mac.num_rar_entries; |
| 1187 | u32 rar; |
| 1188 | |
| 1189 | hw_dbg(hw, " UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n", |
| 1190 | addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); |
| 1191 | |
| 1192 | /* |
| 1193 | * Place this address in the RAR if there is room, |
| 1194 | * else put the controller into promiscuous mode |
| 1195 | */ |
| 1196 | if (hw->addr_ctrl.rar_used_count < rar_entries) { |
| 1197 | rar = hw->addr_ctrl.rar_used_count - |
| 1198 | hw->addr_ctrl.mc_addr_in_rar_count; |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1199 | hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); |
Christopher Leech | 2c5645c | 2008-08-26 04:27:02 -0700 | [diff] [blame] | 1200 | hw_dbg(hw, "Added a secondary address to RAR[%d]\n", rar); |
| 1201 | hw->addr_ctrl.rar_used_count++; |
| 1202 | } else { |
| 1203 | hw->addr_ctrl.overflow_promisc++; |
| 1204 | } |
| 1205 | |
| 1206 | hw_dbg(hw, "ixgbe_add_uc_addr Complete\n"); |
| 1207 | } |
| 1208 | |
| 1209 | /** |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1210 | * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses |
Christopher Leech | 2c5645c | 2008-08-26 04:27:02 -0700 | [diff] [blame] | 1211 | * @hw: pointer to hardware structure |
| 1212 | * @addr_list: the list of new addresses |
| 1213 | * @addr_count: number of addresses |
| 1214 | * @next: iterator function to walk the address list |
| 1215 | * |
| 1216 | * The given list replaces any existing list. Clears the secondary addrs from |
| 1217 | * receive address registers. Uses unused receive address registers for the |
| 1218 | * first secondary addresses, and falls back to promiscuous mode as needed. |
| 1219 | * |
| 1220 | * Drivers using secondary unicast addresses must set user_set_promisc when |
| 1221 | * manually putting the device into promiscuous mode. |
| 1222 | **/ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1223 | s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list, |
Christopher Leech | 2c5645c | 2008-08-26 04:27:02 -0700 | [diff] [blame] | 1224 | u32 addr_count, ixgbe_mc_addr_itr next) |
| 1225 | { |
| 1226 | u8 *addr; |
| 1227 | u32 i; |
| 1228 | u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc; |
| 1229 | u32 uc_addr_in_use; |
| 1230 | u32 fctrl; |
| 1231 | u32 vmdq; |
| 1232 | |
| 1233 | /* |
| 1234 | * Clear accounting of old secondary address list, |
| 1235 | * don't count RAR[0] |
| 1236 | */ |
| 1237 | uc_addr_in_use = hw->addr_ctrl.rar_used_count - |
| 1238 | hw->addr_ctrl.mc_addr_in_rar_count - 1; |
| 1239 | hw->addr_ctrl.rar_used_count -= uc_addr_in_use; |
| 1240 | hw->addr_ctrl.overflow_promisc = 0; |
| 1241 | |
| 1242 | /* Zero out the other receive addresses */ |
| 1243 | hw_dbg(hw, "Clearing RAR[1-%d]\n", uc_addr_in_use); |
| 1244 | for (i = 1; i <= uc_addr_in_use; i++) { |
| 1245 | IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); |
| 1246 | IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); |
| 1247 | } |
| 1248 | |
| 1249 | /* Add the new addresses */ |
| 1250 | for (i = 0; i < addr_count; i++) { |
| 1251 | hw_dbg(hw, " Adding the secondary addresses:\n"); |
| 1252 | addr = next(hw, &addr_list, &vmdq); |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1253 | ixgbe_add_uc_addr(hw, addr, vmdq); |
Christopher Leech | 2c5645c | 2008-08-26 04:27:02 -0700 | [diff] [blame] | 1254 | } |
| 1255 | |
| 1256 | if (hw->addr_ctrl.overflow_promisc) { |
| 1257 | /* enable promisc if not already in overflow or set by user */ |
| 1258 | if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { |
| 1259 | hw_dbg(hw, " Entering address overflow promisc mode\n"); |
| 1260 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); |
| 1261 | fctrl |= IXGBE_FCTRL_UPE; |
| 1262 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); |
| 1263 | } |
| 1264 | } else { |
| 1265 | /* only disable if set by overflow, not by user */ |
| 1266 | if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { |
| 1267 | hw_dbg(hw, " Leaving address overflow promisc mode\n"); |
| 1268 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); |
| 1269 | fctrl &= ~IXGBE_FCTRL_UPE; |
| 1270 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); |
| 1271 | } |
| 1272 | } |
| 1273 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1274 | hw_dbg(hw, "ixgbe_update_uc_addr_list_generic Complete\n"); |
Christopher Leech | 2c5645c | 2008-08-26 04:27:02 -0700 | [diff] [blame] | 1275 | return 0; |
| 1276 | } |
| 1277 | |
| 1278 | /** |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1279 | * ixgbe_mta_vector - Determines bit-vector in multicast table to set |
| 1280 | * @hw: pointer to hardware structure |
| 1281 | * @mc_addr: the multicast address |
| 1282 | * |
| 1283 | * Extracts the 12 bits, from a multicast address, to determine which |
| 1284 | * bit-vector to set in the multicast table. The hardware uses 12 bits, from |
| 1285 | * incoming rx multicast addresses, to determine the bit-vector to check in |
| 1286 | * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1287 | * by the MO field of the MCSTCTRL. The MO field is set during initialization |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1288 | * to mc_filter_type. |
| 1289 | **/ |
| 1290 | static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) |
| 1291 | { |
| 1292 | u32 vector = 0; |
| 1293 | |
| 1294 | switch (hw->mac.mc_filter_type) { |
Peter P Waskiewicz | b461724 | 2008-09-11 20:04:46 -0700 | [diff] [blame] | 1295 | case 0: /* use bits [47:36] of the address */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1296 | vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); |
| 1297 | break; |
Peter P Waskiewicz | b461724 | 2008-09-11 20:04:46 -0700 | [diff] [blame] | 1298 | case 1: /* use bits [46:35] of the address */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1299 | vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); |
| 1300 | break; |
Peter P Waskiewicz | b461724 | 2008-09-11 20:04:46 -0700 | [diff] [blame] | 1301 | case 2: /* use bits [45:34] of the address */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1302 | vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); |
| 1303 | break; |
Peter P Waskiewicz | b461724 | 2008-09-11 20:04:46 -0700 | [diff] [blame] | 1304 | case 3: /* use bits [43:32] of the address */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1305 | vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); |
| 1306 | break; |
Peter P Waskiewicz | b461724 | 2008-09-11 20:04:46 -0700 | [diff] [blame] | 1307 | default: /* Invalid mc_filter_type */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1308 | hw_dbg(hw, "MC filter type param set incorrectly\n"); |
| 1309 | break; |
| 1310 | } |
| 1311 | |
| 1312 | /* vector can only be 12-bits or boundary will be exceeded */ |
| 1313 | vector &= 0xFFF; |
| 1314 | return vector; |
| 1315 | } |
| 1316 | |
| 1317 | /** |
| 1318 | * ixgbe_set_mta - Set bit-vector in multicast table |
| 1319 | * @hw: pointer to hardware structure |
| 1320 | * @hash_value: Multicast address hash value |
| 1321 | * |
| 1322 | * Sets the bit-vector in the multicast table. |
| 1323 | **/ |
| 1324 | static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) |
| 1325 | { |
| 1326 | u32 vector; |
| 1327 | u32 vector_bit; |
| 1328 | u32 vector_reg; |
| 1329 | u32 mta_reg; |
| 1330 | |
| 1331 | hw->addr_ctrl.mta_in_use++; |
| 1332 | |
| 1333 | vector = ixgbe_mta_vector(hw, mc_addr); |
| 1334 | hw_dbg(hw, " bit-vector = 0x%03X\n", vector); |
| 1335 | |
| 1336 | /* |
| 1337 | * The MTA is a register array of 128 32-bit registers. It is treated |
| 1338 | * like an array of 4096 bits. We want to set bit |
| 1339 | * BitArray[vector_value]. So we figure out what register the bit is |
| 1340 | * in, read it, OR in the new bit, then write back the new value. The |
| 1341 | * register is determined by the upper 7 bits of the vector value and |
| 1342 | * the bit within that register are determined by the lower 5 bits of |
| 1343 | * the value. |
| 1344 | */ |
| 1345 | vector_reg = (vector >> 5) & 0x7F; |
| 1346 | vector_bit = vector & 0x1F; |
| 1347 | mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg)); |
| 1348 | mta_reg |= (1 << vector_bit); |
| 1349 | IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg); |
| 1350 | } |
| 1351 | |
| 1352 | /** |
| 1353 | * ixgbe_add_mc_addr - Adds a multicast address. |
| 1354 | * @hw: pointer to hardware structure |
| 1355 | * @mc_addr: new multicast address |
| 1356 | * |
| 1357 | * Adds it to unused receive address register or to the multicast table. |
| 1358 | **/ |
| 1359 | static void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr) |
| 1360 | { |
Christopher Leech | 2c5645c | 2008-08-26 04:27:02 -0700 | [diff] [blame] | 1361 | u32 rar_entries = hw->mac.num_rar_entries; |
Jesse Brandeburg | ce94bf4 | 2008-09-11 19:55:14 -0700 | [diff] [blame] | 1362 | u32 rar; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1363 | |
| 1364 | hw_dbg(hw, " MC Addr =%.2X %.2X %.2X %.2X %.2X %.2X\n", |
Peter P Waskiewicz | b461724 | 2008-09-11 20:04:46 -0700 | [diff] [blame] | 1365 | mc_addr[0], mc_addr[1], mc_addr[2], |
| 1366 | mc_addr[3], mc_addr[4], mc_addr[5]); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1367 | |
| 1368 | /* |
| 1369 | * Place this multicast address in the RAR if there is room, |
| 1370 | * else put it in the MTA |
| 1371 | */ |
| 1372 | if (hw->addr_ctrl.rar_used_count < rar_entries) { |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1373 | /* use RAR from the end up for multicast */ |
Jesse Brandeburg | ce94bf4 | 2008-09-11 19:55:14 -0700 | [diff] [blame] | 1374 | rar = rar_entries - hw->addr_ctrl.mc_addr_in_rar_count - 1; |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1375 | hw->mac.ops.set_rar(hw, rar, mc_addr, 0, IXGBE_RAH_AV); |
| 1376 | hw_dbg(hw, "Added a multicast address to RAR[%d]\n", rar); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1377 | hw->addr_ctrl.rar_used_count++; |
| 1378 | hw->addr_ctrl.mc_addr_in_rar_count++; |
| 1379 | } else { |
| 1380 | ixgbe_set_mta(hw, mc_addr); |
| 1381 | } |
| 1382 | |
| 1383 | hw_dbg(hw, "ixgbe_add_mc_addr Complete\n"); |
| 1384 | } |
| 1385 | |
| 1386 | /** |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1387 | * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1388 | * @hw: pointer to hardware structure |
| 1389 | * @mc_addr_list: the list of new multicast addresses |
| 1390 | * @mc_addr_count: number of addresses |
Christopher Leech | 2c5645c | 2008-08-26 04:27:02 -0700 | [diff] [blame] | 1391 | * @next: iterator function to walk the multicast address list |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1392 | * |
| 1393 | * The given list replaces any existing list. Clears the MC addrs from receive |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1394 | * address registers and the multicast table. Uses unused receive address |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1395 | * registers for the first multicast addresses, and hashes the rest into the |
| 1396 | * multicast table. |
| 1397 | **/ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1398 | s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list, |
Peter P Waskiewicz | b461724 | 2008-09-11 20:04:46 -0700 | [diff] [blame] | 1399 | u32 mc_addr_count, ixgbe_mc_addr_itr next) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1400 | { |
| 1401 | u32 i; |
Christopher Leech | 2c5645c | 2008-08-26 04:27:02 -0700 | [diff] [blame] | 1402 | u32 rar_entries = hw->mac.num_rar_entries; |
| 1403 | u32 vmdq; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1404 | |
| 1405 | /* |
| 1406 | * Set the new number of MC addresses that we are being requested to |
| 1407 | * use. |
| 1408 | */ |
| 1409 | hw->addr_ctrl.num_mc_addrs = mc_addr_count; |
| 1410 | hw->addr_ctrl.rar_used_count -= hw->addr_ctrl.mc_addr_in_rar_count; |
| 1411 | hw->addr_ctrl.mc_addr_in_rar_count = 0; |
| 1412 | hw->addr_ctrl.mta_in_use = 0; |
| 1413 | |
| 1414 | /* Zero out the other receive addresses. */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1415 | hw_dbg(hw, "Clearing RAR[%d-%d]\n", hw->addr_ctrl.rar_used_count, |
| 1416 | rar_entries - 1); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1417 | for (i = hw->addr_ctrl.rar_used_count; i < rar_entries; i++) { |
| 1418 | IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); |
| 1419 | IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); |
| 1420 | } |
| 1421 | |
| 1422 | /* Clear the MTA */ |
| 1423 | hw_dbg(hw, " Clearing MTA\n"); |
Christopher Leech | 2c5645c | 2008-08-26 04:27:02 -0700 | [diff] [blame] | 1424 | for (i = 0; i < hw->mac.mcft_size; i++) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1425 | IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); |
| 1426 | |
| 1427 | /* Add the new addresses */ |
| 1428 | for (i = 0; i < mc_addr_count; i++) { |
| 1429 | hw_dbg(hw, " Adding the multicast addresses:\n"); |
Christopher Leech | 2c5645c | 2008-08-26 04:27:02 -0700 | [diff] [blame] | 1430 | ixgbe_add_mc_addr(hw, next(hw, &mc_addr_list, &vmdq)); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1431 | } |
| 1432 | |
| 1433 | /* Enable mta */ |
| 1434 | if (hw->addr_ctrl.mta_in_use > 0) |
| 1435 | IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, |
Peter P Waskiewicz | b461724 | 2008-09-11 20:04:46 -0700 | [diff] [blame] | 1436 | IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1437 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1438 | hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n"); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1439 | return 0; |
| 1440 | } |
| 1441 | |
| 1442 | /** |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1443 | * ixgbe_enable_mc_generic - Enable multicast address in RAR |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1444 | * @hw: pointer to hardware structure |
| 1445 | * |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1446 | * Enables multicast address in RAR and the use of the multicast hash table. |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1447 | **/ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1448 | s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1449 | { |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1450 | u32 i; |
| 1451 | u32 rar_entries = hw->mac.num_rar_entries; |
| 1452 | struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1453 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1454 | if (a->mc_addr_in_rar_count > 0) |
| 1455 | for (i = (rar_entries - a->mc_addr_in_rar_count); |
| 1456 | i < rar_entries; i++) |
| 1457 | ixgbe_enable_rar(hw, i); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1458 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1459 | if (a->mta_in_use > 0) |
| 1460 | IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | |
| 1461 | hw->mac.mc_filter_type); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1462 | |
| 1463 | return 0; |
| 1464 | } |
| 1465 | |
| 1466 | /** |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1467 | * ixgbe_disable_mc_generic - Disable multicast address in RAR |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1468 | * @hw: pointer to hardware structure |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1469 | * |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1470 | * Disables multicast address in RAR and the use of the multicast hash table. |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1471 | **/ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1472 | s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1473 | { |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1474 | u32 i; |
| 1475 | u32 rar_entries = hw->mac.num_rar_entries; |
| 1476 | struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1477 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1478 | if (a->mc_addr_in_rar_count > 0) |
| 1479 | for (i = (rar_entries - a->mc_addr_in_rar_count); |
| 1480 | i < rar_entries; i++) |
| 1481 | ixgbe_disable_rar(hw, i); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1482 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1483 | if (a->mta_in_use > 0) |
| 1484 | IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1485 | |
| 1486 | return 0; |
| 1487 | } |
| 1488 | |
| 1489 | /** |
| 1490 | * ixgbe_disable_pcie_master - Disable PCI-express master access |
| 1491 | * @hw: pointer to hardware structure |
| 1492 | * |
| 1493 | * Disables PCI-Express master access and verifies there are no pending |
| 1494 | * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable |
| 1495 | * bit hasn't caused the master requests to be disabled, else 0 |
| 1496 | * is returned signifying master requests disabled. |
| 1497 | **/ |
| 1498 | s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) |
| 1499 | { |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1500 | u32 i; |
| 1501 | u32 reg_val; |
| 1502 | u32 number_of_queues; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1503 | s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; |
| 1504 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1505 | /* Disable the receive unit by stopping each queue */ |
| 1506 | number_of_queues = hw->mac.max_rx_queues; |
| 1507 | for (i = 0; i < number_of_queues; i++) { |
| 1508 | reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); |
| 1509 | if (reg_val & IXGBE_RXDCTL_ENABLE) { |
| 1510 | reg_val &= ~IXGBE_RXDCTL_ENABLE; |
| 1511 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); |
| 1512 | } |
| 1513 | } |
| 1514 | |
| 1515 | reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL); |
| 1516 | reg_val |= IXGBE_CTRL_GIO_DIS; |
| 1517 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1518 | |
| 1519 | for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { |
| 1520 | if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) { |
| 1521 | status = 0; |
| 1522 | break; |
| 1523 | } |
| 1524 | udelay(100); |
| 1525 | } |
| 1526 | |
| 1527 | return status; |
| 1528 | } |
| 1529 | |
| 1530 | |
| 1531 | /** |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1532 | * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1533 | * @hw: pointer to hardware structure |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1534 | * @mask: Mask to specify which semaphore to acquire |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1535 | * |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1536 | * Acquires the SWFW semaphore thought the GSSR register for the specified |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1537 | * function (CSR, PHY0, PHY1, EEPROM, Flash) |
| 1538 | **/ |
| 1539 | s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask) |
| 1540 | { |
| 1541 | u32 gssr; |
| 1542 | u32 swmask = mask; |
| 1543 | u32 fwmask = mask << 5; |
| 1544 | s32 timeout = 200; |
| 1545 | |
| 1546 | while (timeout) { |
| 1547 | if (ixgbe_get_eeprom_semaphore(hw)) |
| 1548 | return -IXGBE_ERR_SWFW_SYNC; |
| 1549 | |
| 1550 | gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); |
| 1551 | if (!(gssr & (fwmask | swmask))) |
| 1552 | break; |
| 1553 | |
| 1554 | /* |
| 1555 | * Firmware currently using resource (fwmask) or other software |
| 1556 | * thread currently using resource (swmask) |
| 1557 | */ |
| 1558 | ixgbe_release_eeprom_semaphore(hw); |
| 1559 | msleep(5); |
| 1560 | timeout--; |
| 1561 | } |
| 1562 | |
| 1563 | if (!timeout) { |
| 1564 | hw_dbg(hw, "Driver can't access resource, GSSR timeout.\n"); |
| 1565 | return -IXGBE_ERR_SWFW_SYNC; |
| 1566 | } |
| 1567 | |
| 1568 | gssr |= swmask; |
| 1569 | IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); |
| 1570 | |
| 1571 | ixgbe_release_eeprom_semaphore(hw); |
| 1572 | return 0; |
| 1573 | } |
| 1574 | |
| 1575 | /** |
| 1576 | * ixgbe_release_swfw_sync - Release SWFW semaphore |
| 1577 | * @hw: pointer to hardware structure |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1578 | * @mask: Mask to specify which semaphore to release |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1579 | * |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 1580 | * Releases the SWFW semaphore thought the GSSR register for the specified |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1581 | * function (CSR, PHY0, PHY1, EEPROM, Flash) |
| 1582 | **/ |
| 1583 | void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask) |
| 1584 | { |
| 1585 | u32 gssr; |
| 1586 | u32 swmask = mask; |
| 1587 | |
| 1588 | ixgbe_get_eeprom_semaphore(hw); |
| 1589 | |
| 1590 | gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); |
| 1591 | gssr &= ~swmask; |
| 1592 | IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); |
| 1593 | |
| 1594 | ixgbe_release_eeprom_semaphore(hw); |
| 1595 | } |
| 1596 | |