blob: 0419f52846094950b333c48675991a0a267c1e5a [file] [log] [blame]
Ray Juie6e5dd32015-02-07 21:25:24 -08001/*
2 * Copyright (C) 2014 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/delay.h>
15#include <linux/i2c.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/platform_device.h>
21#include <linux/slab.h>
22
23#define CFG_OFFSET 0x00
24#define CFG_RESET_SHIFT 31
25#define CFG_EN_SHIFT 30
26#define CFG_M_RETRY_CNT_SHIFT 16
27#define CFG_M_RETRY_CNT_MASK 0x0f
28
29#define TIM_CFG_OFFSET 0x04
30#define TIM_CFG_MODE_400_SHIFT 31
31
32#define M_FIFO_CTRL_OFFSET 0x0c
33#define M_FIFO_RX_FLUSH_SHIFT 31
34#define M_FIFO_TX_FLUSH_SHIFT 30
35#define M_FIFO_RX_CNT_SHIFT 16
36#define M_FIFO_RX_CNT_MASK 0x7f
37#define M_FIFO_RX_THLD_SHIFT 8
38#define M_FIFO_RX_THLD_MASK 0x3f
39
40#define M_CMD_OFFSET 0x30
41#define M_CMD_START_BUSY_SHIFT 31
42#define M_CMD_STATUS_SHIFT 25
43#define M_CMD_STATUS_MASK 0x07
44#define M_CMD_STATUS_SUCCESS 0x0
45#define M_CMD_STATUS_LOST_ARB 0x1
46#define M_CMD_STATUS_NACK_ADDR 0x2
47#define M_CMD_STATUS_NACK_DATA 0x3
48#define M_CMD_STATUS_TIMEOUT 0x4
49#define M_CMD_PROTOCOL_SHIFT 9
50#define M_CMD_PROTOCOL_MASK 0xf
51#define M_CMD_PROTOCOL_BLK_WR 0x7
52#define M_CMD_PROTOCOL_BLK_RD 0x8
53#define M_CMD_PEC_SHIFT 8
54#define M_CMD_RD_CNT_SHIFT 0
55#define M_CMD_RD_CNT_MASK 0xff
56
57#define IE_OFFSET 0x38
58#define IE_M_RX_FIFO_FULL_SHIFT 31
59#define IE_M_RX_THLD_SHIFT 30
60#define IE_M_START_BUSY_SHIFT 28
61
62#define IS_OFFSET 0x3c
63#define IS_M_RX_FIFO_FULL_SHIFT 31
64#define IS_M_RX_THLD_SHIFT 30
65#define IS_M_START_BUSY_SHIFT 28
66
67#define M_TX_OFFSET 0x40
68#define M_TX_WR_STATUS_SHIFT 31
69#define M_TX_DATA_SHIFT 0
70#define M_TX_DATA_MASK 0xff
71
72#define M_RX_OFFSET 0x44
73#define M_RX_STATUS_SHIFT 30
74#define M_RX_STATUS_MASK 0x03
75#define M_RX_PEC_ERR_SHIFT 29
76#define M_RX_DATA_SHIFT 0
77#define M_RX_DATA_MASK 0xff
78
79#define I2C_TIMEOUT_MESC 100
80#define M_TX_RX_FIFO_SIZE 64
81
82enum bus_speed_index {
83 I2C_SPD_100K = 0,
84 I2C_SPD_400K,
85};
86
87struct bcm_iproc_i2c_dev {
88 struct device *device;
89 int irq;
90
91 void __iomem *base;
92
93 struct i2c_adapter adapter;
Ray Jui0ee04e92015-05-14 15:36:04 -070094 unsigned int bus_speed;
Ray Juie6e5dd32015-02-07 21:25:24 -080095
96 struct completion done;
97 int xfer_is_done;
98};
99
100/*
101 * Can be expanded in the future if more interrupt status bits are utilized
102 */
103#define ISR_MASK (1 << IS_M_START_BUSY_SHIFT)
104
105static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data)
106{
107 struct bcm_iproc_i2c_dev *iproc_i2c = data;
108 u32 status = readl(iproc_i2c->base + IS_OFFSET);
109
110 status &= ISR_MASK;
111
112 if (!status)
113 return IRQ_NONE;
114
115 writel(status, iproc_i2c->base + IS_OFFSET);
116 iproc_i2c->xfer_is_done = 1;
117 complete_all(&iproc_i2c->done);
118
119 return IRQ_HANDLED;
120}
121
122static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c,
123 struct i2c_msg *msg)
124{
125 u32 val;
126
127 val = readl(iproc_i2c->base + M_CMD_OFFSET);
128 val = (val >> M_CMD_STATUS_SHIFT) & M_CMD_STATUS_MASK;
129
130 switch (val) {
131 case M_CMD_STATUS_SUCCESS:
132 return 0;
133
134 case M_CMD_STATUS_LOST_ARB:
135 dev_dbg(iproc_i2c->device, "lost bus arbitration\n");
136 return -EAGAIN;
137
138 case M_CMD_STATUS_NACK_ADDR:
139 dev_dbg(iproc_i2c->device, "NAK addr:0x%02x\n", msg->addr);
140 return -ENXIO;
141
142 case M_CMD_STATUS_NACK_DATA:
143 dev_dbg(iproc_i2c->device, "NAK data\n");
144 return -ENXIO;
145
146 case M_CMD_STATUS_TIMEOUT:
147 dev_dbg(iproc_i2c->device, "bus timeout\n");
148 return -ETIMEDOUT;
149
150 default:
151 dev_dbg(iproc_i2c->device, "unknown error code=%d\n", val);
152 return -EIO;
153 }
154}
155
156static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c,
157 struct i2c_msg *msg)
158{
159 int ret, i;
160 u8 addr;
161 u32 val;
162 unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT_MESC);
163
Ray Juie6e5dd32015-02-07 21:25:24 -0800164 /* check if bus is busy */
165 if (!!(readl(iproc_i2c->base + M_CMD_OFFSET) &
166 BIT(M_CMD_START_BUSY_SHIFT))) {
167 dev_warn(iproc_i2c->device, "bus is busy\n");
168 return -EBUSY;
169 }
170
171 /* format and load slave address into the TX FIFO */
172 addr = msg->addr << 1 | (msg->flags & I2C_M_RD ? 1 : 0);
173 writel(addr, iproc_i2c->base + M_TX_OFFSET);
174
175 /* for a write transaction, load data into the TX FIFO */
176 if (!(msg->flags & I2C_M_RD)) {
177 for (i = 0; i < msg->len; i++) {
178 val = msg->buf[i];
179
180 /* mark the last byte */
181 if (i == msg->len - 1)
182 val |= 1 << M_TX_WR_STATUS_SHIFT;
183
184 writel(val, iproc_i2c->base + M_TX_OFFSET);
185 }
186 }
187
188 /* mark as incomplete before starting the transaction */
189 reinit_completion(&iproc_i2c->done);
190 iproc_i2c->xfer_is_done = 0;
191
192 /*
193 * Enable the "start busy" interrupt, which will be triggered after the
194 * transaction is done, i.e., the internal start_busy bit, transitions
195 * from 1 to 0.
196 */
197 writel(1 << IE_M_START_BUSY_SHIFT, iproc_i2c->base + IE_OFFSET);
198
199 /*
200 * Now we can activate the transfer. For a read operation, specify the
201 * number of bytes to read
202 */
203 val = 1 << M_CMD_START_BUSY_SHIFT;
204 if (msg->flags & I2C_M_RD) {
205 val |= (M_CMD_PROTOCOL_BLK_RD << M_CMD_PROTOCOL_SHIFT) |
206 (msg->len << M_CMD_RD_CNT_SHIFT);
207 } else {
208 val |= (M_CMD_PROTOCOL_BLK_WR << M_CMD_PROTOCOL_SHIFT);
209 }
210 writel(val, iproc_i2c->base + M_CMD_OFFSET);
211
212 time_left = wait_for_completion_timeout(&iproc_i2c->done, time_left);
213
214 /* disable all interrupts */
215 writel(0, iproc_i2c->base + IE_OFFSET);
216 /* read it back to flush the write */
217 readl(iproc_i2c->base + IE_OFFSET);
218
219 /* make sure the interrupt handler isn't running */
220 synchronize_irq(iproc_i2c->irq);
221
222 if (!time_left && !iproc_i2c->xfer_is_done) {
223 dev_err(iproc_i2c->device, "transaction timed out\n");
224
225 /* flush FIFOs */
226 val = (1 << M_FIFO_RX_FLUSH_SHIFT) |
227 (1 << M_FIFO_TX_FLUSH_SHIFT);
228 writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET);
229 return -ETIMEDOUT;
230 }
231
232 ret = bcm_iproc_i2c_check_status(iproc_i2c, msg);
233 if (ret) {
234 /* flush both TX/RX FIFOs */
235 val = (1 << M_FIFO_RX_FLUSH_SHIFT) |
236 (1 << M_FIFO_TX_FLUSH_SHIFT);
237 writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET);
238 return ret;
239 }
240
241 /*
242 * For a read operation, we now need to load the data from FIFO
243 * into the memory buffer
244 */
245 if (msg->flags & I2C_M_RD) {
246 for (i = 0; i < msg->len; i++) {
247 msg->buf[i] = (readl(iproc_i2c->base + M_RX_OFFSET) >>
248 M_RX_DATA_SHIFT) & M_RX_DATA_MASK;
249 }
250 }
251
252 return 0;
253}
254
255static int bcm_iproc_i2c_xfer(struct i2c_adapter *adapter,
256 struct i2c_msg msgs[], int num)
257{
258 struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(adapter);
259 int ret, i;
260
261 /* go through all messages */
262 for (i = 0; i < num; i++) {
263 ret = bcm_iproc_i2c_xfer_single_msg(iproc_i2c, &msgs[i]);
264 if (ret) {
265 dev_dbg(iproc_i2c->device, "xfer failed\n");
266 return ret;
267 }
268 }
269
270 return num;
271}
272
273static uint32_t bcm_iproc_i2c_functionality(struct i2c_adapter *adap)
274{
275 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
276}
277
278static const struct i2c_algorithm bcm_iproc_algo = {
279 .master_xfer = bcm_iproc_i2c_xfer,
280 .functionality = bcm_iproc_i2c_functionality,
281};
282
Wolfram Sang338f1ab2015-01-07 12:24:10 +0100283static struct i2c_adapter_quirks bcm_iproc_i2c_quirks = {
284 /* need to reserve one byte in the FIFO for the slave address */
285 .max_read_len = M_TX_RX_FIFO_SIZE - 1,
286 .max_write_len = M_TX_RX_FIFO_SIZE - 1,
287};
288
Ray Juie6e5dd32015-02-07 21:25:24 -0800289static int bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev *iproc_i2c)
290{
291 unsigned int bus_speed;
292 u32 val;
293 int ret = of_property_read_u32(iproc_i2c->device->of_node,
294 "clock-frequency", &bus_speed);
295 if (ret < 0) {
296 dev_info(iproc_i2c->device,
297 "unable to interpret clock-frequency DT property\n");
298 bus_speed = 100000;
299 }
300
301 if (bus_speed < 100000) {
302 dev_err(iproc_i2c->device, "%d Hz bus speed not supported\n",
303 bus_speed);
304 dev_err(iproc_i2c->device,
305 "valid speeds are 100khz and 400khz\n");
306 return -EINVAL;
307 } else if (bus_speed < 400000) {
308 bus_speed = 100000;
309 } else {
310 bus_speed = 400000;
311 }
312
Ray Jui0ee04e92015-05-14 15:36:04 -0700313 iproc_i2c->bus_speed = bus_speed;
Ray Juie6e5dd32015-02-07 21:25:24 -0800314 val = readl(iproc_i2c->base + TIM_CFG_OFFSET);
315 val &= ~(1 << TIM_CFG_MODE_400_SHIFT);
316 val |= (bus_speed == 400000) << TIM_CFG_MODE_400_SHIFT;
317 writel(val, iproc_i2c->base + TIM_CFG_OFFSET);
318
319 dev_info(iproc_i2c->device, "bus set to %u Hz\n", bus_speed);
320
321 return 0;
322}
323
324static int bcm_iproc_i2c_init(struct bcm_iproc_i2c_dev *iproc_i2c)
325{
326 u32 val;
327
328 /* put controller in reset */
329 val = readl(iproc_i2c->base + CFG_OFFSET);
330 val |= 1 << CFG_RESET_SHIFT;
331 val &= ~(1 << CFG_EN_SHIFT);
332 writel(val, iproc_i2c->base + CFG_OFFSET);
333
334 /* wait 100 usec per spec */
335 udelay(100);
336
337 /* bring controller out of reset */
338 val &= ~(1 << CFG_RESET_SHIFT);
339 writel(val, iproc_i2c->base + CFG_OFFSET);
340
341 /* flush TX/RX FIFOs and set RX FIFO threshold to zero */
342 val = (1 << M_FIFO_RX_FLUSH_SHIFT) | (1 << M_FIFO_TX_FLUSH_SHIFT);
343 writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET);
344
345 /* disable all interrupts */
346 writel(0, iproc_i2c->base + IE_OFFSET);
347
348 /* clear all pending interrupts */
349 writel(0xffffffff, iproc_i2c->base + IS_OFFSET);
350
351 return 0;
352}
353
354static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,
355 bool enable)
356{
357 u32 val;
358
359 val = readl(iproc_i2c->base + CFG_OFFSET);
360 if (enable)
361 val |= BIT(CFG_EN_SHIFT);
362 else
363 val &= ~BIT(CFG_EN_SHIFT);
364 writel(val, iproc_i2c->base + CFG_OFFSET);
365}
366
367static int bcm_iproc_i2c_probe(struct platform_device *pdev)
368{
369 int irq, ret = 0;
370 struct bcm_iproc_i2c_dev *iproc_i2c;
371 struct i2c_adapter *adap;
372 struct resource *res;
373
374 iproc_i2c = devm_kzalloc(&pdev->dev, sizeof(*iproc_i2c),
375 GFP_KERNEL);
376 if (!iproc_i2c)
377 return -ENOMEM;
378
379 platform_set_drvdata(pdev, iproc_i2c);
380 iproc_i2c->device = &pdev->dev;
381 init_completion(&iproc_i2c->done);
382
383 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
384 iproc_i2c->base = devm_ioremap_resource(iproc_i2c->device, res);
385 if (IS_ERR(iproc_i2c->base))
386 return PTR_ERR(iproc_i2c->base);
387
388 ret = bcm_iproc_i2c_init(iproc_i2c);
389 if (ret)
390 return ret;
391
392 ret = bcm_iproc_i2c_cfg_speed(iproc_i2c);
393 if (ret)
394 return ret;
395
396 irq = platform_get_irq(pdev, 0);
397 if (irq <= 0) {
398 dev_err(iproc_i2c->device, "no irq resource\n");
399 return irq;
400 }
401 iproc_i2c->irq = irq;
402
403 ret = devm_request_irq(iproc_i2c->device, irq, bcm_iproc_i2c_isr, 0,
404 pdev->name, iproc_i2c);
405 if (ret < 0) {
406 dev_err(iproc_i2c->device, "unable to request irq %i\n", irq);
407 return ret;
408 }
409
410 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
411
412 adap = &iproc_i2c->adapter;
413 i2c_set_adapdata(adap, iproc_i2c);
414 strlcpy(adap->name, "Broadcom iProc I2C adapter", sizeof(adap->name));
415 adap->algo = &bcm_iproc_algo;
Wolfram Sang338f1ab2015-01-07 12:24:10 +0100416 adap->quirks = &bcm_iproc_i2c_quirks;
Ray Juie6e5dd32015-02-07 21:25:24 -0800417 adap->dev.parent = &pdev->dev;
418 adap->dev.of_node = pdev->dev.of_node;
419
420 ret = i2c_add_adapter(adap);
421 if (ret) {
422 dev_err(iproc_i2c->device, "failed to add adapter\n");
423 return ret;
424 }
425
426 return 0;
427}
428
429static int bcm_iproc_i2c_remove(struct platform_device *pdev)
430{
431 struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev);
432
433 /* make sure there's no pending interrupt when we remove the adapter */
434 writel(0, iproc_i2c->base + IE_OFFSET);
435 readl(iproc_i2c->base + IE_OFFSET);
436 synchronize_irq(iproc_i2c->irq);
437
438 i2c_del_adapter(&iproc_i2c->adapter);
439 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
440
441 return 0;
442}
443
Ray Jui0ee04e92015-05-14 15:36:04 -0700444#ifdef CONFIG_PM_SLEEP
445
446static int bcm_iproc_i2c_suspend(struct device *dev)
447{
448 struct platform_device *pdev = to_platform_device(dev);
449 struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev);
450
451 /* make sure there's no pending interrupt when we go into suspend */
452 writel(0, iproc_i2c->base + IE_OFFSET);
453 readl(iproc_i2c->base + IE_OFFSET);
454 synchronize_irq(iproc_i2c->irq);
455
456 /* now disable the controller */
457 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
458
459 return 0;
460}
461
462static int bcm_iproc_i2c_resume(struct device *dev)
463{
464 struct platform_device *pdev = to_platform_device(dev);
465 struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev);
466 int ret;
467 u32 val;
468
469 /*
470 * Power domain could have been shut off completely in system deep
471 * sleep, so re-initialize the block here
472 */
473 ret = bcm_iproc_i2c_init(iproc_i2c);
474 if (ret)
475 return ret;
476
477 /* configure to the desired bus speed */
478 val = readl(iproc_i2c->base + TIM_CFG_OFFSET);
479 val &= ~(1 << TIM_CFG_MODE_400_SHIFT);
480 val |= (iproc_i2c->bus_speed == 400000) << TIM_CFG_MODE_400_SHIFT;
481 writel(val, iproc_i2c->base + TIM_CFG_OFFSET);
482
483 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
484
485 return 0;
486}
487
488static const struct dev_pm_ops bcm_iproc_i2c_pm_ops = {
489 .suspend_late = &bcm_iproc_i2c_suspend,
490 .resume_early = &bcm_iproc_i2c_resume
491};
492
493#define BCM_IPROC_I2C_PM_OPS (&bcm_iproc_i2c_pm_ops)
494#else
495#define BCM_IPROC_I2C_PM_OPS NULL
496#endif /* CONFIG_PM_SLEEP */
497
Ray Juie6e5dd32015-02-07 21:25:24 -0800498static const struct of_device_id bcm_iproc_i2c_of_match[] = {
499 { .compatible = "brcm,iproc-i2c" },
500 { /* sentinel */ }
501};
502MODULE_DEVICE_TABLE(of, bcm_iproc_i2c_of_match);
503
504static struct platform_driver bcm_iproc_i2c_driver = {
505 .driver = {
506 .name = "bcm-iproc-i2c",
507 .of_match_table = bcm_iproc_i2c_of_match,
Ray Jui0ee04e92015-05-14 15:36:04 -0700508 .pm = BCM_IPROC_I2C_PM_OPS,
Ray Juie6e5dd32015-02-07 21:25:24 -0800509 },
510 .probe = bcm_iproc_i2c_probe,
511 .remove = bcm_iproc_i2c_remove,
512};
513module_platform_driver(bcm_iproc_i2c_driver);
514
515MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
516MODULE_DESCRIPTION("Broadcom iProc I2C Driver");
517MODULE_LICENSE("GPL v2");