blob: c1ee8b4d2144e64d92777475d29738b83618fd10 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
Ralf Baechle010b8532006-01-29 18:42:08 +00005 * Copyright (C) 1994 - 2006 Ralf Baechle
Ralf Baechle41943182005-05-05 16:45:59 +00006 * Copyright (C) 2003, 2004 Maciej W. Rozycki
Ralf Baechle70342282013-01-22 12:59:30 +01007 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07008 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070014#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
Ralf Baechle631330f2009-06-19 14:05:26 +010017#include <linux/smp.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070018#include <linux/stddef.h>
Paul Gortmaker73bc2562011-07-23 16:30:40 -040019#include <linux/export.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070020
Ralf Baechle57599062007-02-18 19:07:31 +000021#include <asm/bugs.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070022#include <asm/cpu.h>
Ralf Baechle69f24d12013-09-17 10:25:47 +020023#include <asm/cpu-type.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070024#include <asm/fpu.h>
25#include <asm/mipsregs.h>
David Daney654f57b2008-09-23 00:07:16 -070026#include <asm/watch.h>
Paul Gortmaker06372a62011-07-23 16:26:41 -040027#include <asm/elf.h>
Chris Dearmana074f0e2009-07-10 01:51:27 -070028#include <asm/spram.h>
David Daney949e51b2010-10-14 11:32:33 -070029#include <asm/uaccess.h>
30
Paul Gortmaker078a55f2013-06-18 13:38:59 +000031static int mips_fpu_disabled;
Kevin Cernekee0103d232010-05-02 14:43:52 -070032
33static int __init fpu_disable(char *s)
34{
35 cpu_data[0].options &= ~MIPS_CPU_FPU;
36 mips_fpu_disabled = 1;
37
38 return 1;
39}
40
41__setup("nofpu", fpu_disable);
42
Paul Gortmaker078a55f2013-06-18 13:38:59 +000043int mips_dsp_disabled;
Kevin Cernekee0103d232010-05-02 14:43:52 -070044
45static int __init dsp_disable(char *s)
46{
Steven J. Hillee80f7c72012-08-03 10:26:04 -050047 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
Kevin Cernekee0103d232010-05-02 14:43:52 -070048 mips_dsp_disabled = 1;
49
50 return 1;
51}
52
53__setup("nodsp", dsp_disable);
54
Marc St-Jean9267a302007-06-14 15:55:31 -060055static inline void check_errata(void)
56{
57 struct cpuinfo_mips *c = &current_cpu_data;
58
Ralf Baechle69f24d12013-09-17 10:25:47 +020059 switch (current_cpu_type()) {
Marc St-Jean9267a302007-06-14 15:55:31 -060060 case CPU_34K:
61 /*
62 * Erratum "RPS May Cause Incorrect Instruction Execution"
63 * This code only handles VPE0, any SMP/SMTC/RTOS code
64 * making use of VPE1 will be responsable for that VPE.
65 */
66 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
67 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
68 break;
69 default:
70 break;
71 }
72}
73
Linus Torvalds1da177e2005-04-16 15:20:36 -070074void __init check_bugs32(void)
75{
Marc St-Jean9267a302007-06-14 15:55:31 -060076 check_errata();
Linus Torvalds1da177e2005-04-16 15:20:36 -070077}
78
79/*
80 * Probe whether cpu has config register by trying to play with
81 * alternate cache bit and see whether it matters.
82 * It's used by cpu_probe to distinguish between R3000A and R3081.
83 */
84static inline int cpu_has_confreg(void)
85{
86#ifdef CONFIG_CPU_R3000
87 extern unsigned long r3k_cache_size(unsigned long);
88 unsigned long size1, size2;
89 unsigned long cfg = read_c0_conf();
90
91 size1 = r3k_cache_size(ST0_ISC);
92 write_c0_conf(cfg ^ R30XX_CONF_AC);
93 size2 = r3k_cache_size(ST0_ISC);
94 write_c0_conf(cfg);
95 return size1 != size2;
96#else
97 return 0;
98#endif
99}
100
Robert Millanc094c992011-04-18 11:37:55 -0700101static inline void set_elf_platform(int cpu, const char *plat)
102{
103 if (cpu == 0)
104 __elf_platform = plat;
105}
106
Linus Torvalds1da177e2005-04-16 15:20:36 -0700107/*
108 * Get the FPU Implementation/Revision.
109 */
110static inline unsigned long cpu_get_fpu_id(void)
111{
112 unsigned long tmp, fpu_id;
113
114 tmp = read_c0_status();
Paul Burton597ce172013-11-22 13:12:07 +0000115 __enable_fpu(FPU_AS_IS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700116 fpu_id = read_32bit_cp1_register(CP1_REVISION);
117 write_c0_status(tmp);
118 return fpu_id;
119}
120
121/*
122 * Check the CPU has an FPU the official way.
123 */
124static inline int __cpu_has_fpu(void)
125{
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100126 return ((cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700127}
128
Guenter Roeck91dfc422010-02-02 08:52:20 -0800129static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
130{
131#ifdef __NEED_VMBITS_PROBE
David Daney5b7efa82010-02-08 12:27:00 -0800132 write_c0_entryhi(0x3fffffffffffe000ULL);
Guenter Roeck91dfc422010-02-02 08:52:20 -0800133 back_to_back_c0_hazard();
David Daney5b7efa82010-02-08 12:27:00 -0800134 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
Guenter Roeck91dfc422010-02-02 08:52:20 -0800135#endif
136}
137
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000138static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
Steven J. Hilla96102b2012-12-07 04:31:36 +0000139{
140 switch (isa) {
141 case MIPS_CPU_ISA_M64R2:
142 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
143 case MIPS_CPU_ISA_M64R1:
144 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
145 case MIPS_CPU_ISA_V:
146 c->isa_level |= MIPS_CPU_ISA_V;
147 case MIPS_CPU_ISA_IV:
148 c->isa_level |= MIPS_CPU_ISA_IV;
149 case MIPS_CPU_ISA_III:
Ralf Baechle1990e542013-06-26 17:06:34 +0200150 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
Steven J. Hilla96102b2012-12-07 04:31:36 +0000151 break;
152
153 case MIPS_CPU_ISA_M32R2:
154 c->isa_level |= MIPS_CPU_ISA_M32R2;
155 case MIPS_CPU_ISA_M32R1:
156 c->isa_level |= MIPS_CPU_ISA_M32R1;
157 case MIPS_CPU_ISA_II:
158 c->isa_level |= MIPS_CPU_ISA_II;
Steven J. Hilla96102b2012-12-07 04:31:36 +0000159 break;
160 }
161}
162
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000163static char unknown_isa[] = KERN_ERR \
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100164 "Unsupported ISA type, c0.config0: %d.";
165
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +0000166static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
167{
168 unsigned int config6;
169 /*
170 * Config6 is implementation dependent and it's currently only
171 * used by proAptiv
172 */
173 if (c->cputype == CPU_PROAPTIV) {
174 config6 = read_c0_config6();
175 if (enable)
176 /* Enable FTLB */
177 write_c0_config6(config6 | MIPS_CONF6_FTLBEN);
178 else
179 /* Disable FTLB */
180 write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN);
181 back_to_back_c0_hazard();
182 }
183}
184
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100185static inline unsigned int decode_config0(struct cpuinfo_mips *c)
186{
187 unsigned int config0;
188 int isa;
189
190 config0 = read_c0_config();
191
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +0000192 /*
193 * Look for Standard TLB or Dual VTLB and FTLB
194 */
195 if ((((config0 & MIPS_CONF_MT) >> 7) == 1) ||
196 (((config0 & MIPS_CONF_MT) >> 7) == 4))
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100197 c->options |= MIPS_CPU_TLB;
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +0000198
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100199 isa = (config0 & MIPS_CONF_AT) >> 13;
200 switch (isa) {
201 case 0:
202 switch ((config0 & MIPS_CONF_AR) >> 10) {
203 case 0:
Steven J. Hilla96102b2012-12-07 04:31:36 +0000204 set_isa(c, MIPS_CPU_ISA_M32R1);
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100205 break;
206 case 1:
Steven J. Hilla96102b2012-12-07 04:31:36 +0000207 set_isa(c, MIPS_CPU_ISA_M32R2);
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100208 break;
209 default:
210 goto unknown;
211 }
212 break;
213 case 2:
214 switch ((config0 & MIPS_CONF_AR) >> 10) {
215 case 0:
Steven J. Hilla96102b2012-12-07 04:31:36 +0000216 set_isa(c, MIPS_CPU_ISA_M64R1);
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100217 break;
218 case 1:
Steven J. Hilla96102b2012-12-07 04:31:36 +0000219 set_isa(c, MIPS_CPU_ISA_M64R2);
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100220 break;
221 default:
222 goto unknown;
223 }
224 break;
225 default:
226 goto unknown;
227 }
228
229 return config0 & MIPS_CONF_M;
230
231unknown:
232 panic(unknown_isa, config0);
233}
234
235static inline unsigned int decode_config1(struct cpuinfo_mips *c)
236{
237 unsigned int config1;
238
239 config1 = read_c0_config1();
240
241 if (config1 & MIPS_CONF1_MD)
242 c->ases |= MIPS_ASE_MDMX;
243 if (config1 & MIPS_CONF1_WR)
244 c->options |= MIPS_CPU_WATCH;
245 if (config1 & MIPS_CONF1_CA)
246 c->ases |= MIPS_ASE_MIPS16;
247 if (config1 & MIPS_CONF1_EP)
248 c->options |= MIPS_CPU_EJTAG;
249 if (config1 & MIPS_CONF1_FP) {
250 c->options |= MIPS_CPU_FPU;
251 c->options |= MIPS_CPU_32FPR;
252 }
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +0000253 if (cpu_has_tlb) {
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100254 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +0000255 c->tlbsizevtlb = c->tlbsize;
256 c->tlbsizeftlbsets = 0;
257 }
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100258
259 return config1 & MIPS_CONF_M;
260}
261
262static inline unsigned int decode_config2(struct cpuinfo_mips *c)
263{
264 unsigned int config2;
265
266 config2 = read_c0_config2();
267
268 if (config2 & MIPS_CONF2_SL)
269 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
270
271 return config2 & MIPS_CONF_M;
272}
273
274static inline unsigned int decode_config3(struct cpuinfo_mips *c)
275{
276 unsigned int config3;
277
278 config3 = read_c0_config3();
279
Steven J. Hillb2ab4f02012-09-13 16:47:58 -0500280 if (config3 & MIPS_CONF3_SM) {
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100281 c->ases |= MIPS_ASE_SMARTMIPS;
Steven J. Hillb2ab4f02012-09-13 16:47:58 -0500282 c->options |= MIPS_CPU_RIXI;
283 }
284 if (config3 & MIPS_CONF3_RXI)
285 c->options |= MIPS_CPU_RIXI;
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100286 if (config3 & MIPS_CONF3_DSP)
287 c->ases |= MIPS_ASE_DSP;
Steven J. Hillee80f7c72012-08-03 10:26:04 -0500288 if (config3 & MIPS_CONF3_DSP2P)
289 c->ases |= MIPS_ASE_DSP2P;
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100290 if (config3 & MIPS_CONF3_VINT)
291 c->options |= MIPS_CPU_VINT;
292 if (config3 & MIPS_CONF3_VEIC)
293 c->options |= MIPS_CPU_VEIC;
294 if (config3 & MIPS_CONF3_MT)
295 c->ases |= MIPS_ASE_MIPSMT;
296 if (config3 & MIPS_CONF3_ULRI)
297 c->options |= MIPS_CPU_ULRI;
Steven J. Hillf8fa4812012-12-07 03:51:35 +0000298 if (config3 & MIPS_CONF3_ISA)
299 c->options |= MIPS_CPU_MICROMIPS;
David Daney1e7decd2013-02-16 23:42:43 +0100300 if (config3 & MIPS_CONF3_VZ)
301 c->ases |= MIPS_ASE_VZ;
Steven J. Hill4a0156f2013-11-14 16:12:24 +0000302 if (config3 & MIPS_CONF3_SC)
303 c->options |= MIPS_CPU_SEGMENTS;
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100304
305 return config3 & MIPS_CONF_M;
306}
307
308static inline unsigned int decode_config4(struct cpuinfo_mips *c)
309{
310 unsigned int config4;
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +0000311 unsigned int newcf4;
312 unsigned int mmuextdef;
313 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100314
315 config4 = read_c0_config4();
316
Leonid Yegoshin1745c1e2013-11-14 16:12:23 +0000317 if (cpu_has_tlb) {
318 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
319 c->options |= MIPS_CPU_TLBINV;
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +0000320 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
321 switch (mmuextdef) {
322 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
323 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
324 c->tlbsizevtlb = c->tlbsize;
325 break;
326 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
327 c->tlbsizevtlb +=
328 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
329 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
330 c->tlbsize = c->tlbsizevtlb;
331 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
332 /* fall through */
333 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
334 newcf4 = (config4 & ~ftlb_page) |
335 (page_size_ftlb(mmuextdef) <<
336 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
337 write_c0_config4(newcf4);
338 back_to_back_c0_hazard();
339 config4 = read_c0_config4();
340 if (config4 != newcf4) {
341 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
342 PAGE_SIZE, config4);
343 /* Switch FTLB off */
344 set_ftlb_enable(c, 0);
345 break;
346 }
347 c->tlbsizeftlbsets = 1 <<
348 ((config4 & MIPS_CONF4_FTLBSETS) >>
349 MIPS_CONF4_FTLBSETS_SHIFT);
350 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
351 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
352 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
353 break;
354 }
Leonid Yegoshin1745c1e2013-11-14 16:12:23 +0000355 }
356
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100357 c->kscratch_mask = (config4 >> 16) & 0xff;
358
359 return config4 & MIPS_CONF_M;
360}
361
Ralf Baechle8b8a76342013-09-19 11:15:49 +0200362static inline unsigned int decode_config5(struct cpuinfo_mips *c)
363{
364 unsigned int config5;
365
366 config5 = read_c0_config5();
367 config5 &= ~MIPS_CONF5_UFR;
368 write_c0_config5(config5);
369
370 return config5 & MIPS_CONF_M;
371}
372
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000373static void decode_configs(struct cpuinfo_mips *c)
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100374{
375 int ok;
376
377 /* MIPS32 or MIPS64 compliant CPU. */
378 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
379 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
380
381 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
382
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +0000383 /* Enable FTLB if present */
384 set_ftlb_enable(c, 1);
385
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100386 ok = decode_config0(c); /* Read Config registers. */
Ralf Baechle70342282013-01-22 12:59:30 +0100387 BUG_ON(!ok); /* Arch spec violation! */
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100388 if (ok)
389 ok = decode_config1(c);
390 if (ok)
391 ok = decode_config2(c);
392 if (ok)
393 ok = decode_config3(c);
394 if (ok)
395 ok = decode_config4(c);
Ralf Baechle8b8a76342013-09-19 11:15:49 +0200396 if (ok)
397 ok = decode_config5(c);
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100398
399 mips_probe_watch_registers(c);
400
Paul Burton0ee958e2014-01-15 10:31:53 +0000401#ifndef CONFIG_MIPS_CPS
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100402 if (cpu_has_mips_r2)
403 c->core = read_c0_ebase() & 0x3ff;
Paul Burton0ee958e2014-01-15 10:31:53 +0000404#endif
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100405}
406
Ralf Baechle02cf2112005-10-01 13:06:32 +0100407#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700408 | MIPS_CPU_COUNTER)
409
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000410static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700411{
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100412 switch (c->processor_id & PRID_IMP_MASK) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700413 case PRID_IMP_R2000:
414 c->cputype = CPU_R2000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000415 __cpu_name[cpu] = "R2000";
Ralf Baechle02cf2112005-10-01 13:06:32 +0100416 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
Steven J. Hill03751e72012-05-10 23:21:18 -0500417 MIPS_CPU_NOFPUEX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700418 if (__cpu_has_fpu())
419 c->options |= MIPS_CPU_FPU;
420 c->tlbsize = 64;
421 break;
422 case PRID_IMP_R3000:
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100423 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000424 if (cpu_has_confreg()) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700425 c->cputype = CPU_R3081E;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000426 __cpu_name[cpu] = "R3081";
427 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700428 c->cputype = CPU_R3000A;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000429 __cpu_name[cpu] = "R3000A";
430 }
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000431 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700432 c->cputype = CPU_R3000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000433 __cpu_name[cpu] = "R3000";
434 }
Ralf Baechle02cf2112005-10-01 13:06:32 +0100435 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
Steven J. Hill03751e72012-05-10 23:21:18 -0500436 MIPS_CPU_NOFPUEX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700437 if (__cpu_has_fpu())
438 c->options |= MIPS_CPU_FPU;
439 c->tlbsize = 64;
440 break;
441 case PRID_IMP_R4000:
442 if (read_c0_config() & CONF_SC) {
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100443 if ((c->processor_id & PRID_REV_MASK) >=
444 PRID_REV_R4400) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700445 c->cputype = CPU_R4400PC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000446 __cpu_name[cpu] = "R4400PC";
447 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700448 c->cputype = CPU_R4000PC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000449 __cpu_name[cpu] = "R4000PC";
450 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700451 } else {
Maciej W. Rozycki7f177a52013-09-23 14:01:53 +0100452 int cca = read_c0_config() & CONF_CM_CMASK;
453 int mc;
454
455 /*
456 * SC and MC versions can't be reliably told apart,
457 * but only the latter support coherent caching
458 * modes so assume the firmware has set the KSEG0
459 * coherency attribute reasonably (if uncached, we
460 * assume SC).
461 */
462 switch (cca) {
463 case CONF_CM_CACHABLE_CE:
464 case CONF_CM_CACHABLE_COW:
465 case CONF_CM_CACHABLE_CUW:
466 mc = 1;
467 break;
468 default:
469 mc = 0;
470 break;
471 }
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100472 if ((c->processor_id & PRID_REV_MASK) >=
473 PRID_REV_R4400) {
Maciej W. Rozycki7f177a52013-09-23 14:01:53 +0100474 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
475 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000476 } else {
Maciej W. Rozycki7f177a52013-09-23 14:01:53 +0100477 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
478 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000479 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700480 }
481
Steven J. Hilla96102b2012-12-07 04:31:36 +0000482 set_isa(c, MIPS_CPU_ISA_III);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700483 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
Steven J. Hill03751e72012-05-10 23:21:18 -0500484 MIPS_CPU_WATCH | MIPS_CPU_VCE |
485 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700486 c->tlbsize = 48;
487 break;
488 case PRID_IMP_VR41XX:
Yoichi Yuasa9f91e502013-02-21 15:38:19 +0900489 set_isa(c, MIPS_CPU_ISA_III);
490 c->options = R4K_OPTS;
491 c->tlbsize = 32;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700492 switch (c->processor_id & 0xf0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700493 case PRID_REV_VR4111:
494 c->cputype = CPU_VR4111;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000495 __cpu_name[cpu] = "NEC VR4111";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700496 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700497 case PRID_REV_VR4121:
498 c->cputype = CPU_VR4121;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000499 __cpu_name[cpu] = "NEC VR4121";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700500 break;
501 case PRID_REV_VR4122:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000502 if ((c->processor_id & 0xf) < 0x3) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700503 c->cputype = CPU_VR4122;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000504 __cpu_name[cpu] = "NEC VR4122";
505 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700506 c->cputype = CPU_VR4181A;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000507 __cpu_name[cpu] = "NEC VR4181A";
508 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700509 break;
510 case PRID_REV_VR4130:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000511 if ((c->processor_id & 0xf) < 0x4) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700512 c->cputype = CPU_VR4131;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000513 __cpu_name[cpu] = "NEC VR4131";
514 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700515 c->cputype = CPU_VR4133;
Yoichi Yuasa9f91e502013-02-21 15:38:19 +0900516 c->options |= MIPS_CPU_LLSC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000517 __cpu_name[cpu] = "NEC VR4133";
518 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700519 break;
520 default:
521 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
522 c->cputype = CPU_VR41XX;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000523 __cpu_name[cpu] = "NEC Vr41xx";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700524 break;
525 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700526 break;
527 case PRID_IMP_R4300:
528 c->cputype = CPU_R4300;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000529 __cpu_name[cpu] = "R4300";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000530 set_isa(c, MIPS_CPU_ISA_III);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700531 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
Steven J. Hill03751e72012-05-10 23:21:18 -0500532 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700533 c->tlbsize = 32;
534 break;
535 case PRID_IMP_R4600:
536 c->cputype = CPU_R4600;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000537 __cpu_name[cpu] = "R4600";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000538 set_isa(c, MIPS_CPU_ISA_III);
Thiemo Seufer075e7502005-07-27 21:48:12 +0000539 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
540 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700541 c->tlbsize = 48;
542 break;
543 #if 0
Steven J. Hill03751e72012-05-10 23:21:18 -0500544 case PRID_IMP_R4650:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700545 /*
546 * This processor doesn't have an MMU, so it's not
547 * "real easy" to run Linux on it. It is left purely
548 * for documentation. Commented out because it shares
549 * it's c0_prid id number with the TX3900.
550 */
Ralf Baechlea3dddd52006-03-11 08:18:41 +0000551 c->cputype = CPU_R4650;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000552 __cpu_name[cpu] = "R4650";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000553 set_isa(c, MIPS_CPU_ISA_III);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700554 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
Steven J. Hill03751e72012-05-10 23:21:18 -0500555 c->tlbsize = 48;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700556 break;
557 #endif
558 case PRID_IMP_TX39:
Ralf Baechle02cf2112005-10-01 13:06:32 +0100559 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700560
561 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
562 c->cputype = CPU_TX3927;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000563 __cpu_name[cpu] = "TX3927";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700564 c->tlbsize = 64;
565 } else {
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100566 switch (c->processor_id & PRID_REV_MASK) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700567 case PRID_REV_TX3912:
568 c->cputype = CPU_TX3912;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000569 __cpu_name[cpu] = "TX3912";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700570 c->tlbsize = 32;
571 break;
572 case PRID_REV_TX3922:
573 c->cputype = CPU_TX3922;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000574 __cpu_name[cpu] = "TX3922";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700575 c->tlbsize = 64;
576 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700577 }
578 }
579 break;
580 case PRID_IMP_R4700:
581 c->cputype = CPU_R4700;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000582 __cpu_name[cpu] = "R4700";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000583 set_isa(c, MIPS_CPU_ISA_III);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700584 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
Steven J. Hill03751e72012-05-10 23:21:18 -0500585 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700586 c->tlbsize = 48;
587 break;
588 case PRID_IMP_TX49:
589 c->cputype = CPU_TX49XX;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000590 __cpu_name[cpu] = "R49XX";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000591 set_isa(c, MIPS_CPU_ISA_III);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700592 c->options = R4K_OPTS | MIPS_CPU_LLSC;
593 if (!(c->processor_id & 0x08))
594 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
595 c->tlbsize = 48;
596 break;
597 case PRID_IMP_R5000:
598 c->cputype = CPU_R5000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000599 __cpu_name[cpu] = "R5000";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000600 set_isa(c, MIPS_CPU_ISA_IV);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700601 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
Steven J. Hill03751e72012-05-10 23:21:18 -0500602 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700603 c->tlbsize = 48;
604 break;
605 case PRID_IMP_R5432:
606 c->cputype = CPU_R5432;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000607 __cpu_name[cpu] = "R5432";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000608 set_isa(c, MIPS_CPU_ISA_IV);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700609 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
Steven J. Hill03751e72012-05-10 23:21:18 -0500610 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700611 c->tlbsize = 48;
612 break;
613 case PRID_IMP_R5500:
614 c->cputype = CPU_R5500;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000615 __cpu_name[cpu] = "R5500";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000616 set_isa(c, MIPS_CPU_ISA_IV);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700617 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
Steven J. Hill03751e72012-05-10 23:21:18 -0500618 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700619 c->tlbsize = 48;
620 break;
621 case PRID_IMP_NEVADA:
622 c->cputype = CPU_NEVADA;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000623 __cpu_name[cpu] = "Nevada";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000624 set_isa(c, MIPS_CPU_ISA_IV);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700625 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
Steven J. Hill03751e72012-05-10 23:21:18 -0500626 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700627 c->tlbsize = 48;
628 break;
629 case PRID_IMP_R6000:
630 c->cputype = CPU_R6000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000631 __cpu_name[cpu] = "R6000";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000632 set_isa(c, MIPS_CPU_ISA_II);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700633 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
Steven J. Hill03751e72012-05-10 23:21:18 -0500634 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700635 c->tlbsize = 32;
636 break;
637 case PRID_IMP_R6000A:
638 c->cputype = CPU_R6000A;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000639 __cpu_name[cpu] = "R6000A";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000640 set_isa(c, MIPS_CPU_ISA_II);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700641 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
Steven J. Hill03751e72012-05-10 23:21:18 -0500642 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700643 c->tlbsize = 32;
644 break;
645 case PRID_IMP_RM7000:
646 c->cputype = CPU_RM7000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000647 __cpu_name[cpu] = "RM7000";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000648 set_isa(c, MIPS_CPU_ISA_IV);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700649 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
Steven J. Hill03751e72012-05-10 23:21:18 -0500650 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700651 /*
Ralf Baechle70342282013-01-22 12:59:30 +0100652 * Undocumented RM7000: Bit 29 in the info register of
Linus Torvalds1da177e2005-04-16 15:20:36 -0700653 * the RM7000 v2.0 indicates if the TLB has 48 or 64
654 * entries.
655 *
Ralf Baechle70342282013-01-22 12:59:30 +0100656 * 29 1 => 64 entry JTLB
657 * 0 => 48 entry JTLB
Linus Torvalds1da177e2005-04-16 15:20:36 -0700658 */
659 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
660 break;
661 case PRID_IMP_RM9000:
662 c->cputype = CPU_RM9000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000663 __cpu_name[cpu] = "RM9000";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000664 set_isa(c, MIPS_CPU_ISA_IV);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700665 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
Steven J. Hill03751e72012-05-10 23:21:18 -0500666 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700667 /*
668 * Bit 29 in the info register of the RM9000
669 * indicates if the TLB has 48 or 64 entries.
670 *
Ralf Baechle70342282013-01-22 12:59:30 +0100671 * 29 1 => 64 entry JTLB
672 * 0 => 48 entry JTLB
Linus Torvalds1da177e2005-04-16 15:20:36 -0700673 */
674 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
675 break;
676 case PRID_IMP_R8000:
677 c->cputype = CPU_R8000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000678 __cpu_name[cpu] = "RM8000";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000679 set_isa(c, MIPS_CPU_ISA_IV);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700680 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
Steven J. Hill03751e72012-05-10 23:21:18 -0500681 MIPS_CPU_FPU | MIPS_CPU_32FPR |
682 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700683 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
684 break;
685 case PRID_IMP_R10000:
686 c->cputype = CPU_R10000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000687 __cpu_name[cpu] = "R10000";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000688 set_isa(c, MIPS_CPU_ISA_IV);
Ralf Baechle8b366122005-11-22 17:53:59 +0000689 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
Steven J. Hill03751e72012-05-10 23:21:18 -0500690 MIPS_CPU_FPU | MIPS_CPU_32FPR |
Linus Torvalds1da177e2005-04-16 15:20:36 -0700691 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
Steven J. Hill03751e72012-05-10 23:21:18 -0500692 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700693 c->tlbsize = 64;
694 break;
695 case PRID_IMP_R12000:
696 c->cputype = CPU_R12000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000697 __cpu_name[cpu] = "R12000";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000698 set_isa(c, MIPS_CPU_ISA_IV);
Ralf Baechle8b366122005-11-22 17:53:59 +0000699 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
Steven J. Hill03751e72012-05-10 23:21:18 -0500700 MIPS_CPU_FPU | MIPS_CPU_32FPR |
Linus Torvalds1da177e2005-04-16 15:20:36 -0700701 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
Steven J. Hill03751e72012-05-10 23:21:18 -0500702 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700703 c->tlbsize = 64;
704 break;
Kumba44d921b2006-05-16 22:23:59 -0400705 case PRID_IMP_R14000:
706 c->cputype = CPU_R14000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000707 __cpu_name[cpu] = "R14000";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000708 set_isa(c, MIPS_CPU_ISA_IV);
Kumba44d921b2006-05-16 22:23:59 -0400709 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
Steven J. Hill03751e72012-05-10 23:21:18 -0500710 MIPS_CPU_FPU | MIPS_CPU_32FPR |
Kumba44d921b2006-05-16 22:23:59 -0400711 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
Steven J. Hill03751e72012-05-10 23:21:18 -0500712 MIPS_CPU_LLSC;
Kumba44d921b2006-05-16 22:23:59 -0400713 c->tlbsize = 64;
714 break;
Fuxin Zhang2a21c732007-06-06 14:52:43 +0800715 case PRID_IMP_LOONGSON2:
716 c->cputype = CPU_LOONGSON2;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000717 __cpu_name[cpu] = "ICT Loongson-2";
Robert Millan5aac1e82011-04-16 11:29:29 -0700718
719 switch (c->processor_id & PRID_REV_MASK) {
720 case PRID_REV_LOONGSON2E:
721 set_elf_platform(cpu, "loongson2e");
722 break;
723 case PRID_REV_LOONGSON2F:
724 set_elf_platform(cpu, "loongson2f");
725 break;
726 }
727
Steven J. Hilla96102b2012-12-07 04:31:36 +0000728 set_isa(c, MIPS_CPU_ISA_III);
Fuxin Zhang2a21c732007-06-06 14:52:43 +0800729 c->options = R4K_OPTS |
730 MIPS_CPU_FPU | MIPS_CPU_LLSC |
731 MIPS_CPU_32FPR;
732 c->tlbsize = 64;
733 break;
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100734 case PRID_IMP_LOONGSON1:
735 decode_configs(c);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700736
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100737 c->cputype = CPU_LOONGSON1;
Ralf Baechleb4672d32005-12-08 14:04:24 +0000738
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100739 switch (c->processor_id & PRID_REV_MASK) {
740 case PRID_REV_LOONGSON1B:
741 __cpu_name[cpu] = "Loongson 1B";
Ralf Baechleb4672d32005-12-08 14:04:24 +0000742 break;
Ralf Baechleb4672d32005-12-08 14:04:24 +0000743 }
Kelvin Cheung2fa36392012-06-20 20:05:32 +0100744
Ralf Baechle41943182005-05-05 16:45:59 +0000745 break;
Ralf Baechle41943182005-05-05 16:45:59 +0000746 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700747}
748
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000749static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700750{
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100751 switch (c->processor_id & PRID_IMP_MASK) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700752 case PRID_IMP_4KC:
753 c->cputype = CPU_4KC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000754 __cpu_name[cpu] = "MIPS 4Kc";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700755 break;
756 case PRID_IMP_4KEC:
Ralf Baechle2b07bd02005-04-08 20:36:05 +0000757 case PRID_IMP_4KECR2:
758 c->cputype = CPU_4KEC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000759 __cpu_name[cpu] = "MIPS 4KEc";
Ralf Baechle2b07bd02005-04-08 20:36:05 +0000760 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700761 case PRID_IMP_4KSC:
Ralf Baechle8afcb5d2005-10-04 15:01:26 +0100762 case PRID_IMP_4KSD:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700763 c->cputype = CPU_4KSC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000764 __cpu_name[cpu] = "MIPS 4KSc";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700765 break;
766 case PRID_IMP_5KC:
767 c->cputype = CPU_5KC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000768 __cpu_name[cpu] = "MIPS 5Kc";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700769 break;
Leonid Yegoshin78d48032012-07-06 21:56:01 +0200770 case PRID_IMP_5KE:
771 c->cputype = CPU_5KE;
772 __cpu_name[cpu] = "MIPS 5KE";
773 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700774 case PRID_IMP_20KC:
775 c->cputype = CPU_20KC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000776 __cpu_name[cpu] = "MIPS 20Kc";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700777 break;
778 case PRID_IMP_24K:
779 c->cputype = CPU_24K;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000780 __cpu_name[cpu] = "MIPS 24Kc";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700781 break;
John Crispin42f3cae2013-01-11 22:44:10 +0100782 case PRID_IMP_24KE:
783 c->cputype = CPU_24K;
784 __cpu_name[cpu] = "MIPS 24KEc";
785 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700786 case PRID_IMP_25KF:
787 c->cputype = CPU_25KF;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000788 __cpu_name[cpu] = "MIPS 25Kc";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700789 break;
Ralf Baechlebbc7f222005-07-12 16:12:05 +0000790 case PRID_IMP_34K:
791 c->cputype = CPU_34K;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000792 __cpu_name[cpu] = "MIPS 34Kc";
Ralf Baechlebbc7f222005-07-12 16:12:05 +0000793 break;
Chris Dearmanc6209532006-05-02 14:08:46 +0100794 case PRID_IMP_74K:
795 c->cputype = CPU_74K;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000796 __cpu_name[cpu] = "MIPS 74Kc";
Chris Dearmanc6209532006-05-02 14:08:46 +0100797 break;
Steven J. Hill113c62d2012-07-06 23:56:00 +0200798 case PRID_IMP_M14KC:
799 c->cputype = CPU_M14KC;
800 __cpu_name[cpu] = "MIPS M14Kc";
801 break;
Steven J. Hillf8fa4812012-12-07 03:51:35 +0000802 case PRID_IMP_M14KEC:
803 c->cputype = CPU_M14KEC;
804 __cpu_name[cpu] = "MIPS M14KEc";
805 break;
Ralf Baechle39b8d522008-04-28 17:14:26 +0100806 case PRID_IMP_1004K:
807 c->cputype = CPU_1004K;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000808 __cpu_name[cpu] = "MIPS 1004Kc";
Ralf Baechle39b8d522008-04-28 17:14:26 +0100809 break;
Steven J. Hill006a8512012-06-26 04:11:03 +0000810 case PRID_IMP_1074K:
Steven J. Hill442e14a2014-01-17 15:03:50 -0600811 c->cputype = CPU_1074K;
Steven J. Hill006a8512012-06-26 04:11:03 +0000812 __cpu_name[cpu] = "MIPS 1074Kc";
813 break;
Leonid Yegoshinb5f065e2013-11-20 10:46:02 +0000814 case PRID_IMP_INTERAPTIV_UP:
815 c->cputype = CPU_INTERAPTIV;
816 __cpu_name[cpu] = "MIPS interAptiv";
817 break;
818 case PRID_IMP_INTERAPTIV_MP:
819 c->cputype = CPU_INTERAPTIV;
820 __cpu_name[cpu] = "MIPS interAptiv (multi)";
821 break;
Leonid Yegoshinb0d4d302013-11-14 16:12:28 +0000822 case PRID_IMP_PROAPTIV_UP:
823 c->cputype = CPU_PROAPTIV;
824 __cpu_name[cpu] = "MIPS proAptiv";
825 break;
826 case PRID_IMP_PROAPTIV_MP:
827 c->cputype = CPU_PROAPTIV;
828 __cpu_name[cpu] = "MIPS proAptiv (multi)";
829 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700830 }
Chris Dearman0b6d4972007-09-13 12:32:02 +0100831
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +0000832 decode_configs(c);
833
Chris Dearman0b6d4972007-09-13 12:32:02 +0100834 spram_config();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700835}
836
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000837static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700838{
Ralf Baechle41943182005-05-05 16:45:59 +0000839 decode_configs(c);
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100840 switch (c->processor_id & PRID_IMP_MASK) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700841 case PRID_IMP_AU1_REV1:
842 case PRID_IMP_AU1_REV2:
Manuel Lauss270717a2009-03-25 17:49:28 +0100843 c->cputype = CPU_ALCHEMY;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700844 switch ((c->processor_id >> 24) & 0xff) {
845 case 0:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000846 __cpu_name[cpu] = "Au1000";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700847 break;
848 case 1:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000849 __cpu_name[cpu] = "Au1500";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700850 break;
851 case 2:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000852 __cpu_name[cpu] = "Au1100";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700853 break;
854 case 3:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000855 __cpu_name[cpu] = "Au1550";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700856 break;
Pete Popove3ad1c22005-03-01 06:33:16 +0000857 case 4:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000858 __cpu_name[cpu] = "Au1200";
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100859 if ((c->processor_id & PRID_REV_MASK) == 2)
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000860 __cpu_name[cpu] = "Au1250";
Manuel Lauss237cfee2007-12-06 09:07:55 +0100861 break;
862 case 5:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000863 __cpu_name[cpu] = "Au1210";
Pete Popove3ad1c22005-03-01 06:33:16 +0000864 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700865 default:
Manuel Lauss270717a2009-03-25 17:49:28 +0100866 __cpu_name[cpu] = "Au1xxx";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700867 break;
868 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700869 break;
870 }
871}
872
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000873static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700874{
Ralf Baechle41943182005-05-05 16:45:59 +0000875 decode_configs(c);
Ralf Baechle02cf2112005-10-01 13:06:32 +0100876
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100877 switch (c->processor_id & PRID_IMP_MASK) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700878 case PRID_IMP_SB1:
879 c->cputype = CPU_SB1;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000880 __cpu_name[cpu] = "SiByte SB1";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700881 /* FPU in pass1 is known to have issues. */
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100882 if ((c->processor_id & PRID_REV_MASK) < 0x02)
Ralf Baechle010b8532006-01-29 18:42:08 +0000883 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700884 break;
Andrew Isaacson93ce2f522005-10-19 23:56:20 -0700885 case PRID_IMP_SB1A:
886 c->cputype = CPU_SB1A;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000887 __cpu_name[cpu] = "SiByte SB1A";
Andrew Isaacson93ce2f522005-10-19 23:56:20 -0700888 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700889 }
890}
891
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000892static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700893{
Ralf Baechle41943182005-05-05 16:45:59 +0000894 decode_configs(c);
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100895 switch (c->processor_id & PRID_IMP_MASK) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700896 case PRID_IMP_SR71000:
897 c->cputype = CPU_SR71000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000898 __cpu_name[cpu] = "Sandcraft SR71000";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700899 c->scache.ways = 8;
900 c->tlbsize = 64;
901 break;
902 }
903}
904
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000905static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
Pete Popovbdf21b12005-07-14 17:47:57 +0000906{
907 decode_configs(c);
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100908 switch (c->processor_id & PRID_IMP_MASK) {
Pete Popovbdf21b12005-07-14 17:47:57 +0000909 case PRID_IMP_PR4450:
910 c->cputype = CPU_PR4450;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000911 __cpu_name[cpu] = "Philips PR4450";
Steven J. Hilla96102b2012-12-07 04:31:36 +0000912 set_isa(c, MIPS_CPU_ISA_M32R1);
Pete Popovbdf21b12005-07-14 17:47:57 +0000913 break;
Pete Popovbdf21b12005-07-14 17:47:57 +0000914 }
915}
916
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000917static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +0200918{
919 decode_configs(c);
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100920 switch (c->processor_id & PRID_IMP_MASK) {
Kevin Cernekee190fca32010-11-23 10:26:45 -0800921 case PRID_IMP_BMIPS32_REV4:
922 case PRID_IMP_BMIPS32_REV8:
Kevin Cernekee602977b2010-10-16 14:22:30 -0700923 c->cputype = CPU_BMIPS32;
924 __cpu_name[cpu] = "Broadcom BMIPS32";
Kevin Cernekee06785df2011-04-16 11:29:28 -0700925 set_elf_platform(cpu, "bmips32");
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +0200926 break;
Kevin Cernekee602977b2010-10-16 14:22:30 -0700927 case PRID_IMP_BMIPS3300:
928 case PRID_IMP_BMIPS3300_ALT:
929 case PRID_IMP_BMIPS3300_BUG:
930 c->cputype = CPU_BMIPS3300;
931 __cpu_name[cpu] = "Broadcom BMIPS3300";
Kevin Cernekee06785df2011-04-16 11:29:28 -0700932 set_elf_platform(cpu, "bmips3300");
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +0200933 break;
Kevin Cernekee602977b2010-10-16 14:22:30 -0700934 case PRID_IMP_BMIPS43XX: {
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100935 int rev = c->processor_id & PRID_REV_MASK;
Kevin Cernekee602977b2010-10-16 14:22:30 -0700936
937 if (rev >= PRID_REV_BMIPS4380_LO &&
938 rev <= PRID_REV_BMIPS4380_HI) {
939 c->cputype = CPU_BMIPS4380;
940 __cpu_name[cpu] = "Broadcom BMIPS4380";
Kevin Cernekee06785df2011-04-16 11:29:28 -0700941 set_elf_platform(cpu, "bmips4380");
Kevin Cernekee602977b2010-10-16 14:22:30 -0700942 } else {
943 c->cputype = CPU_BMIPS4350;
944 __cpu_name[cpu] = "Broadcom BMIPS4350";
Kevin Cernekee06785df2011-04-16 11:29:28 -0700945 set_elf_platform(cpu, "bmips4350");
Maxime Bizon0de663e2009-08-18 13:23:37 +0100946 }
947 break;
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +0200948 }
Kevin Cernekee602977b2010-10-16 14:22:30 -0700949 case PRID_IMP_BMIPS5000:
950 c->cputype = CPU_BMIPS5000;
951 __cpu_name[cpu] = "Broadcom BMIPS5000";
Kevin Cernekee06785df2011-04-16 11:29:28 -0700952 set_elf_platform(cpu, "bmips5000");
Kevin Cernekee602977b2010-10-16 14:22:30 -0700953 c->options |= MIPS_CPU_ULRI;
954 break;
Kevin Cernekee602977b2010-10-16 14:22:30 -0700955 }
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +0200956}
957
David Daney0dd47812008-12-11 15:33:26 -0800958static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
959{
960 decode_configs(c);
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +0100961 switch (c->processor_id & PRID_IMP_MASK) {
David Daney0dd47812008-12-11 15:33:26 -0800962 case PRID_IMP_CAVIUM_CN38XX:
963 case PRID_IMP_CAVIUM_CN31XX:
964 case PRID_IMP_CAVIUM_CN30XX:
David Daney6f329462010-02-10 15:12:48 -0800965 c->cputype = CPU_CAVIUM_OCTEON;
966 __cpu_name[cpu] = "Cavium Octeon";
967 goto platform;
David Daney0dd47812008-12-11 15:33:26 -0800968 case PRID_IMP_CAVIUM_CN58XX:
969 case PRID_IMP_CAVIUM_CN56XX:
970 case PRID_IMP_CAVIUM_CN50XX:
971 case PRID_IMP_CAVIUM_CN52XX:
David Daney6f329462010-02-10 15:12:48 -0800972 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
973 __cpu_name[cpu] = "Cavium Octeon+";
974platform:
Robert Millanc094c992011-04-18 11:37:55 -0700975 set_elf_platform(cpu, "octeon");
David Daney0dd47812008-12-11 15:33:26 -0800976 break;
David Daneya1431b62011-09-24 02:29:54 +0200977 case PRID_IMP_CAVIUM_CN61XX:
David Daney0e56b382010-10-07 16:03:45 -0700978 case PRID_IMP_CAVIUM_CN63XX:
David Daneya1431b62011-09-24 02:29:54 +0200979 case PRID_IMP_CAVIUM_CN66XX:
980 case PRID_IMP_CAVIUM_CN68XX:
David Daneyaf04bb82013-07-29 15:07:01 -0700981 case PRID_IMP_CAVIUM_CNF71XX:
David Daney0e56b382010-10-07 16:03:45 -0700982 c->cputype = CPU_CAVIUM_OCTEON2;
983 __cpu_name[cpu] = "Cavium Octeon II";
Robert Millanc094c992011-04-18 11:37:55 -0700984 set_elf_platform(cpu, "octeon2");
David Daney0e56b382010-10-07 16:03:45 -0700985 break;
David Daneyaf04bb82013-07-29 15:07:01 -0700986 case PRID_IMP_CAVIUM_CN70XX:
987 case PRID_IMP_CAVIUM_CN78XX:
988 c->cputype = CPU_CAVIUM_OCTEON3;
989 __cpu_name[cpu] = "Cavium Octeon III";
990 set_elf_platform(cpu, "octeon3");
991 break;
David Daney0dd47812008-12-11 15:33:26 -0800992 default:
993 printk(KERN_INFO "Unknown Octeon chip!\n");
994 c->cputype = CPU_UNKNOWN;
995 break;
996 }
997}
998
Lars-Peter Clausen83ccf692010-07-17 11:07:51 +0000999static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1000{
1001 decode_configs(c);
1002 /* JZRISC does not implement the CP0 counter. */
1003 c->options &= ~MIPS_CPU_COUNTER;
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +01001004 switch (c->processor_id & PRID_IMP_MASK) {
Lars-Peter Clausen83ccf692010-07-17 11:07:51 +00001005 case PRID_IMP_JZRISC:
1006 c->cputype = CPU_JZRISC;
1007 __cpu_name[cpu] = "Ingenic JZRISC";
1008 break;
1009 default:
1010 panic("Unknown Ingenic Processor ID!");
1011 break;
1012 }
1013}
1014
Jayachandran Ca7117c62011-05-11 12:04:58 +05301015static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1016{
1017 decode_configs(c);
1018
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +01001019 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
Manuel Lauss809f36c2011-11-01 20:03:30 +01001020 c->cputype = CPU_ALCHEMY;
1021 __cpu_name[cpu] = "Au1300";
1022 /* following stuff is not for Alchemy */
1023 return;
1024 }
1025
Ralf Baechle70342282013-01-22 12:59:30 +01001026 c->options = (MIPS_CPU_TLB |
1027 MIPS_CPU_4KEX |
Jayachandran Ca7117c62011-05-11 12:04:58 +05301028 MIPS_CPU_COUNTER |
Ralf Baechle70342282013-01-22 12:59:30 +01001029 MIPS_CPU_DIVEC |
1030 MIPS_CPU_WATCH |
1031 MIPS_CPU_EJTAG |
Jayachandran Ca7117c62011-05-11 12:04:58 +05301032 MIPS_CPU_LLSC);
1033
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +01001034 switch (c->processor_id & PRID_IMP_MASK) {
Jayachandran C4ca86a22013-08-11 14:43:54 +05301035 case PRID_IMP_NETLOGIC_XLP2XX:
Jayachandran C8907c552013-12-21 16:52:20 +05301036 case PRID_IMP_NETLOGIC_XLP9XX:
Jayachandran C4ca86a22013-08-11 14:43:54 +05301037 c->cputype = CPU_XLP;
1038 __cpu_name[cpu] = "Broadcom XLPII";
1039 break;
1040
Jayachandran C2aa54b22011-11-16 00:21:29 +00001041 case PRID_IMP_NETLOGIC_XLP8XX:
1042 case PRID_IMP_NETLOGIC_XLP3XX:
Jayachandran Ca3d4fb22011-11-16 00:21:20 +00001043 c->cputype = CPU_XLP;
1044 __cpu_name[cpu] = "Netlogic XLP";
1045 break;
1046
Jayachandran Ca7117c62011-05-11 12:04:58 +05301047 case PRID_IMP_NETLOGIC_XLR732:
1048 case PRID_IMP_NETLOGIC_XLR716:
1049 case PRID_IMP_NETLOGIC_XLR532:
1050 case PRID_IMP_NETLOGIC_XLR308:
1051 case PRID_IMP_NETLOGIC_XLR532C:
1052 case PRID_IMP_NETLOGIC_XLR516C:
1053 case PRID_IMP_NETLOGIC_XLR508C:
1054 case PRID_IMP_NETLOGIC_XLR308C:
1055 c->cputype = CPU_XLR;
1056 __cpu_name[cpu] = "Netlogic XLR";
1057 break;
1058
1059 case PRID_IMP_NETLOGIC_XLS608:
1060 case PRID_IMP_NETLOGIC_XLS408:
1061 case PRID_IMP_NETLOGIC_XLS404:
1062 case PRID_IMP_NETLOGIC_XLS208:
1063 case PRID_IMP_NETLOGIC_XLS204:
1064 case PRID_IMP_NETLOGIC_XLS108:
1065 case PRID_IMP_NETLOGIC_XLS104:
1066 case PRID_IMP_NETLOGIC_XLS616B:
1067 case PRID_IMP_NETLOGIC_XLS608B:
1068 case PRID_IMP_NETLOGIC_XLS416B:
1069 case PRID_IMP_NETLOGIC_XLS412B:
1070 case PRID_IMP_NETLOGIC_XLS408B:
1071 case PRID_IMP_NETLOGIC_XLS404B:
1072 c->cputype = CPU_XLR;
1073 __cpu_name[cpu] = "Netlogic XLS";
1074 break;
1075
1076 default:
Jayachandran Ca3d4fb22011-11-16 00:21:20 +00001077 pr_info("Unknown Netlogic chip id [%02x]!\n",
Jayachandran Ca7117c62011-05-11 12:04:58 +05301078 c->processor_id);
1079 c->cputype = CPU_XLR;
1080 break;
1081 }
1082
Jayachandran Ca3d4fb22011-11-16 00:21:20 +00001083 if (c->cputype == CPU_XLP) {
Steven J. Hilla96102b2012-12-07 04:31:36 +00001084 set_isa(c, MIPS_CPU_ISA_M64R2);
Jayachandran Ca3d4fb22011-11-16 00:21:20 +00001085 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1086 /* This will be updated again after all threads are woken up */
1087 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1088 } else {
Steven J. Hilla96102b2012-12-07 04:31:36 +00001089 set_isa(c, MIPS_CPU_ISA_M64R1);
Jayachandran Ca3d4fb22011-11-16 00:21:20 +00001090 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1091 }
Jayachandran C7777b932013-06-11 14:41:35 +00001092 c->kscratch_mask = 0xf;
Jayachandran Ca7117c62011-05-11 12:04:58 +05301093}
1094
David Daney949e51b2010-10-14 11:32:33 -07001095#ifdef CONFIG_64BIT
1096/* For use by uaccess.h */
1097u64 __ua_limit;
1098EXPORT_SYMBOL(__ua_limit);
1099#endif
1100
Ralf Baechle9966db252007-10-11 23:46:17 +01001101const char *__cpu_name[NR_CPUS];
David Daney874fd3b2010-01-28 16:52:12 -08001102const char *__elf_platform;
Ralf Baechle9966db252007-10-11 23:46:17 +01001103
Paul Gortmaker078a55f2013-06-18 13:38:59 +00001104void cpu_probe(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001105{
1106 struct cpuinfo_mips *c = &current_cpu_data;
Ralf Baechle9966db252007-10-11 23:46:17 +01001107 unsigned int cpu = smp_processor_id();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001108
Ralf Baechle70342282013-01-22 12:59:30 +01001109 c->processor_id = PRID_IMP_UNKNOWN;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001110 c->fpu_id = FPIR_IMP_NONE;
1111 c->cputype = CPU_UNKNOWN;
1112
1113 c->processor_id = read_c0_prid();
Maciej W. Rozycki8ff374b2013-09-17 16:58:10 +01001114 switch (c->processor_id & PRID_COMP_MASK) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001115 case PRID_COMP_LEGACY:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001116 cpu_probe_legacy(c, cpu);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001117 break;
1118 case PRID_COMP_MIPS:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001119 cpu_probe_mips(c, cpu);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001120 break;
1121 case PRID_COMP_ALCHEMY:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001122 cpu_probe_alchemy(c, cpu);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001123 break;
1124 case PRID_COMP_SIBYTE:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001125 cpu_probe_sibyte(c, cpu);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001126 break;
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +02001127 case PRID_COMP_BROADCOM:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001128 cpu_probe_broadcom(c, cpu);
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +02001129 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001130 case PRID_COMP_SANDCRAFT:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001131 cpu_probe_sandcraft(c, cpu);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001132 break;
Daniel Lairda92b0582008-03-06 09:07:18 +00001133 case PRID_COMP_NXP:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001134 cpu_probe_nxp(c, cpu);
Ralf Baechlea3dddd52006-03-11 08:18:41 +00001135 break;
David Daney0dd47812008-12-11 15:33:26 -08001136 case PRID_COMP_CAVIUM:
1137 cpu_probe_cavium(c, cpu);
1138 break;
Lars-Peter Clausen83ccf692010-07-17 11:07:51 +00001139 case PRID_COMP_INGENIC:
1140 cpu_probe_ingenic(c, cpu);
1141 break;
Jayachandran Ca7117c62011-05-11 12:04:58 +05301142 case PRID_COMP_NETLOGIC:
1143 cpu_probe_netlogic(c, cpu);
1144 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001145 }
Franck Bui-Huudec8b1c2007-10-08 16:11:51 +02001146
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001147 BUG_ON(!__cpu_name[cpu]);
1148 BUG_ON(c->cputype == CPU_UNKNOWN);
1149
Franck Bui-Huudec8b1c2007-10-08 16:11:51 +02001150 /*
1151 * Platform code can force the cpu type to optimize code
1152 * generation. In that case be sure the cpu type is correctly
1153 * manually setup otherwise it could trigger some nasty bugs.
1154 */
1155 BUG_ON(current_cpu_type() != c->cputype);
1156
Kevin Cernekee0103d232010-05-02 14:43:52 -07001157 if (mips_fpu_disabled)
1158 c->options &= ~MIPS_CPU_FPU;
1159
1160 if (mips_dsp_disabled)
Steven J. Hillee80f7c72012-08-03 10:26:04 -05001161 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
Kevin Cernekee0103d232010-05-02 14:43:52 -07001162
Ralf Baechle41943182005-05-05 16:45:59 +00001163 if (c->options & MIPS_CPU_FPU) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001164 c->fpu_id = cpu_get_fpu_id();
Ralf Baechle41943182005-05-05 16:45:59 +00001165
Deng-Cheng Zhuadb37892013-04-01 18:14:28 +00001166 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1167 MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
Ralf Baechle41943182005-05-05 16:45:59 +00001168 if (c->fpu_id & MIPS_FPIR_3D)
1169 c->ases |= MIPS_ASE_MIPS3D;
1170 }
1171 }
Ralf Baechle9966db252007-10-11 23:46:17 +01001172
Al Cooperda4b62c2012-07-13 16:44:51 -04001173 if (cpu_has_mips_r2) {
Ralf Baechlef6771db2007-11-08 18:02:29 +00001174 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
Al Cooperda4b62c2012-07-13 16:44:51 -04001175 /* R2 has Performance Counter Interrupt indicator */
1176 c->options |= MIPS_CPU_PCI;
1177 }
Ralf Baechlef6771db2007-11-08 18:02:29 +00001178 else
1179 c->srsets = 1;
Guenter Roeck91dfc422010-02-02 08:52:20 -08001180
1181 cpu_probe_vmbits(c);
David Daney949e51b2010-10-14 11:32:33 -07001182
1183#ifdef CONFIG_64BIT
1184 if (cpu == 0)
1185 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1186#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001187}
1188
Paul Gortmaker078a55f2013-06-18 13:38:59 +00001189void cpu_report(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001190{
1191 struct cpuinfo_mips *c = &current_cpu_data;
1192
Leonid Yegoshind9f897c2013-10-07 10:43:32 +01001193 pr_info("CPU%d revision is: %08x (%s)\n",
1194 smp_processor_id(), c->processor_id, cpu_name_string());
Linus Torvalds1da177e2005-04-16 15:20:36 -07001195 if (c->options & MIPS_CPU_FPU)
Ralf Baechle9966db252007-10-11 23:46:17 +01001196 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001197}