blob: 8d9da9d30a61ffcd058c352f22cc6baab8f9e9a4 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * drivers/pci/setup-bus.c
3 *
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
8 *
9 * Support routines for initializing a PCI subsystem.
10 */
11
12/*
13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
14 * PCI-PCI bridges cleanup, sorted resource allocation.
15 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 * Converted to allocation in 3 passes, which gives
17 * tighter packing. Prefetchable range support.
18 */
19
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/pci.h>
24#include <linux/errno.h>
25#include <linux/ioport.h>
26#include <linux/cache.h>
27#include <linux/slab.h>
28
29
Andrew Mortonea741552009-02-18 10:44:29 -080030static void pbus_assign_resources_sorted(const struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -070031{
32 struct pci_dev *dev;
33 struct resource *res;
34 struct resource_list head, *list, *tmp;
35 int idx;
36
Linus Torvalds1da177e2005-04-16 15:20:36 -070037 head.next = NULL;
38 list_for_each_entry(dev, &bus->devices, bus_list) {
39 u16 class = dev->class >> 8;
40
Kenji Kaneshige9bded002006-10-04 02:15:34 -070041 /* Don't touch classless devices or host bridges or ioapics. */
Linus Torvalds1da177e2005-04-16 15:20:36 -070042 if (class == PCI_CLASS_NOT_DEFINED ||
Satoru Takeuchi23186272006-09-12 10:21:44 -070043 class == PCI_CLASS_BRIDGE_HOST)
Linus Torvalds1da177e2005-04-16 15:20:36 -070044 continue;
45
Kenji Kaneshige9bded002006-10-04 02:15:34 -070046 /* Don't touch ioapic devices already enabled by firmware */
Satoru Takeuchi23186272006-09-12 10:21:44 -070047 if (class == PCI_CLASS_SYSTEM_PIC) {
Kenji Kaneshige9bded002006-10-04 02:15:34 -070048 u16 command;
49 pci_read_config_word(dev, PCI_COMMAND, &command);
50 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
Satoru Takeuchi23186272006-09-12 10:21:44 -070051 continue;
52 }
53
Linus Torvalds1da177e2005-04-16 15:20:36 -070054 pdev_sort_resources(dev, &head);
55 }
56
57 for (list = head.next; list;) {
58 res = list->res;
59 idx = res - &list->dev->resource[0];
Rajesh Shah542df5d2005-04-28 00:25:50 -070060 if (pci_assign_resource(list->dev, idx)) {
Ivan Kokshaysky88452562008-03-30 19:50:14 +040061 /* FIXME: get rid of this */
Rajesh Shah542df5d2005-04-28 00:25:50 -070062 res->start = 0;
Ivan Kokshaysky960b8462005-07-07 03:07:56 +040063 res->end = 0;
Rajesh Shah542df5d2005-04-28 00:25:50 -070064 res->flags = 0;
65 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070066 tmp = list;
67 list = list->next;
68 kfree(tmp);
69 }
70}
71
Dominik Brodowskib3743fa2005-09-09 13:03:23 -070072void pci_setup_cardbus(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -070073{
74 struct pci_dev *bridge = bus->self;
75 struct pci_bus_region region;
76
Bjorn Helgaas80ccba12008-06-13 10:52:11 -060077 dev_info(&bridge->dev, "CardBus bridge, secondary bus %04x:%02x\n",
78 pci_domain_nr(bus), bus->number);
Linus Torvalds1da177e2005-04-16 15:20:36 -070079
80 pcibios_resource_to_bus(bridge, &region, bus->resource[0]);
81 if (bus->resource[0]->flags & IORESOURCE_IO) {
82 /*
83 * The IO resource is allocated a range twice as large as it
84 * would normally need. This allows us to set both IO regs.
85 */
Bjorn Helgaas80ccba12008-06-13 10:52:11 -060086 dev_info(&bridge->dev, " IO window: %#08lx-%#08lx\n",
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +110087 (unsigned long)region.start,
88 (unsigned long)region.end);
Linus Torvalds1da177e2005-04-16 15:20:36 -070089 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
90 region.start);
91 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
92 region.end);
93 }
94
95 pcibios_resource_to_bus(bridge, &region, bus->resource[1]);
96 if (bus->resource[1]->flags & IORESOURCE_IO) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -060097 dev_info(&bridge->dev, " IO window: %#08lx-%#08lx\n",
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +110098 (unsigned long)region.start,
99 (unsigned long)region.end);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700100 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
101 region.start);
102 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
103 region.end);
104 }
105
106 pcibios_resource_to_bus(bridge, &region, bus->resource[2]);
107 if (bus->resource[2]->flags & IORESOURCE_MEM) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600108 dev_info(&bridge->dev, " PREFETCH window: %#08lx-%#08lx\n",
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100109 (unsigned long)region.start,
110 (unsigned long)region.end);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700111 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
112 region.start);
113 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
114 region.end);
115 }
116
117 pcibios_resource_to_bus(bridge, &region, bus->resource[3]);
118 if (bus->resource[3]->flags & IORESOURCE_MEM) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600119 dev_info(&bridge->dev, " MEM window: %#08lx-%#08lx\n",
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100120 (unsigned long)region.start,
121 (unsigned long)region.end);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700122 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
123 region.start);
124 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
125 region.end);
126 }
127}
Dominik Brodowskib3743fa2005-09-09 13:03:23 -0700128EXPORT_SYMBOL(pci_setup_cardbus);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700129
130/* Initialize bridges with base/limit values we have collected.
131 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
132 requires that if there is no I/O ports or memory behind the
133 bridge, corresponding range must be turned off by writing base
134 value greater than limit to the bridge's base/limit registers.
135
136 Note: care must be taken when updating I/O base/limit registers
137 of bridges which support 32-bit I/O. This update requires two
138 config space writes, so it's quite possible that an I/O window of
139 the bridge will have some undesirable address (e.g. 0) after the
140 first write. Ditto 64-bit prefetchable MMIO. */
Adrian Bunka391f192008-04-18 13:53:57 -0700141static void pci_setup_bridge(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700142{
143 struct pci_dev *bridge = bus->self;
144 struct pci_bus_region region;
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100145 u32 l, bu, lu, io_upper16;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700146
Yuji Shimada296ccb02009-04-03 16:41:46 +0900147 if (pci_is_enabled(bridge))
Alex Chiangb73e97d2009-03-20 14:56:15 -0600148 return;
149
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600150 dev_info(&bridge->dev, "PCI bridge, secondary bus %04x:%02x\n",
151 pci_domain_nr(bus), bus->number);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700152
153 /* Set up the top and bottom of the PCI I/O segment for this bus. */
154 pcibios_resource_to_bus(bridge, &region, bus->resource[0]);
155 if (bus->resource[0]->flags & IORESOURCE_IO) {
156 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
157 l &= 0xffff0000;
158 l |= (region.start >> 8) & 0x00f0;
159 l |= region.end & 0xf000;
160 /* Set up upper 16 bits of I/O base/limit. */
161 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600162 dev_info(&bridge->dev, " IO window: %#04lx-%#04lx\n",
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100163 (unsigned long)region.start,
164 (unsigned long)region.end);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700165 }
166 else {
167 /* Clear upper 16 bits of I/O base/limit. */
168 io_upper16 = 0;
169 l = 0x00f0;
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600170 dev_info(&bridge->dev, " IO window: disabled\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700171 }
172 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
173 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
174 /* Update lower 16 bits of I/O base/limit. */
175 pci_write_config_dword(bridge, PCI_IO_BASE, l);
176 /* Update upper 16 bits of I/O base/limit. */
177 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
178
179 /* Set up the top and bottom of the PCI Memory segment
180 for this bus. */
181 pcibios_resource_to_bus(bridge, &region, bus->resource[1]);
182 if (bus->resource[1]->flags & IORESOURCE_MEM) {
183 l = (region.start >> 16) & 0xfff0;
184 l |= region.end & 0xfff00000;
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600185 dev_info(&bridge->dev, " MEM window: %#08lx-%#08lx\n",
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100186 (unsigned long)region.start,
187 (unsigned long)region.end);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700188 }
189 else {
190 l = 0x0000fff0;
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600191 dev_info(&bridge->dev, " MEM window: disabled\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700192 }
193 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
194
195 /* Clear out the upper 32 bits of PREF limit.
196 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
197 disables PREF range, which is ok. */
198 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
199
200 /* Set up PREF base/limit. */
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100201 bu = lu = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700202 pcibios_resource_to_bus(bridge, &region, bus->resource[2]);
203 if (bus->resource[2]->flags & IORESOURCE_PREFETCH) {
204 l = (region.start >> 16) & 0xfff0;
205 l |= region.end & 0xfff00000;
Andrew Morton13d36c22008-02-04 23:50:12 -0800206 bu = upper_32_bits(region.start);
207 lu = upper_32_bits(region.end);
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600208 dev_info(&bridge->dev, " PREFETCH window: %#016llx-%#016llx\n",
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100209 (unsigned long long)region.start,
210 (unsigned long long)region.end);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700211 }
212 else {
213 l = 0x0000fff0;
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600214 dev_info(&bridge->dev, " PREFETCH window: disabled\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700215 }
216 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
217
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100218 /* Set the upper 32 bits of PREF base & limit. */
219 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
220 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700221
222 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
223}
224
225/* Check whether the bridge supports optional I/O and
226 prefetchable memory ranges. If not, the respective
227 base/limit registers must be read-only and read as 0. */
Sam Ravnborg96bde062007-03-26 21:53:30 -0800228static void pci_bridge_check_ranges(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700229{
230 u16 io;
231 u32 pmem;
232 struct pci_dev *bridge = bus->self;
233 struct resource *b_res;
234
235 b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
236 b_res[1].flags |= IORESOURCE_MEM;
237
238 pci_read_config_word(bridge, PCI_IO_BASE, &io);
239 if (!io) {
240 pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
241 pci_read_config_word(bridge, PCI_IO_BASE, &io);
242 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
243 }
244 if (io)
245 b_res[0].flags |= IORESOURCE_IO;
246 /* DECchip 21050 pass 2 errata: the bridge may miss an address
247 disconnect boundary by one PCI data phase.
248 Workaround: do not use prefetching on this device. */
249 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
250 return;
251 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
252 if (!pmem) {
253 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
254 0xfff0fff0);
255 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
256 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
257 }
258 if (pmem)
259 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
260}
261
262/* Helper function for sizing routines: find first available
263 bus resource of a given type. Note: we intentionally skip
264 the bus resources which have already been assigned (that is,
265 have non-NULL parent resource). */
Sam Ravnborg96bde062007-03-26 21:53:30 -0800266static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700267{
268 int i;
269 struct resource *r;
270 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
271 IORESOURCE_PREFETCH;
272
273 for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
274 r = bus->resource[i];
Ivan Kokshaysky299de032005-06-15 18:59:27 +0400275 if (r == &ioport_resource || r == &iomem_resource)
276 continue;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700277 if (r && (r->flags & type_mask) == type && !r->parent)
278 return r;
279 }
280 return NULL;
281}
282
283/* Sizing the IO windows of the PCI-PCI bridge is trivial,
284 since these windows have 4K granularity and the IO ranges
285 of non-bridge PCI devices are limited to 256 bytes.
286 We must be careful with the ISA aliasing though. */
Sam Ravnborg96bde062007-03-26 21:53:30 -0800287static void pbus_size_io(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700288{
289 struct pci_dev *dev;
290 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
291 unsigned long size = 0, size1 = 0;
292
293 if (!b_res)
294 return;
295
296 list_for_each_entry(dev, &bus->devices, bus_list) {
297 int i;
298
299 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
300 struct resource *r = &dev->resource[i];
301 unsigned long r_size;
302
303 if (r->parent || !(r->flags & IORESOURCE_IO))
304 continue;
Zhao, Yu022edd82008-10-13 19:24:28 +0800305 r_size = resource_size(r);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700306
307 if (r_size < 0x400)
308 /* Might be re-aligned for ISA */
309 size += r_size;
310 else
311 size1 += r_size;
312 }
313 }
314/* To be fixed in 2.5: we should have sort of HAVE_ISA
315 flag in the struct pci_bus. */
316#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
317 size = (size & 0xff) + ((size & ~0xffUL) << 2);
318#endif
Milind Arun Choudhary6f6f8c22007-07-09 11:55:51 -0700319 size = ALIGN(size + size1, 4096);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700320 if (!size) {
321 b_res->flags = 0;
322 return;
323 }
324 /* Alignment of the IO window is always 4K */
325 b_res->start = 4096;
326 b_res->end = b_res->start + size - 1;
Ivan Kokshaysky88452562008-03-30 19:50:14 +0400327 b_res->flags |= IORESOURCE_STARTALIGN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700328}
329
330/* Calculate the size of the bus and minimal alignment which
331 guarantees that all child resources fit in this size. */
Sam Ravnborg96bde062007-03-26 21:53:30 -0800332static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long type)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700333{
334 struct pci_dev *dev;
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100335 resource_size_t min_align, align, size;
336 resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700337 int order, max_order;
338 struct resource *b_res = find_free_bus_resource(bus, type);
339
340 if (!b_res)
341 return 0;
342
343 memset(aligns, 0, sizeof(aligns));
344 max_order = 0;
345 size = 0;
346
347 list_for_each_entry(dev, &bus->devices, bus_list) {
348 int i;
349
350 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
351 struct resource *r = &dev->resource[i];
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100352 resource_size_t r_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700353
354 if (r->parent || (r->flags & mask) != type)
355 continue;
Zhao, Yu022edd82008-10-13 19:24:28 +0800356 r_size = resource_size(r);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700357 /* For bridges size != alignment */
Linus Torvalds5f17cfc2008-09-04 01:33:59 -0700358 align = resource_alignment(r);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700359 order = __ffs(align) - 20;
360 if (order > 11) {
Linus Torvalds5f17cfc2008-09-04 01:33:59 -0700361 dev_warn(&dev->dev, "BAR %d bad alignment %llx: "
Benjamin Herrenschmidt096e6f62008-10-20 15:07:37 +1100362 "%pR\n", i, (unsigned long long)align, r);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700363 r->flags = 0;
364 continue;
365 }
366 size += r_size;
367 if (order < 0)
368 order = 0;
369 /* Exclude ranges with size > align from
370 calculation of the alignment. */
371 if (r_size == align)
372 aligns[order] += align;
373 if (order > max_order)
374 max_order = order;
375 }
376 }
377
378 align = 0;
379 min_align = 0;
380 for (order = 0; order <= max_order; order++) {
Jeremy Fitzhardinge8308c542008-09-11 01:31:50 -0700381 resource_size_t align1 = 1;
382
383 align1 <<= (order + 20);
384
Linus Torvalds1da177e2005-04-16 15:20:36 -0700385 if (!align)
386 min_align = align1;
Milind Arun Choudhary6f6f8c22007-07-09 11:55:51 -0700387 else if (ALIGN(align + min_align, min_align) < align1)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700388 min_align = align1 >> 1;
389 align += aligns[order];
390 }
Milind Arun Choudhary6f6f8c22007-07-09 11:55:51 -0700391 size = ALIGN(size, min_align);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700392 if (!size) {
393 b_res->flags = 0;
394 return 1;
395 }
396 b_res->start = min_align;
397 b_res->end = size + min_align - 1;
Ivan Kokshaysky88452562008-03-30 19:50:14 +0400398 b_res->flags |= IORESOURCE_STARTALIGN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700399 return 1;
400}
401
Adrian Bunk5468ae62008-04-18 13:53:56 -0700402static void pci_bus_size_cardbus(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700403{
404 struct pci_dev *bridge = bus->self;
405 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
406 u16 ctrl;
407
408 /*
409 * Reserve some resources for CardBus. We reserve
410 * a fixed amount of bus space for CardBus bridges.
411 */
Linus Torvalds934b7022008-04-22 18:16:30 -0700412 b_res[0].start = 0;
413 b_res[0].end = pci_cardbus_io_size - 1;
414 b_res[0].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700415
Linus Torvalds934b7022008-04-22 18:16:30 -0700416 b_res[1].start = 0;
417 b_res[1].end = pci_cardbus_io_size - 1;
418 b_res[1].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700419
420 /*
421 * Check whether prefetchable memory is supported
422 * by this bridge.
423 */
424 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
425 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
426 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
427 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
428 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
429 }
430
431 /*
432 * If we have prefetchable memory support, allocate
433 * two regions. Otherwise, allocate one region of
434 * twice the size.
435 */
436 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
Linus Torvalds934b7022008-04-22 18:16:30 -0700437 b_res[2].start = 0;
438 b_res[2].end = pci_cardbus_mem_size - 1;
439 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SIZEALIGN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700440
Linus Torvalds934b7022008-04-22 18:16:30 -0700441 b_res[3].start = 0;
442 b_res[3].end = pci_cardbus_mem_size - 1;
443 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700444 } else {
Linus Torvalds934b7022008-04-22 18:16:30 -0700445 b_res[3].start = 0;
446 b_res[3].end = pci_cardbus_mem_size * 2 - 1;
447 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700448 }
449}
450
Sam Ravnborg451124a2008-02-02 22:33:43 +0100451void __ref pci_bus_size_bridges(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700452{
453 struct pci_dev *dev;
454 unsigned long mask, prefmask;
455
456 list_for_each_entry(dev, &bus->devices, bus_list) {
457 struct pci_bus *b = dev->subordinate;
458 if (!b)
459 continue;
460
461 switch (dev->class >> 8) {
462 case PCI_CLASS_BRIDGE_CARDBUS:
463 pci_bus_size_cardbus(b);
464 break;
465
466 case PCI_CLASS_BRIDGE_PCI:
467 default:
468 pci_bus_size_bridges(b);
469 break;
470 }
471 }
472
473 /* The root bus? */
474 if (!bus->self)
475 return;
476
477 switch (bus->self->class >> 8) {
478 case PCI_CLASS_BRIDGE_CARDBUS:
479 /* don't size cardbuses yet. */
480 break;
481
482 case PCI_CLASS_BRIDGE_PCI:
483 pci_bridge_check_ranges(bus);
484 default:
485 pbus_size_io(bus);
486 /* If the bridge supports prefetchable range, size it
487 separately. If it doesn't, or its prefetchable window
488 has already been allocated by arch code, try
489 non-prefetchable range for both types of PCI memory
490 resources. */
491 mask = IORESOURCE_MEM;
492 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
493 if (pbus_size_mem(bus, prefmask, prefmask))
494 mask = prefmask; /* Success, size non-prefetch only. */
495 pbus_size_mem(bus, mask, IORESOURCE_MEM);
496 break;
497 }
498}
499EXPORT_SYMBOL(pci_bus_size_bridges);
500
Andrew Mortonea741552009-02-18 10:44:29 -0800501void __ref pci_bus_assign_resources(const struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700502{
503 struct pci_bus *b;
504 struct pci_dev *dev;
505
506 pbus_assign_resources_sorted(bus);
507
Linus Torvalds1da177e2005-04-16 15:20:36 -0700508 list_for_each_entry(dev, &bus->devices, bus_list) {
509 b = dev->subordinate;
510 if (!b)
511 continue;
512
513 pci_bus_assign_resources(b);
514
515 switch (dev->class >> 8) {
516 case PCI_CLASS_BRIDGE_PCI:
517 pci_setup_bridge(b);
518 break;
519
520 case PCI_CLASS_BRIDGE_CARDBUS:
521 pci_setup_cardbus(b);
522 break;
523
524 default:
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600525 dev_info(&dev->dev, "not setting up bridge for bus "
526 "%04x:%02x\n", pci_domain_nr(b), b->number);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700527 break;
528 }
529 }
530}
531EXPORT_SYMBOL(pci_bus_assign_resources);
532
Yinghai Lu76fbc262008-06-23 20:33:06 +0200533static void pci_bus_dump_res(struct pci_bus *bus)
534{
535 int i;
536
537 for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
538 struct resource *res = bus->resource[i];
539 if (!res)
540 continue;
541
Bjorn Helgaasa19f5df2008-12-18 16:34:19 -0700542 dev_printk(KERN_DEBUG, &bus->dev, "resource %d %s %pR\n", i,
543 (res->flags & IORESOURCE_IO) ? "io: " : "mem:", res);
Yinghai Lu76fbc262008-06-23 20:33:06 +0200544 }
545}
546
547static void pci_bus_dump_resources(struct pci_bus *bus)
548{
549 struct pci_bus *b;
550 struct pci_dev *dev;
551
552
553 pci_bus_dump_res(bus);
554
555 list_for_each_entry(dev, &bus->devices, bus_list) {
556 b = dev->subordinate;
557 if (!b)
558 continue;
559
560 pci_bus_dump_resources(b);
561 }
562}
563
Linus Torvalds1da177e2005-04-16 15:20:36 -0700564void __init
565pci_assign_unassigned_resources(void)
566{
567 struct pci_bus *bus;
568
569 /* Depth first, calculate sizes and alignments of all
570 subordinate buses. */
571 list_for_each_entry(bus, &pci_root_buses, node) {
572 pci_bus_size_bridges(bus);
573 }
574 /* Depth last, allocate resources and update the hardware. */
575 list_for_each_entry(bus, &pci_root_buses, node) {
576 pci_bus_assign_resources(bus);
577 pci_enable_bridges(bus);
578 }
Yinghai Lu76fbc262008-06-23 20:33:06 +0200579
580 /* dump the resource on buses */
581 list_for_each_entry(bus, &pci_root_buses, node) {
582 pci_bus_dump_resources(bus);
583 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700584}