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Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001/*
2 * Driver for Atmel AT32 and AT91 SPI Controllers
3 *
4 * Copyright (C) 2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -080012#include <linux/clk.h>
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/delay.h>
16#include <linux/dma-mapping.h>
Nicolas Ferre1ccc4042013-04-03 13:59:19 +080017#include <linux/dmaengine.h>
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -080018#include <linux/err.h>
19#include <linux/interrupt.h>
20#include <linux/spi/spi.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090021#include <linux/slab.h>
Nicolas Ferre1ccc4042013-04-03 13:59:19 +080022#include <linux/platform_data/dma-atmel.h>
Jean-Christophe PLAGNIOL-VILLARD850a5b62012-11-23 13:44:39 +010023#include <linux/of.h>
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -080024
Wenyou Yangd4820b72013-03-19 15:42:15 +080025#include <linux/io.h>
26#include <linux/gpio.h>
Wenyou Yang5bdfd492014-03-05 09:58:49 +080027#include <linux/pinctrl/consumer.h>
Wenyou Yangce0c4ca2014-10-16 17:23:10 +080028#include <linux/pm_runtime.h>
David Brownellbb2d1c32007-02-20 13:58:19 -080029
Grant Likelyca632f52011-06-06 01:16:30 -060030/* SPI register offsets */
31#define SPI_CR 0x0000
32#define SPI_MR 0x0004
33#define SPI_RDR 0x0008
34#define SPI_TDR 0x000c
35#define SPI_SR 0x0010
36#define SPI_IER 0x0014
37#define SPI_IDR 0x0018
38#define SPI_IMR 0x001c
39#define SPI_CSR0 0x0030
40#define SPI_CSR1 0x0034
41#define SPI_CSR2 0x0038
42#define SPI_CSR3 0x003c
Cyrille Pitchen11f27642015-06-16 12:09:31 +020043#define SPI_FMR 0x0040
44#define SPI_FLR 0x0044
Wenyou Yangd4820b72013-03-19 15:42:15 +080045#define SPI_VERSION 0x00fc
Grant Likelyca632f52011-06-06 01:16:30 -060046#define SPI_RPR 0x0100
47#define SPI_RCR 0x0104
48#define SPI_TPR 0x0108
49#define SPI_TCR 0x010c
50#define SPI_RNPR 0x0110
51#define SPI_RNCR 0x0114
52#define SPI_TNPR 0x0118
53#define SPI_TNCR 0x011c
54#define SPI_PTCR 0x0120
55#define SPI_PTSR 0x0124
56
57/* Bitfields in CR */
58#define SPI_SPIEN_OFFSET 0
59#define SPI_SPIEN_SIZE 1
60#define SPI_SPIDIS_OFFSET 1
61#define SPI_SPIDIS_SIZE 1
62#define SPI_SWRST_OFFSET 7
63#define SPI_SWRST_SIZE 1
64#define SPI_LASTXFER_OFFSET 24
65#define SPI_LASTXFER_SIZE 1
Cyrille Pitchen11f27642015-06-16 12:09:31 +020066#define SPI_TXFCLR_OFFSET 16
67#define SPI_TXFCLR_SIZE 1
68#define SPI_RXFCLR_OFFSET 17
69#define SPI_RXFCLR_SIZE 1
70#define SPI_FIFOEN_OFFSET 30
71#define SPI_FIFOEN_SIZE 1
72#define SPI_FIFODIS_OFFSET 31
73#define SPI_FIFODIS_SIZE 1
Grant Likelyca632f52011-06-06 01:16:30 -060074
75/* Bitfields in MR */
76#define SPI_MSTR_OFFSET 0
77#define SPI_MSTR_SIZE 1
78#define SPI_PS_OFFSET 1
79#define SPI_PS_SIZE 1
80#define SPI_PCSDEC_OFFSET 2
81#define SPI_PCSDEC_SIZE 1
82#define SPI_FDIV_OFFSET 3
83#define SPI_FDIV_SIZE 1
84#define SPI_MODFDIS_OFFSET 4
85#define SPI_MODFDIS_SIZE 1
Wenyou Yangd4820b72013-03-19 15:42:15 +080086#define SPI_WDRBT_OFFSET 5
87#define SPI_WDRBT_SIZE 1
Grant Likelyca632f52011-06-06 01:16:30 -060088#define SPI_LLB_OFFSET 7
89#define SPI_LLB_SIZE 1
90#define SPI_PCS_OFFSET 16
91#define SPI_PCS_SIZE 4
92#define SPI_DLYBCS_OFFSET 24
93#define SPI_DLYBCS_SIZE 8
94
95/* Bitfields in RDR */
96#define SPI_RD_OFFSET 0
97#define SPI_RD_SIZE 16
98
99/* Bitfields in TDR */
100#define SPI_TD_OFFSET 0
101#define SPI_TD_SIZE 16
102
103/* Bitfields in SR */
104#define SPI_RDRF_OFFSET 0
105#define SPI_RDRF_SIZE 1
106#define SPI_TDRE_OFFSET 1
107#define SPI_TDRE_SIZE 1
108#define SPI_MODF_OFFSET 2
109#define SPI_MODF_SIZE 1
110#define SPI_OVRES_OFFSET 3
111#define SPI_OVRES_SIZE 1
112#define SPI_ENDRX_OFFSET 4
113#define SPI_ENDRX_SIZE 1
114#define SPI_ENDTX_OFFSET 5
115#define SPI_ENDTX_SIZE 1
116#define SPI_RXBUFF_OFFSET 6
117#define SPI_RXBUFF_SIZE 1
118#define SPI_TXBUFE_OFFSET 7
119#define SPI_TXBUFE_SIZE 1
120#define SPI_NSSR_OFFSET 8
121#define SPI_NSSR_SIZE 1
122#define SPI_TXEMPTY_OFFSET 9
123#define SPI_TXEMPTY_SIZE 1
124#define SPI_SPIENS_OFFSET 16
125#define SPI_SPIENS_SIZE 1
Cyrille Pitchen11f27642015-06-16 12:09:31 +0200126#define SPI_TXFEF_OFFSET 24
127#define SPI_TXFEF_SIZE 1
128#define SPI_TXFFF_OFFSET 25
129#define SPI_TXFFF_SIZE 1
130#define SPI_TXFTHF_OFFSET 26
131#define SPI_TXFTHF_SIZE 1
132#define SPI_RXFEF_OFFSET 27
133#define SPI_RXFEF_SIZE 1
134#define SPI_RXFFF_OFFSET 28
135#define SPI_RXFFF_SIZE 1
136#define SPI_RXFTHF_OFFSET 29
137#define SPI_RXFTHF_SIZE 1
138#define SPI_TXFPTEF_OFFSET 30
139#define SPI_TXFPTEF_SIZE 1
140#define SPI_RXFPTEF_OFFSET 31
141#define SPI_RXFPTEF_SIZE 1
Grant Likelyca632f52011-06-06 01:16:30 -0600142
143/* Bitfields in CSR0 */
144#define SPI_CPOL_OFFSET 0
145#define SPI_CPOL_SIZE 1
146#define SPI_NCPHA_OFFSET 1
147#define SPI_NCPHA_SIZE 1
148#define SPI_CSAAT_OFFSET 3
149#define SPI_CSAAT_SIZE 1
150#define SPI_BITS_OFFSET 4
151#define SPI_BITS_SIZE 4
152#define SPI_SCBR_OFFSET 8
153#define SPI_SCBR_SIZE 8
154#define SPI_DLYBS_OFFSET 16
155#define SPI_DLYBS_SIZE 8
156#define SPI_DLYBCT_OFFSET 24
157#define SPI_DLYBCT_SIZE 8
158
159/* Bitfields in RCR */
160#define SPI_RXCTR_OFFSET 0
161#define SPI_RXCTR_SIZE 16
162
163/* Bitfields in TCR */
164#define SPI_TXCTR_OFFSET 0
165#define SPI_TXCTR_SIZE 16
166
167/* Bitfields in RNCR */
168#define SPI_RXNCR_OFFSET 0
169#define SPI_RXNCR_SIZE 16
170
171/* Bitfields in TNCR */
172#define SPI_TXNCR_OFFSET 0
173#define SPI_TXNCR_SIZE 16
174
175/* Bitfields in PTCR */
176#define SPI_RXTEN_OFFSET 0
177#define SPI_RXTEN_SIZE 1
178#define SPI_RXTDIS_OFFSET 1
179#define SPI_RXTDIS_SIZE 1
180#define SPI_TXTEN_OFFSET 8
181#define SPI_TXTEN_SIZE 1
182#define SPI_TXTDIS_OFFSET 9
183#define SPI_TXTDIS_SIZE 1
184
Cyrille Pitchen11f27642015-06-16 12:09:31 +0200185/* Bitfields in FMR */
186#define SPI_TXRDYM_OFFSET 0
187#define SPI_TXRDYM_SIZE 2
188#define SPI_RXRDYM_OFFSET 4
189#define SPI_RXRDYM_SIZE 2
190#define SPI_TXFTHRES_OFFSET 16
191#define SPI_TXFTHRES_SIZE 6
192#define SPI_RXFTHRES_OFFSET 24
193#define SPI_RXFTHRES_SIZE 6
194
195/* Bitfields in FLR */
196#define SPI_TXFL_OFFSET 0
197#define SPI_TXFL_SIZE 6
198#define SPI_RXFL_OFFSET 16
199#define SPI_RXFL_SIZE 6
200
Grant Likelyca632f52011-06-06 01:16:30 -0600201/* Constants for BITS */
202#define SPI_BITS_8_BPT 0
203#define SPI_BITS_9_BPT 1
204#define SPI_BITS_10_BPT 2
205#define SPI_BITS_11_BPT 3
206#define SPI_BITS_12_BPT 4
207#define SPI_BITS_13_BPT 5
208#define SPI_BITS_14_BPT 6
209#define SPI_BITS_15_BPT 7
210#define SPI_BITS_16_BPT 8
Cyrille Pitchen11f27642015-06-16 12:09:31 +0200211#define SPI_ONE_DATA 0
212#define SPI_TWO_DATA 1
213#define SPI_FOUR_DATA 2
Grant Likelyca632f52011-06-06 01:16:30 -0600214
215/* Bit manipulation macros */
216#define SPI_BIT(name) \
217 (1 << SPI_##name##_OFFSET)
Sachin Kamata536d762013-09-10 17:06:27 +0530218#define SPI_BF(name, value) \
Grant Likelyca632f52011-06-06 01:16:30 -0600219 (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
Sachin Kamata536d762013-09-10 17:06:27 +0530220#define SPI_BFEXT(name, value) \
Grant Likelyca632f52011-06-06 01:16:30 -0600221 (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
Sachin Kamata536d762013-09-10 17:06:27 +0530222#define SPI_BFINS(name, value, old) \
223 (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
224 | SPI_BF(name, value))
Grant Likelyca632f52011-06-06 01:16:30 -0600225
226/* Register access macros */
Ben Dooksea467322015-03-18 15:53:08 +0000227#ifdef CONFIG_AVR32
Sachin Kamata536d762013-09-10 17:06:27 +0530228#define spi_readl(port, reg) \
Grant Likelyca632f52011-06-06 01:16:30 -0600229 __raw_readl((port)->regs + SPI_##reg)
Sachin Kamata536d762013-09-10 17:06:27 +0530230#define spi_writel(port, reg, value) \
Grant Likelyca632f52011-06-06 01:16:30 -0600231 __raw_writel((value), (port)->regs + SPI_##reg)
Cyrille Pitchen11f27642015-06-16 12:09:31 +0200232
233#define spi_readw(port, reg) \
234 __raw_readw((port)->regs + SPI_##reg)
235#define spi_writew(port, reg, value) \
236 __raw_writew((value), (port)->regs + SPI_##reg)
237
238#define spi_readb(port, reg) \
239 __raw_readb((port)->regs + SPI_##reg)
240#define spi_writeb(port, reg, value) \
241 __raw_writeb((value), (port)->regs + SPI_##reg)
Ben Dooksea467322015-03-18 15:53:08 +0000242#else
243#define spi_readl(port, reg) \
244 readl_relaxed((port)->regs + SPI_##reg)
245#define spi_writel(port, reg, value) \
246 writel_relaxed((value), (port)->regs + SPI_##reg)
Cyrille Pitchen11f27642015-06-16 12:09:31 +0200247
248#define spi_readw(port, reg) \
249 readw_relaxed((port)->regs + SPI_##reg)
250#define spi_writew(port, reg, value) \
251 writew_relaxed((value), (port)->regs + SPI_##reg)
252
253#define spi_readb(port, reg) \
254 readb_relaxed((port)->regs + SPI_##reg)
255#define spi_writeb(port, reg, value) \
256 writeb_relaxed((value), (port)->regs + SPI_##reg)
Ben Dooksea467322015-03-18 15:53:08 +0000257#endif
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800258/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
259 * cache operations; better heuristics consider wordsize and bitrate.
260 */
261#define DMA_MIN_BYTES 16
262
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800263#define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
264
Wenyou Yangce0c4ca2014-10-16 17:23:10 +0800265#define AUTOSUSPEND_TIMEOUT 2000
266
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800267struct atmel_spi_dma {
268 struct dma_chan *chan_rx;
269 struct dma_chan *chan_tx;
270 struct scatterlist sgrx;
271 struct scatterlist sgtx;
272 struct dma_async_tx_descriptor *data_desc_rx;
273 struct dma_async_tx_descriptor *data_desc_tx;
274
275 struct at_dma_slave dma_slave;
276};
277
Wenyou Yangd4820b72013-03-19 15:42:15 +0800278struct atmel_spi_caps {
279 bool is_spi2;
280 bool has_wdrbt;
281 bool has_dma_support;
282};
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800283
284/*
285 * The core SPI transfer engine just talks to a register bank to set up
286 * DMA transfers; transfer queue progress is driven by IRQs. The clock
287 * framework provides the base clock, subdivided for each spi_device.
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800288 */
289struct atmel_spi {
290 spinlock_t lock;
Nicolas Ferre8aad7922013-04-03 13:58:36 +0800291 unsigned long flags;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800292
Nicolas Ferredfab30e2013-04-03 13:57:42 +0800293 phys_addr_t phybase;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800294 void __iomem *regs;
295 int irq;
296 struct clk *clk;
297 struct platform_device *pdev;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800298
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800299 struct spi_transfer *current_transfer;
Axel Lin0c3b9742014-03-27 09:26:38 +0800300 int current_remaining_bytes;
Nicolas Ferre823cd042013-03-19 15:45:01 +0800301 int done_status;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800302
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800303 struct completion xfer_completion;
304
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800305 /* scratch buffer */
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800306 void *buffer;
307 dma_addr_t buffer_dma;
Wenyou Yangd4820b72013-03-19 15:42:15 +0800308
309 struct atmel_spi_caps caps;
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800310
311 bool use_dma;
312 bool use_pdc;
Cyrille Pitchen48203032015-06-09 13:53:52 +0200313 bool use_cs_gpios;
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800314 /* dmaengine data */
315 struct atmel_spi_dma dma;
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800316
317 bool keep_cs;
318 bool cs_active;
Cyrille Pitchen11f27642015-06-16 12:09:31 +0200319
320 u32 fifo_size;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800321};
322
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800323/* Controller-specific per-slave state */
324struct atmel_spi_device {
325 unsigned int npcs_pin;
326 u32 csr;
327};
328
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800329#define BUFFER_SIZE PAGE_SIZE
330#define INVALID_DMA_ADDRESS 0xffffffff
331
332/*
Haavard Skinnemoen5bfa26c2009-01-06 14:41:42 -0800333 * Version 2 of the SPI controller has
334 * - CR.LASTXFER
335 * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
336 * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
337 * - SPI_CSRx.CSAAT
338 * - SPI_CSRx.SBCR allows faster clocking
Haavard Skinnemoen5bfa26c2009-01-06 14:41:42 -0800339 */
Wenyou Yangd4820b72013-03-19 15:42:15 +0800340static bool atmel_spi_is_v2(struct atmel_spi *as)
Haavard Skinnemoen5bfa26c2009-01-06 14:41:42 -0800341{
Wenyou Yangd4820b72013-03-19 15:42:15 +0800342 return as->caps.is_spi2;
Haavard Skinnemoen5bfa26c2009-01-06 14:41:42 -0800343}
344
345/*
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800346 * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
347 * they assume that spi slave device state will not change on deselect, so
David Brownelldefbd3b2007-07-17 04:04:08 -0700348 * that automagic deselection is OK. ("NPCSx rises if no data is to be
349 * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer
350 * controllers have CSAAT and friends.
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800351 *
David Brownelldefbd3b2007-07-17 04:04:08 -0700352 * Since the CSAAT functionality is a bit weird on newer controllers as
353 * well, we use GPIO to control nCSx pins on all controllers, updating
354 * MR.PCS to avoid confusing the controller. Using GPIOs also lets us
355 * support active-high chipselects despite the controller's belief that
356 * only active-low devices/systems exists.
357 *
358 * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
359 * right when driven with GPIO. ("Mode Fault does not allow more than one
360 * Master on Chip Select 0.") No workaround exists for that ... so for
361 * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
362 * and (c) will trigger that first erratum in some cases.
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800363 */
364
David Brownelldefbd3b2007-07-17 04:04:08 -0700365static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800366{
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800367 struct atmel_spi_device *asd = spi->controller_state;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800368 unsigned active = spi->mode & SPI_CS_HIGH;
David Brownelldefbd3b2007-07-17 04:04:08 -0700369 u32 mr;
Atsushi Nemotof6febcc2008-02-23 15:23:39 -0800370
Wenyou Yangd4820b72013-03-19 15:42:15 +0800371 if (atmel_spi_is_v2(as)) {
Wenyou Yang97ed4652013-03-19 15:43:01 +0800372 spi_writel(as, CSR0 + 4 * spi->chip_select, asd->csr);
373 /* For the low SPI version, there is a issue that PDC transfer
374 * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800375 */
376 spi_writel(as, CSR0, asd->csr);
Wenyou Yangd4820b72013-03-19 15:42:15 +0800377 if (as->caps.has_wdrbt) {
Wenyou Yang97ed4652013-03-19 15:43:01 +0800378 spi_writel(as, MR,
379 SPI_BF(PCS, ~(0x01 << spi->chip_select))
380 | SPI_BIT(WDRBT)
381 | SPI_BIT(MODFDIS)
382 | SPI_BIT(MSTR));
Wenyou Yangd4820b72013-03-19 15:42:15 +0800383 } else {
Wenyou Yang97ed4652013-03-19 15:43:01 +0800384 spi_writel(as, MR,
385 SPI_BF(PCS, ~(0x01 << spi->chip_select))
386 | SPI_BIT(MODFDIS)
387 | SPI_BIT(MSTR));
Wenyou Yangd4820b72013-03-19 15:42:15 +0800388 }
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800389
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800390 mr = spi_readl(as, MR);
Cyrille Pitchen48203032015-06-09 13:53:52 +0200391 if (as->use_cs_gpios)
392 gpio_set_value(asd->npcs_pin, active);
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800393 } else {
394 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
395 int i;
396 u32 csr;
397
398 /* Make sure clock polarity is correct */
399 for (i = 0; i < spi->master->num_chipselect; i++) {
400 csr = spi_readl(as, CSR0 + 4 * i);
401 if ((csr ^ cpol) & SPI_BIT(CPOL))
402 spi_writel(as, CSR0 + 4 * i,
403 csr ^ SPI_BIT(CPOL));
404 }
405
406 mr = spi_readl(as, MR);
407 mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
Cyrille Pitchen48203032015-06-09 13:53:52 +0200408 if (as->use_cs_gpios && spi->chip_select != 0)
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800409 gpio_set_value(asd->npcs_pin, active);
410 spi_writel(as, MR, mr);
Atsushi Nemotof6febcc2008-02-23 15:23:39 -0800411 }
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800412
David Brownelldefbd3b2007-07-17 04:04:08 -0700413 dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800414 asd->npcs_pin, active ? " (high)" : "",
David Brownelldefbd3b2007-07-17 04:04:08 -0700415 mr);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800416}
417
David Brownelldefbd3b2007-07-17 04:04:08 -0700418static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800419{
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800420 struct atmel_spi_device *asd = spi->controller_state;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800421 unsigned active = spi->mode & SPI_CS_HIGH;
David Brownelldefbd3b2007-07-17 04:04:08 -0700422 u32 mr;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800423
David Brownelldefbd3b2007-07-17 04:04:08 -0700424 /* only deactivate *this* device; sometimes transfers to
425 * another device may be active when this routine is called.
426 */
427 mr = spi_readl(as, MR);
428 if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
429 mr = SPI_BFINS(PCS, 0xf, mr);
430 spi_writel(as, MR, mr);
431 }
432
433 dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800434 asd->npcs_pin, active ? " (low)" : "",
David Brownelldefbd3b2007-07-17 04:04:08 -0700435 mr);
436
Cyrille Pitchen48203032015-06-09 13:53:52 +0200437 if (!as->use_cs_gpios)
438 spi_writel(as, CR, SPI_BIT(LASTXFER));
439 else if (atmel_spi_is_v2(as) || spi->chip_select != 0)
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800440 gpio_set_value(asd->npcs_pin, !active);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800441}
442
Mark Brown6c07ef22013-07-28 14:32:27 +0100443static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock)
Nicolas Ferre8aad7922013-04-03 13:58:36 +0800444{
445 spin_lock_irqsave(&as->lock, as->flags);
446}
447
Mark Brown6c07ef22013-07-28 14:32:27 +0100448static void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock)
Nicolas Ferre8aad7922013-04-03 13:58:36 +0800449{
450 spin_unlock_irqrestore(&as->lock, as->flags);
451}
452
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800453static inline bool atmel_spi_use_dma(struct atmel_spi *as,
454 struct spi_transfer *xfer)
455{
456 return as->use_dma && xfer->len >= DMA_MIN_BYTES;
457}
458
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800459static int atmel_spi_dma_slave_config(struct atmel_spi *as,
460 struct dma_slave_config *slave_config,
461 u8 bits_per_word)
462{
463 int err = 0;
464
465 if (bits_per_word > 8) {
466 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
467 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
468 } else {
469 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
470 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
471 }
472
473 slave_config->dst_addr = (dma_addr_t)as->phybase + SPI_TDR;
474 slave_config->src_addr = (dma_addr_t)as->phybase + SPI_RDR;
475 slave_config->src_maxburst = 1;
476 slave_config->dst_maxburst = 1;
477 slave_config->device_fc = false;
478
Cyrille Pitchen11f27642015-06-16 12:09:31 +0200479 /*
480 * This driver uses fixed peripheral select mode (PS bit set to '0' in
481 * the Mode Register).
482 * So according to the datasheet, when FIFOs are available (and
483 * enabled), the Transmit FIFO operates in Multiple Data Mode.
484 * In this mode, up to 2 data, not 4, can be written into the Transmit
485 * Data Register in a single access.
486 * However, the first data has to be written into the lowest 16 bits and
487 * the second data into the highest 16 bits of the Transmit
488 * Data Register. For 8bit data (the most frequent case), it would
489 * require to rework tx_buf so each data would actualy fit 16 bits.
490 * So we'd rather write only one data at the time. Hence the transmit
491 * path works the same whether FIFOs are available (and enabled) or not.
492 */
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800493 slave_config->direction = DMA_MEM_TO_DEV;
494 if (dmaengine_slave_config(as->dma.chan_tx, slave_config)) {
495 dev_err(&as->pdev->dev,
496 "failed to configure tx dma channel\n");
497 err = -EINVAL;
498 }
499
Cyrille Pitchen11f27642015-06-16 12:09:31 +0200500 /*
501 * This driver configures the spi controller for master mode (MSTR bit
502 * set to '1' in the Mode Register).
503 * So according to the datasheet, when FIFOs are available (and
504 * enabled), the Receive FIFO operates in Single Data Mode.
505 * So the receive path works the same whether FIFOs are available (and
506 * enabled) or not.
507 */
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800508 slave_config->direction = DMA_DEV_TO_MEM;
509 if (dmaengine_slave_config(as->dma.chan_rx, slave_config)) {
510 dev_err(&as->pdev->dev,
511 "failed to configure rx dma channel\n");
512 err = -EINVAL;
513 }
514
515 return err;
516}
517
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800518static int atmel_spi_configure_dma(struct atmel_spi *as)
519{
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800520 struct dma_slave_config slave_config;
Richard Genoud2f767a92013-05-31 17:01:59 +0200521 struct device *dev = &as->pdev->dev;
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800522 int err;
523
Richard Genoud2f767a92013-05-31 17:01:59 +0200524 dma_cap_mask_t mask;
525 dma_cap_zero(mask);
526 dma_cap_set(DMA_SLAVE, mask);
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800527
Ludovic Desroches5e9af372014-11-14 17:12:54 +0100528 as->dma.chan_tx = dma_request_slave_channel_reason(dev, "tx");
529 if (IS_ERR(as->dma.chan_tx)) {
530 err = PTR_ERR(as->dma.chan_tx);
531 if (err == -EPROBE_DEFER) {
532 dev_warn(dev, "no DMA channel available at the moment\n");
533 return err;
534 }
Richard Genoud2f767a92013-05-31 17:01:59 +0200535 dev_err(dev,
536 "DMA TX channel not available, SPI unable to use DMA\n");
537 err = -EBUSY;
538 goto error;
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800539 }
Richard Genoud2f767a92013-05-31 17:01:59 +0200540
Ludovic Desroches5e9af372014-11-14 17:12:54 +0100541 /*
542 * No reason to check EPROBE_DEFER here since we have already requested
543 * tx channel. If it fails here, it's for another reason.
544 */
Ludovic Desroches7758e392014-11-14 17:12:53 +0100545 as->dma.chan_rx = dma_request_slave_channel(dev, "rx");
Richard Genoud2f767a92013-05-31 17:01:59 +0200546
547 if (!as->dma.chan_rx) {
548 dev_err(dev,
549 "DMA RX channel not available, SPI unable to use DMA\n");
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800550 err = -EBUSY;
551 goto error;
552 }
553
554 err = atmel_spi_dma_slave_config(as, &slave_config, 8);
555 if (err)
556 goto error;
557
558 dev_info(&as->pdev->dev,
559 "Using %s (tx) and %s (rx) for DMA transfers\n",
560 dma_chan_name(as->dma.chan_tx),
561 dma_chan_name(as->dma.chan_rx));
562 return 0;
563error:
564 if (as->dma.chan_rx)
565 dma_release_channel(as->dma.chan_rx);
Ludovic Desroches5e9af372014-11-14 17:12:54 +0100566 if (!IS_ERR(as->dma.chan_tx))
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800567 dma_release_channel(as->dma.chan_tx);
568 return err;
569}
570
571static void atmel_spi_stop_dma(struct atmel_spi *as)
572{
573 if (as->dma.chan_rx)
Vinod Koul5398ad62014-10-11 21:10:35 +0530574 dmaengine_terminate_all(as->dma.chan_rx);
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800575 if (as->dma.chan_tx)
Vinod Koul5398ad62014-10-11 21:10:35 +0530576 dmaengine_terminate_all(as->dma.chan_tx);
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800577}
578
579static void atmel_spi_release_dma(struct atmel_spi *as)
580{
581 if (as->dma.chan_rx)
582 dma_release_channel(as->dma.chan_rx);
583 if (as->dma.chan_tx)
584 dma_release_channel(as->dma.chan_tx);
585}
586
587/* This function is called by the DMA driver from tasklet context */
588static void dma_callback(void *data)
589{
590 struct spi_master *master = data;
591 struct atmel_spi *as = spi_master_get_devdata(master);
592
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800593 complete(&as->xfer_completion);
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800594}
595
596/*
Cyrille Pitchen11f27642015-06-16 12:09:31 +0200597 * Next transfer using PIO without FIFO.
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800598 */
Cyrille Pitchen11f27642015-06-16 12:09:31 +0200599static void atmel_spi_next_xfer_single(struct spi_master *master,
600 struct spi_transfer *xfer)
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800601{
602 struct atmel_spi *as = spi_master_get_devdata(master);
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800603 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800604
605 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
606
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800607 /* Make sure data is not remaining in RDR */
608 spi_readl(as, RDR);
609 while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
610 spi_readl(as, RDR);
611 cpu_relax();
612 }
613
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800614 if (xfer->tx_buf) {
Richard Genoudf557c982013-05-02 19:25:11 +0800615 if (xfer->bits_per_word > 8)
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800616 spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos));
Richard Genoudf557c982013-05-02 19:25:11 +0800617 else
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800618 spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos));
619 } else {
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800620 spi_writel(as, TDR, 0);
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800621 }
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800622
623 dev_dbg(master->dev.parent,
Richard Genoudf557c982013-05-02 19:25:11 +0800624 " start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
625 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
626 xfer->bits_per_word);
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800627
628 /* Enable relevant interrupts */
629 spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
630}
631
632/*
Cyrille Pitchen11f27642015-06-16 12:09:31 +0200633 * Next transfer using PIO with FIFO.
634 */
635static void atmel_spi_next_xfer_fifo(struct spi_master *master,
636 struct spi_transfer *xfer)
637{
638 struct atmel_spi *as = spi_master_get_devdata(master);
639 u32 current_remaining_data, num_data;
640 u32 offset = xfer->len - as->current_remaining_bytes;
641 const u16 *words = (const u16 *)((u8 *)xfer->tx_buf + offset);
642 const u8 *bytes = (const u8 *)((u8 *)xfer->tx_buf + offset);
643 u16 td0, td1;
644 u32 fifomr;
645
646 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_fifo\n");
647
648 /* Compute the number of data to transfer in the current iteration */
649 current_remaining_data = ((xfer->bits_per_word > 8) ?
650 ((u32)as->current_remaining_bytes >> 1) :
651 (u32)as->current_remaining_bytes);
652 num_data = min(current_remaining_data, as->fifo_size);
653
654 /* Flush RX and TX FIFOs */
655 spi_writel(as, CR, SPI_BIT(RXFCLR) | SPI_BIT(TXFCLR));
656 while (spi_readl(as, FLR))
657 cpu_relax();
658
659 /* Set RX FIFO Threshold to the number of data to transfer */
660 fifomr = spi_readl(as, FMR);
661 spi_writel(as, FMR, SPI_BFINS(RXFTHRES, num_data, fifomr));
662
663 /* Clear FIFO flags in the Status Register, especially RXFTHF */
664 (void)spi_readl(as, SR);
665
666 /* Fill TX FIFO */
667 while (num_data >= 2) {
668 if (xfer->tx_buf) {
669 if (xfer->bits_per_word > 8) {
670 td0 = *words++;
671 td1 = *words++;
672 } else {
673 td0 = *bytes++;
674 td1 = *bytes++;
675 }
676 } else {
677 td0 = 0;
678 td1 = 0;
679 }
680
681 spi_writel(as, TDR, (td1 << 16) | td0);
682 num_data -= 2;
683 }
684
685 if (num_data) {
686 if (xfer->tx_buf) {
687 if (xfer->bits_per_word > 8)
688 td0 = *words++;
689 else
690 td0 = *bytes++;
691 } else {
692 td0 = 0;
693 }
694
695 spi_writew(as, TDR, td0);
696 num_data--;
697 }
698
699 dev_dbg(master->dev.parent,
700 " start fifo xfer %p: len %u tx %p rx %p bitpw %d\n",
701 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
702 xfer->bits_per_word);
703
704 /*
705 * Enable RX FIFO Threshold Flag interrupt to be notified about
706 * transfer completion.
707 */
708 spi_writel(as, IER, SPI_BIT(RXFTHF) | SPI_BIT(OVRES));
709}
710
711/*
712 * Next transfer using PIO.
713 */
714static void atmel_spi_next_xfer_pio(struct spi_master *master,
715 struct spi_transfer *xfer)
716{
717 struct atmel_spi *as = spi_master_get_devdata(master);
718
719 if (as->fifo_size)
720 atmel_spi_next_xfer_fifo(master, xfer);
721 else
722 atmel_spi_next_xfer_single(master, xfer);
723}
724
725/*
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800726 * Submit next transfer for DMA.
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800727 */
728static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
729 struct spi_transfer *xfer,
730 u32 *plen)
731{
732 struct atmel_spi *as = spi_master_get_devdata(master);
733 struct dma_chan *rxchan = as->dma.chan_rx;
734 struct dma_chan *txchan = as->dma.chan_tx;
735 struct dma_async_tx_descriptor *rxdesc;
736 struct dma_async_tx_descriptor *txdesc;
737 struct dma_slave_config slave_config;
738 dma_cookie_t cookie;
739 u32 len = *plen;
740
741 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n");
742
743 /* Check that the channels are available */
744 if (!rxchan || !txchan)
745 return -ENODEV;
746
747 /* release lock for DMA operations */
748 atmel_spi_unlock(as);
749
750 /* prepare the RX dma transfer */
751 sg_init_table(&as->dma.sgrx, 1);
752 if (xfer->rx_buf) {
753 as->dma.sgrx.dma_address = xfer->rx_dma + xfer->len - *plen;
754 } else {
755 as->dma.sgrx.dma_address = as->buffer_dma;
756 if (len > BUFFER_SIZE)
757 len = BUFFER_SIZE;
758 }
759
760 /* prepare the TX dma transfer */
761 sg_init_table(&as->dma.sgtx, 1);
762 if (xfer->tx_buf) {
763 as->dma.sgtx.dma_address = xfer->tx_dma + xfer->len - *plen;
764 } else {
765 as->dma.sgtx.dma_address = as->buffer_dma;
766 if (len > BUFFER_SIZE)
767 len = BUFFER_SIZE;
768 memset(as->buffer, 0, len);
769 }
770
771 sg_dma_len(&as->dma.sgtx) = len;
772 sg_dma_len(&as->dma.sgrx) = len;
773
774 *plen = len;
775
David Mosberger-Tang06515f82015-10-20 14:26:47 +0200776 if (atmel_spi_dma_slave_config(as, &slave_config,
777 xfer->bits_per_word))
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800778 goto err_exit;
779
780 /* Send both scatterlists */
Geert Uytterhoevenef40eb32014-07-11 18:13:28 +0200781 rxdesc = dmaengine_prep_slave_sg(rxchan, &as->dma.sgrx, 1,
782 DMA_FROM_DEVICE,
783 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800784 if (!rxdesc)
785 goto err_dma;
786
Geert Uytterhoevenef40eb32014-07-11 18:13:28 +0200787 txdesc = dmaengine_prep_slave_sg(txchan, &as->dma.sgtx, 1,
788 DMA_TO_DEVICE,
789 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800790 if (!txdesc)
791 goto err_dma;
792
793 dev_dbg(master->dev.parent,
Emil Goode2de024b2013-07-30 19:35:35 +0200794 " start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
795 xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma,
796 xfer->rx_buf, (unsigned long long)xfer->rx_dma);
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800797
798 /* Enable relevant interrupts */
799 spi_writel(as, IER, SPI_BIT(OVRES));
800
801 /* Put the callback on the RX transfer only, that should finish last */
802 rxdesc->callback = dma_callback;
803 rxdesc->callback_param = master;
804
805 /* Submit and fire RX and TX with TX last so we're ready to read! */
806 cookie = rxdesc->tx_submit(rxdesc);
807 if (dma_submit_error(cookie))
808 goto err_dma;
809 cookie = txdesc->tx_submit(txdesc);
810 if (dma_submit_error(cookie))
811 goto err_dma;
812 rxchan->device->device_issue_pending(rxchan);
813 txchan->device->device_issue_pending(txchan);
814
815 /* take back lock */
816 atmel_spi_lock(as);
817 return 0;
818
819err_dma:
820 spi_writel(as, IDR, SPI_BIT(OVRES));
821 atmel_spi_stop_dma(as);
822err_exit:
823 atmel_spi_lock(as);
824 return -ENOMEM;
825}
826
Silvester Erdeg154443c2008-02-06 01:38:12 -0800827static void atmel_spi_next_xfer_data(struct spi_master *master,
828 struct spi_transfer *xfer,
829 dma_addr_t *tx_dma,
830 dma_addr_t *rx_dma,
831 u32 *plen)
832{
833 struct atmel_spi *as = spi_master_get_devdata(master);
834 u32 len = *plen;
835
836 /* use scratch buffer only when rx or tx data is unspecified */
837 if (xfer->rx_buf)
Ben Nizette6aed4ee2009-12-14 22:20:20 -0800838 *rx_dma = xfer->rx_dma + xfer->len - *plen;
Silvester Erdeg154443c2008-02-06 01:38:12 -0800839 else {
840 *rx_dma = as->buffer_dma;
841 if (len > BUFFER_SIZE)
842 len = BUFFER_SIZE;
843 }
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800844
Silvester Erdeg154443c2008-02-06 01:38:12 -0800845 if (xfer->tx_buf)
Ben Nizette6aed4ee2009-12-14 22:20:20 -0800846 *tx_dma = xfer->tx_dma + xfer->len - *plen;
Silvester Erdeg154443c2008-02-06 01:38:12 -0800847 else {
848 *tx_dma = as->buffer_dma;
849 if (len > BUFFER_SIZE)
850 len = BUFFER_SIZE;
851 memset(as->buffer, 0, len);
852 dma_sync_single_for_device(&as->pdev->dev,
853 as->buffer_dma, len, DMA_TO_DEVICE);
854 }
855
856 *plen = len;
857}
858
Richard Genoudd3b72c72013-11-07 10:34:06 +0100859static int atmel_spi_set_xfer_speed(struct atmel_spi *as,
860 struct spi_device *spi,
861 struct spi_transfer *xfer)
862{
863 u32 scbr, csr;
864 unsigned long bus_hz;
865
866 /* v1 chips start out at half the peripheral bus speed. */
867 bus_hz = clk_get_rate(as->clk);
868 if (!atmel_spi_is_v2(as))
869 bus_hz /= 2;
870
871 /*
872 * Calculate the lowest divider that satisfies the
873 * constraint, assuming div32/fdiv/mbz == 0.
874 */
Jarkko Nikulae8646582015-09-25 09:03:01 +0300875 scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz);
Richard Genoudd3b72c72013-11-07 10:34:06 +0100876
877 /*
878 * If the resulting divider doesn't fit into the
879 * register bitfield, we can't satisfy the constraint.
880 */
881 if (scbr >= (1 << SPI_SCBR_SIZE)) {
882 dev_err(&spi->dev,
883 "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
884 xfer->speed_hz, scbr, bus_hz/255);
885 return -EINVAL;
886 }
887 if (scbr == 0) {
888 dev_err(&spi->dev,
889 "setup: %d Hz too high, scbr %u; max %ld Hz\n",
890 xfer->speed_hz, scbr, bus_hz);
891 return -EINVAL;
892 }
893 csr = spi_readl(as, CSR0 + 4 * spi->chip_select);
894 csr = SPI_BFINS(SCBR, scbr, csr);
895 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
896
897 return 0;
898}
899
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800900/*
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800901 * Submit next transfer for PDC.
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800902 * lock is held, spi irq is blocked
903 */
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800904static void atmel_spi_pdc_next_xfer(struct spi_master *master,
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800905 struct spi_message *msg,
906 struct spi_transfer *xfer)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800907{
908 struct atmel_spi *as = spi_master_get_devdata(master);
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800909 u32 len;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800910 dma_addr_t tx_dma, rx_dma;
911
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800912 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
Silvester Erdeg154443c2008-02-06 01:38:12 -0800913
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800914 len = as->current_remaining_bytes;
915 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
916 as->current_remaining_bytes -= len;
Gerard Kamdc329442008-08-04 13:41:12 -0700917
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800918 spi_writel(as, RPR, rx_dma);
919 spi_writel(as, TPR, tx_dma);
920
921 if (msg->spi->bits_per_word > 8)
922 len >>= 1;
923 spi_writel(as, RCR, len);
924 spi_writel(as, TCR, len);
925
926 dev_dbg(&msg->spi->dev,
927 " start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
928 xfer, xfer->len, xfer->tx_buf,
929 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
930 (unsigned long long)xfer->rx_dma);
931
932 if (as->current_remaining_bytes) {
933 len = as->current_remaining_bytes;
Silvester Erdeg154443c2008-02-06 01:38:12 -0800934 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800935 as->current_remaining_bytes -= len;
Silvester Erdeg154443c2008-02-06 01:38:12 -0800936
937 spi_writel(as, RNPR, rx_dma);
938 spi_writel(as, TNPR, tx_dma);
939
940 if (msg->spi->bits_per_word > 8)
941 len >>= 1;
942 spi_writel(as, RNCR, len);
943 spi_writel(as, TNCR, len);
Haavard Skinnemoen8bacb212008-02-06 01:38:13 -0800944
945 dev_dbg(&msg->spi->dev,
Emil Goode2de024b2013-07-30 19:35:35 +0200946 " next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
947 xfer, xfer->len, xfer->tx_buf,
948 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
949 (unsigned long long)xfer->rx_dma);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800950 }
951
Torsten Fleischer76e1d142015-02-24 16:32:57 +0100952 /* REVISIT: We're waiting for RXBUFF before we start the next
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800953 * transfer because we need to handle some difficult timing
Torsten Fleischer76e1d142015-02-24 16:32:57 +0100954 * issues otherwise. If we wait for TXBUFE in one transfer and
955 * then starts waiting for RXBUFF in the next, it's difficult
956 * to tell the difference between the RXBUFF interrupt we're
957 * actually waiting for and the RXBUFF interrupt of the
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800958 * previous transfer.
959 *
960 * It should be doable, though. Just not now...
961 */
Torsten Fleischer76e1d142015-02-24 16:32:57 +0100962 spi_writel(as, IER, SPI_BIT(RXBUFF) | SPI_BIT(OVRES));
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800963 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
964}
965
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800966/*
David Brownell8da08592007-07-17 04:04:07 -0700967 * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
968 * - The buffer is either valid for CPU access, else NULL
Uwe Kleine-Königb5950762010-11-01 15:38:34 -0400969 * - If the buffer is valid, so is its DMA address
David Brownell8da08592007-07-17 04:04:07 -0700970 *
Uwe Kleine-Königb5950762010-11-01 15:38:34 -0400971 * This driver manages the dma address unless message->is_dma_mapped.
David Brownell8da08592007-07-17 04:04:07 -0700972 */
973static int
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800974atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
975{
David Brownell8da08592007-07-17 04:04:07 -0700976 struct device *dev = &as->pdev->dev;
977
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800978 xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
David Brownell8da08592007-07-17 04:04:07 -0700979 if (xfer->tx_buf) {
Jean-Christophe PLAGNIOL-VILLARD214b5742010-11-20 14:52:53 +0800980 /* tx_buf is a const void* where we need a void * for the dma
981 * mapping */
982 void *nonconst_tx = (void *)xfer->tx_buf;
983
David Brownell8da08592007-07-17 04:04:07 -0700984 xfer->tx_dma = dma_map_single(dev,
Jean-Christophe PLAGNIOL-VILLARD214b5742010-11-20 14:52:53 +0800985 nonconst_tx, xfer->len,
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800986 DMA_TO_DEVICE);
FUJITA Tomonori8d8bb392008-07-25 19:44:49 -0700987 if (dma_mapping_error(dev, xfer->tx_dma))
David Brownell8da08592007-07-17 04:04:07 -0700988 return -ENOMEM;
989 }
990 if (xfer->rx_buf) {
991 xfer->rx_dma = dma_map_single(dev,
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800992 xfer->rx_buf, xfer->len,
993 DMA_FROM_DEVICE);
FUJITA Tomonori8d8bb392008-07-25 19:44:49 -0700994 if (dma_mapping_error(dev, xfer->rx_dma)) {
David Brownell8da08592007-07-17 04:04:07 -0700995 if (xfer->tx_buf)
996 dma_unmap_single(dev,
997 xfer->tx_dma, xfer->len,
998 DMA_TO_DEVICE);
999 return -ENOMEM;
1000 }
1001 }
1002 return 0;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001003}
1004
1005static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
1006 struct spi_transfer *xfer)
1007{
1008 if (xfer->tx_dma != INVALID_DMA_ADDRESS)
Tony Jones49dce682007-10-16 01:27:48 -07001009 dma_unmap_single(master->dev.parent, xfer->tx_dma,
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001010 xfer->len, DMA_TO_DEVICE);
1011 if (xfer->rx_dma != INVALID_DMA_ADDRESS)
Tony Jones49dce682007-10-16 01:27:48 -07001012 dma_unmap_single(master->dev.parent, xfer->rx_dma,
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001013 xfer->len, DMA_FROM_DEVICE);
1014}
1015
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001016static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
1017{
1018 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1019}
1020
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001021static void
Cyrille Pitchen11f27642015-06-16 12:09:31 +02001022atmel_spi_pump_single_data(struct atmel_spi *as, struct spi_transfer *xfer)
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001023{
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001024 u8 *rxp;
Richard Genoudf557c982013-05-02 19:25:11 +08001025 u16 *rxp16;
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001026 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
1027
1028 if (xfer->rx_buf) {
Richard Genoudf557c982013-05-02 19:25:11 +08001029 if (xfer->bits_per_word > 8) {
1030 rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos);
1031 *rxp16 = spi_readl(as, RDR);
1032 } else {
1033 rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
1034 *rxp = spi_readl(as, RDR);
1035 }
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001036 } else {
1037 spi_readl(as, RDR);
1038 }
Richard Genoudf557c982013-05-02 19:25:11 +08001039 if (xfer->bits_per_word > 8) {
Alexandre Bellonib112f052014-05-06 17:44:41 +02001040 if (as->current_remaining_bytes > 2)
1041 as->current_remaining_bytes -= 2;
1042 else
Richard Genoudf557c982013-05-02 19:25:11 +08001043 as->current_remaining_bytes = 0;
1044 } else {
1045 as->current_remaining_bytes--;
1046 }
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001047}
1048
Cyrille Pitchen11f27642015-06-16 12:09:31 +02001049static void
1050atmel_spi_pump_fifo_data(struct atmel_spi *as, struct spi_transfer *xfer)
1051{
1052 u32 fifolr = spi_readl(as, FLR);
1053 u32 num_bytes, num_data = SPI_BFEXT(RXFL, fifolr);
1054 u32 offset = xfer->len - as->current_remaining_bytes;
1055 u16 *words = (u16 *)((u8 *)xfer->rx_buf + offset);
1056 u8 *bytes = (u8 *)((u8 *)xfer->rx_buf + offset);
1057 u16 rd; /* RD field is the lowest 16 bits of RDR */
1058
1059 /* Update the number of remaining bytes to transfer */
1060 num_bytes = ((xfer->bits_per_word > 8) ?
1061 (num_data << 1) :
1062 num_data);
1063
1064 if (as->current_remaining_bytes > num_bytes)
1065 as->current_remaining_bytes -= num_bytes;
1066 else
1067 as->current_remaining_bytes = 0;
1068
1069 /* Handle odd number of bytes when data are more than 8bit width */
1070 if (xfer->bits_per_word > 8)
1071 as->current_remaining_bytes &= ~0x1;
1072
1073 /* Read data */
1074 while (num_data) {
1075 rd = spi_readl(as, RDR);
1076 if (xfer->rx_buf) {
1077 if (xfer->bits_per_word > 8)
1078 *words++ = rd;
1079 else
1080 *bytes++ = rd;
1081 }
1082 num_data--;
1083 }
1084}
1085
1086/* Called from IRQ
1087 *
1088 * Must update "current_remaining_bytes" to keep track of data
1089 * to transfer.
1090 */
1091static void
1092atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
1093{
1094 if (as->fifo_size)
1095 atmel_spi_pump_fifo_data(as, xfer);
1096 else
1097 atmel_spi_pump_single_data(as, xfer);
1098}
1099
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001100/* Interrupt
1101 *
1102 * No need for locking in this Interrupt handler: done_status is the
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001103 * only information modified.
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001104 */
1105static irqreturn_t
1106atmel_spi_pio_interrupt(int irq, void *dev_id)
1107{
1108 struct spi_master *master = dev_id;
1109 struct atmel_spi *as = spi_master_get_devdata(master);
1110 u32 status, pending, imr;
1111 struct spi_transfer *xfer;
1112 int ret = IRQ_NONE;
1113
1114 imr = spi_readl(as, IMR);
1115 status = spi_readl(as, SR);
1116 pending = status & imr;
1117
1118 if (pending & SPI_BIT(OVRES)) {
1119 ret = IRQ_HANDLED;
1120 spi_writel(as, IDR, SPI_BIT(OVRES));
1121 dev_warn(master->dev.parent, "overrun\n");
1122
1123 /*
1124 * When we get an overrun, we disregard the current
1125 * transfer. Data will not be copied back from any
1126 * bounce buffer and msg->actual_len will not be
1127 * updated with the last xfer.
1128 *
1129 * We will also not process any remaning transfers in
1130 * the message.
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001131 */
1132 as->done_status = -EIO;
1133 smp_wmb();
1134
1135 /* Clear any overrun happening while cleaning up */
1136 spi_readl(as, SR);
1137
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001138 complete(&as->xfer_completion);
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001139
Cyrille Pitchen11f27642015-06-16 12:09:31 +02001140 } else if (pending & (SPI_BIT(RDRF) | SPI_BIT(RXFTHF))) {
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001141 atmel_spi_lock(as);
1142
1143 if (as->current_remaining_bytes) {
1144 ret = IRQ_HANDLED;
1145 xfer = as->current_transfer;
1146 atmel_spi_pump_pio_data(as, xfer);
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001147 if (!as->current_remaining_bytes)
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001148 spi_writel(as, IDR, pending);
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001149
1150 complete(&as->xfer_completion);
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001151 }
1152
1153 atmel_spi_unlock(as);
1154 } else {
1155 WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
1156 ret = IRQ_HANDLED;
1157 spi_writel(as, IDR, pending);
1158 }
1159
1160 return ret;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001161}
1162
1163static irqreturn_t
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001164atmel_spi_pdc_interrupt(int irq, void *dev_id)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001165{
1166 struct spi_master *master = dev_id;
1167 struct atmel_spi *as = spi_master_get_devdata(master);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001168 u32 status, pending, imr;
1169 int ret = IRQ_NONE;
1170
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001171 imr = spi_readl(as, IMR);
1172 status = spi_readl(as, SR);
1173 pending = status & imr;
1174
1175 if (pending & SPI_BIT(OVRES)) {
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001176
1177 ret = IRQ_HANDLED;
1178
Gerard Kamdc329442008-08-04 13:41:12 -07001179 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001180 | SPI_BIT(OVRES)));
1181
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001182 /* Clear any overrun happening while cleaning up */
1183 spi_readl(as, SR);
1184
Nicolas Ferre823cd042013-03-19 15:45:01 +08001185 as->done_status = -EIO;
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001186
1187 complete(&as->xfer_completion);
1188
Gerard Kamdc329442008-08-04 13:41:12 -07001189 } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001190 ret = IRQ_HANDLED;
1191
1192 spi_writel(as, IDR, pending);
1193
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001194 complete(&as->xfer_completion);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001195 }
1196
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001197 return ret;
1198}
1199
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001200static int atmel_spi_setup(struct spi_device *spi)
1201{
1202 struct atmel_spi *as;
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -08001203 struct atmel_spi_device *asd;
Richard Genoudd3b72c72013-11-07 10:34:06 +01001204 u32 csr;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001205 unsigned int bits = spi->bits_per_word;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001206 unsigned int npcs_pin;
1207 int ret;
1208
1209 as = spi_master_get_devdata(spi->master);
1210
David Brownelldefbd3b2007-07-17 04:04:08 -07001211 /* see notes above re chipselect */
Wenyou Yangd4820b72013-03-19 15:42:15 +08001212 if (!atmel_spi_is_v2(as)
David Brownelldefbd3b2007-07-17 04:04:08 -07001213 && spi->chip_select == 0
1214 && (spi->mode & SPI_CS_HIGH)) {
1215 dev_dbg(&spi->dev, "setup: can't be active-high\n");
1216 return -EINVAL;
1217 }
1218
Richard Genoudd3b72c72013-11-07 10:34:06 +01001219 csr = SPI_BF(BITS, bits - 8);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001220 if (spi->mode & SPI_CPOL)
1221 csr |= SPI_BIT(CPOL);
1222 if (!(spi->mode & SPI_CPHA))
1223 csr |= SPI_BIT(NCPHA);
Cyrille Pitchen48203032015-06-09 13:53:52 +02001224 if (!as->use_cs_gpios)
1225 csr |= SPI_BIT(CSAAT);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001226
Haavard Skinnemoen1eed29d2008-02-06 01:38:11 -08001227 /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
1228 *
1229 * DLYBCT would add delays between words, slowing down transfers.
1230 * It could potentially be useful to cope with DMA bottlenecks, but
1231 * in those cases it's probably best to just use a lower bitrate.
1232 */
1233 csr |= SPI_BF(DLYBS, 0);
1234 csr |= SPI_BF(DLYBCT, 0);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001235
1236 /* chipselect must have been muxed as GPIO (e.g. in board setup) */
Mark Brown67f08d62014-08-01 17:43:03 +01001237 npcs_pin = (unsigned long)spi->controller_data;
Jean-Christophe PLAGNIOL-VILLARD850a5b62012-11-23 13:44:39 +01001238
Cyrille Pitchen48203032015-06-09 13:53:52 +02001239 if (!as->use_cs_gpios)
1240 npcs_pin = spi->chip_select;
1241 else if (gpio_is_valid(spi->cs_gpio))
Jean-Christophe PLAGNIOL-VILLARD850a5b62012-11-23 13:44:39 +01001242 npcs_pin = spi->cs_gpio;
1243
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -08001244 asd = spi->controller_state;
1245 if (!asd) {
1246 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
1247 if (!asd)
1248 return -ENOMEM;
1249
Cyrille Pitchen48203032015-06-09 13:53:52 +02001250 if (as->use_cs_gpios) {
1251 ret = gpio_request(npcs_pin, dev_name(&spi->dev));
1252 if (ret) {
1253 kfree(asd);
1254 return ret;
1255 }
1256
1257 gpio_direction_output(npcs_pin,
1258 !(spi->mode & SPI_CS_HIGH));
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -08001259 }
1260
1261 asd->npcs_pin = npcs_pin;
1262 spi->controller_state = asd;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001263 }
1264
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -08001265 asd->csr = csr;
1266
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001267 dev_dbg(&spi->dev,
Richard Genoudd3b72c72013-11-07 10:34:06 +01001268 "setup: bpw %u mode 0x%x -> csr%d %08x\n",
1269 bits, spi->mode, spi->chip_select, csr);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001270
Wenyou Yangd4820b72013-03-19 15:42:15 +08001271 if (!atmel_spi_is_v2(as))
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -08001272 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001273
1274 return 0;
1275}
1276
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001277static int atmel_spi_one_transfer(struct spi_master *master,
1278 struct spi_message *msg,
1279 struct spi_transfer *xfer)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001280{
1281 struct atmel_spi *as;
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001282 struct spi_device *spi = msg->spi;
Matthias Bruggerb9d228f2010-10-13 17:51:02 +02001283 u8 bits;
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001284 u32 len;
Matthias Bruggerb9d228f2010-10-13 17:51:02 +02001285 struct atmel_spi_device *asd;
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001286 int timeout;
1287 int ret;
Nicholas Mc Guire1369dea2015-02-02 10:43:31 -05001288 unsigned long dma_timeout;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001289
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001290 as = spi_master_get_devdata(master);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001291
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001292 if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
1293 dev_dbg(&spi->dev, "missing rx or tx buf\n");
1294 return -EINVAL;
1295 }
1296
Jarkko Nikulae8646582015-09-25 09:03:01 +03001297 asd = spi->controller_state;
1298 bits = (asd->csr >> 4) & 0xf;
1299 if (bits != xfer->bits_per_word - 8) {
1300 dev_dbg(&spi->dev,
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001301 "you can't yet change bits_per_word in transfers\n");
Jarkko Nikulae8646582015-09-25 09:03:01 +03001302 return -ENOPROTOOPT;
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001303 }
1304
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001305 /*
1306 * DMA map early, for performance (empties dcache ASAP) and
1307 * better fault reporting.
1308 */
1309 if ((!msg->is_dma_mapped)
1310 && (atmel_spi_use_dma(as, xfer) || as->use_pdc)) {
1311 if (atmel_spi_dma_map_xfer(as, xfer) < 0)
1312 return -ENOMEM;
1313 }
1314
1315 atmel_spi_set_xfer_speed(as, msg->spi, xfer);
1316
1317 as->done_status = 0;
1318 as->current_transfer = xfer;
1319 as->current_remaining_bytes = xfer->len;
1320 while (as->current_remaining_bytes) {
1321 reinit_completion(&as->xfer_completion);
1322
1323 if (as->use_pdc) {
1324 atmel_spi_pdc_next_xfer(master, msg, xfer);
1325 } else if (atmel_spi_use_dma(as, xfer)) {
1326 len = as->current_remaining_bytes;
1327 ret = atmel_spi_next_xfer_dma_submit(master,
1328 xfer, &len);
1329 if (ret) {
1330 dev_err(&spi->dev,
1331 "unable to use DMA, fallback to PIO\n");
1332 atmel_spi_next_xfer_pio(master, xfer);
1333 } else {
1334 as->current_remaining_bytes -= len;
Axel Lin0c3b9742014-03-27 09:26:38 +08001335 if (as->current_remaining_bytes < 0)
1336 as->current_remaining_bytes = 0;
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001337 }
1338 } else {
1339 atmel_spi_next_xfer_pio(master, xfer);
1340 }
1341
Alexander Stein16760142014-04-13 12:45:10 +02001342 /* interrupts are disabled, so free the lock for schedule */
1343 atmel_spi_unlock(as);
Nicholas Mc Guire1369dea2015-02-02 10:43:31 -05001344 dma_timeout = wait_for_completion_timeout(&as->xfer_completion,
1345 SPI_DMA_TIMEOUT);
Alexander Stein16760142014-04-13 12:45:10 +02001346 atmel_spi_lock(as);
Nicholas Mc Guire1369dea2015-02-02 10:43:31 -05001347 if (WARN_ON(dma_timeout == 0)) {
1348 dev_err(&spi->dev, "spi transfer timeout\n");
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001349 as->done_status = -EIO;
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001350 }
1351
1352 if (as->done_status)
1353 break;
1354 }
1355
1356 if (as->done_status) {
1357 if (as->use_pdc) {
1358 dev_warn(master->dev.parent,
1359 "overrun (%u/%u remaining)\n",
1360 spi_readl(as, TCR), spi_readl(as, RCR));
1361
1362 /*
1363 * Clean up DMA registers and make sure the data
1364 * registers are empty.
1365 */
1366 spi_writel(as, RNCR, 0);
1367 spi_writel(as, TNCR, 0);
1368 spi_writel(as, RCR, 0);
1369 spi_writel(as, TCR, 0);
1370 for (timeout = 1000; timeout; timeout--)
1371 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
1372 break;
1373 if (!timeout)
1374 dev_warn(master->dev.parent,
1375 "timeout waiting for TXEMPTY");
1376 while (spi_readl(as, SR) & SPI_BIT(RDRF))
1377 spi_readl(as, RDR);
1378
1379 /* Clear any overrun happening while cleaning up */
1380 spi_readl(as, SR);
1381
1382 } else if (atmel_spi_use_dma(as, xfer)) {
1383 atmel_spi_stop_dma(as);
1384 }
1385
1386 if (!msg->is_dma_mapped
1387 && (atmel_spi_use_dma(as, xfer) || as->use_pdc))
1388 atmel_spi_dma_unmap_xfer(master, xfer);
1389
1390 return 0;
1391
1392 } else {
1393 /* only update length if no error */
1394 msg->actual_length += xfer->len;
1395 }
1396
1397 if (!msg->is_dma_mapped
1398 && (atmel_spi_use_dma(as, xfer) || as->use_pdc))
1399 atmel_spi_dma_unmap_xfer(master, xfer);
1400
1401 if (xfer->delay_usecs)
1402 udelay(xfer->delay_usecs);
1403
1404 if (xfer->cs_change) {
1405 if (list_is_last(&xfer->transfer_list,
1406 &msg->transfers)) {
1407 as->keep_cs = true;
1408 } else {
1409 as->cs_active = !as->cs_active;
1410 if (as->cs_active)
1411 cs_activate(as, msg->spi);
1412 else
1413 cs_deactivate(as, msg->spi);
1414 }
1415 }
1416
1417 return 0;
1418}
1419
1420static int atmel_spi_transfer_one_message(struct spi_master *master,
1421 struct spi_message *msg)
1422{
1423 struct atmel_spi *as;
1424 struct spi_transfer *xfer;
1425 struct spi_device *spi = msg->spi;
1426 int ret = 0;
1427
1428 as = spi_master_get_devdata(master);
1429
1430 dev_dbg(&spi->dev, "new message %p submitted for %s\n",
1431 msg, dev_name(&spi->dev));
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001432
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001433 atmel_spi_lock(as);
1434 cs_activate(as, spi);
1435
1436 as->cs_active = true;
1437 as->keep_cs = false;
1438
1439 msg->status = 0;
1440 msg->actual_length = 0;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001441
1442 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001443 ret = atmel_spi_one_transfer(master, msg, xfer);
1444 if (ret)
1445 goto msg_done;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001446 }
1447
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001448 if (as->use_pdc)
1449 atmel_spi_disable_pdc_transfer(as);
1450
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001451 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001452 dev_dbg(&spi->dev,
Randy Dunlap54f4c512014-03-21 08:53:41 -07001453 " xfer %p: len %u tx %p/%pad rx %p/%pad\n",
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001454 xfer, xfer->len,
Randy Dunlap54f4c512014-03-21 08:53:41 -07001455 xfer->tx_buf, &xfer->tx_dma,
1456 xfer->rx_buf, &xfer->rx_dma);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001457 }
1458
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001459msg_done:
1460 if (!as->keep_cs)
1461 cs_deactivate(as, msg->spi);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001462
Nicolas Ferre8aad7922013-04-03 13:58:36 +08001463 atmel_spi_unlock(as);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001464
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001465 msg->status = as->done_status;
1466 spi_finalize_current_message(spi->master);
1467
1468 return ret;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001469}
1470
David Brownellbb2d1c32007-02-20 13:58:19 -08001471static void atmel_spi_cleanup(struct spi_device *spi)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001472{
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -08001473 struct atmel_spi_device *asd = spi->controller_state;
Mark Brown67f08d62014-08-01 17:43:03 +01001474 unsigned gpio = (unsigned long) spi->controller_data;
David Brownelldefbd3b2007-07-17 04:04:08 -07001475
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -08001476 if (!asd)
David Brownelldefbd3b2007-07-17 04:04:08 -07001477 return;
1478
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -08001479 spi->controller_state = NULL;
David Brownelldefbd3b2007-07-17 04:04:08 -07001480 gpio_free(gpio);
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -08001481 kfree(asd);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001482}
1483
Wenyou Yangd4820b72013-03-19 15:42:15 +08001484static inline unsigned int atmel_get_version(struct atmel_spi *as)
1485{
1486 return spi_readl(as, VERSION) & 0x00000fff;
1487}
1488
1489static void atmel_get_caps(struct atmel_spi *as)
1490{
1491 unsigned int version;
1492
1493 version = atmel_get_version(as);
1494 dev_info(&as->pdev->dev, "version: 0x%x\n", version);
1495
1496 as->caps.is_spi2 = version > 0x121;
1497 as->caps.has_wdrbt = version >= 0x210;
1498 as->caps.has_dma_support = version >= 0x212;
1499}
1500
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001501/*-------------------------------------------------------------------------*/
1502
Grant Likelyfd4a3192012-12-07 16:57:14 +00001503static int atmel_spi_probe(struct platform_device *pdev)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001504{
1505 struct resource *regs;
1506 int irq;
1507 struct clk *clk;
1508 int ret;
1509 struct spi_master *master;
1510 struct atmel_spi *as;
1511
Wenyou Yang5bdfd492014-03-05 09:58:49 +08001512 /* Select default pin state */
1513 pinctrl_pm_select_default_state(&pdev->dev);
1514
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001515 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1516 if (!regs)
1517 return -ENXIO;
1518
1519 irq = platform_get_irq(pdev, 0);
1520 if (irq < 0)
1521 return irq;
1522
Jingoo Han9f87d6f2013-12-04 14:07:51 +09001523 clk = devm_clk_get(&pdev->dev, "spi_clk");
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001524 if (IS_ERR(clk))
1525 return PTR_ERR(clk);
1526
1527 /* setup spi core then atmel-specific driver state */
1528 ret = -ENOMEM;
Sachin Kamata536d762013-09-10 17:06:27 +05301529 master = spi_alloc_master(&pdev->dev, sizeof(*as));
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001530 if (!master)
1531 goto out_free;
1532
David Brownelle7db06b2009-06-17 16:26:04 -07001533 /* the spi->mode bits understood by this driver: */
1534 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
Stephen Warren24778be2013-05-21 20:36:35 -06001535 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
Jean-Christophe PLAGNIOL-VILLARD850a5b62012-11-23 13:44:39 +01001536 master->dev.of_node = pdev->dev.of_node;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001537 master->bus_num = pdev->id;
Jean-Christophe PLAGNIOL-VILLARD850a5b62012-11-23 13:44:39 +01001538 master->num_chipselect = master->dev.of_node ? 0 : 4;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001539 master->setup = atmel_spi_setup;
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001540 master->transfer_one_message = atmel_spi_transfer_one_message;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001541 master->cleanup = atmel_spi_cleanup;
Wenyou Yangce0c4ca2014-10-16 17:23:10 +08001542 master->auto_runtime_pm = true;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001543 platform_set_drvdata(pdev, master);
1544
1545 as = spi_master_get_devdata(master);
1546
David Brownell8da08592007-07-17 04:04:07 -07001547 /*
1548 * Scratch buffer is used for throwaway rx and tx data.
1549 * It's coherent to minimize dcache pollution.
1550 */
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001551 as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
1552 &as->buffer_dma, GFP_KERNEL);
1553 if (!as->buffer)
1554 goto out_free;
1555
1556 spin_lock_init(&as->lock);
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001557
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001558 as->pdev = pdev;
Mark Brown31407472013-10-16 13:22:35 +01001559 as->regs = devm_ioremap_resource(&pdev->dev, regs);
Wei Yongjun543c9542013-10-21 11:12:02 +08001560 if (IS_ERR(as->regs)) {
1561 ret = PTR_ERR(as->regs);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001562 goto out_free_buffer;
Wei Yongjun543c9542013-10-21 11:12:02 +08001563 }
Nicolas Ferredfab30e2013-04-03 13:57:42 +08001564 as->phybase = regs->start;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001565 as->irq = irq;
1566 as->clk = clk;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001567
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001568 init_completion(&as->xfer_completion);
1569
Wenyou Yangd4820b72013-03-19 15:42:15 +08001570 atmel_get_caps(as);
1571
Cyrille Pitchen48203032015-06-09 13:53:52 +02001572 as->use_cs_gpios = true;
1573 if (atmel_spi_is_v2(as) &&
1574 !of_get_property(pdev->dev.of_node, "cs-gpios", NULL)) {
1575 as->use_cs_gpios = false;
1576 master->num_chipselect = 4;
1577 }
1578
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001579 as->use_dma = false;
1580 as->use_pdc = false;
1581 if (as->caps.has_dma_support) {
Ludovic Desroches5e9af372014-11-14 17:12:54 +01001582 ret = atmel_spi_configure_dma(as);
1583 if (ret == 0)
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001584 as->use_dma = true;
Ludovic Desroches5e9af372014-11-14 17:12:54 +01001585 else if (ret == -EPROBE_DEFER)
1586 return ret;
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001587 } else {
1588 as->use_pdc = true;
1589 }
1590
1591 if (as->caps.has_dma_support && !as->use_dma)
1592 dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n");
1593
1594 if (as->use_pdc) {
Jingoo Han9f87d6f2013-12-04 14:07:51 +09001595 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt,
1596 0, dev_name(&pdev->dev), master);
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001597 } else {
Jingoo Han9f87d6f2013-12-04 14:07:51 +09001598 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt,
1599 0, dev_name(&pdev->dev), master);
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001600 }
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001601 if (ret)
1602 goto out_unmap_regs;
1603
1604 /* Initialize the hardware */
Boris BREZILLONdfec4a62013-07-16 17:16:22 +02001605 ret = clk_prepare_enable(clk);
1606 if (ret)
Sachin Kamatde8cc232013-09-10 17:06:26 +05301607 goto out_free_irq;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001608 spi_writel(as, CR, SPI_BIT(SWRST));
Jean-Christophe Lallemand50d7d5b2008-11-12 13:27:00 -08001609 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
Wenyou Yangd4820b72013-03-19 15:42:15 +08001610 if (as->caps.has_wdrbt) {
1611 spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS)
1612 | SPI_BIT(MSTR));
1613 } else {
1614 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
1615 }
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001616
1617 if (as->use_pdc)
1618 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001619 spi_writel(as, CR, SPI_BIT(SPIEN));
1620
Cyrille Pitchen11f27642015-06-16 12:09:31 +02001621 as->fifo_size = 0;
1622 if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size",
1623 &as->fifo_size)) {
1624 dev_info(&pdev->dev, "Using FIFO (%u data)\n", as->fifo_size);
1625 spi_writel(as, CR, SPI_BIT(FIFOEN));
1626 }
1627
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001628 /* go! */
1629 dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
1630 (unsigned long)regs->start, irq);
1631
Wenyou Yangce0c4ca2014-10-16 17:23:10 +08001632 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1633 pm_runtime_use_autosuspend(&pdev->dev);
1634 pm_runtime_set_active(&pdev->dev);
1635 pm_runtime_enable(&pdev->dev);
1636
Jingoo Han9f87d6f2013-12-04 14:07:51 +09001637 ret = devm_spi_register_master(&pdev->dev, master);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001638 if (ret)
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001639 goto out_free_dma;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001640
1641 return 0;
1642
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001643out_free_dma:
Wenyou Yangce0c4ca2014-10-16 17:23:10 +08001644 pm_runtime_disable(&pdev->dev);
1645 pm_runtime_set_suspended(&pdev->dev);
1646
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001647 if (as->use_dma)
1648 atmel_spi_release_dma(as);
1649
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001650 spi_writel(as, CR, SPI_BIT(SWRST));
Jean-Christophe Lallemand50d7d5b2008-11-12 13:27:00 -08001651 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
Boris BREZILLONdfec4a62013-07-16 17:16:22 +02001652 clk_disable_unprepare(clk);
Sachin Kamatde8cc232013-09-10 17:06:26 +05301653out_free_irq:
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001654out_unmap_regs:
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001655out_free_buffer:
1656 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
1657 as->buffer_dma);
1658out_free:
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001659 spi_master_put(master);
1660 return ret;
1661}
1662
Grant Likelyfd4a3192012-12-07 16:57:14 +00001663static int atmel_spi_remove(struct platform_device *pdev)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001664{
1665 struct spi_master *master = platform_get_drvdata(pdev);
1666 struct atmel_spi *as = spi_master_get_devdata(master);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001667
Wenyou Yangce0c4ca2014-10-16 17:23:10 +08001668 pm_runtime_get_sync(&pdev->dev);
1669
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001670 /* reset the hardware and block queue progress */
1671 spin_lock_irq(&as->lock);
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001672 if (as->use_dma) {
1673 atmel_spi_stop_dma(as);
1674 atmel_spi_release_dma(as);
1675 }
1676
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001677 spi_writel(as, CR, SPI_BIT(SWRST));
Jean-Christophe Lallemand50d7d5b2008-11-12 13:27:00 -08001678 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001679 spi_readl(as, SR);
1680 spin_unlock_irq(&as->lock);
1681
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001682 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
1683 as->buffer_dma);
1684
Boris BREZILLONdfec4a62013-07-16 17:16:22 +02001685 clk_disable_unprepare(as->clk);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001686
Wenyou Yangce0c4ca2014-10-16 17:23:10 +08001687 pm_runtime_put_noidle(&pdev->dev);
1688 pm_runtime_disable(&pdev->dev);
1689
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001690 return 0;
1691}
1692
Wenyou Yangce0c4ca2014-10-16 17:23:10 +08001693#ifdef CONFIG_PM
Wenyou Yangce0c4ca2014-10-16 17:23:10 +08001694static int atmel_spi_runtime_suspend(struct device *dev)
1695{
1696 struct spi_master *master = dev_get_drvdata(dev);
1697 struct atmel_spi *as = spi_master_get_devdata(master);
Jingoo Hanec60dd32013-09-09 17:54:12 +09001698
Wenyou Yangce0c4ca2014-10-16 17:23:10 +08001699 clk_disable_unprepare(as->clk);
1700 pinctrl_pm_select_sleep_state(dev);
1701
1702 return 0;
1703}
1704
1705static int atmel_spi_runtime_resume(struct device *dev)
1706{
1707 struct spi_master *master = dev_get_drvdata(dev);
1708 struct atmel_spi *as = spi_master_get_devdata(master);
Wenyou Yangce0c4ca2014-10-16 17:23:10 +08001709
1710 pinctrl_pm_select_default_state(dev);
1711
Fengguang Wud0de6ff2014-10-17 00:18:56 +08001712 return clk_prepare_enable(as->clk);
Wenyou Yangce0c4ca2014-10-16 17:23:10 +08001713}
Wenyou Yangc1ee8f32014-10-21 11:43:34 +08001714
Alexandre Bellonid6305262015-09-10 10:19:52 +02001715#ifdef CONFIG_PM_SLEEP
Wenyou Yangc1ee8f32014-10-21 11:43:34 +08001716static int atmel_spi_suspend(struct device *dev)
1717{
1718 struct spi_master *master = dev_get_drvdata(dev);
1719 int ret;
1720
1721 /* Stop the queue running */
1722 ret = spi_master_suspend(master);
1723 if (ret) {
1724 dev_warn(dev, "cannot suspend master\n");
1725 return ret;
1726 }
1727
1728 if (!pm_runtime_suspended(dev))
1729 atmel_spi_runtime_suspend(dev);
1730
1731 return 0;
1732}
1733
1734static int atmel_spi_resume(struct device *dev)
1735{
1736 struct spi_master *master = dev_get_drvdata(dev);
1737 int ret;
1738
1739 if (!pm_runtime_suspended(dev)) {
1740 ret = atmel_spi_runtime_resume(dev);
1741 if (ret)
1742 return ret;
1743 }
1744
1745 /* Start the queue running */
1746 ret = spi_master_resume(master);
1747 if (ret)
1748 dev_err(dev, "problem starting queue (%d)\n", ret);
1749
1750 return ret;
1751}
Alexandre Bellonid6305262015-09-10 10:19:52 +02001752#endif
Wenyou Yangce0c4ca2014-10-16 17:23:10 +08001753
1754static const struct dev_pm_ops atmel_spi_pm_ops = {
1755 SET_SYSTEM_SLEEP_PM_OPS(atmel_spi_suspend, atmel_spi_resume)
1756 SET_RUNTIME_PM_OPS(atmel_spi_runtime_suspend,
1757 atmel_spi_runtime_resume, NULL)
1758};
Jingoo Hanec60dd32013-09-09 17:54:12 +09001759#define ATMEL_SPI_PM_OPS (&atmel_spi_pm_ops)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001760#else
Jingoo Hanec60dd32013-09-09 17:54:12 +09001761#define ATMEL_SPI_PM_OPS NULL
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001762#endif
1763
Jean-Christophe PLAGNIOL-VILLARD850a5b62012-11-23 13:44:39 +01001764#if defined(CONFIG_OF)
1765static const struct of_device_id atmel_spi_dt_ids[] = {
1766 { .compatible = "atmel,at91rm9200-spi" },
1767 { /* sentinel */ }
1768};
1769
1770MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
1771#endif
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001772
1773static struct platform_driver atmel_spi_driver = {
1774 .driver = {
1775 .name = "atmel_spi",
Jingoo Hanec60dd32013-09-09 17:54:12 +09001776 .pm = ATMEL_SPI_PM_OPS,
Jean-Christophe PLAGNIOL-VILLARD850a5b62012-11-23 13:44:39 +01001777 .of_match_table = of_match_ptr(atmel_spi_dt_ids),
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001778 },
Jean-Christophe PLAGNIOL-VILLARD1cb201a2011-11-04 01:20:21 +08001779 .probe = atmel_spi_probe,
Grant Likely2deff8d2013-02-05 13:27:35 +00001780 .remove = atmel_spi_remove,
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001781};
Grant Likely940ab882011-10-05 11:29:49 -06001782module_platform_driver(atmel_spi_driver);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001783
1784MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
Jean Delvaree05503e2011-05-18 16:49:24 +02001785MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001786MODULE_LICENSE("GPL");
Kay Sievers7e38c3c2008-04-10 21:29:20 -07001787MODULE_ALIAS("platform:atmel_spi");