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Shadi Ammouri60cadec2008-08-05 13:01:09 -07001/*
Grant Likelyca632f52011-06-06 01:16:30 -06002 * Marvell Orion SPI controller driver
Shadi Ammouri60cadec2008-08-05 13:01:09 -07003 *
4 * Author: Shadi Ammouri <shadi@marvell.com>
5 * Copyright (C) 2007-2008 Marvell Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
Shadi Ammouri60cadec2008-08-05 13:01:09 -070012#include <linux/interrupt.h>
13#include <linux/delay.h>
14#include <linux/platform_device.h>
15#include <linux/err.h>
16#include <linux/io.h>
17#include <linux/spi/spi.h>
Paul Gortmakerd7614de2011-07-03 15:44:29 -040018#include <linux/module.h>
Russell King5c678692014-06-21 12:22:37 +010019#include <linux/pm_runtime.h>
Andrew Lunnf814f9a2012-07-23 12:08:09 +020020#include <linux/of.h>
Stefan Roeseb3c195b2016-05-19 09:07:05 +020021#include <linux/of_address.h>
Greg Ungererdf59fa72014-09-28 23:24:04 +100022#include <linux/of_device.h>
Andrew Lunn4574b882012-04-06 17:17:26 +020023#include <linux/clk.h>
Mark Brown895248f2013-07-29 05:10:21 +010024#include <linux/sizes.h>
Shadi Ammouri60cadec2008-08-05 13:01:09 -070025#include <asm/unaligned.h>
26
27#define DRIVER_NAME "orion_spi"
28
Russell King5c678692014-06-21 12:22:37 +010029/* Runtime PM autosuspend timeout: PM is fairly light on this driver */
30#define SPI_AUTOSUSPEND_TIMEOUT 200
31
Ken Wilson23244402015-01-16 13:10:47 +100032/* Some SoCs using this driver support up to 8 chip selects.
33 * It is up to the implementer to only use the chip selects
34 * that are available.
35 */
36#define ORION_NUM_CHIPSELECTS 8
37
Shadi Ammouri60cadec2008-08-05 13:01:09 -070038#define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */
39
40#define ORION_SPI_IF_CTRL_REG 0x00
41#define ORION_SPI_IF_CONFIG_REG 0x04
42#define ORION_SPI_DATA_OUT_REG 0x08
43#define ORION_SPI_DATA_IN_REG 0x0c
44#define ORION_SPI_INT_CAUSE_REG 0x10
Nadav Haklai38d62112015-08-11 11:58:47 +020045#define ORION_SPI_TIMING_PARAMS_REG 0x18
46
Stefan Roeseb3c195b2016-05-19 09:07:05 +020047/* Register for the "Direct Mode" */
48#define SPI_DIRECT_WRITE_CONFIG_REG 0x20
49
Nadav Haklai38d62112015-08-11 11:58:47 +020050#define ORION_SPI_TMISO_SAMPLE_MASK (0x3 << 6)
51#define ORION_SPI_TMISO_SAMPLE_1 (1 << 6)
52#define ORION_SPI_TMISO_SAMPLE_2 (2 << 6)
Shadi Ammouri60cadec2008-08-05 13:01:09 -070053
Jason Gunthorpeb15d5d72012-11-21 12:23:35 -070054#define ORION_SPI_MODE_CPOL (1 << 11)
55#define ORION_SPI_MODE_CPHA (1 << 12)
Shadi Ammouri60cadec2008-08-05 13:01:09 -070056#define ORION_SPI_IF_8_16_BIT_MODE (1 << 5)
57#define ORION_SPI_CLK_PRESCALE_MASK 0x1F
Greg Ungererdf59fa72014-09-28 23:24:04 +100058#define ARMADA_SPI_CLK_PRESCALE_MASK 0xDF
Jason Gunthorpeb15d5d72012-11-21 12:23:35 -070059#define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL | \
60 ORION_SPI_MODE_CPHA)
Ken Wilson23244402015-01-16 13:10:47 +100061#define ORION_SPI_CS_MASK 0x1C
62#define ORION_SPI_CS_SHIFT 2
63#define ORION_SPI_CS(cs) ((cs << ORION_SPI_CS_SHIFT) & \
64 ORION_SPI_CS_MASK)
Shadi Ammouri60cadec2008-08-05 13:01:09 -070065
Greg Ungererdf59fa72014-09-28 23:24:04 +100066enum orion_spi_type {
67 ORION_SPI,
68 ARMADA_SPI,
69};
70
71struct orion_spi_dev {
72 enum orion_spi_type typ;
Gregory CLEMENTce2f6ea2015-05-26 11:44:42 +020073 /*
74 * min_divisor and max_hz should be exclusive, the only we can
75 * have both is for managing the armada-370-spi case with old
76 * device tree
77 */
78 unsigned long max_hz;
Greg Ungererdf59fa72014-09-28 23:24:04 +100079 unsigned int min_divisor;
80 unsigned int max_divisor;
81 u32 prescale_mask;
Nadav Haklai38d62112015-08-11 11:58:47 +020082 bool is_errata_50mhz_ac;
Greg Ungererdf59fa72014-09-28 23:24:04 +100083};
84
Stefan Roeseb3c195b2016-05-19 09:07:05 +020085struct orion_direct_acc {
86 void __iomem *vaddr;
87 u32 size;
88};
89
Shadi Ammouri60cadec2008-08-05 13:01:09 -070090struct orion_spi {
Shadi Ammouri60cadec2008-08-05 13:01:09 -070091 struct spi_master *master;
92 void __iomem *base;
Andrew Lunn4574b882012-04-06 17:17:26 +020093 struct clk *clk;
Greg Ungererdf59fa72014-09-28 23:24:04 +100094 const struct orion_spi_dev *devdata;
Stefan Roeseb3c195b2016-05-19 09:07:05 +020095
96 struct orion_direct_acc direct_access[ORION_NUM_CHIPSELECTS];
Shadi Ammouri60cadec2008-08-05 13:01:09 -070097};
98
Shadi Ammouri60cadec2008-08-05 13:01:09 -070099static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg)
100{
101 return orion_spi->base + reg;
102}
103
104static inline void
105orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
106{
107 void __iomem *reg_addr = spi_reg(orion_spi, reg);
108 u32 val;
109
110 val = readl(reg_addr);
111 val |= mask;
112 writel(val, reg_addr);
113}
114
115static inline void
116orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
117{
118 void __iomem *reg_addr = spi_reg(orion_spi, reg);
119 u32 val;
120
121 val = readl(reg_addr);
122 val &= ~mask;
123 writel(val, reg_addr);
124}
125
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700126static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
127{
128 u32 tclk_hz;
129 u32 rate;
130 u32 prescale;
131 u32 reg;
132 struct orion_spi *orion_spi;
Greg Ungererdf59fa72014-09-28 23:24:04 +1000133 const struct orion_spi_dev *devdata;
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700134
135 orion_spi = spi_master_get_devdata(spi->master);
Greg Ungererdf59fa72014-09-28 23:24:04 +1000136 devdata = orion_spi->devdata;
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700137
Andrew Lunn4574b882012-04-06 17:17:26 +0200138 tclk_hz = clk_get_rate(orion_spi->clk);
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700139
Greg Ungererdf59fa72014-09-28 23:24:04 +1000140 if (devdata->typ == ARMADA_SPI) {
141 unsigned int clk, spr, sppr, sppr2, err;
142 unsigned int best_spr, best_sppr, best_err;
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700143
Greg Ungererdf59fa72014-09-28 23:24:04 +1000144 best_err = speed;
145 best_spr = 0;
146 best_sppr = 0;
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700147
Greg Ungererdf59fa72014-09-28 23:24:04 +1000148 /* Iterate over the valid range looking for best fit */
149 for (sppr = 0; sppr < 8; sppr++) {
150 sppr2 = 0x1 << sppr;
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700151
Greg Ungererdf59fa72014-09-28 23:24:04 +1000152 spr = tclk_hz / sppr2;
153 spr = DIV_ROUND_UP(spr, speed);
154 if ((spr == 0) || (spr > 15))
155 continue;
156
157 clk = tclk_hz / (spr * sppr2);
158 err = speed - clk;
159
160 if (err < best_err) {
161 best_spr = spr;
162 best_sppr = sppr;
163 best_err = err;
164 }
165 }
166
167 if ((best_sppr == 0) && (best_spr == 0))
168 return -EINVAL;
169
170 prescale = ((best_sppr & 0x6) << 5) |
171 ((best_sppr & 0x1) << 4) | best_spr;
172 } else {
173 /*
174 * the supported rates are: 4,6,8...30
175 * round up as we look for equal or less speed
176 */
177 rate = DIV_ROUND_UP(tclk_hz, speed);
178 rate = roundup(rate, 2);
179
180 /* check if requested speed is too small */
181 if (rate > 30)
182 return -EINVAL;
183
184 if (rate < 4)
185 rate = 4;
186
187 /* Convert the rate to SPI clock divisor value. */
188 prescale = 0x10 + rate/2;
189 }
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700190
191 reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
Greg Ungererdf59fa72014-09-28 23:24:04 +1000192 reg = ((reg & ~devdata->prescale_mask) | prescale);
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700193 writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
194
195 return 0;
196}
197
Jason Gunthorpeb15d5d72012-11-21 12:23:35 -0700198static void
199orion_spi_mode_set(struct spi_device *spi)
200{
201 u32 reg;
202 struct orion_spi *orion_spi;
203
204 orion_spi = spi_master_get_devdata(spi->master);
205
206 reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
207 reg &= ~ORION_SPI_MODE_MASK;
208 if (spi->mode & SPI_CPOL)
209 reg |= ORION_SPI_MODE_CPOL;
210 if (spi->mode & SPI_CPHA)
211 reg |= ORION_SPI_MODE_CPHA;
212 writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
213}
214
Nadav Haklai38d62112015-08-11 11:58:47 +0200215static void
216orion_spi_50mhz_ac_timing_erratum(struct spi_device *spi, unsigned int speed)
217{
218 u32 reg;
219 struct orion_spi *orion_spi;
220
221 orion_spi = spi_master_get_devdata(spi->master);
222
223 /*
224 * Erratum description: (Erratum NO. FE-9144572) The device
225 * SPI interface supports frequencies of up to 50 MHz.
226 * However, due to this erratum, when the device core clock is
227 * 250 MHz and the SPI interfaces is configured for 50MHz SPI
228 * clock and CPOL=CPHA=1 there might occur data corruption on
229 * reads from the SPI device.
230 * Erratum Workaround:
231 * Work in one of the following configurations:
232 * 1. Set CPOL=CPHA=0 in "SPI Interface Configuration
233 * Register".
234 * 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1
235 * Register" before setting the interface.
236 */
237 reg = readl(spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG));
238 reg &= ~ORION_SPI_TMISO_SAMPLE_MASK;
239
240 if (clk_get_rate(orion_spi->clk) == 250000000 &&
241 speed == 50000000 && spi->mode & SPI_CPOL &&
242 spi->mode & SPI_CPHA)
243 reg |= ORION_SPI_TMISO_SAMPLE_2;
244 else
245 reg |= ORION_SPI_TMISO_SAMPLE_1; /* This is the default value */
246
247 writel(reg, spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG));
248}
249
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700250/*
251 * called only when no transfer is active on the bus
252 */
253static int
254orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
255{
256 struct orion_spi *orion_spi;
257 unsigned int speed = spi->max_speed_hz;
258 unsigned int bits_per_word = spi->bits_per_word;
259 int rc;
260
261 orion_spi = spi_master_get_devdata(spi->master);
262
263 if ((t != NULL) && t->speed_hz)
264 speed = t->speed_hz;
265
266 if ((t != NULL) && t->bits_per_word)
267 bits_per_word = t->bits_per_word;
268
Jason Gunthorpeb15d5d72012-11-21 12:23:35 -0700269 orion_spi_mode_set(spi);
270
Nadav Haklai38d62112015-08-11 11:58:47 +0200271 if (orion_spi->devdata->is_errata_50mhz_ac)
272 orion_spi_50mhz_ac_timing_erratum(spi, speed);
273
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700274 rc = orion_spi_baudrate_set(spi, speed);
275 if (rc)
276 return rc;
277
Axel Lin495b3352014-02-11 20:51:36 +0800278 if (bits_per_word == 16)
279 orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
280 ORION_SPI_IF_8_16_BIT_MODE);
281 else
282 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
283 ORION_SPI_IF_8_16_BIT_MODE);
284
285 return 0;
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700286}
287
Ken Wilson75872eb2015-01-12 13:13:59 +1000288static void orion_spi_set_cs(struct spi_device *spi, bool enable)
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700289{
Ken Wilson75872eb2015-01-12 13:13:59 +1000290 struct orion_spi *orion_spi;
291
292 orion_spi = spi_master_get_devdata(spi->master);
293
Ken Wilson23244402015-01-16 13:10:47 +1000294 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, ORION_SPI_CS_MASK);
295 orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG,
296 ORION_SPI_CS(spi->chip_select));
297
Ken Wilson75872eb2015-01-12 13:13:59 +1000298 /* Chip select logic is inverted from spi_set_cs */
299 if (!enable)
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700300 orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
301 else
302 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
303}
304
305static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi)
306{
307 int i;
308
309 for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) {
310 if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG)))
311 return 1;
Jingoo Hanb8434042014-09-02 11:51:39 +0900312
313 udelay(1);
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700314 }
315
316 return -1;
317}
318
319static inline int
320orion_spi_write_read_8bit(struct spi_device *spi,
321 const u8 **tx_buf, u8 **rx_buf)
322{
323 void __iomem *tx_reg, *rx_reg, *int_reg;
324 struct orion_spi *orion_spi;
325
326 orion_spi = spi_master_get_devdata(spi->master);
327 tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
328 rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
329 int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
330
331 /* clear the interrupt cause register */
332 writel(0x0, int_reg);
333
334 if (tx_buf && *tx_buf)
335 writel(*(*tx_buf)++, tx_reg);
336 else
337 writel(0, tx_reg);
338
339 if (orion_spi_wait_till_ready(orion_spi) < 0) {
340 dev_err(&spi->dev, "TXS timed out\n");
341 return -1;
342 }
343
344 if (rx_buf && *rx_buf)
345 *(*rx_buf)++ = readl(rx_reg);
346
347 return 1;
348}
349
350static inline int
351orion_spi_write_read_16bit(struct spi_device *spi,
352 const u16 **tx_buf, u16 **rx_buf)
353{
354 void __iomem *tx_reg, *rx_reg, *int_reg;
355 struct orion_spi *orion_spi;
356
357 orion_spi = spi_master_get_devdata(spi->master);
358 tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
359 rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
360 int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
361
362 /* clear the interrupt cause register */
363 writel(0x0, int_reg);
364
365 if (tx_buf && *tx_buf)
366 writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg);
367 else
368 writel(0, tx_reg);
369
370 if (orion_spi_wait_till_ready(orion_spi) < 0) {
371 dev_err(&spi->dev, "TXS timed out\n");
372 return -1;
373 }
374
375 if (rx_buf && *rx_buf)
376 put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++);
377
378 return 1;
379}
380
381static unsigned int
382orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
383{
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700384 unsigned int count;
385 int word_len;
Stefan Roeseb3c195b2016-05-19 09:07:05 +0200386 struct orion_spi *orion_spi;
387 int cs = spi->chip_select;
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700388
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700389 word_len = spi->bits_per_word;
390 count = xfer->len;
391
Stefan Roeseb3c195b2016-05-19 09:07:05 +0200392 orion_spi = spi_master_get_devdata(spi->master);
393
394 /*
395 * Use SPI direct write mode if base address is available. Otherwise
396 * fall back to PIO mode for this transfer.
397 */
398 if ((orion_spi->direct_access[cs].vaddr) && (xfer->tx_buf) &&
399 (word_len == 8)) {
400 unsigned int cnt = count / 4;
401 unsigned int rem = count % 4;
402
403 /*
404 * Send the TX-data to the SPI device via the direct
405 * mapped address window
406 */
407 iowrite32_rep(orion_spi->direct_access[cs].vaddr,
408 xfer->tx_buf, cnt);
409 if (rem) {
410 u32 *buf = (u32 *)xfer->tx_buf;
411
412 iowrite8_rep(orion_spi->direct_access[cs].vaddr,
413 &buf[cnt], rem);
414 }
415
416 return count;
417 }
418
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700419 if (word_len == 8) {
420 const u8 *tx = xfer->tx_buf;
421 u8 *rx = xfer->rx_buf;
422
423 do {
424 if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0)
425 goto out;
426 count--;
427 } while (count);
428 } else if (word_len == 16) {
429 const u16 *tx = xfer->tx_buf;
430 u16 *rx = xfer->rx_buf;
431
432 do {
433 if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0)
434 goto out;
435 count -= 2;
436 } while (count);
437 }
438
439out:
440 return xfer->len - count;
441}
442
Ken Wilson75872eb2015-01-12 13:13:59 +1000443static int orion_spi_transfer_one(struct spi_master *master,
444 struct spi_device *spi,
445 struct spi_transfer *t)
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700446{
Andrew Lunnba59a802012-07-23 13:16:55 +0200447 int status = 0;
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700448
Ken Wilson75872eb2015-01-12 13:13:59 +1000449 status = orion_spi_setup_transfer(spi, t);
Andrew Lunnba59a802012-07-23 13:16:55 +0200450 if (status < 0)
Ken Wilson75872eb2015-01-12 13:13:59 +1000451 return status;
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700452
Ken Wilson75872eb2015-01-12 13:13:59 +1000453 if (t->len)
454 orion_spi_write_read(spi, t);
Andrew Lunnba59a802012-07-23 13:16:55 +0200455
Ken Wilson75872eb2015-01-12 13:13:59 +1000456 return status;
457}
Andrew Lunnba59a802012-07-23 13:16:55 +0200458
Ken Wilson75872eb2015-01-12 13:13:59 +1000459static int orion_spi_setup(struct spi_device *spi)
460{
461 return orion_spi_setup_transfer(spi, NULL);
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700462}
463
Grant Likely2deff8d2013-02-05 13:27:35 +0000464static int orion_spi_reset(struct orion_spi *orion_spi)
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700465{
466 /* Verify that the CS is deasserted */
Ken Wilson75872eb2015-01-12 13:13:59 +1000467 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
Stefan Roeseb3c195b2016-05-19 09:07:05 +0200468
469 /* Don't deassert CS between the direct mapped SPI transfers */
470 writel(0, spi_reg(orion_spi, SPI_DIRECT_WRITE_CONFIG_REG));
471
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700472 return 0;
473}
474
Greg Ungererdf59fa72014-09-28 23:24:04 +1000475static const struct orion_spi_dev orion_spi_dev_data = {
476 .typ = ORION_SPI,
477 .min_divisor = 4,
478 .max_divisor = 30,
479 .prescale_mask = ORION_SPI_CLK_PRESCALE_MASK,
480};
481
Gregory CLEMENT4dacccf2015-05-26 11:44:43 +0200482static const struct orion_spi_dev armada_370_spi_dev_data = {
Greg Ungererdf59fa72014-09-28 23:24:04 +1000483 .typ = ARMADA_SPI,
Gregory CLEMENTce2f6ea2015-05-26 11:44:42 +0200484 .min_divisor = 4,
Greg Ungererdf59fa72014-09-28 23:24:04 +1000485 .max_divisor = 1920,
Gregory CLEMENTce2f6ea2015-05-26 11:44:42 +0200486 .max_hz = 50000000,
Greg Ungererdf59fa72014-09-28 23:24:04 +1000487 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
488};
489
Gregory CLEMENT4dacccf2015-05-26 11:44:43 +0200490static const struct orion_spi_dev armada_xp_spi_dev_data = {
491 .typ = ARMADA_SPI,
492 .max_hz = 50000000,
493 .max_divisor = 1920,
494 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
495};
496
497static const struct orion_spi_dev armada_375_spi_dev_data = {
498 .typ = ARMADA_SPI,
499 .min_divisor = 15,
500 .max_divisor = 1920,
501 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
502};
503
Nadav Haklai38d62112015-08-11 11:58:47 +0200504static const struct orion_spi_dev armada_380_spi_dev_data = {
505 .typ = ARMADA_SPI,
506 .max_hz = 50000000,
507 .max_divisor = 1920,
508 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
509 .is_errata_50mhz_ac = true,
510};
511
Greg Ungererdf59fa72014-09-28 23:24:04 +1000512static const struct of_device_id orion_spi_of_match_table[] = {
Gregory CLEMENT4dacccf2015-05-26 11:44:43 +0200513 {
514 .compatible = "marvell,orion-spi",
515 .data = &orion_spi_dev_data,
516 },
517 {
518 .compatible = "marvell,armada-370-spi",
519 .data = &armada_370_spi_dev_data,
520 },
521 {
522 .compatible = "marvell,armada-375-spi",
523 .data = &armada_375_spi_dev_data,
524 },
525 {
526 .compatible = "marvell,armada-380-spi",
Nadav Haklai38d62112015-08-11 11:58:47 +0200527 .data = &armada_380_spi_dev_data,
Gregory CLEMENT4dacccf2015-05-26 11:44:43 +0200528 },
529 {
530 .compatible = "marvell,armada-390-spi",
531 .data = &armada_xp_spi_dev_data,
532 },
533 {
534 .compatible = "marvell,armada-xp-spi",
535 .data = &armada_xp_spi_dev_data,
536 },
537
Greg Ungererdf59fa72014-09-28 23:24:04 +1000538 {}
539};
540MODULE_DEVICE_TABLE(of, orion_spi_of_match_table);
541
Grant Likely2deff8d2013-02-05 13:27:35 +0000542static int orion_spi_probe(struct platform_device *pdev)
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700543{
Greg Ungererdf59fa72014-09-28 23:24:04 +1000544 const struct of_device_id *of_id;
545 const struct orion_spi_dev *devdata;
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700546 struct spi_master *master;
547 struct orion_spi *spi;
548 struct resource *r;
Andrew Lunn4574b882012-04-06 17:17:26 +0200549 unsigned long tclk_hz;
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700550 int status = 0;
Stefan Roeseb3c195b2016-05-19 09:07:05 +0200551 struct device_node *np;
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700552
Jingoo Han3fed8062013-10-14 10:35:08 +0900553 master = spi_alloc_master(&pdev->dev, sizeof(*spi));
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700554 if (master == NULL) {
555 dev_dbg(&pdev->dev, "master allocation failed\n");
556 return -ENOMEM;
557 }
558
559 if (pdev->id != -1)
560 master->bus_num = pdev->id;
Andrew Lunnf814f9a2012-07-23 12:08:09 +0200561 if (pdev->dev.of_node) {
Thomas Petazzonie06871c2014-07-27 23:53:19 +0200562 u32 cell_index;
Jingoo Hanb8434042014-09-02 11:51:39 +0900563
Thomas Petazzonie06871c2014-07-27 23:53:19 +0200564 if (!of_property_read_u32(pdev->dev.of_node, "cell-index",
565 &cell_index))
566 master->bus_num = cell_index;
Andrew Lunnf814f9a2012-07-23 12:08:09 +0200567 }
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700568
David Brownelle7db06b2009-06-17 16:26:04 -0700569 /* we support only mode 0, and no options */
Jason Gunthorpeb15d5d72012-11-21 12:23:35 -0700570 master->mode_bits = SPI_CPHA | SPI_CPOL;
Ken Wilson75872eb2015-01-12 13:13:59 +1000571 master->set_cs = orion_spi_set_cs;
572 master->transfer_one = orion_spi_transfer_one;
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700573 master->num_chipselect = ORION_NUM_CHIPSELECTS;
Ken Wilson75872eb2015-01-12 13:13:59 +1000574 master->setup = orion_spi_setup;
Axel Lin495b3352014-02-11 20:51:36 +0800575 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
Russell King5c678692014-06-21 12:22:37 +0100576 master->auto_runtime_pm = true;
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700577
Jingoo Han24b5a822013-05-23 19:20:40 +0900578 platform_set_drvdata(pdev, master);
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700579
580 spi = spi_master_get_devdata(master);
581 spi->master = master;
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700582
Greg Ungererdf59fa72014-09-28 23:24:04 +1000583 of_id = of_match_device(orion_spi_of_match_table, &pdev->dev);
Greg Ungerer9a2d3632014-10-21 15:57:48 +1000584 devdata = (of_id) ? of_id->data : &orion_spi_dev_data;
Greg Ungererdf59fa72014-09-28 23:24:04 +1000585 spi->devdata = devdata;
586
Jingoo Hanbb489842013-12-09 19:21:22 +0900587 spi->clk = devm_clk_get(&pdev->dev, NULL);
Andrew Lunn4574b882012-04-06 17:17:26 +0200588 if (IS_ERR(spi->clk)) {
589 status = PTR_ERR(spi->clk);
590 goto out;
591 }
592
Russell Kingc85012a2014-06-21 11:32:23 +0100593 status = clk_prepare_enable(spi->clk);
594 if (status)
595 goto out;
596
Andrew Lunn4574b882012-04-06 17:17:26 +0200597 tclk_hz = clk_get_rate(spi->clk);
Gregory CLEMENTce2f6ea2015-05-26 11:44:42 +0200598
599 /*
600 * With old device tree, armada-370-spi could be used with
601 * Armada XP, however for this SoC the maximum frequency is
602 * 50MHz instead of tclk/4. On Armada 370, tclk cannot be
603 * higher than 200MHz. So, in order to be able to handle both
604 * SoCs, we can take the minimum of 50MHz and tclk/4.
605 */
606 if (of_device_is_compatible(pdev->dev.of_node,
607 "marvell,armada-370-spi"))
608 master->max_speed_hz = min(devdata->max_hz,
609 DIV_ROUND_UP(tclk_hz, devdata->min_divisor));
Gregory CLEMENT4dacccf2015-05-26 11:44:43 +0200610 else if (devdata->min_divisor)
Gregory CLEMENTce2f6ea2015-05-26 11:44:42 +0200611 master->max_speed_hz =
612 DIV_ROUND_UP(tclk_hz, devdata->min_divisor);
Gregory CLEMENT4dacccf2015-05-26 11:44:43 +0200613 else
614 master->max_speed_hz = devdata->max_hz;
Greg Ungererdf59fa72014-09-28 23:24:04 +1000615 master->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor);
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700616
617 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Mark Brown1729ce32013-07-28 14:38:06 +0100618 spi->base = devm_ioremap_resource(&pdev->dev, r);
619 if (IS_ERR(spi->base)) {
620 status = PTR_ERR(spi->base);
Andrew Lunn4574b882012-04-06 17:17:26 +0200621 goto out_rel_clk;
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700622 }
623
Stefan Roeseb3c195b2016-05-19 09:07:05 +0200624 /* Scan all SPI devices of this controller for direct mapped devices */
625 for_each_available_child_of_node(pdev->dev.of_node, np) {
626 u32 cs;
627
628 /* Get chip-select number from the "reg" property */
629 status = of_property_read_u32(np, "reg", &cs);
630 if (status) {
631 dev_err(&pdev->dev,
632 "%s has no valid 'reg' property (%d)\n",
633 np->full_name, status);
634 status = 0;
635 continue;
636 }
637
638 /*
639 * Check if an address is configured for this SPI device. If
640 * not, the MBus mapping via the 'ranges' property in the 'soc'
641 * node is not configured and this device should not use the
642 * direct mode. In this case, just continue with the next
643 * device.
644 */
645 status = of_address_to_resource(pdev->dev.of_node, cs + 1, r);
646 if (status)
647 continue;
648
649 /*
650 * Only map one page for direct access. This is enough for the
651 * simple TX transfer which only writes to the first word.
652 * This needs to get extended for the direct SPI-NOR / SPI-NAND
653 * support, once this gets implemented.
654 */
655 spi->direct_access[cs].vaddr = devm_ioremap(&pdev->dev,
656 r->start,
657 PAGE_SIZE);
Wei Yongjun57c624a2016-06-13 14:32:23 +0000658 if (!spi->direct_access[cs].vaddr) {
659 status = -ENOMEM;
Stefan Roeseb3c195b2016-05-19 09:07:05 +0200660 goto out_rel_clk;
661 }
662 spi->direct_access[cs].size = PAGE_SIZE;
663
664 dev_info(&pdev->dev, "CS%d configured for direct access\n", cs);
665 }
666
Russell King5c678692014-06-21 12:22:37 +0100667 pm_runtime_set_active(&pdev->dev);
668 pm_runtime_use_autosuspend(&pdev->dev);
669 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
670 pm_runtime_enable(&pdev->dev);
671
Wei Yongjun14033812014-07-20 22:03:14 +0800672 status = orion_spi_reset(spi);
673 if (status < 0)
Russell King5c678692014-06-21 12:22:37 +0100674 goto out_rel_pm;
675
676 pm_runtime_mark_last_busy(&pdev->dev);
677 pm_runtime_put_autosuspend(&pdev->dev);
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700678
Andrew Lunnf814f9a2012-07-23 12:08:09 +0200679 master->dev.of_node = pdev->dev.of_node;
Russell King5c678692014-06-21 12:22:37 +0100680 status = spi_register_master(master);
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700681 if (status < 0)
Russell King5c678692014-06-21 12:22:37 +0100682 goto out_rel_pm;
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700683
684 return status;
685
Russell King5c678692014-06-21 12:22:37 +0100686out_rel_pm:
687 pm_runtime_disable(&pdev->dev);
Andrew Lunn4574b882012-04-06 17:17:26 +0200688out_rel_clk:
689 clk_disable_unprepare(spi->clk);
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700690out:
691 spi_master_put(master);
692 return status;
693}
694
695
Grant Likely2deff8d2013-02-05 13:27:35 +0000696static int orion_spi_remove(struct platform_device *pdev)
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700697{
Russell King5c678692014-06-21 12:22:37 +0100698 struct spi_master *master = platform_get_drvdata(pdev);
699 struct orion_spi *spi = spi_master_get_devdata(master);
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700700
Russell King5c678692014-06-21 12:22:37 +0100701 pm_runtime_get_sync(&pdev->dev);
Andrew Lunn4574b882012-04-06 17:17:26 +0200702 clk_disable_unprepare(spi->clk);
Andrew Lunn4574b882012-04-06 17:17:26 +0200703
Russell King5c678692014-06-21 12:22:37 +0100704 spi_unregister_master(master);
705 pm_runtime_disable(&pdev->dev);
706
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700707 return 0;
708}
709
710MODULE_ALIAS("platform:" DRIVER_NAME);
711
Rafael J. Wysockiec833052014-12-13 00:41:15 +0100712#ifdef CONFIG_PM
Russell King5c678692014-06-21 12:22:37 +0100713static int orion_spi_runtime_suspend(struct device *dev)
714{
715 struct spi_master *master = dev_get_drvdata(dev);
716 struct orion_spi *spi = spi_master_get_devdata(master);
717
718 clk_disable_unprepare(spi->clk);
719 return 0;
720}
721
722static int orion_spi_runtime_resume(struct device *dev)
723{
724 struct spi_master *master = dev_get_drvdata(dev);
725 struct orion_spi *spi = spi_master_get_devdata(master);
726
727 return clk_prepare_enable(spi->clk);
728}
729#endif
730
731static const struct dev_pm_ops orion_spi_pm_ops = {
732 SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend,
733 orion_spi_runtime_resume,
734 NULL)
735};
736
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700737static struct platform_driver orion_spi_driver = {
738 .driver = {
739 .name = DRIVER_NAME,
Russell King5c678692014-06-21 12:22:37 +0100740 .pm = &orion_spi_pm_ops,
Andrew Lunnf814f9a2012-07-23 12:08:09 +0200741 .of_match_table = of_match_ptr(orion_spi_of_match_table),
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700742 },
Ezequiel Garcia41ab7242013-02-04 09:26:26 -0300743 .probe = orion_spi_probe,
Grant Likely2deff8d2013-02-05 13:27:35 +0000744 .remove = orion_spi_remove,
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700745};
746
Ezequiel Garcia41ab7242013-02-04 09:26:26 -0300747module_platform_driver(orion_spi_driver);
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700748
749MODULE_DESCRIPTION("Orion SPI driver");
750MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
751MODULE_LICENSE("GPL");