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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* via-rhine.c: A Linux Ethernet device driver for VIA Rhine family chips. */
2/*
3 Written 1998-2001 by Donald Becker.
4
5 Current Maintainer: Roger Luethi <rl@hellgate.ch>
6
7 This software may be used and distributed according to the terms of
8 the GNU General Public License (GPL), incorporated herein by reference.
9 Drivers based on or derived from this code fall under the GPL and must
10 retain the authorship, copyright and license notice. This file is not
11 a complete program and may only be used when the entire operating
12 system is licensed under the GPL.
13
14 This driver is designed for the VIA VT86C100A Rhine-I.
15 It also works with the Rhine-II (6102) and Rhine-III (6105/6105L/6105LOM
16 and management NIC 6105M).
17
18 The author may be reached as becker@scyld.com, or C/O
19 Scyld Computing Corporation
20 410 Severn Ave., Suite 210
21 Annapolis MD 21403
22
23
24 This driver contains some changes from the original Donald Becker
25 version. He may or may not be interested in bug reports on this
26 code. You can find his versions at:
27 http://www.scyld.com/network/via-rhine.html
Jeff Garzik03a8c662006-06-27 07:57:22 -040028 [link no longer provides useful info -jgarzik]
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
30*/
31
32#define DRV_NAME "via-rhine"
Roger Luethie84df482007-03-06 19:57:37 +010033#define DRV_VERSION "1.4.3"
34#define DRV_RELDATE "2007-03-06"
Linus Torvalds1da177e2005-04-16 15:20:36 -070035
36
37/* A few user-configurable values.
38 These may be modified when a driver module is loaded. */
39
40static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
41static int max_interrupt_work = 20;
42
43/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44 Setting to > 1518 effectively disables this feature. */
Dustin Marquessb47157f2007-08-10 14:05:15 -070045#if defined(__alpha__) || defined(__arm__) || defined(__hppa__) \
46 || defined(CONFIG_SPARC) || defined(__ia64__) \
47 || defined(__sh__) || defined(__mips__)
48static int rx_copybreak = 1518;
49#else
Linus Torvalds1da177e2005-04-16 15:20:36 -070050static int rx_copybreak;
Dustin Marquessb47157f2007-08-10 14:05:15 -070051#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070052
Roger Luethib933b4d2006-08-14 23:00:21 -070053/* Work-around for broken BIOSes: they are unable to get the chip back out of
54 power state D3 so PXE booting fails. bootparam(7): via-rhine.avoid_D3=1 */
55static int avoid_D3;
56
Linus Torvalds1da177e2005-04-16 15:20:36 -070057/*
58 * In case you are looking for 'options[]' or 'full_duplex[]', they
59 * are gone. Use ethtool(8) instead.
60 */
61
62/* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
63 The Rhine has a 64 element 8390-like hash table. */
64static const int multicast_filter_limit = 32;
65
66
67/* Operational parameters that are set at compile time. */
68
69/* Keep the ring sizes a power of two for compile efficiency.
70 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
71 Making the Tx ring too large decreases the effectiveness of channel
72 bonding and packet priority.
73 There are no ill effects from too-large receive rings. */
74#define TX_RING_SIZE 16
75#define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */
Roger Luethi633949a2006-08-14 23:00:17 -070076#ifdef CONFIG_VIA_RHINE_NAPI
77#define RX_RING_SIZE 64
78#else
Linus Torvalds1da177e2005-04-16 15:20:36 -070079#define RX_RING_SIZE 16
Roger Luethi633949a2006-08-14 23:00:17 -070080#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070081
82
83/* Operational parameters that usually are not changed. */
84
85/* Time in jiffies before concluding the transmitter is hung. */
86#define TX_TIMEOUT (2*HZ)
87
88#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
89
90#include <linux/module.h>
91#include <linux/moduleparam.h>
92#include <linux/kernel.h>
93#include <linux/string.h>
94#include <linux/timer.h>
95#include <linux/errno.h>
96#include <linux/ioport.h>
97#include <linux/slab.h>
98#include <linux/interrupt.h>
99#include <linux/pci.h>
Domen Puncer1e7f0bd2005-06-26 18:22:14 -0400100#include <linux/dma-mapping.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700101#include <linux/netdevice.h>
102#include <linux/etherdevice.h>
103#include <linux/skbuff.h>
104#include <linux/init.h>
105#include <linux/delay.h>
106#include <linux/mii.h>
107#include <linux/ethtool.h>
108#include <linux/crc32.h>
109#include <linux/bitops.h>
110#include <asm/processor.h> /* Processor type for cache alignment. */
111#include <asm/io.h>
112#include <asm/irq.h>
113#include <asm/uaccess.h>
Roger Luethie84df482007-03-06 19:57:37 +0100114#include <linux/dmi.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700115
116/* These identify the driver base version and may not be removed. */
117static char version[] __devinitdata =
118KERN_INFO DRV_NAME ".c:v1.10-LK" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker\n";
119
120/* This driver was written to use PCI memory space. Some early versions
121 of the Rhine may only work correctly with I/O space accesses. */
122#ifdef CONFIG_VIA_RHINE_MMIO
123#define USE_MMIO
124#else
125#endif
126
127MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
128MODULE_DESCRIPTION("VIA Rhine PCI Fast Ethernet driver");
129MODULE_LICENSE("GPL");
130
131module_param(max_interrupt_work, int, 0);
132module_param(debug, int, 0);
133module_param(rx_copybreak, int, 0);
Roger Luethib933b4d2006-08-14 23:00:21 -0700134module_param(avoid_D3, bool, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700135MODULE_PARM_DESC(max_interrupt_work, "VIA Rhine maximum events handled per interrupt");
136MODULE_PARM_DESC(debug, "VIA Rhine debug level (0-7)");
137MODULE_PARM_DESC(rx_copybreak, "VIA Rhine copy breakpoint for copy-only-tiny-frames");
Roger Luethib933b4d2006-08-14 23:00:21 -0700138MODULE_PARM_DESC(avoid_D3, "Avoid power state D3 (work-around for broken BIOSes)");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700139
140/*
141 Theory of Operation
142
143I. Board Compatibility
144
145This driver is designed for the VIA 86c100A Rhine-II PCI Fast Ethernet
146controller.
147
148II. Board-specific settings
149
150Boards with this chip are functional only in a bus-master PCI slot.
151
152Many operational settings are loaded from the EEPROM to the Config word at
153offset 0x78. For most of these settings, this driver assumes that they are
154correct.
155If this driver is compiled to use PCI memory space operations the EEPROM
156must be configured to enable memory ops.
157
158III. Driver operation
159
160IIIa. Ring buffers
161
162This driver uses two statically allocated fixed-size descriptor lists
163formed into rings by a branch from the final descriptor to the beginning of
164the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
165
166IIIb/c. Transmit/Receive Structure
167
168This driver attempts to use a zero-copy receive and transmit scheme.
169
170Alas, all data buffers are required to start on a 32 bit boundary, so
171the driver must often copy transmit packets into bounce buffers.
172
173The driver allocates full frame size skbuffs for the Rx ring buffers at
174open() time and passes the skb->data field to the chip as receive data
175buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
176a fresh skbuff is allocated and the frame is copied to the new skbuff.
177When the incoming frame is larger, the skbuff is passed directly up the
178protocol stack. Buffers consumed this way are replaced by newly allocated
179skbuffs in the last phase of rhine_rx().
180
181The RX_COPYBREAK value is chosen to trade-off the memory wasted by
182using a full-sized skbuff for small frames vs. the copying costs of larger
183frames. New boards are typically used in generously configured machines
184and the underfilled buffers have negligible impact compared to the benefit of
185a single allocation size, so the default value of zero results in never
186copying packets. When copying is done, the cost is usually mitigated by using
187a combined copy/checksum routine. Copying also preloads the cache, which is
188most useful with small frames.
189
190Since the VIA chips are only able to transfer data to buffers on 32 bit
191boundaries, the IP header at offset 14 in an ethernet frame isn't
192longword aligned for further processing. Copying these unaligned buffers
193has the beneficial effect of 16-byte aligning the IP header.
194
195IIId. Synchronization
196
197The driver runs as two independent, single-threaded flows of control. One
198is the send-packet routine, which enforces single-threaded use by the
199dev->priv->lock spinlock. The other thread is the interrupt handler, which
200is single threaded by the hardware and interrupt handling software.
201
202The send packet thread has partial control over the Tx ring. It locks the
203dev->priv->lock whenever it's queuing a Tx packet. If the next slot in the ring
204is not available it stops the transmit queue by calling netif_stop_queue.
205
206The interrupt handler has exclusive control over the Rx ring and records stats
207from the Tx ring. After reaping the stats, it marks the Tx queue entry as
208empty by incrementing the dirty_tx mark. If at least half of the entries in
209the Rx ring are available the transmit queue is woken up if it was stopped.
210
211IV. Notes
212
213IVb. References
214
215Preliminary VT86C100A manual from http://www.via.com.tw/
216http://www.scyld.com/expert/100mbps.html
217http://www.scyld.com/expert/NWay.html
218ftp://ftp.via.com.tw/public/lan/Products/NIC/VT86C100A/Datasheet/VT86C100A03.pdf
219ftp://ftp.via.com.tw/public/lan/Products/NIC/VT6102/Datasheet/VT6102_021.PDF
220
221
222IVc. Errata
223
224The VT86C100A manual is not reliable information.
225The 3043 chip does not handle unaligned transmit or receive buffers, resulting
226in significant performance degradation for bounce buffer copies on transmit
227and unaligned IP headers on receive.
228The chip does not pad to minimum transmit length.
229
230*/
231
232
233/* This table drives the PCI probe routines. It's mostly boilerplate in all
234 of the drivers, and will likely be provided by some future kernel.
235 Note the matching code -- the first table entry matchs all 56** cards but
236 second only the 1234 card.
237*/
238
239enum rhine_revs {
240 VT86C100A = 0x00,
241 VTunknown0 = 0x20,
242 VT6102 = 0x40,
243 VT8231 = 0x50, /* Integrated MAC */
244 VT8233 = 0x60, /* Integrated MAC */
245 VT8235 = 0x74, /* Integrated MAC */
246 VT8237 = 0x78, /* Integrated MAC */
247 VTunknown1 = 0x7C,
248 VT6105 = 0x80,
249 VT6105_B0 = 0x83,
250 VT6105L = 0x8A,
251 VT6107 = 0x8C,
252 VTunknown2 = 0x8E,
253 VT6105M = 0x90, /* Management adapter */
254};
255
256enum rhine_quirks {
257 rqWOL = 0x0001, /* Wake-On-LAN support */
258 rqForceReset = 0x0002,
259 rq6patterns = 0x0040, /* 6 instead of 4 patterns for WOL */
260 rqStatusWBRace = 0x0080, /* Tx Status Writeback Error possible */
261 rqRhineI = 0x0100, /* See comment below */
262};
263/*
264 * rqRhineI: VT86C100A (aka Rhine-I) uses different bits to enable
265 * MMIO as well as for the collision counter and the Tx FIFO underflow
266 * indicator. In addition, Tx and Rx buffers need to 4 byte aligned.
267 */
268
269/* Beware of PCI posted writes */
270#define IOSYNC do { ioread8(ioaddr + StationAddr); } while (0)
271
Jeff Garzik46009c82006-06-27 09:12:38 -0400272static const struct pci_device_id rhine_pci_tbl[] = {
273 { 0x1106, 0x3043, PCI_ANY_ID, PCI_ANY_ID, }, /* VT86C100A */
274 { 0x1106, 0x3065, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6102 */
275 { 0x1106, 0x3106, PCI_ANY_ID, PCI_ANY_ID, }, /* 6105{,L,LOM} */
276 { 0x1106, 0x3053, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6105M */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700277 { } /* terminate list */
278};
279MODULE_DEVICE_TABLE(pci, rhine_pci_tbl);
280
281
282/* Offsets to the device registers. */
283enum register_offsets {
284 StationAddr=0x00, RxConfig=0x06, TxConfig=0x07, ChipCmd=0x08,
285 ChipCmd1=0x09,
286 IntrStatus=0x0C, IntrEnable=0x0E,
287 MulticastFilter0=0x10, MulticastFilter1=0x14,
288 RxRingPtr=0x18, TxRingPtr=0x1C, GFIFOTest=0x54,
289 MIIPhyAddr=0x6C, MIIStatus=0x6D, PCIBusConfig=0x6E,
290 MIICmd=0x70, MIIRegAddr=0x71, MIIData=0x72, MACRegEEcsr=0x74,
291 ConfigA=0x78, ConfigB=0x79, ConfigC=0x7A, ConfigD=0x7B,
292 RxMissed=0x7C, RxCRCErrs=0x7E, MiscCmd=0x81,
293 StickyHW=0x83, IntrStatus2=0x84,
294 WOLcrSet=0xA0, PwcfgSet=0xA1, WOLcgSet=0xA3, WOLcrClr=0xA4,
295 WOLcrClr1=0xA6, WOLcgClr=0xA7,
296 PwrcsrSet=0xA8, PwrcsrSet1=0xA9, PwrcsrClr=0xAC, PwrcsrClr1=0xAD,
297};
298
299/* Bits in ConfigD */
300enum backoff_bits {
301 BackOptional=0x01, BackModify=0x02,
302 BackCaptureEffect=0x04, BackRandom=0x08
303};
304
305#ifdef USE_MMIO
306/* Registers we check that mmio and reg are the same. */
307static const int mmio_verify_registers[] = {
308 RxConfig, TxConfig, IntrEnable, ConfigA, ConfigB, ConfigC, ConfigD,
309 0
310};
311#endif
312
313/* Bits in the interrupt status/mask registers. */
314enum intr_status_bits {
315 IntrRxDone=0x0001, IntrRxErr=0x0004, IntrRxEmpty=0x0020,
316 IntrTxDone=0x0002, IntrTxError=0x0008, IntrTxUnderrun=0x0210,
317 IntrPCIErr=0x0040,
318 IntrStatsMax=0x0080, IntrRxEarly=0x0100,
319 IntrRxOverflow=0x0400, IntrRxDropped=0x0800, IntrRxNoBuf=0x1000,
320 IntrTxAborted=0x2000, IntrLinkChange=0x4000,
321 IntrRxWakeUp=0x8000,
322 IntrNormalSummary=0x0003, IntrAbnormalSummary=0xC260,
323 IntrTxDescRace=0x080000, /* mapped from IntrStatus2 */
324 IntrTxErrSummary=0x082218,
325};
326
327/* Bits in WOLcrSet/WOLcrClr and PwrcsrSet/PwrcsrClr */
328enum wol_bits {
329 WOLucast = 0x10,
330 WOLmagic = 0x20,
331 WOLbmcast = 0x30,
332 WOLlnkon = 0x40,
333 WOLlnkoff = 0x80,
334};
335
336/* The Rx and Tx buffer descriptors. */
337struct rx_desc {
338 s32 rx_status;
339 u32 desc_length; /* Chain flag, Buffer/frame length */
340 u32 addr;
341 u32 next_desc;
342};
343struct tx_desc {
344 s32 tx_status;
345 u32 desc_length; /* Chain flag, Tx Config, Frame length */
346 u32 addr;
347 u32 next_desc;
348};
349
350/* Initial value for tx_desc.desc_length, Buffer size goes to bits 0-10 */
351#define TXDESC 0x00e08000
352
353enum rx_status_bits {
354 RxOK=0x8000, RxWholePkt=0x0300, RxErr=0x008F
355};
356
357/* Bits in *_desc.*_status */
358enum desc_status_bits {
359 DescOwn=0x80000000
360};
361
362/* Bits in ChipCmd. */
363enum chip_cmd_bits {
364 CmdInit=0x01, CmdStart=0x02, CmdStop=0x04, CmdRxOn=0x08,
365 CmdTxOn=0x10, Cmd1TxDemand=0x20, CmdRxDemand=0x40,
366 Cmd1EarlyRx=0x01, Cmd1EarlyTx=0x02, Cmd1FDuplex=0x04,
367 Cmd1NoTxPoll=0x08, Cmd1Reset=0x80,
368};
369
370struct rhine_private {
371 /* Descriptor rings */
372 struct rx_desc *rx_ring;
373 struct tx_desc *tx_ring;
374 dma_addr_t rx_ring_dma;
375 dma_addr_t tx_ring_dma;
376
377 /* The addresses of receive-in-place skbuffs. */
378 struct sk_buff *rx_skbuff[RX_RING_SIZE];
379 dma_addr_t rx_skbuff_dma[RX_RING_SIZE];
380
381 /* The saved address of a sent-in-place packet/buffer, for later free(). */
382 struct sk_buff *tx_skbuff[TX_RING_SIZE];
383 dma_addr_t tx_skbuff_dma[TX_RING_SIZE];
384
Roger Luethi4be5de22006-04-04 20:49:16 +0200385 /* Tx bounce buffers (Rhine-I only) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700386 unsigned char *tx_buf[TX_RING_SIZE];
387 unsigned char *tx_bufs;
388 dma_addr_t tx_bufs_dma;
389
390 struct pci_dev *pdev;
391 long pioaddr;
392 struct net_device_stats stats;
393 spinlock_t lock;
394
395 /* Frequently used values: keep some adjacent for cache effect. */
396 u32 quirks;
397 struct rx_desc *rx_head_desc;
398 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
399 unsigned int cur_tx, dirty_tx;
400 unsigned int rx_buf_sz; /* Based on MTU+slack. */
401 u8 wolopts;
402
403 u8 tx_thresh, rx_thresh;
404
405 struct mii_if_info mii_if;
406 void __iomem *base;
407};
408
409static int mdio_read(struct net_device *dev, int phy_id, int location);
410static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
411static int rhine_open(struct net_device *dev);
412static void rhine_tx_timeout(struct net_device *dev);
413static int rhine_start_tx(struct sk_buff *skb, struct net_device *dev);
David Howells7d12e782006-10-05 14:55:46 +0100414static irqreturn_t rhine_interrupt(int irq, void *dev_instance);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700415static void rhine_tx(struct net_device *dev);
Roger Luethi633949a2006-08-14 23:00:17 -0700416static int rhine_rx(struct net_device *dev, int limit);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700417static void rhine_error(struct net_device *dev, int intr_status);
418static void rhine_set_rx_mode(struct net_device *dev);
419static struct net_device_stats *rhine_get_stats(struct net_device *dev);
420static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
Jeff Garzik7282d492006-09-13 14:30:00 -0400421static const struct ethtool_ops netdev_ethtool_ops;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700422static int rhine_close(struct net_device *dev);
Greg Kroah-Hartmand18c3db2005-06-23 17:35:56 -0700423static void rhine_shutdown (struct pci_dev *pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700424
425#define RHINE_WAIT_FOR(condition) do { \
426 int i=1024; \
427 while (!(condition) && --i) \
428 ; \
429 if (debug > 1 && i < 512) \
430 printk(KERN_INFO "%s: %4d cycles used @ %s:%d\n", \
431 DRV_NAME, 1024-i, __func__, __LINE__); \
432} while(0)
433
434static inline u32 get_intr_status(struct net_device *dev)
435{
436 struct rhine_private *rp = netdev_priv(dev);
437 void __iomem *ioaddr = rp->base;
438 u32 intr_status;
439
440 intr_status = ioread16(ioaddr + IntrStatus);
441 /* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */
442 if (rp->quirks & rqStatusWBRace)
443 intr_status |= ioread8(ioaddr + IntrStatus2) << 16;
444 return intr_status;
445}
446
447/*
448 * Get power related registers into sane state.
449 * Notify user about past WOL event.
450 */
451static void rhine_power_init(struct net_device *dev)
452{
453 struct rhine_private *rp = netdev_priv(dev);
454 void __iomem *ioaddr = rp->base;
455 u16 wolstat;
456
457 if (rp->quirks & rqWOL) {
458 /* Make sure chip is in power state D0 */
459 iowrite8(ioread8(ioaddr + StickyHW) & 0xFC, ioaddr + StickyHW);
460
461 /* Disable "force PME-enable" */
462 iowrite8(0x80, ioaddr + WOLcgClr);
463
464 /* Clear power-event config bits (WOL) */
465 iowrite8(0xFF, ioaddr + WOLcrClr);
466 /* More recent cards can manage two additional patterns */
467 if (rp->quirks & rq6patterns)
468 iowrite8(0x03, ioaddr + WOLcrClr1);
469
470 /* Save power-event status bits */
471 wolstat = ioread8(ioaddr + PwrcsrSet);
472 if (rp->quirks & rq6patterns)
473 wolstat |= (ioread8(ioaddr + PwrcsrSet1) & 0x03) << 8;
474
475 /* Clear power-event status bits */
476 iowrite8(0xFF, ioaddr + PwrcsrClr);
477 if (rp->quirks & rq6patterns)
478 iowrite8(0x03, ioaddr + PwrcsrClr1);
479
480 if (wolstat) {
481 char *reason;
482 switch (wolstat) {
483 case WOLmagic:
484 reason = "Magic packet";
485 break;
486 case WOLlnkon:
487 reason = "Link went up";
488 break;
489 case WOLlnkoff:
490 reason = "Link went down";
491 break;
492 case WOLucast:
493 reason = "Unicast packet";
494 break;
495 case WOLbmcast:
496 reason = "Multicast/broadcast packet";
497 break;
498 default:
499 reason = "Unknown";
500 }
501 printk(KERN_INFO "%s: Woke system up. Reason: %s.\n",
502 DRV_NAME, reason);
503 }
504 }
505}
506
507static void rhine_chip_reset(struct net_device *dev)
508{
509 struct rhine_private *rp = netdev_priv(dev);
510 void __iomem *ioaddr = rp->base;
511
512 iowrite8(Cmd1Reset, ioaddr + ChipCmd1);
513 IOSYNC;
514
515 if (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) {
516 printk(KERN_INFO "%s: Reset not complete yet. "
517 "Trying harder.\n", DRV_NAME);
518
519 /* Force reset */
520 if (rp->quirks & rqForceReset)
521 iowrite8(0x40, ioaddr + MiscCmd);
522
523 /* Reset can take somewhat longer (rare) */
524 RHINE_WAIT_FOR(!(ioread8(ioaddr + ChipCmd1) & Cmd1Reset));
525 }
526
527 if (debug > 1)
528 printk(KERN_INFO "%s: Reset %s.\n", dev->name,
529 (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) ?
530 "failed" : "succeeded");
531}
532
533#ifdef USE_MMIO
534static void enable_mmio(long pioaddr, u32 quirks)
535{
536 int n;
537 if (quirks & rqRhineI) {
538 /* More recent docs say that this bit is reserved ... */
539 n = inb(pioaddr + ConfigA) | 0x20;
540 outb(n, pioaddr + ConfigA);
541 } else {
542 n = inb(pioaddr + ConfigD) | 0x80;
543 outb(n, pioaddr + ConfigD);
544 }
545}
546#endif
547
548/*
549 * Loads bytes 0x00-0x05, 0x6E-0x6F, 0x78-0x7B from EEPROM
550 * (plus 0x6C for Rhine-I/II)
551 */
552static void __devinit rhine_reload_eeprom(long pioaddr, struct net_device *dev)
553{
554 struct rhine_private *rp = netdev_priv(dev);
555 void __iomem *ioaddr = rp->base;
556
557 outb(0x20, pioaddr + MACRegEEcsr);
558 RHINE_WAIT_FOR(!(inb(pioaddr + MACRegEEcsr) & 0x20));
559
560#ifdef USE_MMIO
561 /*
562 * Reloading from EEPROM overwrites ConfigA-D, so we must re-enable
563 * MMIO. If reloading EEPROM was done first this could be avoided, but
564 * it is not known if that still works with the "win98-reboot" problem.
565 */
566 enable_mmio(pioaddr, rp->quirks);
567#endif
568
569 /* Turn off EEPROM-controlled wake-up (magic packet) */
570 if (rp->quirks & rqWOL)
571 iowrite8(ioread8(ioaddr + ConfigA) & 0xFC, ioaddr + ConfigA);
572
573}
574
575#ifdef CONFIG_NET_POLL_CONTROLLER
576static void rhine_poll(struct net_device *dev)
577{
578 disable_irq(dev->irq);
David Howells7d12e782006-10-05 14:55:46 +0100579 rhine_interrupt(dev->irq, (void *)dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700580 enable_irq(dev->irq);
581}
582#endif
583
Roger Luethi633949a2006-08-14 23:00:17 -0700584#ifdef CONFIG_VIA_RHINE_NAPI
585static int rhine_napipoll(struct net_device *dev, int *budget)
586{
587 struct rhine_private *rp = netdev_priv(dev);
588 void __iomem *ioaddr = rp->base;
589 int done, limit = min(dev->quota, *budget);
590
591 done = rhine_rx(dev, limit);
592 *budget -= done;
593 dev->quota -= done;
594
595 if (done < limit) {
596 netif_rx_complete(dev);
597
598 iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow |
599 IntrRxDropped | IntrRxNoBuf | IntrTxAborted |
600 IntrTxDone | IntrTxError | IntrTxUnderrun |
601 IntrPCIErr | IntrStatsMax | IntrLinkChange,
602 ioaddr + IntrEnable);
603 return 0;
604 }
605 else
606 return 1;
607}
608#endif
609
Linus Torvalds1da177e2005-04-16 15:20:36 -0700610static void rhine_hw_init(struct net_device *dev, long pioaddr)
611{
612 struct rhine_private *rp = netdev_priv(dev);
613
614 /* Reset the chip to erase previous misconfiguration. */
615 rhine_chip_reset(dev);
616
617 /* Rhine-I needs extra time to recuperate before EEPROM reload */
618 if (rp->quirks & rqRhineI)
619 msleep(5);
620
621 /* Reload EEPROM controlled bytes cleared by soft reset */
622 rhine_reload_eeprom(pioaddr, dev);
623}
624
625static int __devinit rhine_init_one(struct pci_dev *pdev,
626 const struct pci_device_id *ent)
627{
628 struct net_device *dev;
629 struct rhine_private *rp;
630 int i, rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700631 u32 quirks;
632 long pioaddr;
633 long memaddr;
634 void __iomem *ioaddr;
635 int io_size, phy_id;
636 const char *name;
637#ifdef USE_MMIO
638 int bar = 1;
639#else
640 int bar = 0;
641#endif
642
643/* when built into the kernel, we only print version if device is found */
644#ifndef MODULE
645 static int printed_version;
646 if (!printed_version++)
647 printk(version);
648#endif
649
Linus Torvalds1da177e2005-04-16 15:20:36 -0700650 io_size = 256;
651 phy_id = 0;
652 quirks = 0;
653 name = "Rhine";
Auke Kok44c10132007-06-08 15:46:36 -0700654 if (pdev->revision < VTunknown0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700655 quirks = rqRhineI;
656 io_size = 128;
657 }
Auke Kok44c10132007-06-08 15:46:36 -0700658 else if (pdev->revision >= VT6102) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700659 quirks = rqWOL | rqForceReset;
Auke Kok44c10132007-06-08 15:46:36 -0700660 if (pdev->revision < VT6105) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700661 name = "Rhine II";
662 quirks |= rqStatusWBRace; /* Rhine-II exclusive */
663 }
664 else {
665 phy_id = 1; /* Integrated PHY, phy_id fixed to 1 */
Auke Kok44c10132007-06-08 15:46:36 -0700666 if (pdev->revision >= VT6105_B0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700667 quirks |= rq6patterns;
Auke Kok44c10132007-06-08 15:46:36 -0700668 if (pdev->revision < VT6105M)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700669 name = "Rhine III";
670 else
671 name = "Rhine III (Management Adapter)";
672 }
673 }
674
675 rc = pci_enable_device(pdev);
676 if (rc)
677 goto err_out;
678
679 /* this should always be supported */
Domen Puncer1e7f0bd2005-06-26 18:22:14 -0400680 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700681 if (rc) {
682 printk(KERN_ERR "32-bit PCI DMA addresses not supported by "
683 "the card!?\n");
684 goto err_out;
685 }
686
687 /* sanity check */
688 if ((pci_resource_len(pdev, 0) < io_size) ||
689 (pci_resource_len(pdev, 1) < io_size)) {
690 rc = -EIO;
691 printk(KERN_ERR "Insufficient PCI resources, aborting\n");
692 goto err_out;
693 }
694
695 pioaddr = pci_resource_start(pdev, 0);
696 memaddr = pci_resource_start(pdev, 1);
697
698 pci_set_master(pdev);
699
700 dev = alloc_etherdev(sizeof(struct rhine_private));
701 if (!dev) {
702 rc = -ENOMEM;
703 printk(KERN_ERR "alloc_etherdev failed\n");
704 goto err_out;
705 }
706 SET_MODULE_OWNER(dev);
707 SET_NETDEV_DEV(dev, &pdev->dev);
708
709 rp = netdev_priv(dev);
710 rp->quirks = quirks;
711 rp->pioaddr = pioaddr;
712 rp->pdev = pdev;
713
714 rc = pci_request_regions(pdev, DRV_NAME);
715 if (rc)
716 goto err_out_free_netdev;
717
718 ioaddr = pci_iomap(pdev, bar, io_size);
719 if (!ioaddr) {
720 rc = -EIO;
721 printk(KERN_ERR "ioremap failed for device %s, region 0x%X "
722 "@ 0x%lX\n", pci_name(pdev), io_size, memaddr);
723 goto err_out_free_res;
724 }
725
726#ifdef USE_MMIO
727 enable_mmio(pioaddr, quirks);
728
729 /* Check that selected MMIO registers match the PIO ones */
730 i = 0;
731 while (mmio_verify_registers[i]) {
732 int reg = mmio_verify_registers[i++];
733 unsigned char a = inb(pioaddr+reg);
734 unsigned char b = readb(ioaddr+reg);
735 if (a != b) {
736 rc = -EIO;
737 printk(KERN_ERR "MMIO do not match PIO [%02x] "
738 "(%02x != %02x)\n", reg, a, b);
739 goto err_out_unmap;
740 }
741 }
742#endif /* USE_MMIO */
743
744 dev->base_addr = (unsigned long)ioaddr;
745 rp->base = ioaddr;
746
747 /* Get chip registers into a sane state */
748 rhine_power_init(dev);
749 rhine_hw_init(dev, pioaddr);
750
751 for (i = 0; i < 6; i++)
752 dev->dev_addr[i] = ioread8(ioaddr + StationAddr + i);
John W. Linvilleb81e8e12005-09-12 10:48:58 -0400753 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700754
John W. Linvilleb81e8e12005-09-12 10:48:58 -0400755 if (!is_valid_ether_addr(dev->perm_addr)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700756 rc = -EIO;
757 printk(KERN_ERR "Invalid MAC address\n");
758 goto err_out_unmap;
759 }
760
761 /* For Rhine-I/II, phy_id is loaded from EEPROM */
762 if (!phy_id)
763 phy_id = ioread8(ioaddr + 0x6C);
764
765 dev->irq = pdev->irq;
766
767 spin_lock_init(&rp->lock);
768 rp->mii_if.dev = dev;
769 rp->mii_if.mdio_read = mdio_read;
770 rp->mii_if.mdio_write = mdio_write;
771 rp->mii_if.phy_id_mask = 0x1f;
772 rp->mii_if.reg_num_mask = 0x1f;
773
774 /* The chip-specific entries in the device structure. */
775 dev->open = rhine_open;
776 dev->hard_start_xmit = rhine_start_tx;
777 dev->stop = rhine_close;
778 dev->get_stats = rhine_get_stats;
779 dev->set_multicast_list = rhine_set_rx_mode;
780 dev->do_ioctl = netdev_ioctl;
781 dev->ethtool_ops = &netdev_ethtool_ops;
782 dev->tx_timeout = rhine_tx_timeout;
783 dev->watchdog_timeo = TX_TIMEOUT;
784#ifdef CONFIG_NET_POLL_CONTROLLER
785 dev->poll_controller = rhine_poll;
786#endif
Roger Luethi633949a2006-08-14 23:00:17 -0700787#ifdef CONFIG_VIA_RHINE_NAPI
788 dev->poll = rhine_napipoll;
789 dev->weight = 64;
790#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700791 if (rp->quirks & rqRhineI)
792 dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM;
793
794 /* dev->name not defined before register_netdev()! */
795 rc = register_netdev(dev);
796 if (rc)
797 goto err_out_unmap;
798
799 printk(KERN_INFO "%s: VIA %s at 0x%lx, ",
800 dev->name, name,
801#ifdef USE_MMIO
802 memaddr
803#else
804 (long)ioaddr
805#endif
806 );
807
808 for (i = 0; i < 5; i++)
809 printk("%2.2x:", dev->dev_addr[i]);
810 printk("%2.2x, IRQ %d.\n", dev->dev_addr[i], pdev->irq);
811
812 pci_set_drvdata(pdev, dev);
813
814 {
815 u16 mii_cmd;
816 int mii_status = mdio_read(dev, phy_id, 1);
817 mii_cmd = mdio_read(dev, phy_id, MII_BMCR) & ~BMCR_ISOLATE;
818 mdio_write(dev, phy_id, MII_BMCR, mii_cmd);
819 if (mii_status != 0xffff && mii_status != 0x0000) {
820 rp->mii_if.advertising = mdio_read(dev, phy_id, 4);
821 printk(KERN_INFO "%s: MII PHY found at address "
822 "%d, status 0x%4.4x advertising %4.4x "
823 "Link %4.4x.\n", dev->name, phy_id,
824 mii_status, rp->mii_if.advertising,
825 mdio_read(dev, phy_id, 5));
826
827 /* set IFF_RUNNING */
828 if (mii_status & BMSR_LSTATUS)
829 netif_carrier_on(dev);
830 else
831 netif_carrier_off(dev);
832
833 }
834 }
835 rp->mii_if.phy_id = phy_id;
Roger Luethib933b4d2006-08-14 23:00:21 -0700836 if (debug > 1 && avoid_D3)
837 printk(KERN_INFO "%s: No D3 power state at shutdown.\n",
838 dev->name);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700839
840 return 0;
841
842err_out_unmap:
843 pci_iounmap(pdev, ioaddr);
844err_out_free_res:
845 pci_release_regions(pdev);
846err_out_free_netdev:
847 free_netdev(dev);
848err_out:
849 return rc;
850}
851
852static int alloc_ring(struct net_device* dev)
853{
854 struct rhine_private *rp = netdev_priv(dev);
855 void *ring;
856 dma_addr_t ring_dma;
857
858 ring = pci_alloc_consistent(rp->pdev,
859 RX_RING_SIZE * sizeof(struct rx_desc) +
860 TX_RING_SIZE * sizeof(struct tx_desc),
861 &ring_dma);
862 if (!ring) {
863 printk(KERN_ERR "Could not allocate DMA memory.\n");
864 return -ENOMEM;
865 }
866 if (rp->quirks & rqRhineI) {
867 rp->tx_bufs = pci_alloc_consistent(rp->pdev,
868 PKT_BUF_SZ * TX_RING_SIZE,
869 &rp->tx_bufs_dma);
870 if (rp->tx_bufs == NULL) {
871 pci_free_consistent(rp->pdev,
872 RX_RING_SIZE * sizeof(struct rx_desc) +
873 TX_RING_SIZE * sizeof(struct tx_desc),
874 ring, ring_dma);
875 return -ENOMEM;
876 }
877 }
878
879 rp->rx_ring = ring;
880 rp->tx_ring = ring + RX_RING_SIZE * sizeof(struct rx_desc);
881 rp->rx_ring_dma = ring_dma;
882 rp->tx_ring_dma = ring_dma + RX_RING_SIZE * sizeof(struct rx_desc);
883
884 return 0;
885}
886
887static void free_ring(struct net_device* dev)
888{
889 struct rhine_private *rp = netdev_priv(dev);
890
891 pci_free_consistent(rp->pdev,
892 RX_RING_SIZE * sizeof(struct rx_desc) +
893 TX_RING_SIZE * sizeof(struct tx_desc),
894 rp->rx_ring, rp->rx_ring_dma);
895 rp->tx_ring = NULL;
896
897 if (rp->tx_bufs)
898 pci_free_consistent(rp->pdev, PKT_BUF_SZ * TX_RING_SIZE,
899 rp->tx_bufs, rp->tx_bufs_dma);
900
901 rp->tx_bufs = NULL;
902
903}
904
905static void alloc_rbufs(struct net_device *dev)
906{
907 struct rhine_private *rp = netdev_priv(dev);
908 dma_addr_t next;
909 int i;
910
911 rp->dirty_rx = rp->cur_rx = 0;
912
913 rp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
914 rp->rx_head_desc = &rp->rx_ring[0];
915 next = rp->rx_ring_dma;
916
917 /* Init the ring entries */
918 for (i = 0; i < RX_RING_SIZE; i++) {
919 rp->rx_ring[i].rx_status = 0;
920 rp->rx_ring[i].desc_length = cpu_to_le32(rp->rx_buf_sz);
921 next += sizeof(struct rx_desc);
922 rp->rx_ring[i].next_desc = cpu_to_le32(next);
923 rp->rx_skbuff[i] = NULL;
924 }
925 /* Mark the last entry as wrapping the ring. */
926 rp->rx_ring[i-1].next_desc = cpu_to_le32(rp->rx_ring_dma);
927
928 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
929 for (i = 0; i < RX_RING_SIZE; i++) {
930 struct sk_buff *skb = dev_alloc_skb(rp->rx_buf_sz);
931 rp->rx_skbuff[i] = skb;
932 if (skb == NULL)
933 break;
934 skb->dev = dev; /* Mark as being used by this device. */
935
936 rp->rx_skbuff_dma[i] =
David S. Miller689be432005-06-28 15:25:31 -0700937 pci_map_single(rp->pdev, skb->data, rp->rx_buf_sz,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700938 PCI_DMA_FROMDEVICE);
939
940 rp->rx_ring[i].addr = cpu_to_le32(rp->rx_skbuff_dma[i]);
941 rp->rx_ring[i].rx_status = cpu_to_le32(DescOwn);
942 }
943 rp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
944}
945
946static void free_rbufs(struct net_device* dev)
947{
948 struct rhine_private *rp = netdev_priv(dev);
949 int i;
950
951 /* Free all the skbuffs in the Rx queue. */
952 for (i = 0; i < RX_RING_SIZE; i++) {
953 rp->rx_ring[i].rx_status = 0;
954 rp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
955 if (rp->rx_skbuff[i]) {
956 pci_unmap_single(rp->pdev,
957 rp->rx_skbuff_dma[i],
958 rp->rx_buf_sz, PCI_DMA_FROMDEVICE);
959 dev_kfree_skb(rp->rx_skbuff[i]);
960 }
961 rp->rx_skbuff[i] = NULL;
962 }
963}
964
965static void alloc_tbufs(struct net_device* dev)
966{
967 struct rhine_private *rp = netdev_priv(dev);
968 dma_addr_t next;
969 int i;
970
971 rp->dirty_tx = rp->cur_tx = 0;
972 next = rp->tx_ring_dma;
973 for (i = 0; i < TX_RING_SIZE; i++) {
974 rp->tx_skbuff[i] = NULL;
975 rp->tx_ring[i].tx_status = 0;
976 rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
977 next += sizeof(struct tx_desc);
978 rp->tx_ring[i].next_desc = cpu_to_le32(next);
Roger Luethi4be5de22006-04-04 20:49:16 +0200979 if (rp->quirks & rqRhineI)
980 rp->tx_buf[i] = &rp->tx_bufs[i * PKT_BUF_SZ];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700981 }
982 rp->tx_ring[i-1].next_desc = cpu_to_le32(rp->tx_ring_dma);
983
984}
985
986static void free_tbufs(struct net_device* dev)
987{
988 struct rhine_private *rp = netdev_priv(dev);
989 int i;
990
991 for (i = 0; i < TX_RING_SIZE; i++) {
992 rp->tx_ring[i].tx_status = 0;
993 rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
994 rp->tx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
995 if (rp->tx_skbuff[i]) {
996 if (rp->tx_skbuff_dma[i]) {
997 pci_unmap_single(rp->pdev,
998 rp->tx_skbuff_dma[i],
999 rp->tx_skbuff[i]->len,
1000 PCI_DMA_TODEVICE);
1001 }
1002 dev_kfree_skb(rp->tx_skbuff[i]);
1003 }
1004 rp->tx_skbuff[i] = NULL;
1005 rp->tx_buf[i] = NULL;
1006 }
1007}
1008
1009static void rhine_check_media(struct net_device *dev, unsigned int init_media)
1010{
1011 struct rhine_private *rp = netdev_priv(dev);
1012 void __iomem *ioaddr = rp->base;
1013
1014 mii_check_media(&rp->mii_if, debug, init_media);
1015
1016 if (rp->mii_if.full_duplex)
1017 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1FDuplex,
1018 ioaddr + ChipCmd1);
1019 else
1020 iowrite8(ioread8(ioaddr + ChipCmd1) & ~Cmd1FDuplex,
1021 ioaddr + ChipCmd1);
Roger Luethi00b428c2006-03-28 20:53:56 +02001022 if (debug > 1)
1023 printk(KERN_INFO "%s: force_media %d, carrier %d\n", dev->name,
1024 rp->mii_if.force_media, netif_carrier_ok(dev));
1025}
1026
1027/* Called after status of force_media possibly changed */
Adrian Bunk0761be42006-04-10 23:22:21 -07001028static void rhine_set_carrier(struct mii_if_info *mii)
Roger Luethi00b428c2006-03-28 20:53:56 +02001029{
1030 if (mii->force_media) {
1031 /* autoneg is off: Link is always assumed to be up */
1032 if (!netif_carrier_ok(mii->dev))
1033 netif_carrier_on(mii->dev);
1034 }
1035 else /* Let MMI library update carrier status */
1036 rhine_check_media(mii->dev, 0);
1037 if (debug > 1)
1038 printk(KERN_INFO "%s: force_media %d, carrier %d\n",
1039 mii->dev->name, mii->force_media,
1040 netif_carrier_ok(mii->dev));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001041}
1042
1043static void init_registers(struct net_device *dev)
1044{
1045 struct rhine_private *rp = netdev_priv(dev);
1046 void __iomem *ioaddr = rp->base;
1047 int i;
1048
1049 for (i = 0; i < 6; i++)
1050 iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i);
1051
1052 /* Initialize other registers. */
1053 iowrite16(0x0006, ioaddr + PCIBusConfig); /* Tune configuration??? */
1054 /* Configure initial FIFO thresholds. */
1055 iowrite8(0x20, ioaddr + TxConfig);
1056 rp->tx_thresh = 0x20;
1057 rp->rx_thresh = 0x60; /* Written in rhine_set_rx_mode(). */
1058
1059 iowrite32(rp->rx_ring_dma, ioaddr + RxRingPtr);
1060 iowrite32(rp->tx_ring_dma, ioaddr + TxRingPtr);
1061
1062 rhine_set_rx_mode(dev);
1063
Stephen Hemmingerab197662006-08-14 23:00:18 -07001064 netif_poll_enable(dev);
1065
Linus Torvalds1da177e2005-04-16 15:20:36 -07001066 /* Enable interrupts by setting the interrupt mask. */
1067 iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow |
1068 IntrRxDropped | IntrRxNoBuf | IntrTxAborted |
1069 IntrTxDone | IntrTxError | IntrTxUnderrun |
1070 IntrPCIErr | IntrStatsMax | IntrLinkChange,
1071 ioaddr + IntrEnable);
1072
1073 iowrite16(CmdStart | CmdTxOn | CmdRxOn | (Cmd1NoTxPoll << 8),
1074 ioaddr + ChipCmd);
1075 rhine_check_media(dev, 1);
1076}
1077
1078/* Enable MII link status auto-polling (required for IntrLinkChange) */
1079static void rhine_enable_linkmon(void __iomem *ioaddr)
1080{
1081 iowrite8(0, ioaddr + MIICmd);
1082 iowrite8(MII_BMSR, ioaddr + MIIRegAddr);
1083 iowrite8(0x80, ioaddr + MIICmd);
1084
1085 RHINE_WAIT_FOR((ioread8(ioaddr + MIIRegAddr) & 0x20));
1086
1087 iowrite8(MII_BMSR | 0x40, ioaddr + MIIRegAddr);
1088}
1089
1090/* Disable MII link status auto-polling (required for MDIO access) */
1091static void rhine_disable_linkmon(void __iomem *ioaddr, u32 quirks)
1092{
1093 iowrite8(0, ioaddr + MIICmd);
1094
1095 if (quirks & rqRhineI) {
1096 iowrite8(0x01, ioaddr + MIIRegAddr); // MII_BMSR
1097
John W. Linville38bb6b22006-05-19 10:51:21 -04001098 /* Can be called from ISR. Evil. */
1099 mdelay(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001100
1101 /* 0x80 must be set immediately before turning it off */
1102 iowrite8(0x80, ioaddr + MIICmd);
1103
1104 RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x20);
1105
1106 /* Heh. Now clear 0x80 again. */
1107 iowrite8(0, ioaddr + MIICmd);
1108 }
1109 else
1110 RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x80);
1111}
1112
1113/* Read and write over the MII Management Data I/O (MDIO) interface. */
1114
1115static int mdio_read(struct net_device *dev, int phy_id, int regnum)
1116{
1117 struct rhine_private *rp = netdev_priv(dev);
1118 void __iomem *ioaddr = rp->base;
1119 int result;
1120
1121 rhine_disable_linkmon(ioaddr, rp->quirks);
1122
1123 /* rhine_disable_linkmon already cleared MIICmd */
1124 iowrite8(phy_id, ioaddr + MIIPhyAddr);
1125 iowrite8(regnum, ioaddr + MIIRegAddr);
1126 iowrite8(0x40, ioaddr + MIICmd); /* Trigger read */
1127 RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x40));
1128 result = ioread16(ioaddr + MIIData);
1129
1130 rhine_enable_linkmon(ioaddr);
1131 return result;
1132}
1133
1134static void mdio_write(struct net_device *dev, int phy_id, int regnum, int value)
1135{
1136 struct rhine_private *rp = netdev_priv(dev);
1137 void __iomem *ioaddr = rp->base;
1138
1139 rhine_disable_linkmon(ioaddr, rp->quirks);
1140
1141 /* rhine_disable_linkmon already cleared MIICmd */
1142 iowrite8(phy_id, ioaddr + MIIPhyAddr);
1143 iowrite8(regnum, ioaddr + MIIRegAddr);
1144 iowrite16(value, ioaddr + MIIData);
1145 iowrite8(0x20, ioaddr + MIICmd); /* Trigger write */
1146 RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x20));
1147
1148 rhine_enable_linkmon(ioaddr);
1149}
1150
1151static int rhine_open(struct net_device *dev)
1152{
1153 struct rhine_private *rp = netdev_priv(dev);
1154 void __iomem *ioaddr = rp->base;
1155 int rc;
1156
Thomas Gleixner1fb9df52006-07-01 19:29:39 -07001157 rc = request_irq(rp->pdev->irq, &rhine_interrupt, IRQF_SHARED, dev->name,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001158 dev);
1159 if (rc)
1160 return rc;
1161
1162 if (debug > 1)
1163 printk(KERN_DEBUG "%s: rhine_open() irq %d.\n",
1164 dev->name, rp->pdev->irq);
1165
1166 rc = alloc_ring(dev);
1167 if (rc) {
1168 free_irq(rp->pdev->irq, dev);
1169 return rc;
1170 }
1171 alloc_rbufs(dev);
1172 alloc_tbufs(dev);
1173 rhine_chip_reset(dev);
1174 init_registers(dev);
1175 if (debug > 2)
1176 printk(KERN_DEBUG "%s: Done rhine_open(), status %4.4x "
1177 "MII status: %4.4x.\n",
1178 dev->name, ioread16(ioaddr + ChipCmd),
1179 mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
1180
1181 netif_start_queue(dev);
1182
1183 return 0;
1184}
1185
1186static void rhine_tx_timeout(struct net_device *dev)
1187{
1188 struct rhine_private *rp = netdev_priv(dev);
1189 void __iomem *ioaddr = rp->base;
1190
1191 printk(KERN_WARNING "%s: Transmit timed out, status %4.4x, PHY status "
1192 "%4.4x, resetting...\n",
1193 dev->name, ioread16(ioaddr + IntrStatus),
1194 mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
1195
1196 /* protect against concurrent rx interrupts */
1197 disable_irq(rp->pdev->irq);
1198
1199 spin_lock(&rp->lock);
1200
1201 /* clear all descriptors */
1202 free_tbufs(dev);
1203 free_rbufs(dev);
1204 alloc_tbufs(dev);
1205 alloc_rbufs(dev);
1206
1207 /* Reinitialize the hardware. */
1208 rhine_chip_reset(dev);
1209 init_registers(dev);
1210
1211 spin_unlock(&rp->lock);
1212 enable_irq(rp->pdev->irq);
1213
1214 dev->trans_start = jiffies;
1215 rp->stats.tx_errors++;
1216 netif_wake_queue(dev);
1217}
1218
1219static int rhine_start_tx(struct sk_buff *skb, struct net_device *dev)
1220{
1221 struct rhine_private *rp = netdev_priv(dev);
1222 void __iomem *ioaddr = rp->base;
1223 unsigned entry;
1224
1225 /* Caution: the write order is important here, set the field
1226 with the "ownership" bits last. */
1227
1228 /* Calculate the next Tx descriptor entry. */
1229 entry = rp->cur_tx % TX_RING_SIZE;
1230
Herbert Xu5b057c62006-06-23 02:06:41 -07001231 if (skb_padto(skb, ETH_ZLEN))
1232 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001233
1234 rp->tx_skbuff[entry] = skb;
1235
1236 if ((rp->quirks & rqRhineI) &&
Patrick McHardy84fa7932006-08-29 16:44:56 -07001237 (((unsigned long)skb->data & 3) || skb_shinfo(skb)->nr_frags != 0 || skb->ip_summed == CHECKSUM_PARTIAL)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001238 /* Must use alignment buffer. */
1239 if (skb->len > PKT_BUF_SZ) {
1240 /* packet too long, drop it */
1241 dev_kfree_skb(skb);
1242 rp->tx_skbuff[entry] = NULL;
1243 rp->stats.tx_dropped++;
1244 return 0;
1245 }
Craig Brind3e0d1672006-04-27 02:30:46 -07001246
1247 /* Padding is not copied and so must be redone. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001248 skb_copy_and_csum_dev(skb, rp->tx_buf[entry]);
Craig Brind3e0d1672006-04-27 02:30:46 -07001249 if (skb->len < ETH_ZLEN)
1250 memset(rp->tx_buf[entry] + skb->len, 0,
1251 ETH_ZLEN - skb->len);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001252 rp->tx_skbuff_dma[entry] = 0;
1253 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_bufs_dma +
1254 (rp->tx_buf[entry] -
1255 rp->tx_bufs));
1256 } else {
1257 rp->tx_skbuff_dma[entry] =
1258 pci_map_single(rp->pdev, skb->data, skb->len,
1259 PCI_DMA_TODEVICE);
1260 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_skbuff_dma[entry]);
1261 }
1262
1263 rp->tx_ring[entry].desc_length =
1264 cpu_to_le32(TXDESC | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
1265
1266 /* lock eth irq */
1267 spin_lock_irq(&rp->lock);
1268 wmb();
1269 rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);
1270 wmb();
1271
1272 rp->cur_tx++;
1273
1274 /* Non-x86 Todo: explicitly flush cache lines here. */
1275
1276 /* Wake the potentially-idle transmit channel */
1277 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
1278 ioaddr + ChipCmd1);
1279 IOSYNC;
1280
1281 if (rp->cur_tx == rp->dirty_tx + TX_QUEUE_LEN)
1282 netif_stop_queue(dev);
1283
1284 dev->trans_start = jiffies;
1285
1286 spin_unlock_irq(&rp->lock);
1287
1288 if (debug > 4) {
1289 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
1290 dev->name, rp->cur_tx-1, entry);
1291 }
1292 return 0;
1293}
1294
1295/* The interrupt handler does all of the Rx thread work and cleans up
1296 after the Tx thread. */
David Howells7d12e782006-10-05 14:55:46 +01001297static irqreturn_t rhine_interrupt(int irq, void *dev_instance)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001298{
1299 struct net_device *dev = dev_instance;
1300 struct rhine_private *rp = netdev_priv(dev);
1301 void __iomem *ioaddr = rp->base;
1302 u32 intr_status;
1303 int boguscnt = max_interrupt_work;
1304 int handled = 0;
1305
1306 while ((intr_status = get_intr_status(dev))) {
1307 handled = 1;
1308
1309 /* Acknowledge all of the current interrupt sources ASAP. */
1310 if (intr_status & IntrTxDescRace)
1311 iowrite8(0x08, ioaddr + IntrStatus2);
1312 iowrite16(intr_status & 0xffff, ioaddr + IntrStatus);
1313 IOSYNC;
1314
1315 if (debug > 4)
1316 printk(KERN_DEBUG "%s: Interrupt, status %8.8x.\n",
1317 dev->name, intr_status);
1318
1319 if (intr_status & (IntrRxDone | IntrRxErr | IntrRxDropped |
Roger Luethi633949a2006-08-14 23:00:17 -07001320 IntrRxWakeUp | IntrRxEmpty | IntrRxNoBuf)) {
1321#ifdef CONFIG_VIA_RHINE_NAPI
1322 iowrite16(IntrTxAborted |
1323 IntrTxDone | IntrTxError | IntrTxUnderrun |
1324 IntrPCIErr | IntrStatsMax | IntrLinkChange,
1325 ioaddr + IntrEnable);
1326
1327 netif_rx_schedule(dev);
1328#else
1329 rhine_rx(dev, RX_RING_SIZE);
1330#endif
1331 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001332
1333 if (intr_status & (IntrTxErrSummary | IntrTxDone)) {
1334 if (intr_status & IntrTxErrSummary) {
1335 /* Avoid scavenging before Tx engine turned off */
1336 RHINE_WAIT_FOR(!(ioread8(ioaddr+ChipCmd) & CmdTxOn));
1337 if (debug > 2 &&
1338 ioread8(ioaddr+ChipCmd) & CmdTxOn)
1339 printk(KERN_WARNING "%s: "
1340 "rhine_interrupt() Tx engine"
1341 "still on.\n", dev->name);
1342 }
1343 rhine_tx(dev);
1344 }
1345
1346 /* Abnormal error summary/uncommon events handlers. */
1347 if (intr_status & (IntrPCIErr | IntrLinkChange |
1348 IntrStatsMax | IntrTxError | IntrTxAborted |
1349 IntrTxUnderrun | IntrTxDescRace))
1350 rhine_error(dev, intr_status);
1351
1352 if (--boguscnt < 0) {
1353 printk(KERN_WARNING "%s: Too much work at interrupt, "
1354 "status=%#8.8x.\n",
1355 dev->name, intr_status);
1356 break;
1357 }
1358 }
1359
1360 if (debug > 3)
1361 printk(KERN_DEBUG "%s: exiting interrupt, status=%8.8x.\n",
1362 dev->name, ioread16(ioaddr + IntrStatus));
1363 return IRQ_RETVAL(handled);
1364}
1365
1366/* This routine is logically part of the interrupt handler, but isolated
1367 for clarity. */
1368static void rhine_tx(struct net_device *dev)
1369{
1370 struct rhine_private *rp = netdev_priv(dev);
1371 int txstatus = 0, entry = rp->dirty_tx % TX_RING_SIZE;
1372
1373 spin_lock(&rp->lock);
1374
1375 /* find and cleanup dirty tx descriptors */
1376 while (rp->dirty_tx != rp->cur_tx) {
1377 txstatus = le32_to_cpu(rp->tx_ring[entry].tx_status);
1378 if (debug > 6)
Denis Vlasenkoed4030d2005-06-17 08:23:17 +03001379 printk(KERN_DEBUG "Tx scavenge %d status %8.8x.\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001380 entry, txstatus);
1381 if (txstatus & DescOwn)
1382 break;
1383 if (txstatus & 0x8000) {
1384 if (debug > 1)
1385 printk(KERN_DEBUG "%s: Transmit error, "
1386 "Tx status %8.8x.\n",
1387 dev->name, txstatus);
1388 rp->stats.tx_errors++;
1389 if (txstatus & 0x0400) rp->stats.tx_carrier_errors++;
1390 if (txstatus & 0x0200) rp->stats.tx_window_errors++;
1391 if (txstatus & 0x0100) rp->stats.tx_aborted_errors++;
1392 if (txstatus & 0x0080) rp->stats.tx_heartbeat_errors++;
1393 if (((rp->quirks & rqRhineI) && txstatus & 0x0002) ||
1394 (txstatus & 0x0800) || (txstatus & 0x1000)) {
1395 rp->stats.tx_fifo_errors++;
1396 rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);
1397 break; /* Keep the skb - we try again */
1398 }
1399 /* Transmitter restarted in 'abnormal' handler. */
1400 } else {
1401 if (rp->quirks & rqRhineI)
1402 rp->stats.collisions += (txstatus >> 3) & 0x0F;
1403 else
1404 rp->stats.collisions += txstatus & 0x0F;
1405 if (debug > 6)
1406 printk(KERN_DEBUG "collisions: %1.1x:%1.1x\n",
1407 (txstatus >> 3) & 0xF,
1408 txstatus & 0xF);
1409 rp->stats.tx_bytes += rp->tx_skbuff[entry]->len;
1410 rp->stats.tx_packets++;
1411 }
1412 /* Free the original skb. */
1413 if (rp->tx_skbuff_dma[entry]) {
1414 pci_unmap_single(rp->pdev,
1415 rp->tx_skbuff_dma[entry],
1416 rp->tx_skbuff[entry]->len,
1417 PCI_DMA_TODEVICE);
1418 }
1419 dev_kfree_skb_irq(rp->tx_skbuff[entry]);
1420 rp->tx_skbuff[entry] = NULL;
1421 entry = (++rp->dirty_tx) % TX_RING_SIZE;
1422 }
1423 if ((rp->cur_tx - rp->dirty_tx) < TX_QUEUE_LEN - 4)
1424 netif_wake_queue(dev);
1425
1426 spin_unlock(&rp->lock);
1427}
1428
Roger Luethi633949a2006-08-14 23:00:17 -07001429/* Process up to limit frames from receive ring */
1430static int rhine_rx(struct net_device *dev, int limit)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001431{
1432 struct rhine_private *rp = netdev_priv(dev);
Roger Luethi633949a2006-08-14 23:00:17 -07001433 int count;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001434 int entry = rp->cur_rx % RX_RING_SIZE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001435
1436 if (debug > 4) {
1437 printk(KERN_DEBUG "%s: rhine_rx(), entry %d status %8.8x.\n",
1438 dev->name, entry,
1439 le32_to_cpu(rp->rx_head_desc->rx_status));
1440 }
1441
1442 /* If EOP is set on the next entry, it's a new packet. Send it up. */
Roger Luethi633949a2006-08-14 23:00:17 -07001443 for (count = 0; count < limit; ++count) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001444 struct rx_desc *desc = rp->rx_head_desc;
1445 u32 desc_status = le32_to_cpu(desc->rx_status);
1446 int data_size = desc_status >> 16;
1447
Roger Luethi633949a2006-08-14 23:00:17 -07001448 if (desc_status & DescOwn)
1449 break;
1450
Linus Torvalds1da177e2005-04-16 15:20:36 -07001451 if (debug > 4)
Denis Vlasenkoed4030d2005-06-17 08:23:17 +03001452 printk(KERN_DEBUG "rhine_rx() status is %8.8x.\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001453 desc_status);
Roger Luethi633949a2006-08-14 23:00:17 -07001454
Linus Torvalds1da177e2005-04-16 15:20:36 -07001455 if ((desc_status & (RxWholePkt | RxErr)) != RxWholePkt) {
1456 if ((desc_status & RxWholePkt) != RxWholePkt) {
1457 printk(KERN_WARNING "%s: Oversized Ethernet "
1458 "frame spanned multiple buffers, entry "
1459 "%#x length %d status %8.8x!\n",
1460 dev->name, entry, data_size,
1461 desc_status);
1462 printk(KERN_WARNING "%s: Oversized Ethernet "
1463 "frame %p vs %p.\n", dev->name,
1464 rp->rx_head_desc, &rp->rx_ring[entry]);
1465 rp->stats.rx_length_errors++;
1466 } else if (desc_status & RxErr) {
1467 /* There was a error. */
1468 if (debug > 2)
Denis Vlasenkoed4030d2005-06-17 08:23:17 +03001469 printk(KERN_DEBUG "rhine_rx() Rx "
Linus Torvalds1da177e2005-04-16 15:20:36 -07001470 "error was %8.8x.\n",
1471 desc_status);
1472 rp->stats.rx_errors++;
1473 if (desc_status & 0x0030) rp->stats.rx_length_errors++;
1474 if (desc_status & 0x0048) rp->stats.rx_fifo_errors++;
1475 if (desc_status & 0x0004) rp->stats.rx_frame_errors++;
1476 if (desc_status & 0x0002) {
1477 /* this can also be updated outside the interrupt handler */
1478 spin_lock(&rp->lock);
1479 rp->stats.rx_crc_errors++;
1480 spin_unlock(&rp->lock);
1481 }
1482 }
1483 } else {
1484 struct sk_buff *skb;
1485 /* Length should omit the CRC */
1486 int pkt_len = data_size - 4;
1487
1488 /* Check if the packet is long enough to accept without
1489 copying to a minimally-sized skbuff. */
1490 if (pkt_len < rx_copybreak &&
1491 (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001492 skb_reserve(skb, 2); /* 16 byte align the IP header */
1493 pci_dma_sync_single_for_cpu(rp->pdev,
1494 rp->rx_skbuff_dma[entry],
1495 rp->rx_buf_sz,
1496 PCI_DMA_FROMDEVICE);
1497
David S. Miller8c7b7fa2007-07-10 22:08:12 -07001498 skb_copy_to_linear_data(skb,
David S. Miller689be432005-06-28 15:25:31 -07001499 rp->rx_skbuff[entry]->data,
David S. Miller8c7b7fa2007-07-10 22:08:12 -07001500 pkt_len);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001501 skb_put(skb, pkt_len);
1502 pci_dma_sync_single_for_device(rp->pdev,
1503 rp->rx_skbuff_dma[entry],
1504 rp->rx_buf_sz,
1505 PCI_DMA_FROMDEVICE);
1506 } else {
1507 skb = rp->rx_skbuff[entry];
1508 if (skb == NULL) {
1509 printk(KERN_ERR "%s: Inconsistent Rx "
1510 "descriptor chain.\n",
1511 dev->name);
1512 break;
1513 }
1514 rp->rx_skbuff[entry] = NULL;
1515 skb_put(skb, pkt_len);
1516 pci_unmap_single(rp->pdev,
1517 rp->rx_skbuff_dma[entry],
1518 rp->rx_buf_sz,
1519 PCI_DMA_FROMDEVICE);
1520 }
1521 skb->protocol = eth_type_trans(skb, dev);
Roger Luethi633949a2006-08-14 23:00:17 -07001522#ifdef CONFIG_VIA_RHINE_NAPI
1523 netif_receive_skb(skb);
1524#else
Linus Torvalds1da177e2005-04-16 15:20:36 -07001525 netif_rx(skb);
Roger Luethi633949a2006-08-14 23:00:17 -07001526#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001527 dev->last_rx = jiffies;
1528 rp->stats.rx_bytes += pkt_len;
1529 rp->stats.rx_packets++;
1530 }
1531 entry = (++rp->cur_rx) % RX_RING_SIZE;
1532 rp->rx_head_desc = &rp->rx_ring[entry];
1533 }
1534
1535 /* Refill the Rx ring buffers. */
1536 for (; rp->cur_rx - rp->dirty_rx > 0; rp->dirty_rx++) {
1537 struct sk_buff *skb;
1538 entry = rp->dirty_rx % RX_RING_SIZE;
1539 if (rp->rx_skbuff[entry] == NULL) {
1540 skb = dev_alloc_skb(rp->rx_buf_sz);
1541 rp->rx_skbuff[entry] = skb;
1542 if (skb == NULL)
1543 break; /* Better luck next round. */
1544 skb->dev = dev; /* Mark as being used by this device. */
1545 rp->rx_skbuff_dma[entry] =
David S. Miller689be432005-06-28 15:25:31 -07001546 pci_map_single(rp->pdev, skb->data,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001547 rp->rx_buf_sz,
1548 PCI_DMA_FROMDEVICE);
1549 rp->rx_ring[entry].addr = cpu_to_le32(rp->rx_skbuff_dma[entry]);
1550 }
1551 rp->rx_ring[entry].rx_status = cpu_to_le32(DescOwn);
1552 }
Roger Luethi633949a2006-08-14 23:00:17 -07001553
1554 return count;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001555}
1556
1557/*
1558 * Clears the "tally counters" for CRC errors and missed frames(?).
1559 * It has been reported that some chips need a write of 0 to clear
1560 * these, for others the counters are set to 1 when written to and
1561 * instead cleared when read. So we clear them both ways ...
1562 */
1563static inline void clear_tally_counters(void __iomem *ioaddr)
1564{
1565 iowrite32(0, ioaddr + RxMissed);
1566 ioread16(ioaddr + RxCRCErrs);
1567 ioread16(ioaddr + RxMissed);
1568}
1569
1570static void rhine_restart_tx(struct net_device *dev) {
1571 struct rhine_private *rp = netdev_priv(dev);
1572 void __iomem *ioaddr = rp->base;
1573 int entry = rp->dirty_tx % TX_RING_SIZE;
1574 u32 intr_status;
1575
1576 /*
1577 * If new errors occured, we need to sort them out before doing Tx.
1578 * In that case the ISR will be back here RSN anyway.
1579 */
1580 intr_status = get_intr_status(dev);
1581
1582 if ((intr_status & IntrTxErrSummary) == 0) {
1583
1584 /* We know better than the chip where it should continue. */
1585 iowrite32(rp->tx_ring_dma + entry * sizeof(struct tx_desc),
1586 ioaddr + TxRingPtr);
1587
1588 iowrite8(ioread8(ioaddr + ChipCmd) | CmdTxOn,
1589 ioaddr + ChipCmd);
1590 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
1591 ioaddr + ChipCmd1);
1592 IOSYNC;
1593 }
1594 else {
1595 /* This should never happen */
1596 if (debug > 1)
1597 printk(KERN_WARNING "%s: rhine_restart_tx() "
1598 "Another error occured %8.8x.\n",
1599 dev->name, intr_status);
1600 }
1601
1602}
1603
1604static void rhine_error(struct net_device *dev, int intr_status)
1605{
1606 struct rhine_private *rp = netdev_priv(dev);
1607 void __iomem *ioaddr = rp->base;
1608
1609 spin_lock(&rp->lock);
1610
1611 if (intr_status & IntrLinkChange)
John W. Linville38bb6b22006-05-19 10:51:21 -04001612 rhine_check_media(dev, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001613 if (intr_status & IntrStatsMax) {
1614 rp->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs);
1615 rp->stats.rx_missed_errors += ioread16(ioaddr + RxMissed);
1616 clear_tally_counters(ioaddr);
1617 }
1618 if (intr_status & IntrTxAborted) {
1619 if (debug > 1)
1620 printk(KERN_INFO "%s: Abort %8.8x, frame dropped.\n",
1621 dev->name, intr_status);
1622 }
1623 if (intr_status & IntrTxUnderrun) {
1624 if (rp->tx_thresh < 0xE0)
1625 iowrite8(rp->tx_thresh += 0x20, ioaddr + TxConfig);
1626 if (debug > 1)
1627 printk(KERN_INFO "%s: Transmitter underrun, Tx "
1628 "threshold now %2.2x.\n",
1629 dev->name, rp->tx_thresh);
1630 }
1631 if (intr_status & IntrTxDescRace) {
1632 if (debug > 2)
1633 printk(KERN_INFO "%s: Tx descriptor write-back race.\n",
1634 dev->name);
1635 }
1636 if ((intr_status & IntrTxError) &&
1637 (intr_status & (IntrTxAborted |
1638 IntrTxUnderrun | IntrTxDescRace)) == 0) {
1639 if (rp->tx_thresh < 0xE0) {
1640 iowrite8(rp->tx_thresh += 0x20, ioaddr + TxConfig);
1641 }
1642 if (debug > 1)
1643 printk(KERN_INFO "%s: Unspecified error. Tx "
1644 "threshold now %2.2x.\n",
1645 dev->name, rp->tx_thresh);
1646 }
1647 if (intr_status & (IntrTxAborted | IntrTxUnderrun | IntrTxDescRace |
1648 IntrTxError))
1649 rhine_restart_tx(dev);
1650
1651 if (intr_status & ~(IntrLinkChange | IntrStatsMax | IntrTxUnderrun |
1652 IntrTxError | IntrTxAborted | IntrNormalSummary |
1653 IntrTxDescRace)) {
1654 if (debug > 1)
1655 printk(KERN_ERR "%s: Something Wicked happened! "
1656 "%8.8x.\n", dev->name, intr_status);
1657 }
1658
1659 spin_unlock(&rp->lock);
1660}
1661
1662static struct net_device_stats *rhine_get_stats(struct net_device *dev)
1663{
1664 struct rhine_private *rp = netdev_priv(dev);
1665 void __iomem *ioaddr = rp->base;
1666 unsigned long flags;
1667
1668 spin_lock_irqsave(&rp->lock, flags);
1669 rp->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs);
1670 rp->stats.rx_missed_errors += ioread16(ioaddr + RxMissed);
1671 clear_tally_counters(ioaddr);
1672 spin_unlock_irqrestore(&rp->lock, flags);
1673
1674 return &rp->stats;
1675}
1676
1677static void rhine_set_rx_mode(struct net_device *dev)
1678{
1679 struct rhine_private *rp = netdev_priv(dev);
1680 void __iomem *ioaddr = rp->base;
1681 u32 mc_filter[2]; /* Multicast hash filter */
1682 u8 rx_mode; /* Note: 0x02=accept runt, 0x01=accept errs */
1683
1684 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001685 rx_mode = 0x1C;
1686 iowrite32(0xffffffff, ioaddr + MulticastFilter0);
1687 iowrite32(0xffffffff, ioaddr + MulticastFilter1);
1688 } else if ((dev->mc_count > multicast_filter_limit)
1689 || (dev->flags & IFF_ALLMULTI)) {
1690 /* Too many to match, or accept all multicasts. */
1691 iowrite32(0xffffffff, ioaddr + MulticastFilter0);
1692 iowrite32(0xffffffff, ioaddr + MulticastFilter1);
1693 rx_mode = 0x0C;
1694 } else {
1695 struct dev_mc_list *mclist;
1696 int i;
1697 memset(mc_filter, 0, sizeof(mc_filter));
1698 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1699 i++, mclist = mclist->next) {
1700 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1701
1702 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1703 }
1704 iowrite32(mc_filter[0], ioaddr + MulticastFilter0);
1705 iowrite32(mc_filter[1], ioaddr + MulticastFilter1);
1706 rx_mode = 0x0C;
1707 }
1708 iowrite8(rp->rx_thresh | rx_mode, ioaddr + RxConfig);
1709}
1710
1711static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1712{
1713 struct rhine_private *rp = netdev_priv(dev);
1714
1715 strcpy(info->driver, DRV_NAME);
1716 strcpy(info->version, DRV_VERSION);
1717 strcpy(info->bus_info, pci_name(rp->pdev));
1718}
1719
1720static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1721{
1722 struct rhine_private *rp = netdev_priv(dev);
1723 int rc;
1724
1725 spin_lock_irq(&rp->lock);
1726 rc = mii_ethtool_gset(&rp->mii_if, cmd);
1727 spin_unlock_irq(&rp->lock);
1728
1729 return rc;
1730}
1731
1732static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1733{
1734 struct rhine_private *rp = netdev_priv(dev);
1735 int rc;
1736
1737 spin_lock_irq(&rp->lock);
1738 rc = mii_ethtool_sset(&rp->mii_if, cmd);
1739 spin_unlock_irq(&rp->lock);
Roger Luethi00b428c2006-03-28 20:53:56 +02001740 rhine_set_carrier(&rp->mii_if);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001741
1742 return rc;
1743}
1744
1745static int netdev_nway_reset(struct net_device *dev)
1746{
1747 struct rhine_private *rp = netdev_priv(dev);
1748
1749 return mii_nway_restart(&rp->mii_if);
1750}
1751
1752static u32 netdev_get_link(struct net_device *dev)
1753{
1754 struct rhine_private *rp = netdev_priv(dev);
1755
1756 return mii_link_ok(&rp->mii_if);
1757}
1758
1759static u32 netdev_get_msglevel(struct net_device *dev)
1760{
1761 return debug;
1762}
1763
1764static void netdev_set_msglevel(struct net_device *dev, u32 value)
1765{
1766 debug = value;
1767}
1768
1769static void rhine_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1770{
1771 struct rhine_private *rp = netdev_priv(dev);
1772
1773 if (!(rp->quirks & rqWOL))
1774 return;
1775
1776 spin_lock_irq(&rp->lock);
1777 wol->supported = WAKE_PHY | WAKE_MAGIC |
1778 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */
1779 wol->wolopts = rp->wolopts;
1780 spin_unlock_irq(&rp->lock);
1781}
1782
1783static int rhine_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1784{
1785 struct rhine_private *rp = netdev_priv(dev);
1786 u32 support = WAKE_PHY | WAKE_MAGIC |
1787 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */
1788
1789 if (!(rp->quirks & rqWOL))
1790 return -EINVAL;
1791
1792 if (wol->wolopts & ~support)
1793 return -EINVAL;
1794
1795 spin_lock_irq(&rp->lock);
1796 rp->wolopts = wol->wolopts;
1797 spin_unlock_irq(&rp->lock);
1798
1799 return 0;
1800}
1801
Jeff Garzik7282d492006-09-13 14:30:00 -04001802static const struct ethtool_ops netdev_ethtool_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001803 .get_drvinfo = netdev_get_drvinfo,
1804 .get_settings = netdev_get_settings,
1805 .set_settings = netdev_set_settings,
1806 .nway_reset = netdev_nway_reset,
1807 .get_link = netdev_get_link,
1808 .get_msglevel = netdev_get_msglevel,
1809 .set_msglevel = netdev_set_msglevel,
1810 .get_wol = rhine_get_wol,
1811 .set_wol = rhine_set_wol,
1812 .get_sg = ethtool_op_get_sg,
1813 .get_tx_csum = ethtool_op_get_tx_csum,
1814};
1815
1816static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1817{
1818 struct rhine_private *rp = netdev_priv(dev);
1819 int rc;
1820
1821 if (!netif_running(dev))
1822 return -EINVAL;
1823
1824 spin_lock_irq(&rp->lock);
1825 rc = generic_mii_ioctl(&rp->mii_if, if_mii(rq), cmd, NULL);
1826 spin_unlock_irq(&rp->lock);
Roger Luethi00b428c2006-03-28 20:53:56 +02001827 rhine_set_carrier(&rp->mii_if);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001828
1829 return rc;
1830}
1831
1832static int rhine_close(struct net_device *dev)
1833{
1834 struct rhine_private *rp = netdev_priv(dev);
1835 void __iomem *ioaddr = rp->base;
1836
1837 spin_lock_irq(&rp->lock);
1838
1839 netif_stop_queue(dev);
Roger Luethi633949a2006-08-14 23:00:17 -07001840 netif_poll_disable(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001841
1842 if (debug > 1)
1843 printk(KERN_DEBUG "%s: Shutting down ethercard, "
1844 "status was %4.4x.\n",
1845 dev->name, ioread16(ioaddr + ChipCmd));
1846
1847 /* Switch to loopback mode to avoid hardware races. */
1848 iowrite8(rp->tx_thresh | 0x02, ioaddr + TxConfig);
1849
1850 /* Disable interrupts by clearing the interrupt mask. */
1851 iowrite16(0x0000, ioaddr + IntrEnable);
1852
1853 /* Stop the chip's Tx and Rx processes. */
1854 iowrite16(CmdStop, ioaddr + ChipCmd);
1855
1856 spin_unlock_irq(&rp->lock);
1857
1858 free_irq(rp->pdev->irq, dev);
1859 free_rbufs(dev);
1860 free_tbufs(dev);
1861 free_ring(dev);
1862
1863 return 0;
1864}
1865
1866
1867static void __devexit rhine_remove_one(struct pci_dev *pdev)
1868{
1869 struct net_device *dev = pci_get_drvdata(pdev);
1870 struct rhine_private *rp = netdev_priv(dev);
1871
1872 unregister_netdev(dev);
1873
1874 pci_iounmap(pdev, rp->base);
1875 pci_release_regions(pdev);
1876
1877 free_netdev(dev);
1878 pci_disable_device(pdev);
1879 pci_set_drvdata(pdev, NULL);
1880}
1881
Greg Kroah-Hartmand18c3db2005-06-23 17:35:56 -07001882static void rhine_shutdown (struct pci_dev *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001883{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001884 struct net_device *dev = pci_get_drvdata(pdev);
1885 struct rhine_private *rp = netdev_priv(dev);
1886 void __iomem *ioaddr = rp->base;
1887
1888 if (!(rp->quirks & rqWOL))
1889 return; /* Nothing to do for non-WOL adapters */
1890
1891 rhine_power_init(dev);
1892
1893 /* Make sure we use pattern 0, 1 and not 4, 5 */
1894 if (rp->quirks & rq6patterns)
1895 iowrite8(0x04, ioaddr + 0xA7);
1896
1897 if (rp->wolopts & WAKE_MAGIC) {
1898 iowrite8(WOLmagic, ioaddr + WOLcrSet);
1899 /*
1900 * Turn EEPROM-controlled wake-up back on -- some hardware may
1901 * not cooperate otherwise.
1902 */
1903 iowrite8(ioread8(ioaddr + ConfigA) | 0x03, ioaddr + ConfigA);
1904 }
1905
1906 if (rp->wolopts & (WAKE_BCAST|WAKE_MCAST))
1907 iowrite8(WOLbmcast, ioaddr + WOLcgSet);
1908
1909 if (rp->wolopts & WAKE_PHY)
1910 iowrite8(WOLlnkon | WOLlnkoff, ioaddr + WOLcrSet);
1911
1912 if (rp->wolopts & WAKE_UCAST)
1913 iowrite8(WOLucast, ioaddr + WOLcrSet);
1914
1915 if (rp->wolopts) {
1916 /* Enable legacy WOL (for old motherboards) */
1917 iowrite8(0x01, ioaddr + PwcfgSet);
1918 iowrite8(ioread8(ioaddr + StickyHW) | 0x04, ioaddr + StickyHW);
1919 }
1920
1921 /* Hit power state D3 (sleep) */
Roger Luethib933b4d2006-08-14 23:00:21 -07001922 if (!avoid_D3)
1923 iowrite8(ioread8(ioaddr + StickyHW) | 0x03, ioaddr + StickyHW);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001924
1925 /* TODO: Check use of pci_enable_wake() */
1926
1927}
1928
1929#ifdef CONFIG_PM
1930static int rhine_suspend(struct pci_dev *pdev, pm_message_t state)
1931{
1932 struct net_device *dev = pci_get_drvdata(pdev);
1933 struct rhine_private *rp = netdev_priv(dev);
1934 unsigned long flags;
1935
1936 if (!netif_running(dev))
1937 return 0;
1938
1939 netif_device_detach(dev);
1940 pci_save_state(pdev);
1941
1942 spin_lock_irqsave(&rp->lock, flags);
Greg Kroah-Hartmand18c3db2005-06-23 17:35:56 -07001943 rhine_shutdown(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001944 spin_unlock_irqrestore(&rp->lock, flags);
1945
1946 free_irq(dev->irq, dev);
1947 return 0;
1948}
1949
1950static int rhine_resume(struct pci_dev *pdev)
1951{
1952 struct net_device *dev = pci_get_drvdata(pdev);
1953 struct rhine_private *rp = netdev_priv(dev);
1954 unsigned long flags;
1955 int ret;
1956
1957 if (!netif_running(dev))
1958 return 0;
1959
Thomas Gleixner1fb9df52006-07-01 19:29:39 -07001960 if (request_irq(dev->irq, rhine_interrupt, IRQF_SHARED, dev->name, dev))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001961 printk(KERN_ERR "via-rhine %s: request_irq failed\n", dev->name);
1962
1963 ret = pci_set_power_state(pdev, PCI_D0);
1964 if (debug > 1)
1965 printk(KERN_INFO "%s: Entering power state D0 %s (%d).\n",
1966 dev->name, ret ? "failed" : "succeeded", ret);
1967
1968 pci_restore_state(pdev);
1969
1970 spin_lock_irqsave(&rp->lock, flags);
1971#ifdef USE_MMIO
1972 enable_mmio(rp->pioaddr, rp->quirks);
1973#endif
1974 rhine_power_init(dev);
1975 free_tbufs(dev);
1976 free_rbufs(dev);
1977 alloc_tbufs(dev);
1978 alloc_rbufs(dev);
1979 init_registers(dev);
1980 spin_unlock_irqrestore(&rp->lock, flags);
1981
1982 netif_device_attach(dev);
1983
1984 return 0;
1985}
1986#endif /* CONFIG_PM */
1987
1988static struct pci_driver rhine_driver = {
1989 .name = DRV_NAME,
1990 .id_table = rhine_pci_tbl,
1991 .probe = rhine_init_one,
1992 .remove = __devexit_p(rhine_remove_one),
1993#ifdef CONFIG_PM
1994 .suspend = rhine_suspend,
1995 .resume = rhine_resume,
1996#endif /* CONFIG_PM */
Greg Kroah-Hartmand18c3db2005-06-23 17:35:56 -07001997 .shutdown = rhine_shutdown,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001998};
1999
Roger Luethie84df482007-03-06 19:57:37 +01002000static struct dmi_system_id __initdata rhine_dmi_table[] = {
2001 {
2002 .ident = "EPIA-M",
2003 .matches = {
2004 DMI_MATCH(DMI_BIOS_VENDOR, "Award Software International, Inc."),
2005 DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"),
2006 },
2007 },
2008 {
2009 .ident = "KV7",
2010 .matches = {
2011 DMI_MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies, LTD"),
2012 DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"),
2013 },
2014 },
2015 { NULL }
2016};
Linus Torvalds1da177e2005-04-16 15:20:36 -07002017
2018static int __init rhine_init(void)
2019{
2020/* when a module, this is printed whether or not devices are found in probe */
2021#ifdef MODULE
2022 printk(version);
2023#endif
Roger Luethie84df482007-03-06 19:57:37 +01002024 if (dmi_check_system(rhine_dmi_table)) {
2025 /* these BIOSes fail at PXE boot if chip is in D3 */
2026 avoid_D3 = 1;
2027 printk(KERN_WARNING "%s: Broken BIOS detected, avoid_D3 "
2028 "enabled.\n",
2029 DRV_NAME);
2030 }
2031 else if (avoid_D3)
2032 printk(KERN_INFO "%s: avoid_D3 set.\n", DRV_NAME);
2033
Jeff Garzik29917622006-08-19 17:48:59 -04002034 return pci_register_driver(&rhine_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002035}
2036
2037
2038static void __exit rhine_cleanup(void)
2039{
2040 pci_unregister_driver(&rhine_driver);
2041}
2042
2043
2044module_init(rhine_init);
2045module_exit(rhine_cleanup);