Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 28 | #include <drm/drmP.h> |
| 29 | #include <drm/i915_drm.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 30 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 31 | #include "i915_trace.h" |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 32 | #include "intel_drv.h" |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 33 | #include <linux/shmem_fs.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 34 | #include <linux/slab.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 35 | #include <linux/swap.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 36 | #include <linux/pci.h> |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 37 | #include <linux/dma-buf.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 38 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 39 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
| 40 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 41 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
| 42 | unsigned alignment, |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 43 | bool map_and_fenceable, |
| 44 | bool nonblocking); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 45 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
| 46 | struct drm_i915_gem_object *obj, |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 47 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 48 | struct drm_file *file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 49 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 50 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
| 51 | struct drm_i915_gem_object *obj); |
| 52 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
| 53 | struct drm_i915_fence_reg *fence, |
| 54 | bool enable); |
| 55 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 56 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
Ying Han | 1495f23 | 2011-05-24 17:12:27 -0700 | [diff] [blame] | 57 | struct shrink_control *sc); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 58 | static long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
| 59 | static void i915_gem_shrink_all(struct drm_i915_private *dev_priv); |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 60 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 61 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 62 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
| 63 | { |
| 64 | if (obj->tiling_mode) |
| 65 | i915_gem_release_mmap(obj); |
| 66 | |
| 67 | /* As we do not have an associated fence register, we will force |
| 68 | * a tiling change if we ever need to acquire one. |
| 69 | */ |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 70 | obj->fence_dirty = false; |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 71 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 72 | } |
| 73 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 74 | /* some bookkeeping */ |
| 75 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, |
| 76 | size_t size) |
| 77 | { |
| 78 | dev_priv->mm.object_count++; |
| 79 | dev_priv->mm.object_memory += size; |
| 80 | } |
| 81 | |
| 82 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, |
| 83 | size_t size) |
| 84 | { |
| 85 | dev_priv->mm.object_count--; |
| 86 | dev_priv->mm.object_memory -= size; |
| 87 | } |
| 88 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 89 | static int |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 90 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 91 | { |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 92 | int ret; |
| 93 | |
Daniel Vetter | 7abb690 | 2013-05-24 21:29:32 +0200 | [diff] [blame] | 94 | #define EXIT_COND (!i915_reset_in_progress(error) || \ |
| 95 | i915_terminally_wedged(error)) |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 96 | if (EXIT_COND) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 97 | return 0; |
| 98 | |
Daniel Vetter | 0a6759c | 2012-07-04 22:18:41 +0200 | [diff] [blame] | 99 | /* |
| 100 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging |
| 101 | * userspace. If it takes that long something really bad is going on and |
| 102 | * we should simply try to bail out and fail as gracefully as possible. |
| 103 | */ |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 104 | ret = wait_event_interruptible_timeout(error->reset_queue, |
| 105 | EXIT_COND, |
| 106 | 10*HZ); |
Daniel Vetter | 0a6759c | 2012-07-04 22:18:41 +0200 | [diff] [blame] | 107 | if (ret == 0) { |
| 108 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); |
| 109 | return -EIO; |
| 110 | } else if (ret < 0) { |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 111 | return ret; |
Daniel Vetter | 0a6759c | 2012-07-04 22:18:41 +0200 | [diff] [blame] | 112 | } |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 113 | #undef EXIT_COND |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 114 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 115 | return 0; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 116 | } |
| 117 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 118 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 119 | { |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 120 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 121 | int ret; |
| 122 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 123 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 124 | if (ret) |
| 125 | return ret; |
| 126 | |
| 127 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 128 | if (ret) |
| 129 | return ret; |
| 130 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 131 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 132 | return 0; |
| 133 | } |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 134 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 135 | static inline bool |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 136 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 137 | { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 138 | return i915_gem_obj_ggtt_bound(obj) && !obj->active; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 139 | } |
| 140 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 141 | int |
| 142 | i915_gem_init_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 143 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 144 | { |
Ben Widawsky | 93d1879 | 2013-01-17 12:45:17 -0800 | [diff] [blame] | 145 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 146 | struct drm_i915_gem_init *args = data; |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 147 | |
Daniel Vetter | 7bb6fb8 | 2012-04-24 08:22:52 +0200 | [diff] [blame] | 148 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 149 | return -ENODEV; |
| 150 | |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 151 | if (args->gtt_start >= args->gtt_end || |
| 152 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) |
| 153 | return -EINVAL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 154 | |
Daniel Vetter | f534bc0 | 2012-03-26 22:37:04 +0200 | [diff] [blame] | 155 | /* GEM with user mode setting was never supported on ilk and later. */ |
| 156 | if (INTEL_INFO(dev)->gen >= 5) |
| 157 | return -ENODEV; |
| 158 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 159 | mutex_lock(&dev->struct_mutex); |
Ben Widawsky | d7e5008 | 2012-12-18 10:31:25 -0800 | [diff] [blame] | 160 | i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end, |
| 161 | args->gtt_end); |
Ben Widawsky | 93d1879 | 2013-01-17 12:45:17 -0800 | [diff] [blame] | 162 | dev_priv->gtt.mappable_end = args->gtt_end; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 163 | mutex_unlock(&dev->struct_mutex); |
| 164 | |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 165 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 166 | } |
| 167 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 168 | int |
| 169 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 170 | struct drm_file *file) |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 171 | { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 172 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 173 | struct drm_i915_gem_get_aperture *args = data; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 174 | struct drm_i915_gem_object *obj; |
| 175 | size_t pinned; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 176 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 177 | pinned = 0; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 178 | mutex_lock(&dev->struct_mutex); |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 179 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 180 | if (obj->pin_count) |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 181 | pinned += i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 182 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 183 | |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 184 | args->aper_size = dev_priv->gtt.total; |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 185 | args->aper_available_size = args->aper_size - pinned; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 186 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 187 | return 0; |
| 188 | } |
| 189 | |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 190 | void *i915_gem_object_alloc(struct drm_device *dev) |
| 191 | { |
| 192 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 193 | return kmem_cache_alloc(dev_priv->slab, GFP_KERNEL | __GFP_ZERO); |
| 194 | } |
| 195 | |
| 196 | void i915_gem_object_free(struct drm_i915_gem_object *obj) |
| 197 | { |
| 198 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 199 | kmem_cache_free(dev_priv->slab, obj); |
| 200 | } |
| 201 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 202 | static int |
| 203 | i915_gem_create(struct drm_file *file, |
| 204 | struct drm_device *dev, |
| 205 | uint64_t size, |
| 206 | uint32_t *handle_p) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 207 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 208 | struct drm_i915_gem_object *obj; |
Pekka Paalanen | a1a2d1d | 2009-08-23 12:40:55 +0300 | [diff] [blame] | 209 | int ret; |
| 210 | u32 handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 211 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 212 | size = roundup(size, PAGE_SIZE); |
Chris Wilson | 8ffc024 | 2011-09-14 14:14:28 +0200 | [diff] [blame] | 213 | if (size == 0) |
| 214 | return -EINVAL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 215 | |
| 216 | /* Allocate the new object */ |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 217 | obj = i915_gem_alloc_object(dev, size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 218 | if (obj == NULL) |
| 219 | return -ENOMEM; |
| 220 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 221 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
Chris Wilson | 1dfd975 | 2010-09-06 14:44:14 +0100 | [diff] [blame] | 222 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 223 | drm_gem_object_release(&obj->base); |
| 224 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 225 | i915_gem_object_free(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 226 | return ret; |
Chris Wilson | 1dfd975 | 2010-09-06 14:44:14 +0100 | [diff] [blame] | 227 | } |
| 228 | |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 229 | /* drop reference from allocate - handle holds it now */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 230 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 231 | trace_i915_gem_object_create(obj); |
| 232 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 233 | *handle_p = handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 234 | return 0; |
| 235 | } |
| 236 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 237 | int |
| 238 | i915_gem_dumb_create(struct drm_file *file, |
| 239 | struct drm_device *dev, |
| 240 | struct drm_mode_create_dumb *args) |
| 241 | { |
| 242 | /* have to work out size/pitch and return them */ |
Chris Wilson | ed0291f | 2011-03-19 08:21:45 +0000 | [diff] [blame] | 243 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 244 | args->size = args->pitch * args->height; |
| 245 | return i915_gem_create(file, dev, |
| 246 | args->size, &args->handle); |
| 247 | } |
| 248 | |
| 249 | int i915_gem_dumb_destroy(struct drm_file *file, |
| 250 | struct drm_device *dev, |
| 251 | uint32_t handle) |
| 252 | { |
| 253 | return drm_gem_handle_delete(file, handle); |
| 254 | } |
| 255 | |
| 256 | /** |
| 257 | * Creates a new mm object and returns a handle to it. |
| 258 | */ |
| 259 | int |
| 260 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 261 | struct drm_file *file) |
| 262 | { |
| 263 | struct drm_i915_gem_create *args = data; |
Daniel Vetter | 63ed2cb | 2012-04-23 16:50:50 +0200 | [diff] [blame] | 264 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 265 | return i915_gem_create(file, dev, |
| 266 | args->size, &args->handle); |
| 267 | } |
| 268 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 269 | static inline int |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 270 | __copy_to_user_swizzled(char __user *cpu_vaddr, |
| 271 | const char *gpu_vaddr, int gpu_offset, |
| 272 | int length) |
| 273 | { |
| 274 | int ret, cpu_offset = 0; |
| 275 | |
| 276 | while (length > 0) { |
| 277 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 278 | int this_length = min(cacheline_end - gpu_offset, length); |
| 279 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 280 | |
| 281 | ret = __copy_to_user(cpu_vaddr + cpu_offset, |
| 282 | gpu_vaddr + swizzled_gpu_offset, |
| 283 | this_length); |
| 284 | if (ret) |
| 285 | return ret + length; |
| 286 | |
| 287 | cpu_offset += this_length; |
| 288 | gpu_offset += this_length; |
| 289 | length -= this_length; |
| 290 | } |
| 291 | |
| 292 | return 0; |
| 293 | } |
| 294 | |
| 295 | static inline int |
Ben Widawsky | 4f0c7cf | 2012-04-16 14:07:47 -0700 | [diff] [blame] | 296 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
| 297 | const char __user *cpu_vaddr, |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 298 | int length) |
| 299 | { |
| 300 | int ret, cpu_offset = 0; |
| 301 | |
| 302 | while (length > 0) { |
| 303 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 304 | int this_length = min(cacheline_end - gpu_offset, length); |
| 305 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 306 | |
| 307 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, |
| 308 | cpu_vaddr + cpu_offset, |
| 309 | this_length); |
| 310 | if (ret) |
| 311 | return ret + length; |
| 312 | |
| 313 | cpu_offset += this_length; |
| 314 | gpu_offset += this_length; |
| 315 | length -= this_length; |
| 316 | } |
| 317 | |
| 318 | return 0; |
| 319 | } |
| 320 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 321 | /* Per-page copy function for the shmem pread fastpath. |
| 322 | * Flushes invalid cachelines before reading the target if |
| 323 | * needs_clflush is set. */ |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 324 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 325 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
| 326 | char __user *user_data, |
| 327 | bool page_do_bit17_swizzling, bool needs_clflush) |
| 328 | { |
| 329 | char *vaddr; |
| 330 | int ret; |
| 331 | |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 332 | if (unlikely(page_do_bit17_swizzling)) |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 333 | return -EINVAL; |
| 334 | |
| 335 | vaddr = kmap_atomic(page); |
| 336 | if (needs_clflush) |
| 337 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 338 | page_length); |
| 339 | ret = __copy_to_user_inatomic(user_data, |
| 340 | vaddr + shmem_page_offset, |
| 341 | page_length); |
| 342 | kunmap_atomic(vaddr); |
| 343 | |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 344 | return ret ? -EFAULT : 0; |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 345 | } |
| 346 | |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 347 | static void |
| 348 | shmem_clflush_swizzled_range(char *addr, unsigned long length, |
| 349 | bool swizzled) |
| 350 | { |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 351 | if (unlikely(swizzled)) { |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 352 | unsigned long start = (unsigned long) addr; |
| 353 | unsigned long end = (unsigned long) addr + length; |
| 354 | |
| 355 | /* For swizzling simply ensure that we always flush both |
| 356 | * channels. Lame, but simple and it works. Swizzled |
| 357 | * pwrite/pread is far from a hotpath - current userspace |
| 358 | * doesn't use it at all. */ |
| 359 | start = round_down(start, 128); |
| 360 | end = round_up(end, 128); |
| 361 | |
| 362 | drm_clflush_virt_range((void *)start, end - start); |
| 363 | } else { |
| 364 | drm_clflush_virt_range(addr, length); |
| 365 | } |
| 366 | |
| 367 | } |
| 368 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 369 | /* Only difference to the fast-path function is that this can handle bit17 |
| 370 | * and uses non-atomic copy and kmap functions. */ |
| 371 | static int |
| 372 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, |
| 373 | char __user *user_data, |
| 374 | bool page_do_bit17_swizzling, bool needs_clflush) |
| 375 | { |
| 376 | char *vaddr; |
| 377 | int ret; |
| 378 | |
| 379 | vaddr = kmap(page); |
| 380 | if (needs_clflush) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 381 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 382 | page_length, |
| 383 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 384 | |
| 385 | if (page_do_bit17_swizzling) |
| 386 | ret = __copy_to_user_swizzled(user_data, |
| 387 | vaddr, shmem_page_offset, |
| 388 | page_length); |
| 389 | else |
| 390 | ret = __copy_to_user(user_data, |
| 391 | vaddr + shmem_page_offset, |
| 392 | page_length); |
| 393 | kunmap(page); |
| 394 | |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 395 | return ret ? - EFAULT : 0; |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 396 | } |
| 397 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 398 | static int |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 399 | i915_gem_shmem_pread(struct drm_device *dev, |
| 400 | struct drm_i915_gem_object *obj, |
| 401 | struct drm_i915_gem_pread *args, |
| 402 | struct drm_file *file) |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 403 | { |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 404 | char __user *user_data; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 405 | ssize_t remain; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 406 | loff_t offset; |
Ben Widawsky | eb2c0c8 | 2012-02-15 14:42:43 +0100 | [diff] [blame] | 407 | int shmem_page_offset, page_length, ret = 0; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 408 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 409 | int prefaulted = 0; |
Daniel Vetter | 8489731 | 2012-03-25 19:47:31 +0200 | [diff] [blame] | 410 | int needs_clflush = 0; |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 411 | struct sg_page_iter sg_iter; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 412 | |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 413 | user_data = to_user_ptr(args->data_ptr); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 414 | remain = args->size; |
| 415 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 416 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 417 | |
Daniel Vetter | 8489731 | 2012-03-25 19:47:31 +0200 | [diff] [blame] | 418 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
| 419 | /* If we're not in the cpu read domain, set ourself into the gtt |
| 420 | * read domain and manually flush cachelines (if required). This |
| 421 | * optimizes for the case when the gpu will dirty the data |
| 422 | * anyway again before the next pread happens. */ |
| 423 | if (obj->cache_level == I915_CACHE_NONE) |
| 424 | needs_clflush = 1; |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 425 | if (i915_gem_obj_ggtt_bound(obj)) { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 426 | ret = i915_gem_object_set_to_gtt_domain(obj, false); |
| 427 | if (ret) |
| 428 | return ret; |
| 429 | } |
Daniel Vetter | 8489731 | 2012-03-25 19:47:31 +0200 | [diff] [blame] | 430 | } |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 431 | |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 432 | ret = i915_gem_object_get_pages(obj); |
| 433 | if (ret) |
| 434 | return ret; |
| 435 | |
| 436 | i915_gem_object_pin_pages(obj); |
| 437 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 438 | offset = args->offset; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 439 | |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 440 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
| 441 | offset >> PAGE_SHIFT) { |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 442 | struct page *page = sg_page_iter_page(&sg_iter); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 443 | |
| 444 | if (remain <= 0) |
| 445 | break; |
| 446 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 447 | /* Operation in this page |
| 448 | * |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 449 | * shmem_page_offset = offset within page in shmem file |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 450 | * page_length = bytes to copy for this page |
| 451 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 452 | shmem_page_offset = offset_in_page(offset); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 453 | page_length = remain; |
| 454 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 455 | page_length = PAGE_SIZE - shmem_page_offset; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 456 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 457 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
| 458 | (page_to_phys(page) & (1 << 17)) != 0; |
| 459 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 460 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
| 461 | user_data, page_do_bit17_swizzling, |
| 462 | needs_clflush); |
| 463 | if (ret == 0) |
| 464 | goto next_page; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 465 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 466 | mutex_unlock(&dev->struct_mutex); |
| 467 | |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 468 | if (!prefaulted) { |
Daniel Vetter | f56f821 | 2012-03-25 19:47:41 +0200 | [diff] [blame] | 469 | ret = fault_in_multipages_writeable(user_data, remain); |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 470 | /* Userspace is tricking us, but we've already clobbered |
| 471 | * its pages with the prefault and promised to write the |
| 472 | * data up to the first fault. Hence ignore any errors |
| 473 | * and just continue. */ |
| 474 | (void)ret; |
| 475 | prefaulted = 1; |
| 476 | } |
| 477 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 478 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
| 479 | user_data, page_do_bit17_swizzling, |
| 480 | needs_clflush); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 481 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 482 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 483 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 484 | next_page: |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 485 | mark_page_accessed(page); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 486 | |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 487 | if (ret) |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 488 | goto out; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 489 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 490 | remain -= page_length; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 491 | user_data += page_length; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 492 | offset += page_length; |
| 493 | } |
| 494 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 495 | out: |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 496 | i915_gem_object_unpin_pages(obj); |
| 497 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 498 | return ret; |
| 499 | } |
| 500 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 501 | /** |
| 502 | * Reads data from the object referenced by handle. |
| 503 | * |
| 504 | * On error, the contents of *data are undefined. |
| 505 | */ |
| 506 | int |
| 507 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 508 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 509 | { |
| 510 | struct drm_i915_gem_pread *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 511 | struct drm_i915_gem_object *obj; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 512 | int ret = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 513 | |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 514 | if (args->size == 0) |
| 515 | return 0; |
| 516 | |
| 517 | if (!access_ok(VERIFY_WRITE, |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 518 | to_user_ptr(args->data_ptr), |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 519 | args->size)) |
| 520 | return -EFAULT; |
| 521 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 522 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 523 | if (ret) |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 524 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 525 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 526 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 527 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 528 | ret = -ENOENT; |
| 529 | goto unlock; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 530 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 531 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 532 | /* Bounds check source. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 533 | if (args->offset > obj->base.size || |
| 534 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 535 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 536 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 537 | } |
| 538 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 539 | /* prime objects have no backing filp to GEM pread/pwrite |
| 540 | * pages from. |
| 541 | */ |
| 542 | if (!obj->base.filp) { |
| 543 | ret = -EINVAL; |
| 544 | goto out; |
| 545 | } |
| 546 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 547 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
| 548 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 549 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 550 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 551 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 552 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 553 | unlock: |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 554 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 555 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 556 | } |
| 557 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 558 | /* This is the fast write path which cannot handle |
| 559 | * page faults in the source data |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 560 | */ |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 561 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 562 | static inline int |
| 563 | fast_user_write(struct io_mapping *mapping, |
| 564 | loff_t page_base, int page_offset, |
| 565 | char __user *user_data, |
| 566 | int length) |
| 567 | { |
Ben Widawsky | 4f0c7cf | 2012-04-16 14:07:47 -0700 | [diff] [blame] | 568 | void __iomem *vaddr_atomic; |
| 569 | void *vaddr; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 570 | unsigned long unwritten; |
| 571 | |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 572 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
Ben Widawsky | 4f0c7cf | 2012-04-16 14:07:47 -0700 | [diff] [blame] | 573 | /* We can use the cpu mem copy function because this is X86. */ |
| 574 | vaddr = (void __force*)vaddr_atomic + page_offset; |
| 575 | unwritten = __copy_from_user_inatomic_nocache(vaddr, |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 576 | user_data, length); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 577 | io_mapping_unmap_atomic(vaddr_atomic); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 578 | return unwritten; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 579 | } |
| 580 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 581 | /** |
| 582 | * This is the fast pwrite path, where we copy the data directly from the |
| 583 | * user into the GTT, uncached. |
| 584 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 585 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 586 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
| 587 | struct drm_i915_gem_object *obj, |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 588 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 589 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 590 | { |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 591 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 592 | ssize_t remain; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 593 | loff_t offset, page_base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 594 | char __user *user_data; |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 595 | int page_offset, page_length, ret; |
| 596 | |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 597 | ret = i915_gem_object_pin(obj, 0, true, true); |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 598 | if (ret) |
| 599 | goto out; |
| 600 | |
| 601 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 602 | if (ret) |
| 603 | goto out_unpin; |
| 604 | |
| 605 | ret = i915_gem_object_put_fence(obj); |
| 606 | if (ret) |
| 607 | goto out_unpin; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 608 | |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 609 | user_data = to_user_ptr(args->data_ptr); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 610 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 611 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 612 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 613 | |
| 614 | while (remain > 0) { |
| 615 | /* Operation in this page |
| 616 | * |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 617 | * page_base = page offset within aperture |
| 618 | * page_offset = offset within page |
| 619 | * page_length = bytes to copy for this page |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 620 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 621 | page_base = offset & PAGE_MASK; |
| 622 | page_offset = offset_in_page(offset); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 623 | page_length = remain; |
| 624 | if ((page_offset + remain) > PAGE_SIZE) |
| 625 | page_length = PAGE_SIZE - page_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 626 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 627 | /* If we get a fault while copying data, then (presumably) our |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 628 | * source page isn't available. Return the error and we'll |
| 629 | * retry in the slow path. |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 630 | */ |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 631 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 632 | page_offset, user_data, page_length)) { |
| 633 | ret = -EFAULT; |
| 634 | goto out_unpin; |
| 635 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 636 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 637 | remain -= page_length; |
| 638 | user_data += page_length; |
| 639 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 640 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 641 | |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 642 | out_unpin: |
| 643 | i915_gem_object_unpin(obj); |
| 644 | out: |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 645 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 646 | } |
| 647 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 648 | /* Per-page copy function for the shmem pwrite fastpath. |
| 649 | * Flushes invalid cachelines before writing to the target if |
| 650 | * needs_clflush_before is set and flushes out any written cachelines after |
| 651 | * writing if needs_clflush is set. */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 652 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 653 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
| 654 | char __user *user_data, |
| 655 | bool page_do_bit17_swizzling, |
| 656 | bool needs_clflush_before, |
| 657 | bool needs_clflush_after) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 658 | { |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 659 | char *vaddr; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 660 | int ret; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 661 | |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 662 | if (unlikely(page_do_bit17_swizzling)) |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 663 | return -EINVAL; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 664 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 665 | vaddr = kmap_atomic(page); |
| 666 | if (needs_clflush_before) |
| 667 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 668 | page_length); |
| 669 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, |
| 670 | user_data, |
| 671 | page_length); |
| 672 | if (needs_clflush_after) |
| 673 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 674 | page_length); |
| 675 | kunmap_atomic(vaddr); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 676 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 677 | return ret ? -EFAULT : 0; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 678 | } |
| 679 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 680 | /* Only difference to the fast-path function is that this can handle bit17 |
| 681 | * and uses non-atomic copy and kmap functions. */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 682 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 683 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
| 684 | char __user *user_data, |
| 685 | bool page_do_bit17_swizzling, |
| 686 | bool needs_clflush_before, |
| 687 | bool needs_clflush_after) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 688 | { |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 689 | char *vaddr; |
| 690 | int ret; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 691 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 692 | vaddr = kmap(page); |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 693 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 694 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 695 | page_length, |
| 696 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 697 | if (page_do_bit17_swizzling) |
| 698 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 699 | user_data, |
| 700 | page_length); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 701 | else |
| 702 | ret = __copy_from_user(vaddr + shmem_page_offset, |
| 703 | user_data, |
| 704 | page_length); |
| 705 | if (needs_clflush_after) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 706 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 707 | page_length, |
| 708 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 709 | kunmap(page); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 710 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 711 | return ret ? -EFAULT : 0; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 712 | } |
| 713 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 714 | static int |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 715 | i915_gem_shmem_pwrite(struct drm_device *dev, |
| 716 | struct drm_i915_gem_object *obj, |
| 717 | struct drm_i915_gem_pwrite *args, |
| 718 | struct drm_file *file) |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 719 | { |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 720 | ssize_t remain; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 721 | loff_t offset; |
| 722 | char __user *user_data; |
Ben Widawsky | eb2c0c8 | 2012-02-15 14:42:43 +0100 | [diff] [blame] | 723 | int shmem_page_offset, page_length, ret = 0; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 724 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 725 | int hit_slowpath = 0; |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 726 | int needs_clflush_after = 0; |
| 727 | int needs_clflush_before = 0; |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 728 | struct sg_page_iter sg_iter; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 729 | |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 730 | user_data = to_user_ptr(args->data_ptr); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 731 | remain = args->size; |
| 732 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 733 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 734 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 735 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
| 736 | /* If we're not in the cpu write domain, set ourself into the gtt |
| 737 | * write domain and manually flush cachelines (if required). This |
| 738 | * optimizes for the case when the gpu will use the data |
| 739 | * right away and we therefore have to clflush anyway. */ |
| 740 | if (obj->cache_level == I915_CACHE_NONE) |
| 741 | needs_clflush_after = 1; |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 742 | if (i915_gem_obj_ggtt_bound(obj)) { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 743 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 744 | if (ret) |
| 745 | return ret; |
| 746 | } |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 747 | } |
| 748 | /* Same trick applies for invalidate partially written cachelines before |
| 749 | * writing. */ |
| 750 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU) |
| 751 | && obj->cache_level == I915_CACHE_NONE) |
| 752 | needs_clflush_before = 1; |
| 753 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 754 | ret = i915_gem_object_get_pages(obj); |
| 755 | if (ret) |
| 756 | return ret; |
| 757 | |
| 758 | i915_gem_object_pin_pages(obj); |
| 759 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 760 | offset = args->offset; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 761 | obj->dirty = 1; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 762 | |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 763 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
| 764 | offset >> PAGE_SHIFT) { |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 765 | struct page *page = sg_page_iter_page(&sg_iter); |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 766 | int partial_cacheline_write; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 767 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 768 | if (remain <= 0) |
| 769 | break; |
| 770 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 771 | /* Operation in this page |
| 772 | * |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 773 | * shmem_page_offset = offset within page in shmem file |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 774 | * page_length = bytes to copy for this page |
| 775 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 776 | shmem_page_offset = offset_in_page(offset); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 777 | |
| 778 | page_length = remain; |
| 779 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 780 | page_length = PAGE_SIZE - shmem_page_offset; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 781 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 782 | /* If we don't overwrite a cacheline completely we need to be |
| 783 | * careful to have up-to-date data by first clflushing. Don't |
| 784 | * overcomplicate things and flush the entire patch. */ |
| 785 | partial_cacheline_write = needs_clflush_before && |
| 786 | ((shmem_page_offset | page_length) |
| 787 | & (boot_cpu_data.x86_clflush_size - 1)); |
| 788 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 789 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
| 790 | (page_to_phys(page) & (1 << 17)) != 0; |
| 791 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 792 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
| 793 | user_data, page_do_bit17_swizzling, |
| 794 | partial_cacheline_write, |
| 795 | needs_clflush_after); |
| 796 | if (ret == 0) |
| 797 | goto next_page; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 798 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 799 | hit_slowpath = 1; |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 800 | mutex_unlock(&dev->struct_mutex); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 801 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
| 802 | user_data, page_do_bit17_swizzling, |
| 803 | partial_cacheline_write, |
| 804 | needs_clflush_after); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 805 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 806 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 807 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 808 | next_page: |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 809 | set_page_dirty(page); |
| 810 | mark_page_accessed(page); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 811 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 812 | if (ret) |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 813 | goto out; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 814 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 815 | remain -= page_length; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 816 | user_data += page_length; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 817 | offset += page_length; |
| 818 | } |
| 819 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 820 | out: |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 821 | i915_gem_object_unpin_pages(obj); |
| 822 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 823 | if (hit_slowpath) { |
Daniel Vetter | 8dcf015 | 2012-11-15 16:53:58 +0100 | [diff] [blame] | 824 | /* |
| 825 | * Fixup: Flush cpu caches in case we didn't flush the dirty |
| 826 | * cachelines in-line while writing and the object moved |
| 827 | * out of the cpu write domain while we've dropped the lock. |
| 828 | */ |
| 829 | if (!needs_clflush_after && |
| 830 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 831 | i915_gem_clflush_object(obj); |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 832 | i915_gem_chipset_flush(dev); |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 833 | } |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 834 | } |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 835 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 836 | if (needs_clflush_after) |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 837 | i915_gem_chipset_flush(dev); |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 838 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 839 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 840 | } |
| 841 | |
| 842 | /** |
| 843 | * Writes data to the object referenced by handle. |
| 844 | * |
| 845 | * On error, the contents of the buffer that were to be modified are undefined. |
| 846 | */ |
| 847 | int |
| 848 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 849 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 850 | { |
| 851 | struct drm_i915_gem_pwrite *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 852 | struct drm_i915_gem_object *obj; |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 853 | int ret; |
| 854 | |
| 855 | if (args->size == 0) |
| 856 | return 0; |
| 857 | |
| 858 | if (!access_ok(VERIFY_READ, |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 859 | to_user_ptr(args->data_ptr), |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 860 | args->size)) |
| 861 | return -EFAULT; |
| 862 | |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 863 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), |
Daniel Vetter | f56f821 | 2012-03-25 19:47:41 +0200 | [diff] [blame] | 864 | args->size); |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 865 | if (ret) |
| 866 | return -EFAULT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 867 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 868 | ret = i915_mutex_lock_interruptible(dev); |
| 869 | if (ret) |
| 870 | return ret; |
| 871 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 872 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 873 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 874 | ret = -ENOENT; |
| 875 | goto unlock; |
| 876 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 877 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 878 | /* Bounds check destination. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 879 | if (args->offset > obj->base.size || |
| 880 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 881 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 882 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 883 | } |
| 884 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 885 | /* prime objects have no backing filp to GEM pread/pwrite |
| 886 | * pages from. |
| 887 | */ |
| 888 | if (!obj->base.filp) { |
| 889 | ret = -EINVAL; |
| 890 | goto out; |
| 891 | } |
| 892 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 893 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
| 894 | |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 895 | ret = -EFAULT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 896 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
| 897 | * it would end up going through the fenced access, and we'll get |
| 898 | * different detiling behavior between reading and writing. |
| 899 | * pread/pwrite currently are reading and writing from the CPU |
| 900 | * perspective, requiring manual detiling by the client. |
| 901 | */ |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 902 | if (obj->phys_obj) { |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 903 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 904 | goto out; |
| 905 | } |
| 906 | |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 907 | if (obj->cache_level == I915_CACHE_NONE && |
Daniel Vetter | c07496f | 2012-04-13 15:51:51 +0200 | [diff] [blame] | 908 | obj->tiling_mode == I915_TILING_NONE && |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 909 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 910 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 911 | /* Note that the gtt paths might fail with non-page-backed user |
| 912 | * pointers (e.g. gtt mappings when moving data between |
| 913 | * textures). Fallback to the shmem path in that case. */ |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 914 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 915 | |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 916 | if (ret == -EFAULT || ret == -ENOSPC) |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 917 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 918 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 919 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 920 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 921 | unlock: |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 922 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 923 | return ret; |
| 924 | } |
| 925 | |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 926 | int |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 927 | i915_gem_check_wedge(struct i915_gpu_error *error, |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 928 | bool interruptible) |
| 929 | { |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 930 | if (i915_reset_in_progress(error)) { |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 931 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
| 932 | * -EIO unconditionally for these. */ |
| 933 | if (!interruptible) |
| 934 | return -EIO; |
| 935 | |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 936 | /* Recovery complete, but the reset failed ... */ |
| 937 | if (i915_terminally_wedged(error)) |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 938 | return -EIO; |
| 939 | |
| 940 | return -EAGAIN; |
| 941 | } |
| 942 | |
| 943 | return 0; |
| 944 | } |
| 945 | |
| 946 | /* |
| 947 | * Compare seqno against outstanding lazy request. Emit a request if they are |
| 948 | * equal. |
| 949 | */ |
| 950 | static int |
| 951 | i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) |
| 952 | { |
| 953 | int ret; |
| 954 | |
| 955 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); |
| 956 | |
| 957 | ret = 0; |
| 958 | if (seqno == ring->outstanding_lazy_request) |
Mika Kuoppala | 0025c07 | 2013-06-12 12:35:30 +0300 | [diff] [blame] | 959 | ret = i915_add_request(ring, NULL); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 960 | |
| 961 | return ret; |
| 962 | } |
| 963 | |
| 964 | /** |
| 965 | * __wait_seqno - wait until execution of seqno has finished |
| 966 | * @ring: the ring expected to report seqno |
| 967 | * @seqno: duh! |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 968 | * @reset_counter: reset sequence associated with the given seqno |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 969 | * @interruptible: do an interruptible wait (normally yes) |
| 970 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining |
| 971 | * |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 972 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
| 973 | * values have been read by the caller in an smp safe manner. Where read-side |
| 974 | * locks are involved, it is sufficient to read the reset_counter before |
| 975 | * unlocking the lock that protects the seqno. For lockless tricks, the |
| 976 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be |
| 977 | * inserted. |
| 978 | * |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 979 | * Returns 0 if the seqno was found within the alloted time. Else returns the |
| 980 | * errno with remaining time filled in timeout argument. |
| 981 | */ |
| 982 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 983 | unsigned reset_counter, |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 984 | bool interruptible, struct timespec *timeout) |
| 985 | { |
| 986 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
| 987 | struct timespec before, now, wait_time={1,0}; |
| 988 | unsigned long timeout_jiffies; |
| 989 | long end; |
| 990 | bool wait_forever = true; |
| 991 | int ret; |
| 992 | |
| 993 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) |
| 994 | return 0; |
| 995 | |
| 996 | trace_i915_gem_request_wait_begin(ring, seqno); |
| 997 | |
| 998 | if (timeout != NULL) { |
| 999 | wait_time = *timeout; |
| 1000 | wait_forever = false; |
| 1001 | } |
| 1002 | |
Imre Deak | e054cc3 | 2013-05-21 20:03:19 +0300 | [diff] [blame] | 1003 | timeout_jiffies = timespec_to_jiffies_timeout(&wait_time); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1004 | |
| 1005 | if (WARN_ON(!ring->irq_get(ring))) |
| 1006 | return -ENODEV; |
| 1007 | |
| 1008 | /* Record current time in case interrupted by signal, or wedged * */ |
| 1009 | getrawmonotonic(&before); |
| 1010 | |
| 1011 | #define EXIT_COND \ |
| 1012 | (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \ |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1013 | i915_reset_in_progress(&dev_priv->gpu_error) || \ |
| 1014 | reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1015 | do { |
| 1016 | if (interruptible) |
| 1017 | end = wait_event_interruptible_timeout(ring->irq_queue, |
| 1018 | EXIT_COND, |
| 1019 | timeout_jiffies); |
| 1020 | else |
| 1021 | end = wait_event_timeout(ring->irq_queue, EXIT_COND, |
| 1022 | timeout_jiffies); |
| 1023 | |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1024 | /* We need to check whether any gpu reset happened in between |
| 1025 | * the caller grabbing the seqno and now ... */ |
| 1026 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) |
| 1027 | end = -EAGAIN; |
| 1028 | |
| 1029 | /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely |
| 1030 | * gone. */ |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 1031 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1032 | if (ret) |
| 1033 | end = ret; |
| 1034 | } while (end == 0 && wait_forever); |
| 1035 | |
| 1036 | getrawmonotonic(&now); |
| 1037 | |
| 1038 | ring->irq_put(ring); |
| 1039 | trace_i915_gem_request_wait_end(ring, seqno); |
| 1040 | #undef EXIT_COND |
| 1041 | |
| 1042 | if (timeout) { |
| 1043 | struct timespec sleep_time = timespec_sub(now, before); |
| 1044 | *timeout = timespec_sub(*timeout, sleep_time); |
Chris Wilson | 4f42f4e | 2013-04-26 16:22:46 +0300 | [diff] [blame] | 1045 | if (!timespec_valid(timeout)) /* i.e. negative time remains */ |
| 1046 | set_normalized_timespec(timeout, 0, 0); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1047 | } |
| 1048 | |
| 1049 | switch (end) { |
| 1050 | case -EIO: |
| 1051 | case -EAGAIN: /* Wedged */ |
| 1052 | case -ERESTARTSYS: /* Signal */ |
| 1053 | return (int)end; |
| 1054 | case 0: /* Timeout */ |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1055 | return -ETIME; |
| 1056 | default: /* Completed */ |
| 1057 | WARN_ON(end < 0); /* We're not aware of other errors */ |
| 1058 | return 0; |
| 1059 | } |
| 1060 | } |
| 1061 | |
| 1062 | /** |
| 1063 | * Waits for a sequence number to be signaled, and cleans up the |
| 1064 | * request and object lists appropriately for that event. |
| 1065 | */ |
| 1066 | int |
| 1067 | i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) |
| 1068 | { |
| 1069 | struct drm_device *dev = ring->dev; |
| 1070 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1071 | bool interruptible = dev_priv->mm.interruptible; |
| 1072 | int ret; |
| 1073 | |
| 1074 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 1075 | BUG_ON(seqno == 0); |
| 1076 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 1077 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1078 | if (ret) |
| 1079 | return ret; |
| 1080 | |
| 1081 | ret = i915_gem_check_olr(ring, seqno); |
| 1082 | if (ret) |
| 1083 | return ret; |
| 1084 | |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1085 | return __wait_seqno(ring, seqno, |
| 1086 | atomic_read(&dev_priv->gpu_error.reset_counter), |
| 1087 | interruptible, NULL); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1088 | } |
| 1089 | |
Chris Wilson | d26e3af | 2013-06-29 22:05:26 +0100 | [diff] [blame] | 1090 | static int |
| 1091 | i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj, |
| 1092 | struct intel_ring_buffer *ring) |
| 1093 | { |
| 1094 | i915_gem_retire_requests_ring(ring); |
| 1095 | |
| 1096 | /* Manually manage the write flush as we may have not yet |
| 1097 | * retired the buffer. |
| 1098 | * |
| 1099 | * Note that the last_write_seqno is always the earlier of |
| 1100 | * the two (read/write) seqno, so if we haved successfully waited, |
| 1101 | * we know we have passed the last write. |
| 1102 | */ |
| 1103 | obj->last_write_seqno = 0; |
| 1104 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; |
| 1105 | |
| 1106 | return 0; |
| 1107 | } |
| 1108 | |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1109 | /** |
| 1110 | * Ensures that all rendering to the object has completed and the object is |
| 1111 | * safe to unbind from the GTT or access from the CPU. |
| 1112 | */ |
| 1113 | static __must_check int |
| 1114 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
| 1115 | bool readonly) |
| 1116 | { |
| 1117 | struct intel_ring_buffer *ring = obj->ring; |
| 1118 | u32 seqno; |
| 1119 | int ret; |
| 1120 | |
| 1121 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; |
| 1122 | if (seqno == 0) |
| 1123 | return 0; |
| 1124 | |
| 1125 | ret = i915_wait_seqno(ring, seqno); |
| 1126 | if (ret) |
| 1127 | return ret; |
| 1128 | |
Chris Wilson | d26e3af | 2013-06-29 22:05:26 +0100 | [diff] [blame] | 1129 | return i915_gem_object_wait_rendering__tail(obj, ring); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1130 | } |
| 1131 | |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1132 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
| 1133 | * as the object state may change during this call. |
| 1134 | */ |
| 1135 | static __must_check int |
| 1136 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, |
| 1137 | bool readonly) |
| 1138 | { |
| 1139 | struct drm_device *dev = obj->base.dev; |
| 1140 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1141 | struct intel_ring_buffer *ring = obj->ring; |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1142 | unsigned reset_counter; |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1143 | u32 seqno; |
| 1144 | int ret; |
| 1145 | |
| 1146 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 1147 | BUG_ON(!dev_priv->mm.interruptible); |
| 1148 | |
| 1149 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; |
| 1150 | if (seqno == 0) |
| 1151 | return 0; |
| 1152 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 1153 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1154 | if (ret) |
| 1155 | return ret; |
| 1156 | |
| 1157 | ret = i915_gem_check_olr(ring, seqno); |
| 1158 | if (ret) |
| 1159 | return ret; |
| 1160 | |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1161 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1162 | mutex_unlock(&dev->struct_mutex); |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1163 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL); |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1164 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | d26e3af | 2013-06-29 22:05:26 +0100 | [diff] [blame] | 1165 | if (ret) |
| 1166 | return ret; |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1167 | |
Chris Wilson | d26e3af | 2013-06-29 22:05:26 +0100 | [diff] [blame] | 1168 | return i915_gem_object_wait_rendering__tail(obj, ring); |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1169 | } |
| 1170 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1171 | /** |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1172 | * Called when user space prepares to use an object with the CPU, either |
| 1173 | * through the mmap ioctl's mapping or a GTT mapping. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1174 | */ |
| 1175 | int |
| 1176 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1177 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1178 | { |
| 1179 | struct drm_i915_gem_set_domain *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1180 | struct drm_i915_gem_object *obj; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1181 | uint32_t read_domains = args->read_domains; |
| 1182 | uint32_t write_domain = args->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1183 | int ret; |
| 1184 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1185 | /* Only handle setting domains to types used by the CPU. */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1186 | if (write_domain & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1187 | return -EINVAL; |
| 1188 | |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1189 | if (read_domains & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1190 | return -EINVAL; |
| 1191 | |
| 1192 | /* Having something in the write domain implies it's in the read |
| 1193 | * domain, and only that read domain. Enforce that in the request. |
| 1194 | */ |
| 1195 | if (write_domain != 0 && read_domains != write_domain) |
| 1196 | return -EINVAL; |
| 1197 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1198 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1199 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1200 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1201 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1202 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1203 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1204 | ret = -ENOENT; |
| 1205 | goto unlock; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1206 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1207 | |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1208 | /* Try to flush the object off the GPU without holding the lock. |
| 1209 | * We will repeat the flush holding the lock in the normal manner |
| 1210 | * to catch cases where we are gazumped. |
| 1211 | */ |
| 1212 | ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain); |
| 1213 | if (ret) |
| 1214 | goto unref; |
| 1215 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1216 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
| 1217 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 1218 | |
| 1219 | /* Silently promote "you're not bound, there was nothing to do" |
| 1220 | * to success, since the client was just asking us to |
| 1221 | * make sure everything was done. |
| 1222 | */ |
| 1223 | if (ret == -EINVAL) |
| 1224 | ret = 0; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1225 | } else { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1226 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1227 | } |
| 1228 | |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1229 | unref: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1230 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1231 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1232 | mutex_unlock(&dev->struct_mutex); |
| 1233 | return ret; |
| 1234 | } |
| 1235 | |
| 1236 | /** |
| 1237 | * Called when user space has done writes to this buffer |
| 1238 | */ |
| 1239 | int |
| 1240 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1241 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1242 | { |
| 1243 | struct drm_i915_gem_sw_finish *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1244 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1245 | int ret = 0; |
| 1246 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1247 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1248 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1249 | return ret; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1250 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1251 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1252 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1253 | ret = -ENOENT; |
| 1254 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1255 | } |
| 1256 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1257 | /* Pinned buffers may be scanout, so flush the cache */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1258 | if (obj->pin_count) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1259 | i915_gem_object_flush_cpu_write_domain(obj); |
| 1260 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1261 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1262 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1263 | mutex_unlock(&dev->struct_mutex); |
| 1264 | return ret; |
| 1265 | } |
| 1266 | |
| 1267 | /** |
| 1268 | * Maps the contents of an object, returning the address it is mapped |
| 1269 | * into. |
| 1270 | * |
| 1271 | * While the mapping holds a reference on the contents of the object, it doesn't |
| 1272 | * imply a ref on the object itself. |
| 1273 | */ |
| 1274 | int |
| 1275 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1276 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1277 | { |
| 1278 | struct drm_i915_gem_mmap *args = data; |
| 1279 | struct drm_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1280 | unsigned long addr; |
| 1281 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1282 | obj = drm_gem_object_lookup(dev, file, args->handle); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1283 | if (obj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 1284 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1285 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1286 | /* prime objects have no backing filp to GEM mmap |
| 1287 | * pages from. |
| 1288 | */ |
| 1289 | if (!obj->filp) { |
| 1290 | drm_gem_object_unreference_unlocked(obj); |
| 1291 | return -EINVAL; |
| 1292 | } |
| 1293 | |
Linus Torvalds | 6be5ceb | 2012-04-20 17:13:58 -0700 | [diff] [blame] | 1294 | addr = vm_mmap(obj->filp, 0, args->size, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1295 | PROT_READ | PROT_WRITE, MAP_SHARED, |
| 1296 | args->offset); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 1297 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1298 | if (IS_ERR((void *)addr)) |
| 1299 | return addr; |
| 1300 | |
| 1301 | args->addr_ptr = (uint64_t) addr; |
| 1302 | |
| 1303 | return 0; |
| 1304 | } |
| 1305 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1306 | /** |
| 1307 | * i915_gem_fault - fault a page into the GTT |
| 1308 | * vma: VMA in question |
| 1309 | * vmf: fault info |
| 1310 | * |
| 1311 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped |
| 1312 | * from userspace. The fault handler takes care of binding the object to |
| 1313 | * the GTT (if needed), allocating and programming a fence register (again, |
| 1314 | * only if needed based on whether the old reg is still valid or the object |
| 1315 | * is tiled) and inserting a new PTE into the faulting process. |
| 1316 | * |
| 1317 | * Note that the faulting process may involve evicting existing objects |
| 1318 | * from the GTT and/or fence registers to make room. So performance may |
| 1319 | * suffer if the GTT working set is large or there are few fence registers |
| 1320 | * left. |
| 1321 | */ |
| 1322 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) |
| 1323 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1324 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
| 1325 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1326 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1327 | pgoff_t page_offset; |
| 1328 | unsigned long pfn; |
| 1329 | int ret = 0; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1330 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1331 | |
| 1332 | /* We don't use vmf->pgoff since that has the fake offset */ |
| 1333 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> |
| 1334 | PAGE_SHIFT; |
| 1335 | |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1336 | ret = i915_mutex_lock_interruptible(dev); |
| 1337 | if (ret) |
| 1338 | goto out; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1339 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1340 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
| 1341 | |
Chris Wilson | eb119bd | 2012-12-16 12:43:36 +0000 | [diff] [blame] | 1342 | /* Access to snoopable pages through the GTT is incoherent. */ |
| 1343 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { |
| 1344 | ret = -EINVAL; |
| 1345 | goto unlock; |
| 1346 | } |
| 1347 | |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1348 | /* Now bind it into the GTT if needed */ |
Chris Wilson | c983930 | 2012-11-20 10:45:17 +0000 | [diff] [blame] | 1349 | ret = i915_gem_object_pin(obj, 0, true, false); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 1350 | if (ret) |
| 1351 | goto unlock; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1352 | |
Chris Wilson | c983930 | 2012-11-20 10:45:17 +0000 | [diff] [blame] | 1353 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
| 1354 | if (ret) |
| 1355 | goto unpin; |
| 1356 | |
| 1357 | ret = i915_gem_object_get_fence(obj); |
| 1358 | if (ret) |
| 1359 | goto unpin; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1360 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1361 | obj->fault_mappable = true; |
| 1362 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 1363 | pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj); |
| 1364 | pfn >>= PAGE_SHIFT; |
| 1365 | pfn += page_offset; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1366 | |
| 1367 | /* Finally, remap it using the new GTT offset */ |
| 1368 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); |
Chris Wilson | c983930 | 2012-11-20 10:45:17 +0000 | [diff] [blame] | 1369 | unpin: |
| 1370 | i915_gem_object_unpin(obj); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1371 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1372 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1373 | out: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1374 | switch (ret) { |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1375 | case -EIO: |
Daniel Vetter | a9340cc | 2012-07-04 22:18:42 +0200 | [diff] [blame] | 1376 | /* If this -EIO is due to a gpu hang, give the reset code a |
| 1377 | * chance to clean up the mess. Otherwise return the proper |
| 1378 | * SIGBUS. */ |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1379 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
Daniel Vetter | a9340cc | 2012-07-04 22:18:42 +0200 | [diff] [blame] | 1380 | return VM_FAULT_SIGBUS; |
Chris Wilson | 045e769 | 2010-11-07 09:18:22 +0000 | [diff] [blame] | 1381 | case -EAGAIN: |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1382 | /* Give the error handler a chance to run and move the |
| 1383 | * objects off the GPU active list. Next time we service the |
| 1384 | * fault, we should be able to transition the page into the |
| 1385 | * GTT without touching the GPU (and so avoid further |
| 1386 | * EIO/EGAIN). If the GPU is wedged, then there is no issue |
| 1387 | * with coherency, just lost writes. |
| 1388 | */ |
Chris Wilson | 045e769 | 2010-11-07 09:18:22 +0000 | [diff] [blame] | 1389 | set_need_resched(); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1390 | case 0: |
| 1391 | case -ERESTARTSYS: |
Chris Wilson | bed636a | 2011-02-11 20:31:19 +0000 | [diff] [blame] | 1392 | case -EINTR: |
Dmitry Rogozhkin | e79e0fe | 2012-10-03 17:15:26 +0300 | [diff] [blame] | 1393 | case -EBUSY: |
| 1394 | /* |
| 1395 | * EBUSY is ok: this just means that another thread |
| 1396 | * already did the job. |
| 1397 | */ |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1398 | return VM_FAULT_NOPAGE; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1399 | case -ENOMEM: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1400 | return VM_FAULT_OOM; |
Daniel Vetter | a7c2e1a | 2012-10-17 11:17:16 +0200 | [diff] [blame] | 1401 | case -ENOSPC: |
| 1402 | return VM_FAULT_SIGBUS; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1403 | default: |
Daniel Vetter | a7c2e1a | 2012-10-17 11:17:16 +0200 | [diff] [blame] | 1404 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1405 | return VM_FAULT_SIGBUS; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1406 | } |
| 1407 | } |
| 1408 | |
| 1409 | /** |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1410 | * i915_gem_release_mmap - remove physical page mappings |
| 1411 | * @obj: obj in question |
| 1412 | * |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 1413 | * Preserve the reservation of the mmapping with the DRM core code, but |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1414 | * relinquish ownership of the pages back to the system. |
| 1415 | * |
| 1416 | * It is vital that we remove the page mapping if we have mapped a tiled |
| 1417 | * object through the GTT and then lose the fence register due to |
| 1418 | * resource pressure. Similarly if the object has been moved out of the |
| 1419 | * aperture, than pages mapped into userspace must be revoked. Removing the |
| 1420 | * mapping will then trigger a page fault on the next user access, allowing |
| 1421 | * fixup by i915_gem_fault(). |
| 1422 | */ |
Eric Anholt | d05ca30 | 2009-07-10 13:02:26 -0700 | [diff] [blame] | 1423 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1424 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1425 | { |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1426 | if (!obj->fault_mappable) |
| 1427 | return; |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1428 | |
Chris Wilson | f6e4788 | 2011-03-20 21:09:12 +0000 | [diff] [blame] | 1429 | if (obj->base.dev->dev_mapping) |
| 1430 | unmap_mapping_range(obj->base.dev->dev_mapping, |
| 1431 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, |
| 1432 | obj->base.size, 1); |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 1433 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1434 | obj->fault_mappable = false; |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1435 | } |
| 1436 | |
Imre Deak | 0fa8779 | 2013-01-07 21:47:35 +0200 | [diff] [blame] | 1437 | uint32_t |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1438 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1439 | { |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1440 | uint32_t gtt_size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1441 | |
| 1442 | if (INTEL_INFO(dev)->gen >= 4 || |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1443 | tiling_mode == I915_TILING_NONE) |
| 1444 | return size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1445 | |
| 1446 | /* Previous chips need a power-of-two fence region when tiling */ |
| 1447 | if (INTEL_INFO(dev)->gen == 3) |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1448 | gtt_size = 1024*1024; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1449 | else |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1450 | gtt_size = 512*1024; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1451 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1452 | while (gtt_size < size) |
| 1453 | gtt_size <<= 1; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1454 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1455 | return gtt_size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1456 | } |
| 1457 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1458 | /** |
| 1459 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
| 1460 | * @obj: object to check |
| 1461 | * |
| 1462 | * Return the required GTT alignment for an object, taking into account |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1463 | * potential fence register mapping. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1464 | */ |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 1465 | uint32_t |
| 1466 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
| 1467 | int tiling_mode, bool fenced) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1468 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1469 | /* |
| 1470 | * Minimum alignment is 4k (GTT page size), but might be greater |
| 1471 | * if a fence register is needed for the object. |
| 1472 | */ |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 1473 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1474 | tiling_mode == I915_TILING_NONE) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1475 | return 4096; |
| 1476 | |
| 1477 | /* |
| 1478 | * Previous chips need to be aligned to the size of the smallest |
| 1479 | * fence register that can contain the object. |
| 1480 | */ |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1481 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1482 | } |
| 1483 | |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1484 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
| 1485 | { |
| 1486 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 1487 | int ret; |
| 1488 | |
| 1489 | if (obj->base.map_list.map) |
| 1490 | return 0; |
| 1491 | |
Daniel Vetter | da494d7 | 2012-12-20 15:11:16 +0100 | [diff] [blame] | 1492 | dev_priv->mm.shrinker_no_lock_stealing = true; |
| 1493 | |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1494 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 1495 | if (ret != -ENOSPC) |
Daniel Vetter | da494d7 | 2012-12-20 15:11:16 +0100 | [diff] [blame] | 1496 | goto out; |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1497 | |
| 1498 | /* Badly fragmented mmap space? The only way we can recover |
| 1499 | * space is by destroying unwanted objects. We can't randomly release |
| 1500 | * mmap_offsets as userspace expects them to be persistent for the |
| 1501 | * lifetime of the objects. The closest we can is to release the |
| 1502 | * offsets on purgeable objects by truncating it and marking it purged, |
| 1503 | * which prevents userspace from ever using that object again. |
| 1504 | */ |
| 1505 | i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT); |
| 1506 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 1507 | if (ret != -ENOSPC) |
Daniel Vetter | da494d7 | 2012-12-20 15:11:16 +0100 | [diff] [blame] | 1508 | goto out; |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1509 | |
| 1510 | i915_gem_shrink_all(dev_priv); |
Daniel Vetter | da494d7 | 2012-12-20 15:11:16 +0100 | [diff] [blame] | 1511 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 1512 | out: |
| 1513 | dev_priv->mm.shrinker_no_lock_stealing = false; |
| 1514 | |
| 1515 | return ret; |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1516 | } |
| 1517 | |
| 1518 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) |
| 1519 | { |
| 1520 | if (!obj->base.map_list.map) |
| 1521 | return; |
| 1522 | |
| 1523 | drm_gem_free_mmap_offset(&obj->base); |
| 1524 | } |
| 1525 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1526 | int |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1527 | i915_gem_mmap_gtt(struct drm_file *file, |
| 1528 | struct drm_device *dev, |
| 1529 | uint32_t handle, |
| 1530 | uint64_t *offset) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1531 | { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1532 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1533 | struct drm_i915_gem_object *obj; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1534 | int ret; |
| 1535 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1536 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1537 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1538 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1539 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1540 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1541 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1542 | ret = -ENOENT; |
| 1543 | goto unlock; |
| 1544 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1545 | |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 1546 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1547 | ret = -E2BIG; |
Eric Anholt | ff56b0b | 2011-10-31 23:16:21 -0700 | [diff] [blame] | 1548 | goto out; |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1549 | } |
| 1550 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1551 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1552 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1553 | ret = -EINVAL; |
| 1554 | goto out; |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1555 | } |
| 1556 | |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1557 | ret = i915_gem_object_create_mmap_offset(obj); |
| 1558 | if (ret) |
| 1559 | goto out; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1560 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1561 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1562 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1563 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1564 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1565 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1566 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1567 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1568 | } |
| 1569 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1570 | /** |
| 1571 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
| 1572 | * @dev: DRM device |
| 1573 | * @data: GTT mapping ioctl data |
| 1574 | * @file: GEM object info |
| 1575 | * |
| 1576 | * Simply returns the fake offset to userspace so it can mmap it. |
| 1577 | * The mmap call will end up in drm_gem_mmap(), which will set things |
| 1578 | * up so we can get faults in the handler above. |
| 1579 | * |
| 1580 | * The fault handler will take care of binding the object into the GTT |
| 1581 | * (since it may have been evicted to make room for something), allocating |
| 1582 | * a fence register, and mapping the appropriate aperture address into |
| 1583 | * userspace. |
| 1584 | */ |
| 1585 | int |
| 1586 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 1587 | struct drm_file *file) |
| 1588 | { |
| 1589 | struct drm_i915_gem_mmap_gtt *args = data; |
| 1590 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1591 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
| 1592 | } |
| 1593 | |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1594 | /* Immediately discard the backing storage */ |
| 1595 | static void |
| 1596 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1597 | { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1598 | struct inode *inode; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1599 | |
Chris Wilson | 4d6294bf | 2012-08-11 15:41:05 +0100 | [diff] [blame] | 1600 | i915_gem_object_free_mmap_offset(obj); |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1601 | |
Chris Wilson | 4d6294bf | 2012-08-11 15:41:05 +0100 | [diff] [blame] | 1602 | if (obj->base.filp == NULL) |
| 1603 | return; |
| 1604 | |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1605 | /* Our goal here is to return as much of the memory as |
| 1606 | * is possible back to the system as we are called from OOM. |
| 1607 | * To do this we must instruct the shmfs to drop all of its |
| 1608 | * backing pages, *now*. |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1609 | */ |
Al Viro | 496ad9a | 2013-01-23 17:07:38 -0500 | [diff] [blame] | 1610 | inode = file_inode(obj->base.filp); |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1611 | shmem_truncate_range(inode, 0, (loff_t)-1); |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 1612 | |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1613 | obj->madv = __I915_MADV_PURGED; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1614 | } |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1615 | |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1616 | static inline int |
| 1617 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
| 1618 | { |
| 1619 | return obj->madv == I915_MADV_DONTNEED; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1620 | } |
| 1621 | |
Chris Wilson | 5cdf588 | 2010-09-27 15:51:07 +0100 | [diff] [blame] | 1622 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1623 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1624 | { |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 1625 | struct sg_page_iter sg_iter; |
| 1626 | int ret; |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1627 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1628 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1629 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1630 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
| 1631 | if (ret) { |
| 1632 | /* In the event of a disaster, abandon all caches and |
| 1633 | * hope for the best. |
| 1634 | */ |
| 1635 | WARN_ON(ret != -EIO); |
| 1636 | i915_gem_clflush_object(obj); |
| 1637 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 1638 | } |
| 1639 | |
Daniel Vetter | 6dacfd2 | 2011-09-12 21:30:02 +0200 | [diff] [blame] | 1640 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1641 | i915_gem_object_save_bit_17_swizzle(obj); |
| 1642 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1643 | if (obj->madv == I915_MADV_DONTNEED) |
| 1644 | obj->dirty = 0; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1645 | |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 1646 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 1647 | struct page *page = sg_page_iter_page(&sg_iter); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1648 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1649 | if (obj->dirty) |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1650 | set_page_dirty(page); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1651 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1652 | if (obj->madv == I915_MADV_WILLNEED) |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1653 | mark_page_accessed(page); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1654 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1655 | page_cache_release(page); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1656 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1657 | obj->dirty = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1658 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1659 | sg_free_table(obj->pages); |
| 1660 | kfree(obj->pages); |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1661 | } |
| 1662 | |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1663 | int |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1664 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
| 1665 | { |
| 1666 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
| 1667 | |
Chris Wilson | 2f745ad | 2012-09-04 21:02:58 +0100 | [diff] [blame] | 1668 | if (obj->pages == NULL) |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1669 | return 0; |
| 1670 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 1671 | BUG_ON(i915_gem_obj_ggtt_bound(obj)); |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1672 | |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 1673 | if (obj->pages_pin_count) |
| 1674 | return -EBUSY; |
| 1675 | |
Chris Wilson | a2165e3 | 2012-12-03 11:49:00 +0000 | [diff] [blame] | 1676 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
| 1677 | * array, hence protect them from being reaped by removing them from gtt |
| 1678 | * lists early. */ |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 1679 | list_del(&obj->global_list); |
Chris Wilson | a2165e3 | 2012-12-03 11:49:00 +0000 | [diff] [blame] | 1680 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1681 | ops->put_pages(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1682 | obj->pages = NULL; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1683 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1684 | if (i915_gem_object_is_purgeable(obj)) |
| 1685 | i915_gem_object_truncate(obj); |
| 1686 | |
| 1687 | return 0; |
| 1688 | } |
| 1689 | |
| 1690 | static long |
Daniel Vetter | 93927ca | 2013-01-10 18:03:00 +0100 | [diff] [blame] | 1691 | __i915_gem_shrink(struct drm_i915_private *dev_priv, long target, |
| 1692 | bool purgeable_only) |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1693 | { |
| 1694 | struct drm_i915_gem_object *obj, *next; |
| 1695 | long count = 0; |
| 1696 | |
| 1697 | list_for_each_entry_safe(obj, next, |
| 1698 | &dev_priv->mm.unbound_list, |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 1699 | global_list) { |
Daniel Vetter | 93927ca | 2013-01-10 18:03:00 +0100 | [diff] [blame] | 1700 | if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) && |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1701 | i915_gem_object_put_pages(obj) == 0) { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1702 | count += obj->base.size >> PAGE_SHIFT; |
| 1703 | if (count >= target) |
| 1704 | return count; |
| 1705 | } |
| 1706 | } |
| 1707 | |
| 1708 | list_for_each_entry_safe(obj, next, |
| 1709 | &dev_priv->mm.inactive_list, |
| 1710 | mm_list) { |
Daniel Vetter | 93927ca | 2013-01-10 18:03:00 +0100 | [diff] [blame] | 1711 | if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) && |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1712 | i915_gem_object_unbind(obj) == 0 && |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1713 | i915_gem_object_put_pages(obj) == 0) { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1714 | count += obj->base.size >> PAGE_SHIFT; |
| 1715 | if (count >= target) |
| 1716 | return count; |
| 1717 | } |
| 1718 | } |
| 1719 | |
| 1720 | return count; |
| 1721 | } |
| 1722 | |
Daniel Vetter | 93927ca | 2013-01-10 18:03:00 +0100 | [diff] [blame] | 1723 | static long |
| 1724 | i915_gem_purge(struct drm_i915_private *dev_priv, long target) |
| 1725 | { |
| 1726 | return __i915_gem_shrink(dev_priv, target, true); |
| 1727 | } |
| 1728 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1729 | static void |
| 1730 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) |
| 1731 | { |
| 1732 | struct drm_i915_gem_object *obj, *next; |
| 1733 | |
| 1734 | i915_gem_evict_everything(dev_priv->dev); |
| 1735 | |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 1736 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
| 1737 | global_list) |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1738 | i915_gem_object_put_pages(obj); |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1739 | } |
| 1740 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1741 | static int |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1742 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1743 | { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1744 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1745 | int page_count, i; |
| 1746 | struct address_space *mapping; |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1747 | struct sg_table *st; |
| 1748 | struct scatterlist *sg; |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 1749 | struct sg_page_iter sg_iter; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1750 | struct page *page; |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 1751 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1752 | gfp_t gfp; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1753 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1754 | /* Assert that the object is not currently in any GPU domain. As it |
| 1755 | * wasn't in the GTT, there shouldn't be any way it could have been in |
| 1756 | * a GPU cache |
| 1757 | */ |
| 1758 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
| 1759 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); |
| 1760 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1761 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
| 1762 | if (st == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1763 | return -ENOMEM; |
| 1764 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1765 | page_count = obj->base.size / PAGE_SIZE; |
| 1766 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
| 1767 | sg_free_table(st); |
| 1768 | kfree(st); |
| 1769 | return -ENOMEM; |
| 1770 | } |
| 1771 | |
| 1772 | /* Get the list of pages out of our struct file. They'll be pinned |
| 1773 | * at this point until we release them. |
| 1774 | * |
| 1775 | * Fail silently without starting the shrinker |
| 1776 | */ |
Al Viro | 496ad9a | 2013-01-23 17:07:38 -0500 | [diff] [blame] | 1777 | mapping = file_inode(obj->base.filp)->i_mapping; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1778 | gfp = mapping_gfp_mask(mapping); |
Linus Torvalds | caf4919 | 2012-12-10 10:51:16 -0800 | [diff] [blame] | 1779 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1780 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 1781 | sg = st->sgl; |
| 1782 | st->nents = 0; |
| 1783 | for (i = 0; i < page_count; i++) { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1784 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
| 1785 | if (IS_ERR(page)) { |
| 1786 | i915_gem_purge(dev_priv, page_count); |
| 1787 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
| 1788 | } |
| 1789 | if (IS_ERR(page)) { |
| 1790 | /* We've tried hard to allocate the memory by reaping |
| 1791 | * our own buffer, now let the real VM do its job and |
| 1792 | * go down in flames if truly OOM. |
| 1793 | */ |
Linus Torvalds | caf4919 | 2012-12-10 10:51:16 -0800 | [diff] [blame] | 1794 | gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1795 | gfp |= __GFP_IO | __GFP_WAIT; |
| 1796 | |
| 1797 | i915_gem_shrink_all(dev_priv); |
| 1798 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
| 1799 | if (IS_ERR(page)) |
| 1800 | goto err_pages; |
| 1801 | |
Linus Torvalds | caf4919 | 2012-12-10 10:51:16 -0800 | [diff] [blame] | 1802 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1803 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
| 1804 | } |
Konrad Rzeszutek Wilk | 1625e7e | 2013-06-24 11:47:48 -0400 | [diff] [blame] | 1805 | #ifdef CONFIG_SWIOTLB |
| 1806 | if (swiotlb_nr_tbl()) { |
| 1807 | st->nents++; |
| 1808 | sg_set_page(sg, page, PAGE_SIZE, 0); |
| 1809 | sg = sg_next(sg); |
| 1810 | continue; |
| 1811 | } |
| 1812 | #endif |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 1813 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
| 1814 | if (i) |
| 1815 | sg = sg_next(sg); |
| 1816 | st->nents++; |
| 1817 | sg_set_page(sg, page, PAGE_SIZE, 0); |
| 1818 | } else { |
| 1819 | sg->length += PAGE_SIZE; |
| 1820 | } |
| 1821 | last_pfn = page_to_pfn(page); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1822 | } |
Konrad Rzeszutek Wilk | 1625e7e | 2013-06-24 11:47:48 -0400 | [diff] [blame] | 1823 | #ifdef CONFIG_SWIOTLB |
| 1824 | if (!swiotlb_nr_tbl()) |
| 1825 | #endif |
| 1826 | sg_mark_end(sg); |
Chris Wilson | 74ce6b6 | 2012-10-19 15:51:06 +0100 | [diff] [blame] | 1827 | obj->pages = st; |
| 1828 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1829 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
| 1830 | i915_gem_object_do_bit_17_swizzle(obj); |
| 1831 | |
| 1832 | return 0; |
| 1833 | |
| 1834 | err_pages: |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 1835 | sg_mark_end(sg); |
| 1836 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 1837 | page_cache_release(sg_page_iter_page(&sg_iter)); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1838 | sg_free_table(st); |
| 1839 | kfree(st); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1840 | return PTR_ERR(page); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1841 | } |
| 1842 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1843 | /* Ensure that the associated pages are gathered from the backing storage |
| 1844 | * and pinned into our object. i915_gem_object_get_pages() may be called |
| 1845 | * multiple times before they are released by a single call to |
| 1846 | * i915_gem_object_put_pages() - once the pages are no longer referenced |
| 1847 | * either as a result of memory pressure (reaping pages under the shrinker) |
| 1848 | * or as the object is itself released. |
| 1849 | */ |
| 1850 | int |
| 1851 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) |
| 1852 | { |
| 1853 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 1854 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
| 1855 | int ret; |
| 1856 | |
Chris Wilson | 2f745ad | 2012-09-04 21:02:58 +0100 | [diff] [blame] | 1857 | if (obj->pages) |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1858 | return 0; |
| 1859 | |
Chris Wilson | 43e28f0 | 2013-01-08 10:53:09 +0000 | [diff] [blame] | 1860 | if (obj->madv != I915_MADV_WILLNEED) { |
| 1861 | DRM_ERROR("Attempting to obtain a purgeable object\n"); |
| 1862 | return -EINVAL; |
| 1863 | } |
| 1864 | |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 1865 | BUG_ON(obj->pages_pin_count); |
| 1866 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1867 | ret = ops->get_pages(obj); |
| 1868 | if (ret) |
| 1869 | return ret; |
| 1870 | |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 1871 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1872 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1873 | } |
| 1874 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1875 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1876 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1877 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1878 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1879 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1880 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1881 | u32 seqno = intel_ring_get_seqno(ring); |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 1882 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1883 | BUG_ON(ring == NULL); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1884 | obj->ring = ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1885 | |
| 1886 | /* Add a reference if we're newly entering the active list. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1887 | if (!obj->active) { |
| 1888 | drm_gem_object_reference(&obj->base); |
| 1889 | obj->active = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1890 | } |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 1891 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1892 | /* Move from whatever list we were on to the tail of execution. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1893 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
| 1894 | list_move_tail(&obj->ring_list, &ring->active_list); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1895 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 1896 | obj->last_read_seqno = seqno; |
Chris Wilson | 7dd4906 | 2012-03-21 10:48:18 +0000 | [diff] [blame] | 1897 | |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1898 | if (obj->fenced_gpu_access) { |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1899 | obj->last_fenced_seqno = seqno; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1900 | |
Chris Wilson | 7dd4906 | 2012-03-21 10:48:18 +0000 | [diff] [blame] | 1901 | /* Bump MRU to take account of the delayed flush */ |
| 1902 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 1903 | struct drm_i915_fence_reg *reg; |
| 1904 | |
| 1905 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
| 1906 | list_move_tail(®->lru_list, |
| 1907 | &dev_priv->mm.fence_list); |
| 1908 | } |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1909 | } |
| 1910 | } |
| 1911 | |
| 1912 | static void |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1913 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
| 1914 | { |
| 1915 | struct drm_device *dev = obj->base.dev; |
| 1916 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1917 | |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 1918 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1919 | BUG_ON(!obj->active); |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 1920 | |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1921 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
| 1922 | |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 1923 | list_del_init(&obj->ring_list); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1924 | obj->ring = NULL; |
| 1925 | |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 1926 | obj->last_read_seqno = 0; |
| 1927 | obj->last_write_seqno = 0; |
| 1928 | obj->base.write_domain = 0; |
| 1929 | |
| 1930 | obj->last_fenced_seqno = 0; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1931 | obj->fenced_gpu_access = false; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1932 | |
| 1933 | obj->active = 0; |
| 1934 | drm_gem_object_unreference(&obj->base); |
| 1935 | |
| 1936 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1937 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1938 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1939 | static int |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 1940 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 1941 | { |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1942 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1943 | struct intel_ring_buffer *ring; |
| 1944 | int ret, i, j; |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 1945 | |
Chris Wilson | 107f27a5 | 2012-12-10 13:56:17 +0200 | [diff] [blame] | 1946 | /* Carefully retire all requests without writing to the rings */ |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1947 | for_each_ring(ring, dev_priv, i) { |
Chris Wilson | 107f27a5 | 2012-12-10 13:56:17 +0200 | [diff] [blame] | 1948 | ret = intel_ring_idle(ring); |
| 1949 | if (ret) |
| 1950 | return ret; |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1951 | } |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1952 | i915_gem_retire_requests(dev); |
Chris Wilson | 107f27a5 | 2012-12-10 13:56:17 +0200 | [diff] [blame] | 1953 | |
| 1954 | /* Finally reset hw state */ |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1955 | for_each_ring(ring, dev_priv, i) { |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 1956 | intel_ring_init_seqno(ring, seqno); |
Mika Kuoppala | 498d2ac | 2012-12-04 15:12:04 +0200 | [diff] [blame] | 1957 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1958 | for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++) |
| 1959 | ring->sync_seqno[j] = 0; |
| 1960 | } |
| 1961 | |
| 1962 | return 0; |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 1963 | } |
| 1964 | |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 1965 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
| 1966 | { |
| 1967 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1968 | int ret; |
| 1969 | |
| 1970 | if (seqno == 0) |
| 1971 | return -EINVAL; |
| 1972 | |
| 1973 | /* HWS page needs to be set less than what we |
| 1974 | * will inject to ring |
| 1975 | */ |
| 1976 | ret = i915_gem_init_seqno(dev, seqno - 1); |
| 1977 | if (ret) |
| 1978 | return ret; |
| 1979 | |
| 1980 | /* Carefully set the last_seqno value so that wrap |
| 1981 | * detection still works |
| 1982 | */ |
| 1983 | dev_priv->next_seqno = seqno; |
| 1984 | dev_priv->last_seqno = seqno - 1; |
| 1985 | if (dev_priv->last_seqno == 0) |
| 1986 | dev_priv->last_seqno--; |
| 1987 | |
| 1988 | return 0; |
| 1989 | } |
| 1990 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1991 | int |
| 1992 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 1993 | { |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1994 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 1995 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1996 | /* reserve 0 for non-seqno */ |
| 1997 | if (dev_priv->next_seqno == 0) { |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 1998 | int ret = i915_gem_init_seqno(dev, 0); |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1999 | if (ret) |
| 2000 | return ret; |
| 2001 | |
| 2002 | dev_priv->next_seqno = 1; |
| 2003 | } |
| 2004 | |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 2005 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2006 | return 0; |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2007 | } |
| 2008 | |
Mika Kuoppala | 0025c07 | 2013-06-12 12:35:30 +0300 | [diff] [blame] | 2009 | int __i915_add_request(struct intel_ring_buffer *ring, |
| 2010 | struct drm_file *file, |
Mika Kuoppala | 7d736f4 | 2013-06-12 15:01:39 +0300 | [diff] [blame] | 2011 | struct drm_i915_gem_object *obj, |
Mika Kuoppala | 0025c07 | 2013-06-12 12:35:30 +0300 | [diff] [blame] | 2012 | u32 *out_seqno) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2013 | { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2014 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Chris Wilson | acb868d | 2012-09-26 13:47:30 +0100 | [diff] [blame] | 2015 | struct drm_i915_gem_request *request; |
Mika Kuoppala | 7d736f4 | 2013-06-12 15:01:39 +0300 | [diff] [blame] | 2016 | u32 request_ring_position, request_start; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2017 | int was_empty; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 2018 | int ret; |
| 2019 | |
Mika Kuoppala | 7d736f4 | 2013-06-12 15:01:39 +0300 | [diff] [blame] | 2020 | request_start = intel_ring_get_tail(ring); |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 2021 | /* |
| 2022 | * Emit any outstanding flushes - execbuf can fail to emit the flush |
| 2023 | * after having emitted the batchbuffer command. Hence we need to fix |
| 2024 | * things up similar to emitting the lazy request. The difference here |
| 2025 | * is that the flush _must_ happen before the next request, no matter |
| 2026 | * what. |
| 2027 | */ |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 2028 | ret = intel_ring_flush_all_caches(ring); |
| 2029 | if (ret) |
| 2030 | return ret; |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 2031 | |
Chris Wilson | acb868d | 2012-09-26 13:47:30 +0100 | [diff] [blame] | 2032 | request = kmalloc(sizeof(*request), GFP_KERNEL); |
| 2033 | if (request == NULL) |
| 2034 | return -ENOMEM; |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 2035 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2036 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2037 | /* Record the position of the start of the request so that |
| 2038 | * should we detect the updated seqno part-way through the |
| 2039 | * GPU processing the request, we never over-estimate the |
| 2040 | * position of the head. |
| 2041 | */ |
| 2042 | request_ring_position = intel_ring_get_tail(ring); |
| 2043 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2044 | ret = ring->add_request(ring); |
Chris Wilson | 3bb73ab | 2012-07-20 12:40:59 +0100 | [diff] [blame] | 2045 | if (ret) { |
| 2046 | kfree(request); |
| 2047 | return ret; |
| 2048 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2049 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2050 | request->seqno = intel_ring_get_seqno(ring); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2051 | request->ring = ring; |
Mika Kuoppala | 7d736f4 | 2013-06-12 15:01:39 +0300 | [diff] [blame] | 2052 | request->head = request_start; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2053 | request->tail = request_ring_position; |
Mika Kuoppala | 0e50e96 | 2013-05-02 16:48:08 +0300 | [diff] [blame] | 2054 | request->ctx = ring->last_context; |
Mika Kuoppala | 7d736f4 | 2013-06-12 15:01:39 +0300 | [diff] [blame] | 2055 | request->batch_obj = obj; |
| 2056 | |
| 2057 | /* Whilst this request exists, batch_obj will be on the |
| 2058 | * active_list, and so will hold the active reference. Only when this |
| 2059 | * request is retired will the the batch_obj be moved onto the |
| 2060 | * inactive_list and lose its active reference. Hence we do not need |
| 2061 | * to explicitly hold another reference here. |
| 2062 | */ |
Mika Kuoppala | 0e50e96 | 2013-05-02 16:48:08 +0300 | [diff] [blame] | 2063 | |
| 2064 | if (request->ctx) |
| 2065 | i915_gem_context_reference(request->ctx); |
| 2066 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2067 | request->emitted_jiffies = jiffies; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2068 | was_empty = list_empty(&ring->request_list); |
| 2069 | list_add_tail(&request->list, &ring->request_list); |
Chris Wilson | 3bb73ab | 2012-07-20 12:40:59 +0100 | [diff] [blame] | 2070 | request->file_priv = NULL; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2071 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2072 | if (file) { |
| 2073 | struct drm_i915_file_private *file_priv = file->driver_priv; |
| 2074 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2075 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2076 | request->file_priv = file_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 2077 | list_add_tail(&request->client_list, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2078 | &file_priv->mm.request_list); |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2079 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 2080 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2081 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2082 | trace_i915_gem_request_add(ring, request->seqno); |
Daniel Vetter | 5391d0c | 2012-01-25 14:03:57 +0100 | [diff] [blame] | 2083 | ring->outstanding_lazy_request = 0; |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2084 | |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 2085 | if (!dev_priv->ums.mm_suspended) { |
Mika Kuoppala | 10cd45b | 2013-07-03 17:22:08 +0300 | [diff] [blame^] | 2086 | i915_queue_hangcheck(ring->dev); |
| 2087 | |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 2088 | if (was_empty) { |
Chris Wilson | b3b079d | 2010-09-13 23:44:34 +0100 | [diff] [blame] | 2089 | queue_delayed_work(dev_priv->wq, |
Chris Wilson | bcb4508 | 2012-10-05 17:02:57 +0100 | [diff] [blame] | 2090 | &dev_priv->mm.retire_work, |
| 2091 | round_jiffies_up_relative(HZ)); |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 2092 | intel_mark_busy(dev_priv->dev); |
| 2093 | } |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 2094 | } |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 2095 | |
Chris Wilson | acb868d | 2012-09-26 13:47:30 +0100 | [diff] [blame] | 2096 | if (out_seqno) |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2097 | *out_seqno = request->seqno; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 2098 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2099 | } |
| 2100 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2101 | static inline void |
| 2102 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2103 | { |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2104 | struct drm_i915_file_private *file_priv = request->file_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2105 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2106 | if (!file_priv) |
| 2107 | return; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2108 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2109 | spin_lock(&file_priv->mm.lock); |
Herton Ronaldo Krzesinski | 09bfa51 | 2011-03-17 13:45:12 +0000 | [diff] [blame] | 2110 | if (request->file_priv) { |
| 2111 | list_del(&request->client_list); |
| 2112 | request->file_priv = NULL; |
| 2113 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2114 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2115 | } |
| 2116 | |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2117 | static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj) |
| 2118 | { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2119 | if (acthd >= i915_gem_obj_ggtt_offset(obj) && |
| 2120 | acthd < i915_gem_obj_ggtt_offset(obj) + obj->base.size) |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2121 | return true; |
| 2122 | |
| 2123 | return false; |
| 2124 | } |
| 2125 | |
| 2126 | static bool i915_head_inside_request(const u32 acthd_unmasked, |
| 2127 | const u32 request_start, |
| 2128 | const u32 request_end) |
| 2129 | { |
| 2130 | const u32 acthd = acthd_unmasked & HEAD_ADDR; |
| 2131 | |
| 2132 | if (request_start < request_end) { |
| 2133 | if (acthd >= request_start && acthd < request_end) |
| 2134 | return true; |
| 2135 | } else if (request_start > request_end) { |
| 2136 | if (acthd >= request_start || acthd < request_end) |
| 2137 | return true; |
| 2138 | } |
| 2139 | |
| 2140 | return false; |
| 2141 | } |
| 2142 | |
| 2143 | static bool i915_request_guilty(struct drm_i915_gem_request *request, |
| 2144 | const u32 acthd, bool *inside) |
| 2145 | { |
| 2146 | /* There is a possibility that unmasked head address |
| 2147 | * pointing inside the ring, matches the batch_obj address range. |
| 2148 | * However this is extremely unlikely. |
| 2149 | */ |
| 2150 | |
| 2151 | if (request->batch_obj) { |
| 2152 | if (i915_head_inside_object(acthd, request->batch_obj)) { |
| 2153 | *inside = true; |
| 2154 | return true; |
| 2155 | } |
| 2156 | } |
| 2157 | |
| 2158 | if (i915_head_inside_request(acthd, request->head, request->tail)) { |
| 2159 | *inside = false; |
| 2160 | return true; |
| 2161 | } |
| 2162 | |
| 2163 | return false; |
| 2164 | } |
| 2165 | |
| 2166 | static void i915_set_reset_status(struct intel_ring_buffer *ring, |
| 2167 | struct drm_i915_gem_request *request, |
| 2168 | u32 acthd) |
| 2169 | { |
| 2170 | struct i915_ctx_hang_stats *hs = NULL; |
| 2171 | bool inside, guilty; |
| 2172 | |
| 2173 | /* Innocent until proven guilty */ |
| 2174 | guilty = false; |
| 2175 | |
| 2176 | if (ring->hangcheck.action != wait && |
| 2177 | i915_request_guilty(request, acthd, &inside)) { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2178 | DRM_ERROR("%s hung %s bo (0x%lx ctx %d) at 0x%x\n", |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2179 | ring->name, |
| 2180 | inside ? "inside" : "flushing", |
| 2181 | request->batch_obj ? |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2182 | i915_gem_obj_ggtt_offset(request->batch_obj) : 0, |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2183 | request->ctx ? request->ctx->id : 0, |
| 2184 | acthd); |
| 2185 | |
| 2186 | guilty = true; |
| 2187 | } |
| 2188 | |
| 2189 | /* If contexts are disabled or this is the default context, use |
| 2190 | * file_priv->reset_state |
| 2191 | */ |
| 2192 | if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID) |
| 2193 | hs = &request->ctx->hang_stats; |
| 2194 | else if (request->file_priv) |
| 2195 | hs = &request->file_priv->hang_stats; |
| 2196 | |
| 2197 | if (hs) { |
| 2198 | if (guilty) |
| 2199 | hs->batch_active++; |
| 2200 | else |
| 2201 | hs->batch_pending++; |
| 2202 | } |
| 2203 | } |
| 2204 | |
Mika Kuoppala | 0e50e96 | 2013-05-02 16:48:08 +0300 | [diff] [blame] | 2205 | static void i915_gem_free_request(struct drm_i915_gem_request *request) |
| 2206 | { |
| 2207 | list_del(&request->list); |
| 2208 | i915_gem_request_remove_from_client(request); |
| 2209 | |
| 2210 | if (request->ctx) |
| 2211 | i915_gem_context_unreference(request->ctx); |
| 2212 | |
| 2213 | kfree(request); |
| 2214 | } |
| 2215 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2216 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
| 2217 | struct intel_ring_buffer *ring) |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 2218 | { |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2219 | u32 completed_seqno; |
| 2220 | u32 acthd; |
| 2221 | |
| 2222 | acthd = intel_ring_get_active_head(ring); |
| 2223 | completed_seqno = ring->get_seqno(ring, false); |
| 2224 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2225 | while (!list_empty(&ring->request_list)) { |
| 2226 | struct drm_i915_gem_request *request; |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 2227 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2228 | request = list_first_entry(&ring->request_list, |
| 2229 | struct drm_i915_gem_request, |
| 2230 | list); |
| 2231 | |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2232 | if (request->seqno > completed_seqno) |
| 2233 | i915_set_reset_status(ring, request, acthd); |
| 2234 | |
Mika Kuoppala | 0e50e96 | 2013-05-02 16:48:08 +0300 | [diff] [blame] | 2235 | i915_gem_free_request(request); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2236 | } |
| 2237 | |
| 2238 | while (!list_empty(&ring->active_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2239 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2240 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2241 | obj = list_first_entry(&ring->active_list, |
| 2242 | struct drm_i915_gem_object, |
| 2243 | ring_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2244 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2245 | i915_gem_object_move_to_inactive(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2246 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2247 | } |
| 2248 | |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 2249 | static void i915_gem_reset_fences(struct drm_device *dev) |
| 2250 | { |
| 2251 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2252 | int i; |
| 2253 | |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 2254 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 2255 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
Chris Wilson | 7d2cb39 | 2010-11-27 17:38:29 +0000 | [diff] [blame] | 2256 | |
Chris Wilson | ada726c | 2012-04-17 15:31:32 +0100 | [diff] [blame] | 2257 | if (reg->obj) |
| 2258 | i915_gem_object_fence_lost(reg->obj); |
Chris Wilson | 7d2cb39 | 2010-11-27 17:38:29 +0000 | [diff] [blame] | 2259 | |
Chris Wilson | f9c513e | 2013-03-26 11:29:27 +0000 | [diff] [blame] | 2260 | i915_gem_write_fence(dev, i, NULL); |
| 2261 | |
Chris Wilson | ada726c | 2012-04-17 15:31:32 +0100 | [diff] [blame] | 2262 | reg->pin_count = 0; |
| 2263 | reg->obj = NULL; |
| 2264 | INIT_LIST_HEAD(®->lru_list); |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 2265 | } |
Chris Wilson | ada726c | 2012-04-17 15:31:32 +0100 | [diff] [blame] | 2266 | |
| 2267 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 2268 | } |
| 2269 | |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 2270 | void i915_gem_reset(struct drm_device *dev) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2271 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2272 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2273 | struct drm_i915_gem_object *obj; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2274 | struct intel_ring_buffer *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2275 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2276 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2277 | for_each_ring(ring, dev_priv, i) |
| 2278 | i915_gem_reset_ring_lists(dev_priv, ring); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2279 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2280 | /* Move everything out of the GPU domains to ensure we do any |
| 2281 | * necessary invalidation upon reuse. |
| 2282 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2283 | list_for_each_entry(obj, |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 2284 | &dev_priv->mm.inactive_list, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 2285 | mm_list) |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 2286 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2287 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 2288 | } |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 2289 | |
| 2290 | /* The fence registers are invalidated so clear them out */ |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 2291 | i915_gem_reset_fences(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2292 | } |
| 2293 | |
| 2294 | /** |
| 2295 | * This function clears the request list as sequence numbers are passed. |
| 2296 | */ |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2297 | void |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2298 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2299 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2300 | uint32_t seqno; |
| 2301 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2302 | if (list_empty(&ring->request_list)) |
Karsten Wiese | 6c0594a | 2009-02-23 15:07:57 +0100 | [diff] [blame] | 2303 | return; |
| 2304 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2305 | WARN_ON(i915_verify_lists(ring->dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2306 | |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 2307 | seqno = ring->get_seqno(ring, true); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2308 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2309 | while (!list_empty(&ring->request_list)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2310 | struct drm_i915_gem_request *request; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2311 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2312 | request = list_first_entry(&ring->request_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2313 | struct drm_i915_gem_request, |
| 2314 | list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2315 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2316 | if (!i915_seqno_passed(seqno, request->seqno)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2317 | break; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2318 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2319 | trace_i915_gem_request_retire(ring, request->seqno); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2320 | /* We know the GPU must have read the request to have |
| 2321 | * sent us the seqno + interrupt, so use the position |
| 2322 | * of tail of the request to update the last known position |
| 2323 | * of the GPU head. |
| 2324 | */ |
| 2325 | ring->last_retired_head = request->tail; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2326 | |
Mika Kuoppala | 0e50e96 | 2013-05-02 16:48:08 +0300 | [diff] [blame] | 2327 | i915_gem_free_request(request); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2328 | } |
| 2329 | |
| 2330 | /* Move any buffers on the active list that are no longer referenced |
| 2331 | * by the ringbuffer to the flushing/inactive lists as appropriate. |
| 2332 | */ |
| 2333 | while (!list_empty(&ring->active_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2334 | struct drm_i915_gem_object *obj; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2335 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2336 | obj = list_first_entry(&ring->active_list, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2337 | struct drm_i915_gem_object, |
| 2338 | ring_list); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2339 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 2340 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2341 | break; |
| 2342 | |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 2343 | i915_gem_object_move_to_inactive(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2344 | } |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 2345 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2346 | if (unlikely(ring->trace_irq_seqno && |
| 2347 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2348 | ring->irq_put(ring); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2349 | ring->trace_irq_seqno = 0; |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 2350 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 2351 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2352 | WARN_ON(i915_verify_lists(ring->dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2353 | } |
| 2354 | |
| 2355 | void |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2356 | i915_gem_retire_requests(struct drm_device *dev) |
| 2357 | { |
| 2358 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2359 | struct intel_ring_buffer *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2360 | int i; |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2361 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2362 | for_each_ring(ring, dev_priv, i) |
| 2363 | i915_gem_retire_requests_ring(ring); |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2364 | } |
| 2365 | |
Daniel Vetter | 75ef9da | 2010-08-21 00:25:16 +0200 | [diff] [blame] | 2366 | static void |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2367 | i915_gem_retire_work_handler(struct work_struct *work) |
| 2368 | { |
| 2369 | drm_i915_private_t *dev_priv; |
| 2370 | struct drm_device *dev; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2371 | struct intel_ring_buffer *ring; |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 2372 | bool idle; |
| 2373 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2374 | |
| 2375 | dev_priv = container_of(work, drm_i915_private_t, |
| 2376 | mm.retire_work.work); |
| 2377 | dev = dev_priv->dev; |
| 2378 | |
Chris Wilson | 891b48c | 2010-09-29 12:26:37 +0100 | [diff] [blame] | 2379 | /* Come back later if the device is busy... */ |
| 2380 | if (!mutex_trylock(&dev->struct_mutex)) { |
Chris Wilson | bcb4508 | 2012-10-05 17:02:57 +0100 | [diff] [blame] | 2381 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
| 2382 | round_jiffies_up_relative(HZ)); |
Chris Wilson | 891b48c | 2010-09-29 12:26:37 +0100 | [diff] [blame] | 2383 | return; |
| 2384 | } |
| 2385 | |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2386 | i915_gem_retire_requests(dev); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2387 | |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 2388 | /* Send a periodic flush down the ring so we don't hold onto GEM |
| 2389 | * objects indefinitely. |
| 2390 | */ |
| 2391 | idle = true; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2392 | for_each_ring(ring, dev_priv, i) { |
Chris Wilson | 3bb73ab | 2012-07-20 12:40:59 +0100 | [diff] [blame] | 2393 | if (ring->gpu_caches_dirty) |
Mika Kuoppala | 0025c07 | 2013-06-12 12:35:30 +0300 | [diff] [blame] | 2394 | i915_add_request(ring, NULL); |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 2395 | |
| 2396 | idle &= list_empty(&ring->request_list); |
| 2397 | } |
| 2398 | |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 2399 | if (!dev_priv->ums.mm_suspended && !idle) |
Chris Wilson | bcb4508 | 2012-10-05 17:02:57 +0100 | [diff] [blame] | 2400 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
| 2401 | round_jiffies_up_relative(HZ)); |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 2402 | if (idle) |
| 2403 | intel_mark_idle(dev); |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 2404 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2405 | mutex_unlock(&dev->struct_mutex); |
| 2406 | } |
| 2407 | |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 2408 | /** |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 2409 | * Ensures that an object will eventually get non-busy by flushing any required |
| 2410 | * write domains, emitting any outstanding lazy request and retiring and |
| 2411 | * completed requests. |
| 2412 | */ |
| 2413 | static int |
| 2414 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) |
| 2415 | { |
| 2416 | int ret; |
| 2417 | |
| 2418 | if (obj->active) { |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 2419 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 2420 | if (ret) |
| 2421 | return ret; |
| 2422 | |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 2423 | i915_gem_retire_requests_ring(obj->ring); |
| 2424 | } |
| 2425 | |
| 2426 | return 0; |
| 2427 | } |
| 2428 | |
| 2429 | /** |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2430 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT |
| 2431 | * @DRM_IOCTL_ARGS: standard ioctl arguments |
| 2432 | * |
| 2433 | * Returns 0 if successful, else an error is returned with the remaining time in |
| 2434 | * the timeout parameter. |
| 2435 | * -ETIME: object is still busy after timeout |
| 2436 | * -ERESTARTSYS: signal interrupted the wait |
| 2437 | * -ENONENT: object doesn't exist |
| 2438 | * Also possible, but rare: |
| 2439 | * -EAGAIN: GPU wedged |
| 2440 | * -ENOMEM: damn |
| 2441 | * -ENODEV: Internal IRQ fail |
| 2442 | * -E?: The add request failed |
| 2443 | * |
| 2444 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any |
| 2445 | * non-zero timeout parameter the wait ioctl will wait for the given number of |
| 2446 | * nanoseconds on an object becoming unbusy. Since the wait itself does so |
| 2447 | * without holding struct_mutex the object may become re-busied before this |
| 2448 | * function completes. A similar but shorter * race condition exists in the busy |
| 2449 | * ioctl |
| 2450 | */ |
| 2451 | int |
| 2452 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) |
| 2453 | { |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 2454 | drm_i915_private_t *dev_priv = dev->dev_private; |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2455 | struct drm_i915_gem_wait *args = data; |
| 2456 | struct drm_i915_gem_object *obj; |
| 2457 | struct intel_ring_buffer *ring = NULL; |
Ben Widawsky | eac1f14 | 2012-06-05 15:24:24 -0700 | [diff] [blame] | 2458 | struct timespec timeout_stack, *timeout = NULL; |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 2459 | unsigned reset_counter; |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2460 | u32 seqno = 0; |
| 2461 | int ret = 0; |
| 2462 | |
Ben Widawsky | eac1f14 | 2012-06-05 15:24:24 -0700 | [diff] [blame] | 2463 | if (args->timeout_ns >= 0) { |
| 2464 | timeout_stack = ns_to_timespec(args->timeout_ns); |
| 2465 | timeout = &timeout_stack; |
| 2466 | } |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2467 | |
| 2468 | ret = i915_mutex_lock_interruptible(dev); |
| 2469 | if (ret) |
| 2470 | return ret; |
| 2471 | |
| 2472 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); |
| 2473 | if (&obj->base == NULL) { |
| 2474 | mutex_unlock(&dev->struct_mutex); |
| 2475 | return -ENOENT; |
| 2476 | } |
| 2477 | |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 2478 | /* Need to make sure the object gets inactive eventually. */ |
| 2479 | ret = i915_gem_object_flush_active(obj); |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2480 | if (ret) |
| 2481 | goto out; |
| 2482 | |
| 2483 | if (obj->active) { |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 2484 | seqno = obj->last_read_seqno; |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2485 | ring = obj->ring; |
| 2486 | } |
| 2487 | |
| 2488 | if (seqno == 0) |
| 2489 | goto out; |
| 2490 | |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2491 | /* Do this after OLR check to make sure we make forward progress polling |
| 2492 | * on this IOCTL with a 0 timeout (like busy ioctl) |
| 2493 | */ |
| 2494 | if (!args->timeout_ns) { |
| 2495 | ret = -ETIME; |
| 2496 | goto out; |
| 2497 | } |
| 2498 | |
| 2499 | drm_gem_object_unreference(&obj->base); |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 2500 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2501 | mutex_unlock(&dev->struct_mutex); |
| 2502 | |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 2503 | ret = __wait_seqno(ring, seqno, reset_counter, true, timeout); |
Chris Wilson | 4f42f4e | 2013-04-26 16:22:46 +0300 | [diff] [blame] | 2504 | if (timeout) |
Ben Widawsky | eac1f14 | 2012-06-05 15:24:24 -0700 | [diff] [blame] | 2505 | args->timeout_ns = timespec_to_ns(timeout); |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2506 | return ret; |
| 2507 | |
| 2508 | out: |
| 2509 | drm_gem_object_unreference(&obj->base); |
| 2510 | mutex_unlock(&dev->struct_mutex); |
| 2511 | return ret; |
| 2512 | } |
| 2513 | |
| 2514 | /** |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 2515 | * i915_gem_object_sync - sync an object to a ring. |
| 2516 | * |
| 2517 | * @obj: object which may be in use on another ring. |
| 2518 | * @to: ring we wish to use the object on. May be NULL. |
| 2519 | * |
| 2520 | * This code is meant to abstract object synchronization with the GPU. |
| 2521 | * Calling with NULL implies synchronizing the object with the CPU |
| 2522 | * rather than a particular GPU ring. |
| 2523 | * |
| 2524 | * Returns 0 if successful, else propagates up the lower layer error. |
| 2525 | */ |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2526 | int |
| 2527 | i915_gem_object_sync(struct drm_i915_gem_object *obj, |
| 2528 | struct intel_ring_buffer *to) |
| 2529 | { |
| 2530 | struct intel_ring_buffer *from = obj->ring; |
| 2531 | u32 seqno; |
| 2532 | int ret, idx; |
| 2533 | |
| 2534 | if (from == NULL || to == from) |
| 2535 | return 0; |
| 2536 | |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 2537 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 2538 | return i915_gem_object_wait_rendering(obj, false); |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2539 | |
| 2540 | idx = intel_ring_sync_index(from, to); |
| 2541 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 2542 | seqno = obj->last_read_seqno; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2543 | if (seqno <= from->sync_seqno[idx]) |
| 2544 | return 0; |
| 2545 | |
Ben Widawsky | b4aca01 | 2012-04-25 20:50:12 -0700 | [diff] [blame] | 2546 | ret = i915_gem_check_olr(obj->ring, seqno); |
| 2547 | if (ret) |
| 2548 | return ret; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2549 | |
Ben Widawsky | 1500f7e | 2012-04-11 11:18:21 -0700 | [diff] [blame] | 2550 | ret = to->sync_to(to, from, seqno); |
Ben Widawsky | e3a5a22 | 2012-04-11 11:18:20 -0700 | [diff] [blame] | 2551 | if (!ret) |
Mika Kuoppala | 7b01e26 | 2012-11-28 17:18:45 +0200 | [diff] [blame] | 2552 | /* We use last_read_seqno because sync_to() |
| 2553 | * might have just caused seqno wrap under |
| 2554 | * the radar. |
| 2555 | */ |
| 2556 | from->sync_seqno[idx] = obj->last_read_seqno; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2557 | |
Ben Widawsky | e3a5a22 | 2012-04-11 11:18:20 -0700 | [diff] [blame] | 2558 | return ret; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2559 | } |
| 2560 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 2561 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
| 2562 | { |
| 2563 | u32 old_write_domain, old_read_domains; |
| 2564 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 2565 | /* Force a pagefault for domain tracking on next user access */ |
| 2566 | i915_gem_release_mmap(obj); |
| 2567 | |
Keith Packard | b97c3d9 | 2011-06-24 21:02:59 -0700 | [diff] [blame] | 2568 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
| 2569 | return; |
| 2570 | |
Chris Wilson | 97c809fd | 2012-10-09 19:24:38 +0100 | [diff] [blame] | 2571 | /* Wait for any direct GTT access to complete */ |
| 2572 | mb(); |
| 2573 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 2574 | old_read_domains = obj->base.read_domains; |
| 2575 | old_write_domain = obj->base.write_domain; |
| 2576 | |
| 2577 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; |
| 2578 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; |
| 2579 | |
| 2580 | trace_i915_gem_object_change_domain(obj, |
| 2581 | old_read_domains, |
| 2582 | old_write_domain); |
| 2583 | } |
| 2584 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2585 | /** |
| 2586 | * Unbinds an object from the GTT aperture. |
| 2587 | */ |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2588 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2589 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2590 | { |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2591 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | 43e28f0 | 2013-01-08 10:53:09 +0000 | [diff] [blame] | 2592 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2593 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2594 | if (!i915_gem_obj_ggtt_bound(obj)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2595 | return 0; |
| 2596 | |
Chris Wilson | 31d8d65 | 2012-05-24 19:11:20 +0100 | [diff] [blame] | 2597 | if (obj->pin_count) |
| 2598 | return -EBUSY; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2599 | |
Chris Wilson | c4670ad | 2012-08-20 10:23:27 +0100 | [diff] [blame] | 2600 | BUG_ON(obj->pages == NULL); |
| 2601 | |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2602 | ret = i915_gem_object_finish_gpu(obj); |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 2603 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2604 | return ret; |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2605 | /* Continue on if we fail due to EIO, the GPU is hung so we |
| 2606 | * should be safe and we need to cleanup or else we might |
| 2607 | * cause memory corruption through use-after-free. |
| 2608 | */ |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2609 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 2610 | i915_gem_object_finish_gtt(obj); |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2611 | |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 2612 | /* release the fence reg _after_ flushing */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2613 | ret = i915_gem_object_put_fence(obj); |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 2614 | if (ret) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2615 | return ret; |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 2616 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2617 | trace_i915_gem_object_unbind(obj); |
| 2618 | |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 2619 | if (obj->has_global_gtt_mapping) |
| 2620 | i915_gem_gtt_unbind_object(obj); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2621 | if (obj->has_aliasing_ppgtt_mapping) { |
| 2622 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); |
| 2623 | obj->has_aliasing_ppgtt_mapping = 0; |
| 2624 | } |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 2625 | i915_gem_gtt_finish_object(obj); |
Ben Widawsky | 401c29f | 2013-05-31 11:28:47 -0700 | [diff] [blame] | 2626 | i915_gem_object_unpin_pages(obj); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2627 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2628 | list_del(&obj->mm_list); |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 2629 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2630 | /* Avoid an unnecessary call to unbind on rebind. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2631 | obj->map_and_fenceable = true; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2632 | |
Ben Widawsky | c6cfb32 | 2013-07-05 14:41:06 -0700 | [diff] [blame] | 2633 | drm_mm_remove_node(&obj->gtt_space); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2634 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2635 | return 0; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 2636 | } |
| 2637 | |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 2638 | int i915_gpu_idle(struct drm_device *dev) |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2639 | { |
| 2640 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2641 | struct intel_ring_buffer *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2642 | int ret, i; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2643 | |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2644 | /* Flush everything onto the inactive list. */ |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2645 | for_each_ring(ring, dev_priv, i) { |
Ben Widawsky | b6c7488 | 2012-08-14 14:35:14 -0700 | [diff] [blame] | 2646 | ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID); |
| 2647 | if (ret) |
| 2648 | return ret; |
| 2649 | |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 2650 | ret = intel_ring_idle(ring); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2651 | if (ret) |
| 2652 | return ret; |
| 2653 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2654 | |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 2655 | return 0; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2656 | } |
| 2657 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2658 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
| 2659 | struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2660 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2661 | drm_i915_private_t *dev_priv = dev->dev_private; |
Imre Deak | 56c844e | 2013-01-07 21:47:34 +0200 | [diff] [blame] | 2662 | int fence_reg; |
| 2663 | int fence_pitch_shift; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2664 | uint64_t val; |
| 2665 | |
Imre Deak | 56c844e | 2013-01-07 21:47:34 +0200 | [diff] [blame] | 2666 | if (INTEL_INFO(dev)->gen >= 6) { |
| 2667 | fence_reg = FENCE_REG_SANDYBRIDGE_0; |
| 2668 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; |
| 2669 | } else { |
| 2670 | fence_reg = FENCE_REG_965_0; |
| 2671 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; |
| 2672 | } |
| 2673 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2674 | if (obj) { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2675 | u32 size = i915_gem_obj_ggtt_size(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2676 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2677 | val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) & |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2678 | 0xfffff000) << 32; |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2679 | val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000; |
Imre Deak | 56c844e | 2013-01-07 21:47:34 +0200 | [diff] [blame] | 2680 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2681 | if (obj->tiling_mode == I915_TILING_Y) |
| 2682 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2683 | val |= I965_FENCE_REG_VALID; |
| 2684 | } else |
| 2685 | val = 0; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2686 | |
Imre Deak | 56c844e | 2013-01-07 21:47:34 +0200 | [diff] [blame] | 2687 | fence_reg += reg * 8; |
| 2688 | I915_WRITE64(fence_reg, val); |
| 2689 | POSTING_READ(fence_reg); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2690 | } |
| 2691 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2692 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
| 2693 | struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2694 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2695 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2696 | u32 val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2697 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2698 | if (obj) { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2699 | u32 size = i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2700 | int pitch_val; |
| 2701 | int tile_width; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2702 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2703 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) || |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2704 | (size & -size) != size || |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2705 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
| 2706 | "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", |
| 2707 | i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size); |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2708 | |
| 2709 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
| 2710 | tile_width = 128; |
| 2711 | else |
| 2712 | tile_width = 512; |
| 2713 | |
| 2714 | /* Note: pitch better be a power of two tile widths */ |
| 2715 | pitch_val = obj->stride / tile_width; |
| 2716 | pitch_val = ffs(pitch_val) - 1; |
| 2717 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2718 | val = i915_gem_obj_ggtt_offset(obj); |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2719 | if (obj->tiling_mode == I915_TILING_Y) |
| 2720 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 2721 | val |= I915_FENCE_SIZE_BITS(size); |
| 2722 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2723 | val |= I830_FENCE_REG_VALID; |
| 2724 | } else |
| 2725 | val = 0; |
| 2726 | |
| 2727 | if (reg < 8) |
| 2728 | reg = FENCE_REG_830_0 + reg * 4; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2729 | else |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2730 | reg = FENCE_REG_945_8 + (reg - 8) * 4; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2731 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2732 | I915_WRITE(reg, val); |
| 2733 | POSTING_READ(reg); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2734 | } |
| 2735 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2736 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
| 2737 | struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2738 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2739 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2740 | uint32_t val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2741 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2742 | if (obj) { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2743 | u32 size = i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2744 | uint32_t pitch_val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2745 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2746 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) || |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2747 | (size & -size) != size || |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2748 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
| 2749 | "object 0x%08lx not 512K or pot-size 0x%08x aligned\n", |
| 2750 | i915_gem_obj_ggtt_offset(obj), size); |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 2751 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2752 | pitch_val = obj->stride / 128; |
| 2753 | pitch_val = ffs(pitch_val) - 1; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2754 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2755 | val = i915_gem_obj_ggtt_offset(obj); |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2756 | if (obj->tiling_mode == I915_TILING_Y) |
| 2757 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 2758 | val |= I830_FENCE_SIZE_BITS(size); |
| 2759 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2760 | val |= I830_FENCE_REG_VALID; |
| 2761 | } else |
| 2762 | val = 0; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2763 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2764 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
| 2765 | POSTING_READ(FENCE_REG_830_0 + reg * 4); |
| 2766 | } |
| 2767 | |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 2768 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
| 2769 | { |
| 2770 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; |
| 2771 | } |
| 2772 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2773 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
| 2774 | struct drm_i915_gem_object *obj) |
| 2775 | { |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 2776 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2777 | |
| 2778 | /* Ensure that all CPU reads are completed before installing a fence |
| 2779 | * and all writes before removing the fence. |
| 2780 | */ |
| 2781 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) |
| 2782 | mb(); |
| 2783 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2784 | switch (INTEL_INFO(dev)->gen) { |
| 2785 | case 7: |
Imre Deak | 56c844e | 2013-01-07 21:47:34 +0200 | [diff] [blame] | 2786 | case 6: |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2787 | case 5: |
| 2788 | case 4: i965_write_fence_reg(dev, reg, obj); break; |
| 2789 | case 3: i915_write_fence_reg(dev, reg, obj); break; |
| 2790 | case 2: i830_write_fence_reg(dev, reg, obj); break; |
Ben Widawsky | 7dbf9d6 | 2012-12-18 10:31:22 -0800 | [diff] [blame] | 2791 | default: BUG(); |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2792 | } |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 2793 | |
| 2794 | /* And similarly be paranoid that no direct access to this region |
| 2795 | * is reordered to before the fence is installed. |
| 2796 | */ |
| 2797 | if (i915_gem_object_needs_mb(obj)) |
| 2798 | mb(); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2799 | } |
| 2800 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 2801 | static inline int fence_number(struct drm_i915_private *dev_priv, |
| 2802 | struct drm_i915_fence_reg *fence) |
| 2803 | { |
| 2804 | return fence - dev_priv->fence_regs; |
| 2805 | } |
| 2806 | |
Chris Wilson | 2dc8aae | 2013-05-22 17:08:06 +0100 | [diff] [blame] | 2807 | struct write_fence { |
| 2808 | struct drm_device *dev; |
| 2809 | struct drm_i915_gem_object *obj; |
| 2810 | int fence; |
| 2811 | }; |
| 2812 | |
Chris Wilson | 25ff119 | 2013-04-04 21:31:03 +0100 | [diff] [blame] | 2813 | static void i915_gem_write_fence__ipi(void *data) |
| 2814 | { |
Chris Wilson | 2dc8aae | 2013-05-22 17:08:06 +0100 | [diff] [blame] | 2815 | struct write_fence *args = data; |
| 2816 | |
| 2817 | /* Required for SNB+ with LLC */ |
Chris Wilson | 25ff119 | 2013-04-04 21:31:03 +0100 | [diff] [blame] | 2818 | wbinvd(); |
Chris Wilson | 2dc8aae | 2013-05-22 17:08:06 +0100 | [diff] [blame] | 2819 | |
| 2820 | /* Required for VLV */ |
| 2821 | i915_gem_write_fence(args->dev, args->fence, args->obj); |
Chris Wilson | 25ff119 | 2013-04-04 21:31:03 +0100 | [diff] [blame] | 2822 | } |
| 2823 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 2824 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
| 2825 | struct drm_i915_fence_reg *fence, |
| 2826 | bool enable) |
| 2827 | { |
Chris Wilson | 2dc8aae | 2013-05-22 17:08:06 +0100 | [diff] [blame] | 2828 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 2829 | struct write_fence args = { |
| 2830 | .dev = obj->base.dev, |
| 2831 | .fence = fence_number(dev_priv, fence), |
| 2832 | .obj = enable ? obj : NULL, |
| 2833 | }; |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 2834 | |
Chris Wilson | 25ff119 | 2013-04-04 21:31:03 +0100 | [diff] [blame] | 2835 | /* In order to fully serialize access to the fenced region and |
| 2836 | * the update to the fence register we need to take extreme |
| 2837 | * measures on SNB+. In theory, the write to the fence register |
| 2838 | * flushes all memory transactions before, and coupled with the |
| 2839 | * mb() placed around the register write we serialise all memory |
| 2840 | * operations with respect to the changes in the tiler. Yet, on |
| 2841 | * SNB+ we need to take a step further and emit an explicit wbinvd() |
| 2842 | * on each processor in order to manually flush all memory |
| 2843 | * transactions before updating the fence register. |
Chris Wilson | 2dc8aae | 2013-05-22 17:08:06 +0100 | [diff] [blame] | 2844 | * |
| 2845 | * However, Valleyview complicates matter. There the wbinvd is |
| 2846 | * insufficient and unlike SNB/IVB requires the serialising |
| 2847 | * register write. (Note that that register write by itself is |
| 2848 | * conversely not sufficient for SNB+.) To compromise, we do both. |
Chris Wilson | 25ff119 | 2013-04-04 21:31:03 +0100 | [diff] [blame] | 2849 | */ |
Chris Wilson | 2dc8aae | 2013-05-22 17:08:06 +0100 | [diff] [blame] | 2850 | if (INTEL_INFO(args.dev)->gen >= 6) |
| 2851 | on_each_cpu(i915_gem_write_fence__ipi, &args, 1); |
| 2852 | else |
| 2853 | i915_gem_write_fence(args.dev, args.fence, args.obj); |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 2854 | |
| 2855 | if (enable) { |
Chris Wilson | 2dc8aae | 2013-05-22 17:08:06 +0100 | [diff] [blame] | 2856 | obj->fence_reg = args.fence; |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 2857 | fence->obj = obj; |
| 2858 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); |
| 2859 | } else { |
| 2860 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 2861 | fence->obj = NULL; |
| 2862 | list_del_init(&fence->lru_list); |
| 2863 | } |
| 2864 | } |
| 2865 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2866 | static int |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 2867 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2868 | { |
Chris Wilson | 1c293ea | 2012-04-17 15:31:27 +0100 | [diff] [blame] | 2869 | if (obj->last_fenced_seqno) { |
Chris Wilson | 86d5bc3 | 2012-07-20 12:41:04 +0100 | [diff] [blame] | 2870 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
Chris Wilson | 1899184 | 2012-04-17 15:31:29 +0100 | [diff] [blame] | 2871 | if (ret) |
| 2872 | return ret; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2873 | |
| 2874 | obj->last_fenced_seqno = 0; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2875 | } |
| 2876 | |
Chris Wilson | 86d5bc3 | 2012-07-20 12:41:04 +0100 | [diff] [blame] | 2877 | obj->fenced_gpu_access = false; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2878 | return 0; |
| 2879 | } |
| 2880 | |
| 2881 | int |
| 2882 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) |
| 2883 | { |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 2884 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | f9c513e | 2013-03-26 11:29:27 +0000 | [diff] [blame] | 2885 | struct drm_i915_fence_reg *fence; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2886 | int ret; |
| 2887 | |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 2888 | ret = i915_gem_object_wait_fence(obj); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2889 | if (ret) |
| 2890 | return ret; |
| 2891 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 2892 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
| 2893 | return 0; |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2894 | |
Chris Wilson | f9c513e | 2013-03-26 11:29:27 +0000 | [diff] [blame] | 2895 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
| 2896 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 2897 | i915_gem_object_fence_lost(obj); |
Chris Wilson | f9c513e | 2013-03-26 11:29:27 +0000 | [diff] [blame] | 2898 | i915_gem_object_update_fence(obj, fence, false); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2899 | |
| 2900 | return 0; |
| 2901 | } |
| 2902 | |
| 2903 | static struct drm_i915_fence_reg * |
Chris Wilson | a360bb1 | 2012-04-17 15:31:25 +0100 | [diff] [blame] | 2904 | i915_find_fence_reg(struct drm_device *dev) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2905 | { |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2906 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 8fe301a | 2012-04-17 15:31:28 +0100 | [diff] [blame] | 2907 | struct drm_i915_fence_reg *reg, *avail; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2908 | int i; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2909 | |
| 2910 | /* First try to find a free reg */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2911 | avail = NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2912 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
| 2913 | reg = &dev_priv->fence_regs[i]; |
| 2914 | if (!reg->obj) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2915 | return reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2916 | |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2917 | if (!reg->pin_count) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2918 | avail = reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2919 | } |
| 2920 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2921 | if (avail == NULL) |
| 2922 | return NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2923 | |
| 2924 | /* None available, try to steal one or wait for a user to finish */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2925 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2926 | if (reg->pin_count) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2927 | continue; |
| 2928 | |
Chris Wilson | 8fe301a | 2012-04-17 15:31:28 +0100 | [diff] [blame] | 2929 | return reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2930 | } |
| 2931 | |
Chris Wilson | 8fe301a | 2012-04-17 15:31:28 +0100 | [diff] [blame] | 2932 | return NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2933 | } |
| 2934 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2935 | /** |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 2936 | * i915_gem_object_get_fence - set up fencing for an object |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2937 | * @obj: object to map through a fence reg |
| 2938 | * |
| 2939 | * When mapping objects through the GTT, userspace wants to be able to write |
| 2940 | * to them without having to worry about swizzling if the object is tiled. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2941 | * This function walks the fence regs looking for a free one for @obj, |
| 2942 | * stealing one if it can't find any. |
| 2943 | * |
| 2944 | * It then sets up the reg based on the object's properties: address, pitch |
| 2945 | * and tiling format. |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 2946 | * |
| 2947 | * For an untiled surface, this removes any existing fence. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2948 | */ |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 2949 | int |
Chris Wilson | 06d9813 | 2012-04-17 15:31:24 +0100 | [diff] [blame] | 2950 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2951 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2952 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2953 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2954 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2955 | struct drm_i915_fence_reg *reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2956 | int ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2957 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2958 | /* Have we updated the tiling parameters upon the object and so |
| 2959 | * will need to serialise the write to the associated fence register? |
| 2960 | */ |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 2961 | if (obj->fence_dirty) { |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 2962 | ret = i915_gem_object_wait_fence(obj); |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2963 | if (ret) |
| 2964 | return ret; |
| 2965 | } |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 2966 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2967 | /* Just update our place in the LRU if our fence is getting reused. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2968 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 2969 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 2970 | if (!obj->fence_dirty) { |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2971 | list_move_tail(®->lru_list, |
| 2972 | &dev_priv->mm.fence_list); |
| 2973 | return 0; |
| 2974 | } |
| 2975 | } else if (enable) { |
| 2976 | reg = i915_find_fence_reg(dev); |
| 2977 | if (reg == NULL) |
| 2978 | return -EDEADLK; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2979 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2980 | if (reg->obj) { |
| 2981 | struct drm_i915_gem_object *old = reg->obj; |
| 2982 | |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 2983 | ret = i915_gem_object_wait_fence(old); |
Chris Wilson | 29c5a58 | 2011-03-17 15:23:22 +0000 | [diff] [blame] | 2984 | if (ret) |
| 2985 | return ret; |
| 2986 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2987 | i915_gem_object_fence_lost(old); |
Chris Wilson | 29c5a58 | 2011-03-17 15:23:22 +0000 | [diff] [blame] | 2988 | } |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2989 | } else |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2990 | return 0; |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2991 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2992 | i915_gem_object_update_fence(obj, reg, enable); |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 2993 | obj->fence_dirty = false; |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2994 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2995 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2996 | } |
| 2997 | |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 2998 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
| 2999 | struct drm_mm_node *gtt_space, |
| 3000 | unsigned long cache_level) |
| 3001 | { |
| 3002 | struct drm_mm_node *other; |
| 3003 | |
| 3004 | /* On non-LLC machines we have to be careful when putting differing |
| 3005 | * types of snoopable memory together to avoid the prefetcher |
Damien Lespiau | 4239ca7 | 2012-12-03 16:26:16 +0000 | [diff] [blame] | 3006 | * crossing memory domains and dying. |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3007 | */ |
| 3008 | if (HAS_LLC(dev)) |
| 3009 | return true; |
| 3010 | |
Ben Widawsky | c6cfb32 | 2013-07-05 14:41:06 -0700 | [diff] [blame] | 3011 | if (!drm_mm_node_allocated(gtt_space)) |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3012 | return true; |
| 3013 | |
| 3014 | if (list_empty(>t_space->node_list)) |
| 3015 | return true; |
| 3016 | |
| 3017 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); |
| 3018 | if (other->allocated && !other->hole_follows && other->color != cache_level) |
| 3019 | return false; |
| 3020 | |
| 3021 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); |
| 3022 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) |
| 3023 | return false; |
| 3024 | |
| 3025 | return true; |
| 3026 | } |
| 3027 | |
| 3028 | static void i915_gem_verify_gtt(struct drm_device *dev) |
| 3029 | { |
| 3030 | #if WATCH_GTT |
| 3031 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3032 | struct drm_i915_gem_object *obj; |
| 3033 | int err = 0; |
| 3034 | |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 3035 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) { |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3036 | if (obj->gtt_space == NULL) { |
| 3037 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); |
| 3038 | err++; |
| 3039 | continue; |
| 3040 | } |
| 3041 | |
| 3042 | if (obj->cache_level != obj->gtt_space->color) { |
| 3043 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3044 | i915_gem_obj_ggtt_offset(obj), |
| 3045 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3046 | obj->cache_level, |
| 3047 | obj->gtt_space->color); |
| 3048 | err++; |
| 3049 | continue; |
| 3050 | } |
| 3051 | |
| 3052 | if (!i915_gem_valid_gtt_space(dev, |
| 3053 | obj->gtt_space, |
| 3054 | obj->cache_level)) { |
| 3055 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3056 | i915_gem_obj_ggtt_offset(obj), |
| 3057 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3058 | obj->cache_level); |
| 3059 | err++; |
| 3060 | continue; |
| 3061 | } |
| 3062 | } |
| 3063 | |
| 3064 | WARN_ON(err); |
| 3065 | #endif |
| 3066 | } |
| 3067 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3068 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3069 | * Finds free space in the GTT aperture and binds the object there. |
| 3070 | */ |
| 3071 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3072 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 3073 | unsigned alignment, |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 3074 | bool map_and_fenceable, |
| 3075 | bool nonblocking) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3076 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3077 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3078 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 3079 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3080 | bool mappable, fenceable; |
Ben Widawsky | 0a9ae0d | 2013-05-25 12:26:35 -0700 | [diff] [blame] | 3081 | size_t gtt_max = map_and_fenceable ? |
| 3082 | dev_priv->gtt.mappable_end : dev_priv->gtt.total; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 3083 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3084 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 3085 | fence_size = i915_gem_get_gtt_size(dev, |
| 3086 | obj->base.size, |
| 3087 | obj->tiling_mode); |
| 3088 | fence_alignment = i915_gem_get_gtt_alignment(dev, |
| 3089 | obj->base.size, |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 3090 | obj->tiling_mode, true); |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 3091 | unfenced_alignment = |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 3092 | i915_gem_get_gtt_alignment(dev, |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 3093 | obj->base.size, |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 3094 | obj->tiling_mode, false); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 3095 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3096 | if (alignment == 0) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 3097 | alignment = map_and_fenceable ? fence_alignment : |
| 3098 | unfenced_alignment; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3099 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3100 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
| 3101 | return -EINVAL; |
| 3102 | } |
| 3103 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3104 | size = map_and_fenceable ? fence_size : obj->base.size; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 3105 | |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 3106 | /* If the object is bigger than the entire aperture, reject it early |
| 3107 | * before evicting everything in a vain attempt to find space. |
| 3108 | */ |
Ben Widawsky | 0a9ae0d | 2013-05-25 12:26:35 -0700 | [diff] [blame] | 3109 | if (obj->base.size > gtt_max) { |
Jani Nikula | 3765f30 | 2013-06-07 16:03:50 +0300 | [diff] [blame] | 3110 | DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n", |
Chris Wilson | a36689c | 2013-05-21 16:58:49 +0100 | [diff] [blame] | 3111 | obj->base.size, |
| 3112 | map_and_fenceable ? "mappable" : "total", |
Ben Widawsky | 0a9ae0d | 2013-05-25 12:26:35 -0700 | [diff] [blame] | 3113 | gtt_max); |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 3114 | return -E2BIG; |
| 3115 | } |
| 3116 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 3117 | ret = i915_gem_object_get_pages(obj); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 3118 | if (ret) |
| 3119 | return ret; |
| 3120 | |
Chris Wilson | fbdda6f | 2012-11-20 10:45:16 +0000 | [diff] [blame] | 3121 | i915_gem_object_pin_pages(obj); |
| 3122 | |
Ben Widawsky | 0a9ae0d | 2013-05-25 12:26:35 -0700 | [diff] [blame] | 3123 | search_free: |
Ben Widawsky | c6cfb32 | 2013-07-05 14:41:06 -0700 | [diff] [blame] | 3124 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->mm.gtt_space, |
| 3125 | &obj->gtt_space, |
Ben Widawsky | 0a9ae0d | 2013-05-25 12:26:35 -0700 | [diff] [blame] | 3126 | size, alignment, |
| 3127 | obj->cache_level, 0, gtt_max); |
Chris Wilson | dc9dd7a | 2012-12-07 20:37:07 +0000 | [diff] [blame] | 3128 | if (ret) { |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3129 | ret = i915_gem_evict_something(dev, size, alignment, |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3130 | obj->cache_level, |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 3131 | map_and_fenceable, |
| 3132 | nonblocking); |
Chris Wilson | dc9dd7a | 2012-12-07 20:37:07 +0000 | [diff] [blame] | 3133 | if (ret == 0) |
| 3134 | goto search_free; |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 3135 | |
Chris Wilson | fbdda6f | 2012-11-20 10:45:16 +0000 | [diff] [blame] | 3136 | i915_gem_object_unpin_pages(obj); |
Chris Wilson | dc9dd7a | 2012-12-07 20:37:07 +0000 | [diff] [blame] | 3137 | return ret; |
| 3138 | } |
Ben Widawsky | c6cfb32 | 2013-07-05 14:41:06 -0700 | [diff] [blame] | 3139 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, &obj->gtt_space, |
| 3140 | obj->cache_level))) { |
Chris Wilson | dc9dd7a | 2012-12-07 20:37:07 +0000 | [diff] [blame] | 3141 | i915_gem_object_unpin_pages(obj); |
Ben Widawsky | c6cfb32 | 2013-07-05 14:41:06 -0700 | [diff] [blame] | 3142 | drm_mm_remove_node(&obj->gtt_space); |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3143 | return -EINVAL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3144 | } |
| 3145 | |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 3146 | ret = i915_gem_gtt_prepare_object(obj); |
Daniel Vetter | 7c2e6fd | 2010-11-06 10:10:47 +0100 | [diff] [blame] | 3147 | if (ret) { |
Chris Wilson | fbdda6f | 2012-11-20 10:45:16 +0000 | [diff] [blame] | 3148 | i915_gem_object_unpin_pages(obj); |
Ben Widawsky | c6cfb32 | 2013-07-05 14:41:06 -0700 | [diff] [blame] | 3149 | drm_mm_remove_node(&obj->gtt_space); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 3150 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3151 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3152 | |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 3153 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3154 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
Chris Wilson | bf1a109 | 2010-08-07 11:01:20 +0100 | [diff] [blame] | 3155 | |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3156 | fenceable = |
Ben Widawsky | c6cfb32 | 2013-07-05 14:41:06 -0700 | [diff] [blame] | 3157 | i915_gem_obj_ggtt_size(obj) == fence_size && |
| 3158 | (i915_gem_obj_ggtt_offset(obj) & (fence_alignment - 1)) == 0; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 3159 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3160 | mappable = i915_gem_obj_ggtt_offset(obj) + obj->base.size <= |
| 3161 | dev_priv->gtt.mappable_end; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 3162 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3163 | obj->map_and_fenceable = mappable && fenceable; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3164 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 3165 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3166 | i915_gem_verify_gtt(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3167 | return 0; |
| 3168 | } |
| 3169 | |
| 3170 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3171 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3172 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3173 | /* If we don't have a page list set up, then we're not pinned |
| 3174 | * to GPU, and we can ignore the cache flush because it'll happen |
| 3175 | * again at bind time. |
| 3176 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3177 | if (obj->pages == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3178 | return; |
| 3179 | |
Imre Deak | 769ce46 | 2013-02-13 21:56:05 +0200 | [diff] [blame] | 3180 | /* |
| 3181 | * Stolen memory is always coherent with the GPU as it is explicitly |
| 3182 | * marked as wc by the system, or the system is cache-coherent. |
| 3183 | */ |
| 3184 | if (obj->stolen) |
| 3185 | return; |
| 3186 | |
Chris Wilson | 9c23f7f | 2011-03-29 16:59:52 -0700 | [diff] [blame] | 3187 | /* If the GPU is snooping the contents of the CPU cache, |
| 3188 | * we do not need to manually clear the CPU cache lines. However, |
| 3189 | * the caches are only snooped when the render cache is |
| 3190 | * flushed/invalidated. As we always have to emit invalidations |
| 3191 | * and flushes when moving into and out of the RENDER domain, correct |
| 3192 | * snooping behaviour occurs naturally as the result of our domain |
| 3193 | * tracking. |
| 3194 | */ |
| 3195 | if (obj->cache_level != I915_CACHE_NONE) |
| 3196 | return; |
| 3197 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3198 | trace_i915_gem_object_clflush(obj); |
Eric Anholt | cfa16a0 | 2009-05-26 18:46:16 -0700 | [diff] [blame] | 3199 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 3200 | drm_clflush_sg(obj->pages); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3201 | } |
| 3202 | |
| 3203 | /** Flushes the GTT write domain for the object if it's dirty. */ |
| 3204 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3205 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3206 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3207 | uint32_t old_write_domain; |
| 3208 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3209 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3210 | return; |
| 3211 | |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 3212 | /* No actual flushing is required for the GTT write domain. Writes |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3213 | * to it immediately go to main memory as far as we know, so there's |
| 3214 | * no chipset flush. It also doesn't land in render cache. |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 3215 | * |
| 3216 | * However, we do have to enforce the order so that all writes through |
| 3217 | * the GTT land before any writes to the device, such as updates to |
| 3218 | * the GATT itself. |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3219 | */ |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 3220 | wmb(); |
| 3221 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3222 | old_write_domain = obj->base.write_domain; |
| 3223 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3224 | |
| 3225 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3226 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3227 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3228 | } |
| 3229 | |
| 3230 | /** Flushes the CPU write domain for the object if it's dirty. */ |
| 3231 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3232 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3233 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3234 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3235 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3236 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3237 | return; |
| 3238 | |
| 3239 | i915_gem_clflush_object(obj); |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 3240 | i915_gem_chipset_flush(obj->base.dev); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3241 | old_write_domain = obj->base.write_domain; |
| 3242 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3243 | |
| 3244 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3245 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3246 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3247 | } |
| 3248 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3249 | /** |
| 3250 | * Moves a single object to the GTT read, and possibly write domain. |
| 3251 | * |
| 3252 | * This function returns when the move is complete, including waiting on |
| 3253 | * flushes to occur. |
| 3254 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3255 | int |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 3256 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3257 | { |
Chris Wilson | 8325a09 | 2012-04-24 15:52:35 +0100 | [diff] [blame] | 3258 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3259 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3260 | int ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3261 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 3262 | /* Not valid to be called on unbound objects. */ |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3263 | if (!i915_gem_obj_ggtt_bound(obj)) |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 3264 | return -EINVAL; |
| 3265 | |
Chris Wilson | 8d7e3de | 2011-02-07 15:23:02 +0000 | [diff] [blame] | 3266 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
| 3267 | return 0; |
| 3268 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 3269 | ret = i915_gem_object_wait_rendering(obj, !write); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3270 | if (ret) |
| 3271 | return ret; |
| 3272 | |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 3273 | i915_gem_object_flush_cpu_write_domain(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3274 | |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 3275 | /* Serialise direct access to this object with the barriers for |
| 3276 | * coherent writes from the GPU, by effectively invalidating the |
| 3277 | * GTT domain upon first access. |
| 3278 | */ |
| 3279 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
| 3280 | mb(); |
| 3281 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3282 | old_write_domain = obj->base.write_domain; |
| 3283 | old_read_domains = obj->base.read_domains; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3284 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3285 | /* It should now be out of any other write domains, and we can update |
| 3286 | * the domain values for our changes. |
| 3287 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3288 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
| 3289 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3290 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3291 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
| 3292 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; |
| 3293 | obj->dirty = 1; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3294 | } |
| 3295 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3296 | trace_i915_gem_object_change_domain(obj, |
| 3297 | old_read_domains, |
| 3298 | old_write_domain); |
| 3299 | |
Chris Wilson | 8325a09 | 2012-04-24 15:52:35 +0100 | [diff] [blame] | 3300 | /* And bump the LRU for this access */ |
| 3301 | if (i915_gem_object_is_inactive(obj)) |
| 3302 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
| 3303 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3304 | return 0; |
| 3305 | } |
| 3306 | |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3307 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
| 3308 | enum i915_cache_level cache_level) |
| 3309 | { |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 3310 | struct drm_device *dev = obj->base.dev; |
| 3311 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3312 | int ret; |
| 3313 | |
| 3314 | if (obj->cache_level == cache_level) |
| 3315 | return 0; |
| 3316 | |
| 3317 | if (obj->pin_count) { |
| 3318 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
| 3319 | return -EBUSY; |
| 3320 | } |
| 3321 | |
Ben Widawsky | c6cfb32 | 2013-07-05 14:41:06 -0700 | [diff] [blame] | 3322 | if (!i915_gem_valid_gtt_space(dev, &obj->gtt_space, cache_level)) { |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3323 | ret = i915_gem_object_unbind(obj); |
| 3324 | if (ret) |
| 3325 | return ret; |
| 3326 | } |
| 3327 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3328 | if (i915_gem_obj_ggtt_bound(obj)) { |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3329 | ret = i915_gem_object_finish_gpu(obj); |
| 3330 | if (ret) |
| 3331 | return ret; |
| 3332 | |
| 3333 | i915_gem_object_finish_gtt(obj); |
| 3334 | |
| 3335 | /* Before SandyBridge, you could not use tiling or fence |
| 3336 | * registers with snooped memory, so relinquish any fences |
| 3337 | * currently pointing to our region in the aperture. |
| 3338 | */ |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3339 | if (INTEL_INFO(dev)->gen < 6) { |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3340 | ret = i915_gem_object_put_fence(obj); |
| 3341 | if (ret) |
| 3342 | return ret; |
| 3343 | } |
| 3344 | |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 3345 | if (obj->has_global_gtt_mapping) |
| 3346 | i915_gem_gtt_bind_object(obj, cache_level); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 3347 | if (obj->has_aliasing_ppgtt_mapping) |
| 3348 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, |
| 3349 | obj, cache_level); |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3350 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3351 | i915_gem_obj_ggtt_set_color(obj, cache_level); |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3352 | } |
| 3353 | |
| 3354 | if (cache_level == I915_CACHE_NONE) { |
| 3355 | u32 old_read_domains, old_write_domain; |
| 3356 | |
| 3357 | /* If we're coming from LLC cached, then we haven't |
| 3358 | * actually been tracking whether the data is in the |
| 3359 | * CPU cache or not, since we only allow one bit set |
| 3360 | * in obj->write_domain and have been skipping the clflushes. |
| 3361 | * Just set it to the CPU cache for now. |
| 3362 | */ |
| 3363 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); |
| 3364 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); |
| 3365 | |
| 3366 | old_read_domains = obj->base.read_domains; |
| 3367 | old_write_domain = obj->base.write_domain; |
| 3368 | |
| 3369 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 3370 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 3371 | |
| 3372 | trace_i915_gem_object_change_domain(obj, |
| 3373 | old_read_domains, |
| 3374 | old_write_domain); |
| 3375 | } |
| 3376 | |
| 3377 | obj->cache_level = cache_level; |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3378 | i915_gem_verify_gtt(dev); |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3379 | return 0; |
| 3380 | } |
| 3381 | |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3382 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
| 3383 | struct drm_file *file) |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3384 | { |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3385 | struct drm_i915_gem_caching *args = data; |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3386 | struct drm_i915_gem_object *obj; |
| 3387 | int ret; |
| 3388 | |
| 3389 | ret = i915_mutex_lock_interruptible(dev); |
| 3390 | if (ret) |
| 3391 | return ret; |
| 3392 | |
| 3393 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 3394 | if (&obj->base == NULL) { |
| 3395 | ret = -ENOENT; |
| 3396 | goto unlock; |
| 3397 | } |
| 3398 | |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3399 | args->caching = obj->cache_level != I915_CACHE_NONE; |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3400 | |
| 3401 | drm_gem_object_unreference(&obj->base); |
| 3402 | unlock: |
| 3403 | mutex_unlock(&dev->struct_mutex); |
| 3404 | return ret; |
| 3405 | } |
| 3406 | |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3407 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
| 3408 | struct drm_file *file) |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3409 | { |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3410 | struct drm_i915_gem_caching *args = data; |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3411 | struct drm_i915_gem_object *obj; |
| 3412 | enum i915_cache_level level; |
| 3413 | int ret; |
| 3414 | |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3415 | switch (args->caching) { |
| 3416 | case I915_CACHING_NONE: |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3417 | level = I915_CACHE_NONE; |
| 3418 | break; |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3419 | case I915_CACHING_CACHED: |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3420 | level = I915_CACHE_LLC; |
| 3421 | break; |
| 3422 | default: |
| 3423 | return -EINVAL; |
| 3424 | } |
| 3425 | |
Ben Widawsky | 3bc2913 | 2012-09-26 16:15:20 -0700 | [diff] [blame] | 3426 | ret = i915_mutex_lock_interruptible(dev); |
| 3427 | if (ret) |
| 3428 | return ret; |
| 3429 | |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3430 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 3431 | if (&obj->base == NULL) { |
| 3432 | ret = -ENOENT; |
| 3433 | goto unlock; |
| 3434 | } |
| 3435 | |
| 3436 | ret = i915_gem_object_set_cache_level(obj, level); |
| 3437 | |
| 3438 | drm_gem_object_unreference(&obj->base); |
| 3439 | unlock: |
| 3440 | mutex_unlock(&dev->struct_mutex); |
| 3441 | return ret; |
| 3442 | } |
| 3443 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3444 | /* |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3445 | * Prepare buffer for display plane (scanout, cursors, etc). |
| 3446 | * Can be called from an uninterruptible phase (modesetting) and allows |
| 3447 | * any flushes to be pipelined (for pageflips). |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3448 | */ |
| 3449 | int |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3450 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
| 3451 | u32 alignment, |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 3452 | struct intel_ring_buffer *pipelined) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3453 | { |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3454 | u32 old_read_domains, old_write_domain; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3455 | int ret; |
| 3456 | |
Chris Wilson | 0be7328 | 2010-12-06 14:36:27 +0000 | [diff] [blame] | 3457 | if (pipelined != obj->ring) { |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 3458 | ret = i915_gem_object_sync(obj, pipelined); |
| 3459 | if (ret) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3460 | return ret; |
| 3461 | } |
| 3462 | |
Eric Anholt | a7ef064 | 2011-03-29 16:59:54 -0700 | [diff] [blame] | 3463 | /* The display engine is not coherent with the LLC cache on gen6. As |
| 3464 | * a result, we make sure that the pinning that is about to occur is |
| 3465 | * done with uncached PTEs. This is lowest common denominator for all |
| 3466 | * chipsets. |
| 3467 | * |
| 3468 | * However for gen6+, we could do better by using the GFDT bit instead |
| 3469 | * of uncaching, which would allow us to flush all the LLC-cached data |
| 3470 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. |
| 3471 | */ |
| 3472 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); |
| 3473 | if (ret) |
| 3474 | return ret; |
| 3475 | |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3476 | /* As the user may map the buffer once pinned in the display plane |
| 3477 | * (e.g. libkms for the bootup splash), we have to ensure that we |
| 3478 | * always use map_and_fenceable for all scanout buffers. |
| 3479 | */ |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 3480 | ret = i915_gem_object_pin(obj, alignment, true, false); |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3481 | if (ret) |
| 3482 | return ret; |
| 3483 | |
Chris Wilson | b118c1e | 2010-05-27 13:18:14 +0100 | [diff] [blame] | 3484 | i915_gem_object_flush_cpu_write_domain(obj); |
| 3485 | |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3486 | old_write_domain = obj->base.write_domain; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3487 | old_read_domains = obj->base.read_domains; |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3488 | |
| 3489 | /* It should now be out of any other write domains, and we can update |
| 3490 | * the domain values for our changes. |
| 3491 | */ |
Chris Wilson | e5f1d96 | 2012-07-20 12:41:00 +0100 | [diff] [blame] | 3492 | obj->base.write_domain = 0; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3493 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3494 | |
| 3495 | trace_i915_gem_object_change_domain(obj, |
| 3496 | old_read_domains, |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3497 | old_write_domain); |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3498 | |
| 3499 | return 0; |
| 3500 | } |
| 3501 | |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3502 | int |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 3503 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3504 | { |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3505 | int ret; |
| 3506 | |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 3507 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3508 | return 0; |
| 3509 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 3510 | ret = i915_gem_object_wait_rendering(obj, false); |
Chris Wilson | c501ae7 | 2011-12-14 13:57:23 +0100 | [diff] [blame] | 3511 | if (ret) |
| 3512 | return ret; |
| 3513 | |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 3514 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
| 3515 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
Chris Wilson | c501ae7 | 2011-12-14 13:57:23 +0100 | [diff] [blame] | 3516 | return 0; |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3517 | } |
| 3518 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3519 | /** |
| 3520 | * Moves a single object to the CPU read, and possibly write domain. |
| 3521 | * |
| 3522 | * This function returns when the move is complete, including waiting on |
| 3523 | * flushes to occur. |
| 3524 | */ |
Chris Wilson | dabdfe0 | 2012-03-26 10:10:27 +0200 | [diff] [blame] | 3525 | int |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 3526 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3527 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3528 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3529 | int ret; |
| 3530 | |
Chris Wilson | 8d7e3de | 2011-02-07 15:23:02 +0000 | [diff] [blame] | 3531 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
| 3532 | return 0; |
| 3533 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 3534 | ret = i915_gem_object_wait_rendering(obj, !write); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3535 | if (ret) |
| 3536 | return ret; |
| 3537 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3538 | i915_gem_object_flush_gtt_write_domain(obj); |
| 3539 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3540 | old_write_domain = obj->base.write_domain; |
| 3541 | old_read_domains = obj->base.read_domains; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3542 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3543 | /* Flush the CPU cache if it's still invalid. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3544 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3545 | i915_gem_clflush_object(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3546 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3547 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3548 | } |
| 3549 | |
| 3550 | /* It should now be out of any other write domains, and we can update |
| 3551 | * the domain values for our changes. |
| 3552 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3553 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3554 | |
| 3555 | /* If we're writing through the CPU, then the GPU read domains will |
| 3556 | * need to be invalidated at next use. |
| 3557 | */ |
| 3558 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3559 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 3560 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3561 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3562 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3563 | trace_i915_gem_object_change_domain(obj, |
| 3564 | old_read_domains, |
| 3565 | old_write_domain); |
| 3566 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3567 | return 0; |
| 3568 | } |
| 3569 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3570 | /* Throttle our rendering by waiting until the ring has completed our requests |
| 3571 | * emitted over 20 msec ago. |
| 3572 | * |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3573 | * Note that if we were to use the current jiffies each time around the loop, |
| 3574 | * we wouldn't escape the function with any frames outstanding if the time to |
| 3575 | * render a frame was over 20ms. |
| 3576 | * |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3577 | * This should get us reasonable parallelism between CPU and GPU but also |
| 3578 | * relatively low latency when blocking on a particular request to finish. |
| 3579 | */ |
| 3580 | static int |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3581 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3582 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3583 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3584 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3585 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3586 | struct drm_i915_gem_request *request; |
| 3587 | struct intel_ring_buffer *ring = NULL; |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 3588 | unsigned reset_counter; |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3589 | u32 seqno = 0; |
| 3590 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3591 | |
Daniel Vetter | 308887a | 2012-11-14 17:14:06 +0100 | [diff] [blame] | 3592 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
| 3593 | if (ret) |
| 3594 | return ret; |
| 3595 | |
| 3596 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); |
| 3597 | if (ret) |
| 3598 | return ret; |
Chris Wilson | e110e8d | 2011-01-26 15:39:14 +0000 | [diff] [blame] | 3599 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3600 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3601 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3602 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
| 3603 | break; |
| 3604 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3605 | ring = request->ring; |
| 3606 | seqno = request->seqno; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3607 | } |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 3608 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3609 | spin_unlock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3610 | |
| 3611 | if (seqno == 0) |
| 3612 | return 0; |
| 3613 | |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 3614 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3615 | if (ret == 0) |
| 3616 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3617 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3618 | return ret; |
| 3619 | } |
| 3620 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3621 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3622 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
| 3623 | uint32_t alignment, |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 3624 | bool map_and_fenceable, |
| 3625 | bool nonblocking) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3626 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3627 | int ret; |
| 3628 | |
Chris Wilson | 7e81a42 | 2012-09-15 09:41:57 +0100 | [diff] [blame] | 3629 | if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
| 3630 | return -EBUSY; |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 3631 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3632 | if (i915_gem_obj_ggtt_bound(obj)) { |
| 3633 | if ((alignment && i915_gem_obj_ggtt_offset(obj) & (alignment - 1)) || |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3634 | (map_and_fenceable && !obj->map_and_fenceable)) { |
| 3635 | WARN(obj->pin_count, |
Chris Wilson | ae7d49d | 2010-08-04 12:37:41 +0100 | [diff] [blame] | 3636 | "bo is already pinned with incorrect alignment:" |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3637 | " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3638 | " obj->map_and_fenceable=%d\n", |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3639 | i915_gem_obj_ggtt_offset(obj), alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3640 | map_and_fenceable, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3641 | obj->map_and_fenceable); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 3642 | ret = i915_gem_object_unbind(obj); |
| 3643 | if (ret) |
| 3644 | return ret; |
| 3645 | } |
| 3646 | } |
| 3647 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3648 | if (!i915_gem_obj_ggtt_bound(obj)) { |
Chris Wilson | 8742267 | 2012-11-21 13:04:03 +0000 | [diff] [blame] | 3649 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 3650 | |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 3651 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 3652 | map_and_fenceable, |
| 3653 | nonblocking); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 3654 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3655 | return ret; |
Chris Wilson | 8742267 | 2012-11-21 13:04:03 +0000 | [diff] [blame] | 3656 | |
| 3657 | if (!dev_priv->mm.aliasing_ppgtt) |
| 3658 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
Chris Wilson | 22c344e | 2009-02-11 14:26:45 +0000 | [diff] [blame] | 3659 | } |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3660 | |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 3661 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
| 3662 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
| 3663 | |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 3664 | obj->pin_count++; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 3665 | obj->pin_mappable |= map_and_fenceable; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3666 | |
| 3667 | return 0; |
| 3668 | } |
| 3669 | |
| 3670 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3671 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3672 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3673 | BUG_ON(obj->pin_count == 0); |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3674 | BUG_ON(!i915_gem_obj_ggtt_bound(obj)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3675 | |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 3676 | if (--obj->pin_count == 0) |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 3677 | obj->pin_mappable = false; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3678 | } |
| 3679 | |
| 3680 | int |
| 3681 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3682 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3683 | { |
| 3684 | struct drm_i915_gem_pin *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3685 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3686 | int ret; |
| 3687 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3688 | ret = i915_mutex_lock_interruptible(dev); |
| 3689 | if (ret) |
| 3690 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3691 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3692 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3693 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3694 | ret = -ENOENT; |
| 3695 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3696 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3697 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3698 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 3699 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3700 | ret = -EINVAL; |
| 3701 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3702 | } |
| 3703 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3704 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3705 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
| 3706 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3707 | ret = -EINVAL; |
| 3708 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3709 | } |
| 3710 | |
Chris Wilson | 93be878 | 2013-01-02 10:31:22 +0000 | [diff] [blame] | 3711 | if (obj->user_pin_count == 0) { |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 3712 | ret = i915_gem_object_pin(obj, args->alignment, true, false); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3713 | if (ret) |
| 3714 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3715 | } |
| 3716 | |
Chris Wilson | 93be878 | 2013-01-02 10:31:22 +0000 | [diff] [blame] | 3717 | obj->user_pin_count++; |
| 3718 | obj->pin_filp = file; |
| 3719 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3720 | /* XXX - flush the CPU caches for pinned objects |
| 3721 | * as the X server doesn't manage domains yet |
| 3722 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3723 | i915_gem_object_flush_cpu_write_domain(obj); |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3724 | args->offset = i915_gem_obj_ggtt_offset(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3725 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3726 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3727 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3728 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3729 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3730 | } |
| 3731 | |
| 3732 | int |
| 3733 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3734 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3735 | { |
| 3736 | struct drm_i915_gem_pin *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3737 | struct drm_i915_gem_object *obj; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3738 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3739 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3740 | ret = i915_mutex_lock_interruptible(dev); |
| 3741 | if (ret) |
| 3742 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3743 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3744 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3745 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3746 | ret = -ENOENT; |
| 3747 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3748 | } |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3749 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3750 | if (obj->pin_filp != file) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3751 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
| 3752 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3753 | ret = -EINVAL; |
| 3754 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3755 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3756 | obj->user_pin_count--; |
| 3757 | if (obj->user_pin_count == 0) { |
| 3758 | obj->pin_filp = NULL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3759 | i915_gem_object_unpin(obj); |
| 3760 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3761 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3762 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3763 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3764 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3765 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3766 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3767 | } |
| 3768 | |
| 3769 | int |
| 3770 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3771 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3772 | { |
| 3773 | struct drm_i915_gem_busy *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3774 | struct drm_i915_gem_object *obj; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 3775 | int ret; |
| 3776 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3777 | ret = i915_mutex_lock_interruptible(dev); |
| 3778 | if (ret) |
| 3779 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3780 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3781 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3782 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3783 | ret = -ENOENT; |
| 3784 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3785 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3786 | |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 3787 | /* Count all active objects as busy, even if they are currently not used |
| 3788 | * by the gpu. Users of this interface expect objects to eventually |
| 3789 | * become non-busy without any further actions, therefore emit any |
| 3790 | * necessary flushes here. |
Eric Anholt | c4de0a5 | 2008-12-14 19:05:04 -0800 | [diff] [blame] | 3791 | */ |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 3792 | ret = i915_gem_object_flush_active(obj); |
| 3793 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3794 | args->busy = obj->active; |
Chris Wilson | e9808ed | 2012-07-04 12:25:08 +0100 | [diff] [blame] | 3795 | if (obj->ring) { |
| 3796 | BUILD_BUG_ON(I915_NUM_RINGS > 16); |
| 3797 | args->busy |= intel_ring_flag(obj->ring) << 16; |
| 3798 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3799 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3800 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3801 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3802 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3803 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3804 | } |
| 3805 | |
| 3806 | int |
| 3807 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 3808 | struct drm_file *file_priv) |
| 3809 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 3810 | return i915_gem_ring_throttle(dev, file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3811 | } |
| 3812 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3813 | int |
| 3814 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 3815 | struct drm_file *file_priv) |
| 3816 | { |
| 3817 | struct drm_i915_gem_madvise *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3818 | struct drm_i915_gem_object *obj; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3819 | int ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3820 | |
| 3821 | switch (args->madv) { |
| 3822 | case I915_MADV_DONTNEED: |
| 3823 | case I915_MADV_WILLNEED: |
| 3824 | break; |
| 3825 | default: |
| 3826 | return -EINVAL; |
| 3827 | } |
| 3828 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3829 | ret = i915_mutex_lock_interruptible(dev); |
| 3830 | if (ret) |
| 3831 | return ret; |
| 3832 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3833 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3834 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3835 | ret = -ENOENT; |
| 3836 | goto unlock; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3837 | } |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3838 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3839 | if (obj->pin_count) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3840 | ret = -EINVAL; |
| 3841 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3842 | } |
| 3843 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3844 | if (obj->madv != __I915_MADV_PURGED) |
| 3845 | obj->madv = args->madv; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3846 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 3847 | /* if the object is no longer attached, discard its backing storage */ |
| 3848 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame] | 3849 | i915_gem_object_truncate(obj); |
| 3850 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3851 | args->retained = obj->madv != __I915_MADV_PURGED; |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 3852 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3853 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3854 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3855 | unlock: |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3856 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3857 | return ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3858 | } |
| 3859 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 3860 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
| 3861 | const struct drm_i915_gem_object_ops *ops) |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 3862 | { |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 3863 | INIT_LIST_HEAD(&obj->mm_list); |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 3864 | INIT_LIST_HEAD(&obj->global_list); |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 3865 | INIT_LIST_HEAD(&obj->ring_list); |
| 3866 | INIT_LIST_HEAD(&obj->exec_list); |
| 3867 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 3868 | obj->ops = ops; |
| 3869 | |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 3870 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 3871 | obj->madv = I915_MADV_WILLNEED; |
| 3872 | /* Avoid an unnecessary call to unbind on the first bind. */ |
| 3873 | obj->map_and_fenceable = true; |
| 3874 | |
| 3875 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); |
| 3876 | } |
| 3877 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 3878 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
| 3879 | .get_pages = i915_gem_object_get_pages_gtt, |
| 3880 | .put_pages = i915_gem_object_put_pages_gtt, |
| 3881 | }; |
| 3882 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3883 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
| 3884 | size_t size) |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 3885 | { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3886 | struct drm_i915_gem_object *obj; |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 3887 | struct address_space *mapping; |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 3888 | gfp_t mask; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3889 | |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 3890 | obj = i915_gem_object_alloc(dev); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3891 | if (obj == NULL) |
| 3892 | return NULL; |
| 3893 | |
| 3894 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 3895 | i915_gem_object_free(obj); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3896 | return NULL; |
| 3897 | } |
| 3898 | |
Chris Wilson | bed1ea9 | 2012-05-24 20:48:12 +0100 | [diff] [blame] | 3899 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
| 3900 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { |
| 3901 | /* 965gm cannot relocate objects above 4GiB. */ |
| 3902 | mask &= ~__GFP_HIGHMEM; |
| 3903 | mask |= __GFP_DMA32; |
| 3904 | } |
| 3905 | |
Al Viro | 496ad9a | 2013-01-23 17:07:38 -0500 | [diff] [blame] | 3906 | mapping = file_inode(obj->base.filp)->i_mapping; |
Chris Wilson | bed1ea9 | 2012-05-24 20:48:12 +0100 | [diff] [blame] | 3907 | mapping_set_gfp_mask(mapping, mask); |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 3908 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 3909 | i915_gem_object_init(obj, &i915_gem_object_ops); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 3910 | |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3911 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 3912 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 3913 | |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 3914 | if (HAS_LLC(dev)) { |
| 3915 | /* On some devices, we can have the GPU use the LLC (the CPU |
Eric Anholt | a187111 | 2011-03-29 16:59:55 -0700 | [diff] [blame] | 3916 | * cache) for about a 10% performance improvement |
| 3917 | * compared to uncached. Graphics requests other than |
| 3918 | * display scanout are coherent with the CPU in |
| 3919 | * accessing this cache. This means in this mode we |
| 3920 | * don't need to clflush on the CPU side, and on the |
| 3921 | * GPU side we only need to flush internal caches to |
| 3922 | * get data visible to the CPU. |
| 3923 | * |
| 3924 | * However, we maintain the display planes as UC, and so |
| 3925 | * need to rebind when first used as such. |
| 3926 | */ |
| 3927 | obj->cache_level = I915_CACHE_LLC; |
| 3928 | } else |
| 3929 | obj->cache_level = I915_CACHE_NONE; |
| 3930 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3931 | return obj; |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 3932 | } |
| 3933 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3934 | int i915_gem_init_object(struct drm_gem_object *obj) |
| 3935 | { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3936 | BUG(); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3937 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3938 | return 0; |
| 3939 | } |
| 3940 | |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 3941 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3942 | { |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 3943 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3944 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3945 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3946 | |
Chris Wilson | 26e12f89 | 2011-03-20 11:20:19 +0000 | [diff] [blame] | 3947 | trace_i915_gem_object_destroy(obj); |
| 3948 | |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 3949 | if (obj->phys_obj) |
| 3950 | i915_gem_detach_phys_object(dev, obj); |
| 3951 | |
| 3952 | obj->pin_count = 0; |
| 3953 | if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) { |
| 3954 | bool was_interruptible; |
| 3955 | |
| 3956 | was_interruptible = dev_priv->mm.interruptible; |
| 3957 | dev_priv->mm.interruptible = false; |
| 3958 | |
| 3959 | WARN_ON(i915_gem_object_unbind(obj)); |
| 3960 | |
| 3961 | dev_priv->mm.interruptible = was_interruptible; |
| 3962 | } |
| 3963 | |
Ben Widawsky | 1d64ae7 | 2013-05-31 14:46:20 -0700 | [diff] [blame] | 3964 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
| 3965 | * before progressing. */ |
| 3966 | if (obj->stolen) |
| 3967 | i915_gem_object_unpin_pages(obj); |
| 3968 | |
Ben Widawsky | 401c29f | 2013-05-31 11:28:47 -0700 | [diff] [blame] | 3969 | if (WARN_ON(obj->pages_pin_count)) |
| 3970 | obj->pages_pin_count = 0; |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 3971 | i915_gem_object_put_pages(obj); |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 3972 | i915_gem_object_free_mmap_offset(obj); |
Chris Wilson | 0104fdb | 2012-11-15 11:32:26 +0000 | [diff] [blame] | 3973 | i915_gem_object_release_stolen(obj); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3974 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 3975 | BUG_ON(obj->pages); |
| 3976 | |
Chris Wilson | 2f745ad | 2012-09-04 21:02:58 +0100 | [diff] [blame] | 3977 | if (obj->base.import_attach) |
| 3978 | drm_prime_gem_destroy(&obj->base, NULL); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3979 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3980 | drm_gem_object_release(&obj->base); |
| 3981 | i915_gem_info_remove_obj(dev_priv, obj->base.size); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3982 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3983 | kfree(obj->bit_17); |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 3984 | i915_gem_object_free(obj); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3985 | } |
| 3986 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 3987 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3988 | i915_gem_idle(struct drm_device *dev) |
| 3989 | { |
| 3990 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3991 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3992 | |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 3993 | if (dev_priv->ums.mm_suspended) { |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3994 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3995 | return 0; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3996 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3997 | |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 3998 | ret = i915_gpu_idle(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3999 | if (ret) { |
| 4000 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4001 | return ret; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4002 | } |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 4003 | i915_gem_retire_requests(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4004 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4005 | /* Under UMS, be paranoid and evict. */ |
Chris Wilson | a39d7ef | 2012-04-24 18:22:52 +0100 | [diff] [blame] | 4006 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4007 | i915_gem_evict_everything(dev); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4008 | |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 4009 | i915_gem_reset_fences(dev); |
| 4010 | |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 4011 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4012 | |
| 4013 | i915_kernel_lost_context(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4014 | i915_gem_cleanup_ringbuffer(dev); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4015 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4016 | /* Cancel the retire work handler, which should be idle now. */ |
| 4017 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
| 4018 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4019 | return 0; |
| 4020 | } |
| 4021 | |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4022 | void i915_gem_l3_remap(struct drm_device *dev) |
| 4023 | { |
| 4024 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4025 | u32 misccpctl; |
| 4026 | int i; |
| 4027 | |
Daniel Vetter | eb32e45 | 2013-02-14 19:46:07 +0100 | [diff] [blame] | 4028 | if (!HAS_L3_GPU_CACHE(dev)) |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4029 | return; |
| 4030 | |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 4031 | if (!dev_priv->l3_parity.remap_info) |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4032 | return; |
| 4033 | |
| 4034 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
| 4035 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); |
| 4036 | POSTING_READ(GEN7_MISCCPCTL); |
| 4037 | |
| 4038 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { |
| 4039 | u32 remap = I915_READ(GEN7_L3LOG_BASE + i); |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 4040 | if (remap && remap != dev_priv->l3_parity.remap_info[i/4]) |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4041 | DRM_DEBUG("0x%x was already programmed to %x\n", |
| 4042 | GEN7_L3LOG_BASE + i, remap); |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 4043 | if (remap && !dev_priv->l3_parity.remap_info[i/4]) |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4044 | DRM_DEBUG_DRIVER("Clearing remapped register\n"); |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 4045 | I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]); |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4046 | } |
| 4047 | |
| 4048 | /* Make sure all the writes land before disabling dop clock gating */ |
| 4049 | POSTING_READ(GEN7_L3LOG_BASE); |
| 4050 | |
| 4051 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
| 4052 | } |
| 4053 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4054 | void i915_gem_init_swizzling(struct drm_device *dev) |
| 4055 | { |
| 4056 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4057 | |
Daniel Vetter | 11782b0 | 2012-01-31 16:47:55 +0100 | [diff] [blame] | 4058 | if (INTEL_INFO(dev)->gen < 5 || |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4059 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
| 4060 | return; |
| 4061 | |
| 4062 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | |
| 4063 | DISP_TILE_SURFACE_SWIZZLING); |
| 4064 | |
Daniel Vetter | 11782b0 | 2012-01-31 16:47:55 +0100 | [diff] [blame] | 4065 | if (IS_GEN5(dev)) |
| 4066 | return; |
| 4067 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4068 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
| 4069 | if (IS_GEN6(dev)) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 4070 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
Ben Widawsky | 8782e26 | 2012-12-18 10:31:23 -0800 | [diff] [blame] | 4071 | else if (IS_GEN7(dev)) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 4072 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
Ben Widawsky | 8782e26 | 2012-12-18 10:31:23 -0800 | [diff] [blame] | 4073 | else |
| 4074 | BUG(); |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4075 | } |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 4076 | |
Chris Wilson | 67b1b57 | 2012-07-05 23:49:40 +0100 | [diff] [blame] | 4077 | static bool |
| 4078 | intel_enable_blt(struct drm_device *dev) |
| 4079 | { |
| 4080 | if (!HAS_BLT(dev)) |
| 4081 | return false; |
| 4082 | |
| 4083 | /* The blitter was dysfunctional on early prototypes */ |
| 4084 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { |
| 4085 | DRM_INFO("BLT not supported on this pre-production hardware;" |
| 4086 | " graphics performance will be degraded.\n"); |
| 4087 | return false; |
| 4088 | } |
| 4089 | |
| 4090 | return true; |
| 4091 | } |
| 4092 | |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4093 | static int i915_gem_init_rings(struct drm_device *dev) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4094 | { |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4095 | struct drm_i915_private *dev_priv = dev->dev_private; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4096 | int ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4097 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 4098 | ret = intel_init_render_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4099 | if (ret) |
Chris Wilson | b6913e4 | 2010-11-12 10:46:37 +0000 | [diff] [blame] | 4100 | return ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4101 | |
| 4102 | if (HAS_BSD(dev)) { |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 4103 | ret = intel_init_bsd_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4104 | if (ret) |
| 4105 | goto cleanup_render_ring; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4106 | } |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4107 | |
Chris Wilson | 67b1b57 | 2012-07-05 23:49:40 +0100 | [diff] [blame] | 4108 | if (intel_enable_blt(dev)) { |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 4109 | ret = intel_init_blt_ring_buffer(dev); |
| 4110 | if (ret) |
| 4111 | goto cleanup_bsd_ring; |
| 4112 | } |
| 4113 | |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 4114 | if (HAS_VEBOX(dev)) { |
| 4115 | ret = intel_init_vebox_ring_buffer(dev); |
| 4116 | if (ret) |
| 4117 | goto cleanup_blt_ring; |
| 4118 | } |
| 4119 | |
| 4120 | |
Mika Kuoppala | 9943393 | 2013-01-22 14:12:17 +0200 | [diff] [blame] | 4121 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
| 4122 | if (ret) |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 4123 | goto cleanup_vebox_ring; |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4124 | |
| 4125 | return 0; |
| 4126 | |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 4127 | cleanup_vebox_ring: |
| 4128 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4129 | cleanup_blt_ring: |
| 4130 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); |
| 4131 | cleanup_bsd_ring: |
| 4132 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
| 4133 | cleanup_render_ring: |
| 4134 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
| 4135 | |
| 4136 | return ret; |
| 4137 | } |
| 4138 | |
| 4139 | int |
| 4140 | i915_gem_init_hw(struct drm_device *dev) |
| 4141 | { |
| 4142 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4143 | int ret; |
| 4144 | |
| 4145 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) |
| 4146 | return -EIO; |
| 4147 | |
Ben Widawsky | 5912450 | 2013-07-04 11:02:05 -0700 | [diff] [blame] | 4148 | if (dev_priv->ellc_size) |
Ben Widawsky | 05e21cc | 2013-07-04 11:02:04 -0700 | [diff] [blame] | 4149 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4150 | |
Ben Widawsky | 88a2b2a | 2013-04-05 13:12:43 -0700 | [diff] [blame] | 4151 | if (HAS_PCH_NOP(dev)) { |
| 4152 | u32 temp = I915_READ(GEN7_MSG_CTL); |
| 4153 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); |
| 4154 | I915_WRITE(GEN7_MSG_CTL, temp); |
| 4155 | } |
| 4156 | |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4157 | i915_gem_l3_remap(dev); |
| 4158 | |
| 4159 | i915_gem_init_swizzling(dev); |
| 4160 | |
| 4161 | ret = i915_gem_init_rings(dev); |
| 4162 | if (ret) |
Mika Kuoppala | 9943393 | 2013-01-22 14:12:17 +0200 | [diff] [blame] | 4163 | return ret; |
| 4164 | |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 4165 | /* |
| 4166 | * XXX: There was some w/a described somewhere suggesting loading |
| 4167 | * contexts before PPGTT. |
| 4168 | */ |
| 4169 | i915_gem_context_init(dev); |
Ben Widawsky | b7c36d2 | 2013-04-08 18:43:56 -0700 | [diff] [blame] | 4170 | if (dev_priv->mm.aliasing_ppgtt) { |
| 4171 | ret = dev_priv->mm.aliasing_ppgtt->enable(dev); |
| 4172 | if (ret) { |
| 4173 | i915_gem_cleanup_aliasing_ppgtt(dev); |
| 4174 | DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n"); |
| 4175 | } |
| 4176 | } |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 4177 | |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4178 | return 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4179 | } |
| 4180 | |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4181 | int i915_gem_init(struct drm_device *dev) |
| 4182 | { |
| 4183 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4184 | int ret; |
| 4185 | |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4186 | mutex_lock(&dev->struct_mutex); |
Jesse Barnes | d62b489 | 2013-03-08 10:45:53 -0800 | [diff] [blame] | 4187 | |
| 4188 | if (IS_VALLEYVIEW(dev)) { |
| 4189 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ |
| 4190 | I915_WRITE(VLV_GTLC_WAKE_CTRL, 1); |
| 4191 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10)) |
| 4192 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); |
| 4193 | } |
| 4194 | |
Ben Widawsky | d7e5008 | 2012-12-18 10:31:25 -0800 | [diff] [blame] | 4195 | i915_gem_init_global_gtt(dev); |
Jesse Barnes | d62b489 | 2013-03-08 10:45:53 -0800 | [diff] [blame] | 4196 | |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4197 | ret = i915_gem_init_hw(dev); |
| 4198 | mutex_unlock(&dev->struct_mutex); |
| 4199 | if (ret) { |
| 4200 | i915_gem_cleanup_aliasing_ppgtt(dev); |
| 4201 | return ret; |
| 4202 | } |
| 4203 | |
Daniel Vetter | 53ca26c | 2012-04-26 23:28:03 +0200 | [diff] [blame] | 4204 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
| 4205 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4206 | dev_priv->dri1.allow_batchbuffer = 1; |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4207 | return 0; |
| 4208 | } |
| 4209 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4210 | void |
| 4211 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
| 4212 | { |
| 4213 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 4214 | struct intel_ring_buffer *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 4215 | int i; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4216 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 4217 | for_each_ring(ring, dev_priv, i) |
| 4218 | intel_cleanup_ring_buffer(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4219 | } |
| 4220 | |
| 4221 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4222 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
| 4223 | struct drm_file *file_priv) |
| 4224 | { |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 4225 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 4226 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4227 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4228 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4229 | return 0; |
| 4230 | |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 4231 | if (i915_reset_in_progress(&dev_priv->gpu_error)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4232 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 4233 | atomic_set(&dev_priv->gpu_error.reset_counter, 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4234 | } |
| 4235 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4236 | mutex_lock(&dev->struct_mutex); |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 4237 | dev_priv->ums.mm_suspended = 0; |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4238 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4239 | ret = i915_gem_init_hw(dev); |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 4240 | if (ret != 0) { |
| 4241 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4242 | return ret; |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 4243 | } |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4244 | |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4245 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4246 | mutex_unlock(&dev->struct_mutex); |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4247 | |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 4248 | ret = drm_irq_install(dev); |
| 4249 | if (ret) |
| 4250 | goto cleanup_ringbuffer; |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4251 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4252 | return 0; |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 4253 | |
| 4254 | cleanup_ringbuffer: |
| 4255 | mutex_lock(&dev->struct_mutex); |
| 4256 | i915_gem_cleanup_ringbuffer(dev); |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 4257 | dev_priv->ums.mm_suspended = 1; |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 4258 | mutex_unlock(&dev->struct_mutex); |
| 4259 | |
| 4260 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4261 | } |
| 4262 | |
| 4263 | int |
| 4264 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
| 4265 | struct drm_file *file_priv) |
| 4266 | { |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 4267 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4268 | int ret; |
| 4269 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4270 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4271 | return 0; |
| 4272 | |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4273 | drm_irq_uninstall(dev); |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 4274 | |
| 4275 | mutex_lock(&dev->struct_mutex); |
| 4276 | ret = i915_gem_idle(dev); |
| 4277 | |
| 4278 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
| 4279 | * We need to replace this with a semaphore, or something. |
| 4280 | * And not confound ums.mm_suspended! |
| 4281 | */ |
| 4282 | if (ret != 0) |
| 4283 | dev_priv->ums.mm_suspended = 1; |
| 4284 | mutex_unlock(&dev->struct_mutex); |
| 4285 | |
| 4286 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4287 | } |
| 4288 | |
| 4289 | void |
| 4290 | i915_gem_lastclose(struct drm_device *dev) |
| 4291 | { |
| 4292 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4293 | |
Eric Anholt | e806b49 | 2009-01-22 09:56:58 -0800 | [diff] [blame] | 4294 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4295 | return; |
| 4296 | |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 4297 | mutex_lock(&dev->struct_mutex); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4298 | ret = i915_gem_idle(dev); |
| 4299 | if (ret) |
| 4300 | DRM_ERROR("failed to idle hardware: %d\n", ret); |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 4301 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4302 | } |
| 4303 | |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 4304 | static void |
| 4305 | init_ring_lists(struct intel_ring_buffer *ring) |
| 4306 | { |
| 4307 | INIT_LIST_HEAD(&ring->active_list); |
| 4308 | INIT_LIST_HEAD(&ring->request_list); |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 4309 | } |
| 4310 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4311 | void |
| 4312 | i915_gem_load(struct drm_device *dev) |
| 4313 | { |
| 4314 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 4315 | int i; |
| 4316 | |
| 4317 | dev_priv->slab = |
| 4318 | kmem_cache_create("i915_gem_object", |
| 4319 | sizeof(struct drm_i915_gem_object), 0, |
| 4320 | SLAB_HWCACHE_ALIGN, |
| 4321 | NULL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4322 | |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4323 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4324 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4325 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
| 4326 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 4327 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 4328 | for (i = 0; i < I915_NUM_RINGS; i++) |
| 4329 | init_ring_lists(&dev_priv->ring[i]); |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 4330 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 4331 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4332 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
| 4333 | i915_gem_retire_work_handler); |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 4334 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4335 | |
Dave Airlie | 9440012 | 2010-07-20 13:15:31 +1000 | [diff] [blame] | 4336 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
| 4337 | if (IS_GEN3(dev)) { |
Daniel Vetter | 5074329 | 2012-04-26 22:02:54 +0200 | [diff] [blame] | 4338 | I915_WRITE(MI_ARB_STATE, |
| 4339 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); |
Dave Airlie | 9440012 | 2010-07-20 13:15:31 +1000 | [diff] [blame] | 4340 | } |
| 4341 | |
Chris Wilson | 72bfa19 | 2010-12-19 11:42:05 +0000 | [diff] [blame] | 4342 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
| 4343 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4344 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
Eric Anholt | b397c83 | 2010-01-26 09:43:10 -0800 | [diff] [blame] | 4345 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4346 | dev_priv->fence_reg_start = 3; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4347 | |
Ville Syrjälä | 42b5aea | 2013-04-09 13:02:47 +0300 | [diff] [blame] | 4348 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
| 4349 | dev_priv->num_fence_regs = 32; |
| 4350 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4351 | dev_priv->num_fence_regs = 16; |
| 4352 | else |
| 4353 | dev_priv->num_fence_regs = 8; |
| 4354 | |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4355 | /* Initialize fence registers to zero */ |
Chris Wilson | ada726c | 2012-04-17 15:31:32 +0100 | [diff] [blame] | 4356 | i915_gem_reset_fences(dev); |
Eric Anholt | 10ed13e | 2011-05-06 13:53:49 -0700 | [diff] [blame] | 4357 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4358 | i915_gem_detect_bit_6_swizzle(dev); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4359 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4360 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 4361 | dev_priv->mm.interruptible = true; |
| 4362 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4363 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
| 4364 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; |
| 4365 | register_shrinker(&dev_priv->mm.inactive_shrinker); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4366 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4367 | |
| 4368 | /* |
| 4369 | * Create a physically contiguous memory object for this object |
| 4370 | * e.g. for cursor + overlay regs |
| 4371 | */ |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 4372 | static int i915_gem_init_phys_object(struct drm_device *dev, |
| 4373 | int id, int size, int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4374 | { |
| 4375 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4376 | struct drm_i915_gem_phys_object *phys_obj; |
| 4377 | int ret; |
| 4378 | |
| 4379 | if (dev_priv->mm.phys_objs[id - 1] || !size) |
| 4380 | return 0; |
| 4381 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4382 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4383 | if (!phys_obj) |
| 4384 | return -ENOMEM; |
| 4385 | |
| 4386 | phys_obj->id = id; |
| 4387 | |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4388 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4389 | if (!phys_obj->handle) { |
| 4390 | ret = -ENOMEM; |
| 4391 | goto kfree_obj; |
| 4392 | } |
| 4393 | #ifdef CONFIG_X86 |
| 4394 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 4395 | #endif |
| 4396 | |
| 4397 | dev_priv->mm.phys_objs[id - 1] = phys_obj; |
| 4398 | |
| 4399 | return 0; |
| 4400 | kfree_obj: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4401 | kfree(phys_obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4402 | return ret; |
| 4403 | } |
| 4404 | |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 4405 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4406 | { |
| 4407 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4408 | struct drm_i915_gem_phys_object *phys_obj; |
| 4409 | |
| 4410 | if (!dev_priv->mm.phys_objs[id - 1]) |
| 4411 | return; |
| 4412 | |
| 4413 | phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 4414 | if (phys_obj->cur_obj) { |
| 4415 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); |
| 4416 | } |
| 4417 | |
| 4418 | #ifdef CONFIG_X86 |
| 4419 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 4420 | #endif |
| 4421 | drm_pci_free(dev, phys_obj->handle); |
| 4422 | kfree(phys_obj); |
| 4423 | dev_priv->mm.phys_objs[id - 1] = NULL; |
| 4424 | } |
| 4425 | |
| 4426 | void i915_gem_free_all_phys_object(struct drm_device *dev) |
| 4427 | { |
| 4428 | int i; |
| 4429 | |
Dave Airlie | 260883c | 2009-01-22 17:58:49 +1000 | [diff] [blame] | 4430 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4431 | i915_gem_free_phys_object(dev, i); |
| 4432 | } |
| 4433 | |
| 4434 | void i915_gem_detach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4435 | struct drm_i915_gem_object *obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4436 | { |
Al Viro | 496ad9a | 2013-01-23 17:07:38 -0500 | [diff] [blame] | 4437 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4438 | char *vaddr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4439 | int i; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4440 | int page_count; |
| 4441 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4442 | if (!obj->phys_obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4443 | return; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4444 | vaddr = obj->phys_obj->handle->vaddr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4445 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4446 | page_count = obj->base.size / PAGE_SIZE; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4447 | for (i = 0; i < page_count; i++) { |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 4448 | struct page *page = shmem_read_mapping_page(mapping, i); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4449 | if (!IS_ERR(page)) { |
| 4450 | char *dst = kmap_atomic(page); |
| 4451 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); |
| 4452 | kunmap_atomic(dst); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4453 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4454 | drm_clflush_pages(&page, 1); |
| 4455 | |
| 4456 | set_page_dirty(page); |
| 4457 | mark_page_accessed(page); |
| 4458 | page_cache_release(page); |
| 4459 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4460 | } |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 4461 | i915_gem_chipset_flush(dev); |
Chris Wilson | d78b47b | 2009-06-17 21:52:49 +0100 | [diff] [blame] | 4462 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4463 | obj->phys_obj->cur_obj = NULL; |
| 4464 | obj->phys_obj = NULL; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4465 | } |
| 4466 | |
| 4467 | int |
| 4468 | i915_gem_attach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4469 | struct drm_i915_gem_object *obj, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4470 | int id, |
| 4471 | int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4472 | { |
Al Viro | 496ad9a | 2013-01-23 17:07:38 -0500 | [diff] [blame] | 4473 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4474 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4475 | int ret = 0; |
| 4476 | int page_count; |
| 4477 | int i; |
| 4478 | |
| 4479 | if (id > I915_MAX_PHYS_OBJECT) |
| 4480 | return -EINVAL; |
| 4481 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4482 | if (obj->phys_obj) { |
| 4483 | if (obj->phys_obj->id == id) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4484 | return 0; |
| 4485 | i915_gem_detach_phys_object(dev, obj); |
| 4486 | } |
| 4487 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4488 | /* create a new object */ |
| 4489 | if (!dev_priv->mm.phys_objs[id - 1]) { |
| 4490 | ret = i915_gem_init_phys_object(dev, id, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4491 | obj->base.size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4492 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4493 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
| 4494 | id, obj->base.size); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4495 | return ret; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4496 | } |
| 4497 | } |
| 4498 | |
| 4499 | /* bind to the object */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4500 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 4501 | obj->phys_obj->cur_obj = obj; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4502 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4503 | page_count = obj->base.size / PAGE_SIZE; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4504 | |
| 4505 | for (i = 0; i < page_count; i++) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4506 | struct page *page; |
| 4507 | char *dst, *src; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4508 | |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 4509 | page = shmem_read_mapping_page(mapping, i); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4510 | if (IS_ERR(page)) |
| 4511 | return PTR_ERR(page); |
| 4512 | |
Chris Wilson | ff75b9b | 2010-10-30 22:52:31 +0100 | [diff] [blame] | 4513 | src = kmap_atomic(page); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4514 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4515 | memcpy(dst, src, PAGE_SIZE); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 4516 | kunmap_atomic(src); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4517 | |
| 4518 | mark_page_accessed(page); |
| 4519 | page_cache_release(page); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4520 | } |
| 4521 | |
| 4522 | return 0; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4523 | } |
| 4524 | |
| 4525 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4526 | i915_gem_phys_pwrite(struct drm_device *dev, |
| 4527 | struct drm_i915_gem_object *obj, |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4528 | struct drm_i915_gem_pwrite *args, |
| 4529 | struct drm_file *file_priv) |
| 4530 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4531 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 4532 | char __user *user_data = to_user_ptr(args->data_ptr); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4533 | |
Chris Wilson | b47b30c | 2010-11-08 01:12:29 +0000 | [diff] [blame] | 4534 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
| 4535 | unsigned long unwritten; |
| 4536 | |
| 4537 | /* The physical object once assigned is fixed for the lifetime |
| 4538 | * of the obj, so we can safely drop the lock and continue |
| 4539 | * to access vaddr. |
| 4540 | */ |
| 4541 | mutex_unlock(&dev->struct_mutex); |
| 4542 | unwritten = copy_from_user(vaddr, user_data, args->size); |
| 4543 | mutex_lock(&dev->struct_mutex); |
| 4544 | if (unwritten) |
| 4545 | return -EFAULT; |
| 4546 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4547 | |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 4548 | i915_gem_chipset_flush(dev); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4549 | return 0; |
| 4550 | } |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4551 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4552 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4553 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4554 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4555 | |
| 4556 | /* Clean up our request list when the client is going away, so that |
| 4557 | * later retire_requests won't dereference our soon-to-be-gone |
| 4558 | * file_priv. |
| 4559 | */ |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4560 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4561 | while (!list_empty(&file_priv->mm.request_list)) { |
| 4562 | struct drm_i915_gem_request *request; |
| 4563 | |
| 4564 | request = list_first_entry(&file_priv->mm.request_list, |
| 4565 | struct drm_i915_gem_request, |
| 4566 | client_list); |
| 4567 | list_del(&request->client_list); |
| 4568 | request->file_priv = NULL; |
| 4569 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4570 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4571 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4572 | |
Chris Wilson | 5774506 | 2012-11-21 13:04:04 +0000 | [diff] [blame] | 4573 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
| 4574 | { |
| 4575 | if (!mutex_is_locked(mutex)) |
| 4576 | return false; |
| 4577 | |
| 4578 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) |
| 4579 | return mutex->owner == task; |
| 4580 | #else |
| 4581 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ |
| 4582 | return false; |
| 4583 | #endif |
| 4584 | } |
| 4585 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4586 | static int |
Ying Han | 1495f23 | 2011-05-24 17:12:27 -0700 | [diff] [blame] | 4587 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4588 | { |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4589 | struct drm_i915_private *dev_priv = |
| 4590 | container_of(shrinker, |
| 4591 | struct drm_i915_private, |
| 4592 | mm.inactive_shrinker); |
| 4593 | struct drm_device *dev = dev_priv->dev; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4594 | struct drm_i915_gem_object *obj; |
Ying Han | 1495f23 | 2011-05-24 17:12:27 -0700 | [diff] [blame] | 4595 | int nr_to_scan = sc->nr_to_scan; |
Chris Wilson | 5774506 | 2012-11-21 13:04:04 +0000 | [diff] [blame] | 4596 | bool unlock = true; |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4597 | int cnt; |
| 4598 | |
Chris Wilson | 5774506 | 2012-11-21 13:04:04 +0000 | [diff] [blame] | 4599 | if (!mutex_trylock(&dev->struct_mutex)) { |
| 4600 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) |
| 4601 | return 0; |
| 4602 | |
Daniel Vetter | 677feac | 2012-12-19 14:33:45 +0100 | [diff] [blame] | 4603 | if (dev_priv->mm.shrinker_no_lock_stealing) |
| 4604 | return 0; |
| 4605 | |
Chris Wilson | 5774506 | 2012-11-21 13:04:04 +0000 | [diff] [blame] | 4606 | unlock = false; |
| 4607 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4608 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4609 | if (nr_to_scan) { |
| 4610 | nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan); |
| 4611 | if (nr_to_scan > 0) |
Daniel Vetter | 93927ca | 2013-01-10 18:03:00 +0100 | [diff] [blame] | 4612 | nr_to_scan -= __i915_gem_shrink(dev_priv, nr_to_scan, |
| 4613 | false); |
| 4614 | if (nr_to_scan > 0) |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4615 | i915_gem_shrink_all(dev_priv); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4616 | } |
| 4617 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4618 | cnt = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 4619 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 4620 | if (obj->pages_pin_count == 0) |
| 4621 | cnt += obj->base.size >> PAGE_SHIFT; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 4622 | list_for_each_entry(obj, &dev_priv->mm.inactive_list, global_list) |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 4623 | if (obj->pin_count == 0 && obj->pages_pin_count == 0) |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4624 | cnt += obj->base.size >> PAGE_SHIFT; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4625 | |
Chris Wilson | 5774506 | 2012-11-21 13:04:04 +0000 | [diff] [blame] | 4626 | if (unlock) |
| 4627 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4628 | return cnt; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4629 | } |