blob: 2a6412f5d117b9c61e66c13380a4045d5877f599 [file] [log] [blame]
Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
2 * pata_efar.c - EFAR PIIX clone controller driver
3 *
Alan Coxab771632008-10-27 15:09:10 +00004 * (C) 2005 Red Hat
Jeff Garzik669a5db2006-08-29 18:12:40 -04005 *
6 * Some parts based on ata_piix.c by Jeff Garzik and others.
7 *
8 * The EFAR is a PIIX4 clone with UDMA66 support. Unlike the later
9 * Intel ICH controllers the EFAR widened the UDMA mode register bits
10 * and doesn't require the funky clock selection.
11 */
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/pci.h>
16#include <linux/init.h>
17#include <linux/blkdev.h>
18#include <linux/delay.h>
19#include <linux/device.h>
20#include <scsi/scsi_host.h>
21#include <linux/libata.h>
22#include <linux/ata.h>
23
24#define DRV_NAME "pata_efar"
Sergei Shtylyov5f33b3b2009-06-01 22:42:10 +030025#define DRV_VERSION "0.4.5"
Jeff Garzik669a5db2006-08-29 18:12:40 -040026
27/**
Alan Cox6bfed3f2007-03-08 19:33:29 +000028 * efar_pre_reset - Enable bits
Tejun Heocc0680a2007-08-06 18:36:23 +090029 * @link: ATA link
Tejun Heod4b2bab2007-02-02 16:50:52 +090030 * @deadline: deadline jiffies for the operation
Jeff Garzik669a5db2006-08-29 18:12:40 -040031 *
32 * Perform cable detection for the EFAR ATA interface. This is
33 * different to the PIIX arrangement
34 */
35
Tejun Heocc0680a2007-08-06 18:36:23 +090036static int efar_pre_reset(struct ata_link *link, unsigned long deadline)
Jeff Garzik669a5db2006-08-29 18:12:40 -040037{
38 static const struct pci_bits efar_enable_bits[] = {
39 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
40 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
41 };
Tejun Heocc0680a2007-08-06 18:36:23 +090042 struct ata_port *ap = link->ap;
Jeff Garzik669a5db2006-08-29 18:12:40 -040043 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Jeff Garzik669a5db2006-08-29 18:12:40 -040044
Alan Coxc9619222006-09-26 17:53:38 +010045 if (!pci_test_config_bits(pdev, &efar_enable_bits[ap->port_no]))
46 return -ENOENT;
47
Tejun Heo9363c382008-04-07 22:47:16 +090048 return ata_sff_prereset(link, deadline);
Jeff Garzik669a5db2006-08-29 18:12:40 -040049}
50
51/**
Alan Cox6bfed3f2007-03-08 19:33:29 +000052 * efar_cable_detect - check for 40/80 pin
53 * @ap: Port
54 *
55 * Perform cable detection for the EFAR ATA interface. This is
56 * different to the PIIX arrangement
57 */
58
59static int efar_cable_detect(struct ata_port *ap)
60{
61 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
62 u8 tmp;
63
64 pci_read_config_byte(pdev, 0x47, &tmp);
65 if (tmp & (2 >> ap->port_no))
66 return ATA_CBL_PATA40;
67 return ATA_CBL_PATA80;
68}
69
70/**
Jeff Garzik669a5db2006-08-29 18:12:40 -040071 * efar_set_piomode - Initialize host controller PATA PIO timings
72 * @ap: Port whose timings we are configuring
73 * @adev: um
74 *
75 * Set PIO mode for device, in host controller PCI config space.
76 *
77 * LOCKING:
78 * None (inherited from caller).
79 */
80
81static void efar_set_piomode (struct ata_port *ap, struct ata_device *adev)
82{
83 unsigned int pio = adev->pio_mode - XFER_PIO_0;
84 struct pci_dev *dev = to_pci_dev(ap->host->dev);
85 unsigned int idetm_port= ap->port_no ? 0x42 : 0x40;
86 u16 idetm_data;
87 int control = 0;
88
89 /*
90 * See Intel Document 298600-004 for the timing programing rules
91 * for PIIX/ICH. The EFAR is a clone so very similar
92 */
93
94 static const /* ISP RTC */
95 u8 timings[][2] = { { 0, 0 },
96 { 0, 0 },
97 { 1, 0 },
98 { 2, 1 },
99 { 2, 3 }, };
100
Sergei Shtylyov5f33b3b2009-06-01 22:42:10 +0300101 if (pio > 1)
102 control |= 1; /* TIME */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400103 if (ata_pio_need_iordy(adev)) /* PIO 3/4 require IORDY */
Sergei Shtylyov5f33b3b2009-06-01 22:42:10 +0300104 control |= 2; /* IE */
105 /* Intel specifies that the prefetch/posting is for disk only */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400106 if (adev->class == ATA_DEV_ATA)
Sergei Shtylyov5f33b3b2009-06-01 22:42:10 +0300107 control |= 4; /* PPE */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400108
109 pci_read_config_word(dev, idetm_port, &idetm_data);
110
Sergei Shtylyov5f33b3b2009-06-01 22:42:10 +0300111 /* Set PPE, IE, and TIME as appropriate */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400112 if (adev->devno == 0) {
113 idetm_data &= 0xCCF0;
114 idetm_data |= control;
115 idetm_data |= (timings[pio][0] << 12) |
116 (timings[pio][1] << 8);
117 } else {
118 int shift = 4 * ap->port_no;
119 u8 slave_data;
120
121 idetm_data &= 0xCC0F;
122 idetm_data |= (control << 4);
123
Joe Perches1967b7f2008-02-03 17:08:11 +0200124 /* Slave timing in separate register */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400125 pci_read_config_byte(dev, 0x44, &slave_data);
126 slave_data &= 0x0F << shift;
127 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << shift;
128 pci_write_config_byte(dev, 0x44, slave_data);
129 }
130
Sergei Shtylyov5f33b3b2009-06-01 22:42:10 +0300131 idetm_data |= 0x4000; /* Ensure SITRE is set */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400132 pci_write_config_word(dev, idetm_port, idetm_data);
133}
134
135/**
136 * efar_set_dmamode - Initialize host controller PATA DMA timings
137 * @ap: Port whose timings we are configuring
138 * @adev: Device to program
139 *
140 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
141 *
142 * LOCKING:
143 * None (inherited from caller).
144 */
145
146static void efar_set_dmamode (struct ata_port *ap, struct ata_device *adev)
147{
148 struct pci_dev *dev = to_pci_dev(ap->host->dev);
149 u8 master_port = ap->port_no ? 0x42 : 0x40;
150 u16 master_data;
151 u8 speed = adev->dma_mode;
152 int devid = adev->devno + 2 * ap->port_no;
153 u8 udma_enable;
154
155 static const /* ISP RTC */
156 u8 timings[][2] = { { 0, 0 },
157 { 0, 0 },
158 { 1, 0 },
159 { 2, 1 },
160 { 2, 3 }, };
161
162 pci_read_config_word(dev, master_port, &master_data);
163 pci_read_config_byte(dev, 0x48, &udma_enable);
164
165 if (speed >= XFER_UDMA_0) {
166 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
167 u16 udma_timing;
168
169 udma_enable |= (1 << devid);
170
171 /* Load the UDMA mode number */
172 pci_read_config_word(dev, 0x4A, &udma_timing);
173 udma_timing &= ~(7 << (4 * devid));
174 udma_timing |= udma << (4 * devid);
175 pci_write_config_word(dev, 0x4A, udma_timing);
176 } else {
177 /*
178 * MWDMA is driven by the PIO timings. We must also enable
179 * IORDY unconditionally along with TIME1. PPE has already
180 * been set when the PIO timing was set.
181 */
182 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
183 unsigned int control;
184 u8 slave_data;
185 const unsigned int needed_pio[3] = {
186 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
187 };
188 int pio = needed_pio[mwdma] - XFER_PIO_0;
189
190 control = 3; /* IORDY|TIME1 */
191
192 /* If the drive MWDMA is faster than it can do PIO then
193 we must force PIO into PIO0 */
194
195 if (adev->pio_mode < needed_pio[mwdma])
196 /* Enable DMA timing only */
197 control |= 8; /* PIO cycles in PIO0 */
198
199 if (adev->devno) { /* Slave */
200 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
201 master_data |= control << 4;
202 pci_read_config_byte(dev, 0x44, &slave_data);
203 slave_data &= (0x0F + 0xE1 * ap->port_no);
204 /* Load the matching timing */
205 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
206 pci_write_config_byte(dev, 0x44, slave_data);
207 } else { /* Master */
208 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
209 and master timing bits */
210 master_data |= control;
211 master_data |=
212 (timings[pio][0] << 12) |
213 (timings[pio][1] << 8);
214 }
215 udma_enable &= ~(1 << devid);
216 pci_write_config_word(dev, master_port, master_data);
217 }
218 pci_write_config_byte(dev, 0x48, udma_enable);
219}
220
221static struct scsi_host_template efar_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900222 ATA_BMDMA_SHT(DRV_NAME),
Jeff Garzik669a5db2006-08-29 18:12:40 -0400223};
224
Tejun Heo029cfd62008-03-25 12:22:49 +0900225static struct ata_port_operations efar_ops = {
226 .inherits = &ata_bmdma_port_ops,
227 .cable_detect = efar_cable_detect,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400228 .set_piomode = efar_set_piomode,
229 .set_dmamode = efar_set_dmamode,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900230 .prereset = efar_pre_reset,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400231};
232
233
234/**
235 * efar_init_one - Register EFAR ATA PCI device with kernel services
236 * @pdev: PCI device to register
237 * @ent: Entry in efar_pci_tbl matching with @pdev
238 *
239 * Called from kernel PCI layer.
240 *
241 * LOCKING:
242 * Inherited from PCI layer (may sleep).
243 *
244 * RETURNS:
245 * Zero on success, or -ERRNO value.
246 */
247
248static int efar_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
249{
250 static int printed_version;
Tejun Heo1626aeb2007-05-04 12:43:58 +0200251 static const struct ata_port_info info = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400252 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100253 .pio_mask = ATA_PIO4,
Erik Inge Bolsøb2a034c2009-03-14 23:08:20 +0100254 .mwdma_mask = ATA_MWDMA2,
255 .udma_mask = ATA_UDMA4,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400256 .port_ops = &efar_ops,
257 };
Tejun Heo1626aeb2007-05-04 12:43:58 +0200258 const struct ata_port_info *ppi[] = { &info, NULL };
Jeff Garzik669a5db2006-08-29 18:12:40 -0400259
260 if (!printed_version++)
261 dev_printk(KERN_DEBUG, &pdev->dev,
262 "version " DRV_VERSION "\n");
263
Tejun Heo9363c382008-04-07 22:47:16 +0900264 return ata_pci_sff_init_one(pdev, ppi, &efar_sht, NULL);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400265}
266
267static const struct pci_device_id efar_pci_tbl[] = {
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400268 { PCI_VDEVICE(EFAR, 0x9130), },
269
Jeff Garzik669a5db2006-08-29 18:12:40 -0400270 { } /* terminate list */
271};
272
273static struct pci_driver efar_pci_driver = {
274 .name = DRV_NAME,
275 .id_table = efar_pci_tbl,
276 .probe = efar_init_one,
277 .remove = ata_pci_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900278#ifdef CONFIG_PM
Alan30ced0f2006-11-22 16:57:36 +0000279 .suspend = ata_pci_device_suspend,
280 .resume = ata_pci_device_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900281#endif
Jeff Garzik669a5db2006-08-29 18:12:40 -0400282};
283
284static int __init efar_init(void)
285{
286 return pci_register_driver(&efar_pci_driver);
287}
288
289static void __exit efar_exit(void)
290{
291 pci_unregister_driver(&efar_pci_driver);
292}
293
Jeff Garzik669a5db2006-08-29 18:12:40 -0400294module_init(efar_init);
295module_exit(efar_exit);
296
297MODULE_AUTHOR("Alan Cox");
298MODULE_DESCRIPTION("SCSI low-level driver for EFAR PIIX clones");
299MODULE_LICENSE("GPL");
300MODULE_DEVICE_TABLE(pci, efar_pci_tbl);
301MODULE_VERSION(DRV_VERSION);
302