Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2009 Francisco Jerez. |
| 3 | * All Rights Reserved. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining |
| 6 | * a copy of this software and associated documentation files (the |
| 7 | * "Software"), to deal in the Software without restriction, including |
| 8 | * without limitation the rights to use, copy, modify, merge, publish, |
| 9 | * distribute, sublicense, and/or sell copies of the Software, and to |
| 10 | * permit persons to whom the Software is furnished to do so, subject to |
| 11 | * the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice (including the |
| 14 | * next paragraph) shall be included in all copies or substantial |
| 15 | * portions of the Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 18 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| 20 | * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE |
| 21 | * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION |
| 22 | * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION |
| 23 | * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 24 | * |
| 25 | */ |
| 26 | |
| 27 | #include "drmP.h" |
| 28 | #include "drm_crtc_helper.h" |
| 29 | #include "nouveau_drv.h" |
| 30 | #include "nouveau_encoder.h" |
| 31 | #include "nouveau_connector.h" |
| 32 | #include "nouveau_crtc.h" |
| 33 | #include "nouveau_hw.h" |
| 34 | #include "nv17_tv.h" |
| 35 | |
Francisco Jerez | 11d6eb2 | 2009-12-17 18:52:44 +0100 | [diff] [blame^] | 36 | static enum drm_connector_status |
| 37 | nv17_tv_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 38 | { |
Francisco Jerez | 11d6eb2 | 2009-12-17 18:52:44 +0100 | [diff] [blame^] | 39 | struct drm_device *dev = encoder->dev; |
| 40 | struct drm_mode_config *conf = &dev->mode_config; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 41 | struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); |
Francisco Jerez | 11d6eb2 | 2009-12-17 18:52:44 +0100 | [diff] [blame^] | 42 | struct dcb_entry *dcb = tv_enc->base.dcb; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 43 | |
Francisco Jerez | 11d6eb2 | 2009-12-17 18:52:44 +0100 | [diff] [blame^] | 44 | tv_enc->pin_mask = nv17_dac_sample_load(encoder) >> 28 & 0xe; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 45 | |
| 46 | switch (tv_enc->pin_mask) { |
| 47 | case 0x2: |
| 48 | case 0x4: |
| 49 | tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Composite; |
| 50 | break; |
| 51 | case 0xc: |
| 52 | tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SVIDEO; |
| 53 | break; |
| 54 | case 0xe: |
Francisco Jerez | 11d6eb2 | 2009-12-17 18:52:44 +0100 | [diff] [blame^] | 55 | if (dcb->tvconf.has_component_output) |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 56 | tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Component; |
| 57 | else |
| 58 | tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SCART; |
| 59 | break; |
| 60 | default: |
| 61 | tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Unknown; |
| 62 | break; |
| 63 | } |
| 64 | |
| 65 | drm_connector_property_set_value(connector, |
Francisco Jerez | 11d6eb2 | 2009-12-17 18:52:44 +0100 | [diff] [blame^] | 66 | conf->tv_subconnector_property, |
| 67 | tv_enc->subconnector); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 68 | |
Francisco Jerez | 11d6eb2 | 2009-12-17 18:52:44 +0100 | [diff] [blame^] | 69 | if (tv_enc->subconnector) { |
| 70 | NV_INFO(dev, "Load detected on output %c\n", |
| 71 | '@' + ffs(dcb->or)); |
| 72 | return connector_status_connected; |
| 73 | } else { |
| 74 | return connector_status_disconnected; |
| 75 | } |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 76 | } |
| 77 | |
| 78 | static const struct { |
| 79 | int hdisplay; |
| 80 | int vdisplay; |
| 81 | } modes[] = { |
| 82 | { 640, 400 }, |
| 83 | { 640, 480 }, |
| 84 | { 720, 480 }, |
| 85 | { 720, 576 }, |
| 86 | { 800, 600 }, |
| 87 | { 1024, 768 }, |
| 88 | { 1280, 720 }, |
| 89 | { 1280, 1024 }, |
| 90 | { 1920, 1080 } |
| 91 | }; |
| 92 | |
| 93 | static int nv17_tv_get_modes(struct drm_encoder *encoder, |
| 94 | struct drm_connector *connector) |
| 95 | { |
| 96 | struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); |
| 97 | struct drm_display_mode *mode; |
| 98 | struct drm_display_mode *output_mode; |
| 99 | int n = 0; |
| 100 | int i; |
| 101 | |
| 102 | if (tv_norm->kind != CTV_ENC_MODE) { |
| 103 | struct drm_display_mode *tv_mode; |
| 104 | |
| 105 | for (tv_mode = nv17_tv_modes; tv_mode->hdisplay; tv_mode++) { |
| 106 | mode = drm_mode_duplicate(encoder->dev, tv_mode); |
| 107 | |
| 108 | mode->clock = tv_norm->tv_enc_mode.vrefresh * |
| 109 | mode->htotal / 1000 * |
| 110 | mode->vtotal / 1000; |
| 111 | |
| 112 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 113 | mode->clock *= 2; |
| 114 | |
| 115 | if (mode->hdisplay == tv_norm->tv_enc_mode.hdisplay && |
| 116 | mode->vdisplay == tv_norm->tv_enc_mode.vdisplay) |
| 117 | mode->type |= DRM_MODE_TYPE_PREFERRED; |
| 118 | |
| 119 | drm_mode_probed_add(connector, mode); |
| 120 | n++; |
| 121 | } |
| 122 | return n; |
| 123 | } |
| 124 | |
| 125 | /* tv_norm->kind == CTV_ENC_MODE */ |
| 126 | output_mode = &tv_norm->ctv_enc_mode.mode; |
| 127 | for (i = 0; i < ARRAY_SIZE(modes); i++) { |
| 128 | if (modes[i].hdisplay > output_mode->hdisplay || |
| 129 | modes[i].vdisplay > output_mode->vdisplay) |
| 130 | continue; |
| 131 | |
| 132 | if (modes[i].hdisplay == output_mode->hdisplay && |
| 133 | modes[i].vdisplay == output_mode->vdisplay) { |
| 134 | mode = drm_mode_duplicate(encoder->dev, output_mode); |
| 135 | mode->type |= DRM_MODE_TYPE_PREFERRED; |
| 136 | } else { |
| 137 | mode = drm_cvt_mode(encoder->dev, modes[i].hdisplay, |
| 138 | modes[i].vdisplay, 60, false, |
| 139 | output_mode->flags & DRM_MODE_FLAG_INTERLACE, |
| 140 | false); |
| 141 | } |
| 142 | |
| 143 | /* CVT modes are sometimes unsuitable... */ |
| 144 | if (output_mode->hdisplay <= 720 |
| 145 | || output_mode->hdisplay >= 1920) { |
| 146 | mode->htotal = output_mode->htotal; |
| 147 | mode->hsync_start = (mode->hdisplay + (mode->htotal |
| 148 | - mode->hdisplay) * 9 / 10) & ~7; |
| 149 | mode->hsync_end = mode->hsync_start + 8; |
| 150 | } |
| 151 | if (output_mode->vdisplay >= 1024) { |
| 152 | mode->vtotal = output_mode->vtotal; |
| 153 | mode->vsync_start = output_mode->vsync_start; |
| 154 | mode->vsync_end = output_mode->vsync_end; |
| 155 | } |
| 156 | |
| 157 | mode->type |= DRM_MODE_TYPE_DRIVER; |
| 158 | drm_mode_probed_add(connector, mode); |
| 159 | n++; |
| 160 | } |
| 161 | return n; |
| 162 | } |
| 163 | |
| 164 | static int nv17_tv_mode_valid(struct drm_encoder *encoder, |
| 165 | struct drm_display_mode *mode) |
| 166 | { |
| 167 | struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); |
| 168 | |
| 169 | if (tv_norm->kind == CTV_ENC_MODE) { |
| 170 | struct drm_display_mode *output_mode = |
| 171 | &tv_norm->ctv_enc_mode.mode; |
| 172 | |
| 173 | if (mode->clock > 400000) |
| 174 | return MODE_CLOCK_HIGH; |
| 175 | |
| 176 | if (mode->hdisplay > output_mode->hdisplay || |
| 177 | mode->vdisplay > output_mode->vdisplay) |
| 178 | return MODE_BAD; |
| 179 | |
| 180 | if ((mode->flags & DRM_MODE_FLAG_INTERLACE) != |
| 181 | (output_mode->flags & DRM_MODE_FLAG_INTERLACE)) |
| 182 | return MODE_NO_INTERLACE; |
| 183 | |
| 184 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 185 | return MODE_NO_DBLESCAN; |
| 186 | |
| 187 | } else { |
| 188 | const int vsync_tolerance = 600; |
| 189 | |
| 190 | if (mode->clock > 70000) |
| 191 | return MODE_CLOCK_HIGH; |
| 192 | |
| 193 | if (abs(drm_mode_vrefresh(mode) * 1000 - |
| 194 | tv_norm->tv_enc_mode.vrefresh) > vsync_tolerance) |
| 195 | return MODE_VSYNC; |
| 196 | |
| 197 | /* The encoder takes care of the actual interlacing */ |
| 198 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 199 | return MODE_NO_INTERLACE; |
| 200 | } |
| 201 | |
| 202 | return MODE_OK; |
| 203 | } |
| 204 | |
| 205 | static bool nv17_tv_mode_fixup(struct drm_encoder *encoder, |
| 206 | struct drm_display_mode *mode, |
| 207 | struct drm_display_mode *adjusted_mode) |
| 208 | { |
| 209 | struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); |
| 210 | |
| 211 | if (tv_norm->kind == CTV_ENC_MODE) |
| 212 | adjusted_mode->clock = tv_norm->ctv_enc_mode.mode.clock; |
| 213 | else |
| 214 | adjusted_mode->clock = 90000; |
| 215 | |
| 216 | return true; |
| 217 | } |
| 218 | |
| 219 | static void nv17_tv_dpms(struct drm_encoder *encoder, int mode) |
| 220 | { |
| 221 | struct drm_device *dev = encoder->dev; |
| 222 | struct nv17_tv_state *regs = &to_tv_enc(encoder)->state; |
| 223 | struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); |
| 224 | |
| 225 | if (nouveau_encoder(encoder)->last_dpms == mode) |
| 226 | return; |
| 227 | nouveau_encoder(encoder)->last_dpms = mode; |
| 228 | |
Maarten Maathuis | ef2bb50 | 2009-12-13 16:53:12 +0100 | [diff] [blame] | 229 | NV_INFO(dev, "Setting dpms mode %d on TV encoder (output %d)\n", |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 230 | mode, nouveau_encoder(encoder)->dcb->index); |
| 231 | |
| 232 | regs->ptv_200 &= ~1; |
| 233 | |
| 234 | if (tv_norm->kind == CTV_ENC_MODE) { |
| 235 | nv04_dfp_update_fp_control(encoder, mode); |
| 236 | |
| 237 | } else { |
| 238 | nv04_dfp_update_fp_control(encoder, DRM_MODE_DPMS_OFF); |
| 239 | |
| 240 | if (mode == DRM_MODE_DPMS_ON) |
| 241 | regs->ptv_200 |= 1; |
| 242 | } |
| 243 | |
| 244 | nv_load_ptv(dev, regs, 200); |
| 245 | |
| 246 | nv17_gpio_set(dev, DCB_GPIO_TVDAC1, mode == DRM_MODE_DPMS_ON); |
| 247 | nv17_gpio_set(dev, DCB_GPIO_TVDAC0, mode == DRM_MODE_DPMS_ON); |
| 248 | |
| 249 | nv04_dac_update_dacclk(encoder, mode == DRM_MODE_DPMS_ON); |
| 250 | } |
| 251 | |
| 252 | static void nv17_tv_prepare(struct drm_encoder *encoder) |
| 253 | { |
| 254 | struct drm_device *dev = encoder->dev; |
| 255 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 256 | struct drm_encoder_helper_funcs *helper = encoder->helper_private; |
| 257 | struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); |
| 258 | int head = nouveau_crtc(encoder->crtc)->index; |
| 259 | uint8_t *cr_lcd = &dev_priv->mode_reg.crtc_reg[head].CRTC[ |
| 260 | NV_CIO_CRE_LCD__INDEX]; |
| 261 | uint32_t dacclk_off = NV_PRAMDAC_DACCLK + |
| 262 | nv04_dac_output_offset(encoder); |
| 263 | uint32_t dacclk; |
| 264 | |
| 265 | helper->dpms(encoder, DRM_MODE_DPMS_OFF); |
| 266 | |
| 267 | nv04_dfp_disable(dev, head); |
| 268 | |
| 269 | /* Unbind any FP encoders from this head if we need the FP |
| 270 | * stuff enabled. */ |
| 271 | if (tv_norm->kind == CTV_ENC_MODE) { |
| 272 | struct drm_encoder *enc; |
| 273 | |
| 274 | list_for_each_entry(enc, &dev->mode_config.encoder_list, head) { |
| 275 | struct dcb_entry *dcb = nouveau_encoder(enc)->dcb; |
| 276 | |
| 277 | if ((dcb->type == OUTPUT_TMDS || |
| 278 | dcb->type == OUTPUT_LVDS) && |
| 279 | !enc->crtc && |
| 280 | nv04_dfp_get_bound_head(dev, dcb) == head) { |
| 281 | nv04_dfp_bind_head(dev, dcb, head ^ 1, |
| 282 | dev_priv->VBIOS.fp.dual_link); |
| 283 | } |
| 284 | } |
| 285 | |
| 286 | } |
| 287 | |
| 288 | /* Some NV4x have unknown values (0x3f, 0x50, 0x54, 0x6b, 0x79, 0x7f) |
| 289 | * at LCD__INDEX which we don't alter |
| 290 | */ |
| 291 | if (!(*cr_lcd & 0x44)) { |
| 292 | if (tv_norm->kind == CTV_ENC_MODE) |
| 293 | *cr_lcd = 0x1 | (head ? 0x0 : 0x8); |
| 294 | else |
| 295 | *cr_lcd = 0; |
| 296 | } |
| 297 | |
| 298 | /* Set the DACCLK register */ |
| 299 | dacclk = (NVReadRAMDAC(dev, 0, dacclk_off) & ~0x30) | 0x1; |
| 300 | |
| 301 | if (dev_priv->card_type == NV_40) |
| 302 | dacclk |= 0x1a << 16; |
| 303 | |
| 304 | if (tv_norm->kind == CTV_ENC_MODE) { |
| 305 | dacclk |= 0x20; |
| 306 | |
| 307 | if (head) |
| 308 | dacclk |= 0x100; |
| 309 | else |
| 310 | dacclk &= ~0x100; |
| 311 | |
| 312 | } else { |
| 313 | dacclk |= 0x10; |
| 314 | |
| 315 | } |
| 316 | |
| 317 | NVWriteRAMDAC(dev, 0, dacclk_off, dacclk); |
| 318 | } |
| 319 | |
| 320 | static void nv17_tv_mode_set(struct drm_encoder *encoder, |
| 321 | struct drm_display_mode *drm_mode, |
| 322 | struct drm_display_mode *adjusted_mode) |
| 323 | { |
| 324 | struct drm_device *dev = encoder->dev; |
| 325 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 326 | int head = nouveau_crtc(encoder->crtc)->index; |
| 327 | struct nv04_crtc_reg *regs = &dev_priv->mode_reg.crtc_reg[head]; |
| 328 | struct nv17_tv_state *tv_regs = &to_tv_enc(encoder)->state; |
| 329 | struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); |
| 330 | int i; |
| 331 | |
| 332 | regs->CRTC[NV_CIO_CRE_53] = 0x40; /* FP_HTIMING */ |
| 333 | regs->CRTC[NV_CIO_CRE_54] = 0; /* FP_VTIMING */ |
| 334 | regs->ramdac_630 = 0x2; /* turn off green mode (tv test pattern?) */ |
| 335 | regs->tv_setup = 1; |
| 336 | regs->ramdac_8c0 = 0x0; |
| 337 | |
| 338 | if (tv_norm->kind == TV_ENC_MODE) { |
| 339 | tv_regs->ptv_200 = 0x13111100; |
| 340 | if (head) |
| 341 | tv_regs->ptv_200 |= 0x10; |
| 342 | |
| 343 | tv_regs->ptv_20c = 0x808010; |
| 344 | tv_regs->ptv_304 = 0x2d00000; |
| 345 | tv_regs->ptv_600 = 0x0; |
| 346 | tv_regs->ptv_60c = 0x0; |
| 347 | tv_regs->ptv_610 = 0x1e00000; |
| 348 | |
| 349 | if (tv_norm->tv_enc_mode.vdisplay == 576) { |
| 350 | tv_regs->ptv_508 = 0x1200000; |
| 351 | tv_regs->ptv_614 = 0x33; |
| 352 | |
| 353 | } else if (tv_norm->tv_enc_mode.vdisplay == 480) { |
| 354 | tv_regs->ptv_508 = 0xf00000; |
| 355 | tv_regs->ptv_614 = 0x13; |
| 356 | } |
| 357 | |
| 358 | if (dev_priv->card_type >= NV_30) { |
| 359 | tv_regs->ptv_500 = 0xe8e0; |
| 360 | tv_regs->ptv_504 = 0x1710; |
| 361 | tv_regs->ptv_604 = 0x0; |
| 362 | tv_regs->ptv_608 = 0x0; |
| 363 | } else { |
| 364 | if (tv_norm->tv_enc_mode.vdisplay == 576) { |
| 365 | tv_regs->ptv_604 = 0x20; |
| 366 | tv_regs->ptv_608 = 0x10; |
| 367 | tv_regs->ptv_500 = 0x19710; |
| 368 | tv_regs->ptv_504 = 0x68f0; |
| 369 | |
| 370 | } else if (tv_norm->tv_enc_mode.vdisplay == 480) { |
| 371 | tv_regs->ptv_604 = 0x10; |
| 372 | tv_regs->ptv_608 = 0x20; |
| 373 | tv_regs->ptv_500 = 0x4b90; |
| 374 | tv_regs->ptv_504 = 0x1b480; |
| 375 | } |
| 376 | } |
| 377 | |
| 378 | for (i = 0; i < 0x40; i++) |
| 379 | tv_regs->tv_enc[i] = tv_norm->tv_enc_mode.tv_enc[i]; |
| 380 | |
| 381 | } else { |
| 382 | struct drm_display_mode *output_mode = |
| 383 | &tv_norm->ctv_enc_mode.mode; |
| 384 | |
| 385 | /* The registers in PRAMDAC+0xc00 control some timings and CSC |
| 386 | * parameters for the CTV encoder (It's only used for "HD" TV |
| 387 | * modes, I don't think I have enough working to guess what |
| 388 | * they exactly mean...), it's probably connected at the |
| 389 | * output of the FP encoder, but it also needs the analog |
| 390 | * encoder in its OR enabled and routed to the head it's |
| 391 | * using. It's enabled with the DACCLK register, bits [5:4]. |
| 392 | */ |
| 393 | for (i = 0; i < 38; i++) |
| 394 | regs->ctv_regs[i] = tv_norm->ctv_enc_mode.ctv_regs[i]; |
| 395 | |
| 396 | regs->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1; |
| 397 | regs->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1; |
| 398 | regs->fp_horiz_regs[FP_SYNC_START] = |
| 399 | output_mode->hsync_start - 1; |
| 400 | regs->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1; |
| 401 | regs->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay + |
| 402 | max((output_mode->hdisplay-600)/40 - 1, 1); |
| 403 | |
| 404 | regs->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1; |
| 405 | regs->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1; |
| 406 | regs->fp_vert_regs[FP_SYNC_START] = |
| 407 | output_mode->vsync_start - 1; |
| 408 | regs->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1; |
| 409 | regs->fp_vert_regs[FP_CRTC] = output_mode->vdisplay - 1; |
| 410 | |
| 411 | regs->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS | |
| 412 | NV_PRAMDAC_FP_TG_CONTROL_READ_PROG | |
| 413 | NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12; |
| 414 | |
| 415 | if (output_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 416 | regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS; |
| 417 | if (output_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 418 | regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS; |
| 419 | |
| 420 | regs->fp_debug_0 = NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND | |
| 421 | NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND | |
| 422 | NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR | |
| 423 | NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR | |
| 424 | NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED | |
| 425 | NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE | |
| 426 | NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE; |
| 427 | |
| 428 | regs->fp_debug_2 = 0; |
| 429 | |
| 430 | regs->fp_margin_color = 0x801080; |
| 431 | |
| 432 | } |
| 433 | } |
| 434 | |
| 435 | static void nv17_tv_commit(struct drm_encoder *encoder) |
| 436 | { |
| 437 | struct drm_device *dev = encoder->dev; |
| 438 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 439 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); |
| 440 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
| 441 | struct drm_encoder_helper_funcs *helper = encoder->helper_private; |
| 442 | |
| 443 | if (get_tv_norm(encoder)->kind == TV_ENC_MODE) { |
| 444 | nv17_tv_update_rescaler(encoder); |
| 445 | nv17_tv_update_properties(encoder); |
| 446 | } else { |
| 447 | nv17_ctv_update_rescaler(encoder); |
| 448 | } |
| 449 | |
| 450 | nv17_tv_state_load(dev, &to_tv_enc(encoder)->state); |
| 451 | |
| 452 | /* This could use refinement for flatpanels, but it should work */ |
| 453 | if (dev_priv->chipset < 0x44) |
| 454 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + |
| 455 | nv04_dac_output_offset(encoder), |
| 456 | 0xf0000000); |
| 457 | else |
| 458 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + |
| 459 | nv04_dac_output_offset(encoder), |
| 460 | 0x00100000); |
| 461 | |
| 462 | helper->dpms(encoder, DRM_MODE_DPMS_ON); |
| 463 | |
| 464 | NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n", |
| 465 | drm_get_connector_name( |
| 466 | &nouveau_encoder_connector_get(nv_encoder)->base), |
| 467 | nv_crtc->index, '@' + ffs(nv_encoder->dcb->or)); |
| 468 | } |
| 469 | |
| 470 | static void nv17_tv_save(struct drm_encoder *encoder) |
| 471 | { |
| 472 | struct drm_device *dev = encoder->dev; |
| 473 | struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); |
| 474 | |
| 475 | nouveau_encoder(encoder)->restore.output = |
| 476 | NVReadRAMDAC(dev, 0, |
| 477 | NV_PRAMDAC_DACCLK + |
| 478 | nv04_dac_output_offset(encoder)); |
| 479 | |
| 480 | nv17_tv_state_save(dev, &tv_enc->saved_state); |
| 481 | |
| 482 | tv_enc->state.ptv_200 = tv_enc->saved_state.ptv_200; |
| 483 | } |
| 484 | |
| 485 | static void nv17_tv_restore(struct drm_encoder *encoder) |
| 486 | { |
| 487 | struct drm_device *dev = encoder->dev; |
| 488 | |
| 489 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + |
| 490 | nv04_dac_output_offset(encoder), |
| 491 | nouveau_encoder(encoder)->restore.output); |
| 492 | |
| 493 | nv17_tv_state_load(dev, &to_tv_enc(encoder)->saved_state); |
| 494 | } |
| 495 | |
| 496 | static int nv17_tv_create_resources(struct drm_encoder *encoder, |
| 497 | struct drm_connector *connector) |
| 498 | { |
| 499 | struct drm_device *dev = encoder->dev; |
| 500 | struct drm_mode_config *conf = &dev->mode_config; |
| 501 | struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); |
| 502 | struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb; |
| 503 | int num_tv_norms = dcb->tvconf.has_component_output ? NUM_TV_NORMS : |
| 504 | NUM_LD_TV_NORMS; |
| 505 | int i; |
| 506 | |
| 507 | if (nouveau_tv_norm) { |
| 508 | for (i = 0; i < num_tv_norms; i++) { |
| 509 | if (!strcmp(nv17_tv_norm_names[i], nouveau_tv_norm)) { |
| 510 | tv_enc->tv_norm = i; |
| 511 | break; |
| 512 | } |
| 513 | } |
| 514 | |
| 515 | if (i == num_tv_norms) |
| 516 | NV_WARN(dev, "Invalid TV norm setting \"%s\"\n", |
| 517 | nouveau_tv_norm); |
| 518 | } |
| 519 | |
| 520 | drm_mode_create_tv_properties(dev, num_tv_norms, nv17_tv_norm_names); |
| 521 | |
| 522 | drm_connector_attach_property(connector, |
| 523 | conf->tv_select_subconnector_property, |
| 524 | tv_enc->select_subconnector); |
| 525 | drm_connector_attach_property(connector, |
| 526 | conf->tv_subconnector_property, |
| 527 | tv_enc->subconnector); |
| 528 | drm_connector_attach_property(connector, |
| 529 | conf->tv_mode_property, |
| 530 | tv_enc->tv_norm); |
| 531 | drm_connector_attach_property(connector, |
| 532 | conf->tv_flicker_reduction_property, |
| 533 | tv_enc->flicker); |
| 534 | drm_connector_attach_property(connector, |
| 535 | conf->tv_saturation_property, |
| 536 | tv_enc->saturation); |
| 537 | drm_connector_attach_property(connector, |
| 538 | conf->tv_hue_property, |
| 539 | tv_enc->hue); |
| 540 | drm_connector_attach_property(connector, |
| 541 | conf->tv_overscan_property, |
| 542 | tv_enc->overscan); |
| 543 | |
| 544 | return 0; |
| 545 | } |
| 546 | |
| 547 | static int nv17_tv_set_property(struct drm_encoder *encoder, |
| 548 | struct drm_connector *connector, |
| 549 | struct drm_property *property, |
| 550 | uint64_t val) |
| 551 | { |
| 552 | struct drm_mode_config *conf = &encoder->dev->mode_config; |
| 553 | struct drm_crtc *crtc = encoder->crtc; |
| 554 | struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); |
| 555 | struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); |
| 556 | bool modes_changed = false; |
| 557 | |
| 558 | if (property == conf->tv_overscan_property) { |
| 559 | tv_enc->overscan = val; |
| 560 | if (encoder->crtc) { |
| 561 | if (tv_norm->kind == CTV_ENC_MODE) |
| 562 | nv17_ctv_update_rescaler(encoder); |
| 563 | else |
| 564 | nv17_tv_update_rescaler(encoder); |
| 565 | } |
| 566 | |
| 567 | } else if (property == conf->tv_saturation_property) { |
| 568 | if (tv_norm->kind != TV_ENC_MODE) |
| 569 | return -EINVAL; |
| 570 | |
| 571 | tv_enc->saturation = val; |
| 572 | nv17_tv_update_properties(encoder); |
| 573 | |
| 574 | } else if (property == conf->tv_hue_property) { |
| 575 | if (tv_norm->kind != TV_ENC_MODE) |
| 576 | return -EINVAL; |
| 577 | |
| 578 | tv_enc->hue = val; |
| 579 | nv17_tv_update_properties(encoder); |
| 580 | |
| 581 | } else if (property == conf->tv_flicker_reduction_property) { |
| 582 | if (tv_norm->kind != TV_ENC_MODE) |
| 583 | return -EINVAL; |
| 584 | |
| 585 | tv_enc->flicker = val; |
| 586 | if (encoder->crtc) |
| 587 | nv17_tv_update_rescaler(encoder); |
| 588 | |
| 589 | } else if (property == conf->tv_mode_property) { |
| 590 | if (connector->dpms != DRM_MODE_DPMS_OFF) |
| 591 | return -EINVAL; |
| 592 | |
| 593 | tv_enc->tv_norm = val; |
| 594 | |
| 595 | modes_changed = true; |
| 596 | |
| 597 | } else if (property == conf->tv_select_subconnector_property) { |
| 598 | if (tv_norm->kind != TV_ENC_MODE) |
| 599 | return -EINVAL; |
| 600 | |
| 601 | tv_enc->select_subconnector = val; |
| 602 | nv17_tv_update_properties(encoder); |
| 603 | |
| 604 | } else { |
| 605 | return -EINVAL; |
| 606 | } |
| 607 | |
| 608 | if (modes_changed) { |
| 609 | drm_helper_probe_single_connector_modes(connector, 0, 0); |
| 610 | |
| 611 | /* Disable the crtc to ensure a full modeset is |
| 612 | * performed whenever it's turned on again. */ |
| 613 | if (crtc) { |
| 614 | struct drm_mode_set modeset = { |
| 615 | .crtc = crtc, |
| 616 | }; |
| 617 | |
| 618 | crtc->funcs->set_config(&modeset); |
| 619 | } |
| 620 | } |
| 621 | |
| 622 | return 0; |
| 623 | } |
| 624 | |
| 625 | static void nv17_tv_destroy(struct drm_encoder *encoder) |
| 626 | { |
| 627 | struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); |
| 628 | |
Maarten Maathuis | ef2bb50 | 2009-12-13 16:53:12 +0100 | [diff] [blame] | 629 | NV_DEBUG_KMS(encoder->dev, "\n"); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 630 | |
| 631 | drm_encoder_cleanup(encoder); |
| 632 | kfree(tv_enc); |
| 633 | } |
| 634 | |
| 635 | static struct drm_encoder_helper_funcs nv17_tv_helper_funcs = { |
| 636 | .dpms = nv17_tv_dpms, |
| 637 | .save = nv17_tv_save, |
| 638 | .restore = nv17_tv_restore, |
| 639 | .mode_fixup = nv17_tv_mode_fixup, |
| 640 | .prepare = nv17_tv_prepare, |
| 641 | .commit = nv17_tv_commit, |
| 642 | .mode_set = nv17_tv_mode_set, |
Francisco Jerez | 11d6eb2 | 2009-12-17 18:52:44 +0100 | [diff] [blame^] | 643 | .detect = nv17_tv_detect, |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 644 | }; |
| 645 | |
| 646 | static struct drm_encoder_slave_funcs nv17_tv_slave_funcs = { |
| 647 | .get_modes = nv17_tv_get_modes, |
| 648 | .mode_valid = nv17_tv_mode_valid, |
| 649 | .create_resources = nv17_tv_create_resources, |
| 650 | .set_property = nv17_tv_set_property, |
| 651 | }; |
| 652 | |
| 653 | static struct drm_encoder_funcs nv17_tv_funcs = { |
| 654 | .destroy = nv17_tv_destroy, |
| 655 | }; |
| 656 | |
| 657 | int nv17_tv_create(struct drm_device *dev, struct dcb_entry *entry) |
| 658 | { |
| 659 | struct drm_encoder *encoder; |
| 660 | struct nv17_tv_encoder *tv_enc = NULL; |
| 661 | |
| 662 | tv_enc = kzalloc(sizeof(*tv_enc), GFP_KERNEL); |
| 663 | if (!tv_enc) |
| 664 | return -ENOMEM; |
| 665 | |
| 666 | tv_enc->overscan = 50; |
| 667 | tv_enc->flicker = 50; |
| 668 | tv_enc->saturation = 50; |
| 669 | tv_enc->hue = 0; |
| 670 | tv_enc->tv_norm = TV_NORM_PAL; |
| 671 | tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Unknown; |
| 672 | tv_enc->select_subconnector = DRM_MODE_SUBCONNECTOR_Automatic; |
| 673 | tv_enc->pin_mask = 0; |
| 674 | |
| 675 | encoder = to_drm_encoder(&tv_enc->base); |
| 676 | |
| 677 | tv_enc->base.dcb = entry; |
| 678 | tv_enc->base.or = ffs(entry->or) - 1; |
| 679 | |
| 680 | drm_encoder_init(dev, encoder, &nv17_tv_funcs, DRM_MODE_ENCODER_TVDAC); |
| 681 | drm_encoder_helper_add(encoder, &nv17_tv_helper_funcs); |
| 682 | to_encoder_slave(encoder)->slave_funcs = &nv17_tv_slave_funcs; |
| 683 | |
| 684 | encoder->possible_crtcs = entry->heads; |
| 685 | encoder->possible_clones = 0; |
| 686 | |
| 687 | return 0; |
| 688 | } |