blob: 9a7f3b6e02de38acc1655b9e74fae3d5dac91448 [file] [log] [blame]
Alex Deucher0af62b02011-01-06 21:19:31 -05001/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#ifndef NI_H
25#define NI_H
26
Alex Deucherfecf1d02011-03-02 20:07:29 -050027#define CAYMAN_MAX_SH_GPRS 256
28#define CAYMAN_MAX_TEMP_GPRS 16
29#define CAYMAN_MAX_SH_THREADS 256
30#define CAYMAN_MAX_SH_STACK_ENTRIES 4096
31#define CAYMAN_MAX_FRC_EOV_CNT 16384
32#define CAYMAN_MAX_BACKENDS 8
33#define CAYMAN_MAX_BACKENDS_MASK 0xFF
34#define CAYMAN_MAX_BACKENDS_PER_SE_MASK 0xF
35#define CAYMAN_MAX_SIMDS 16
36#define CAYMAN_MAX_SIMDS_MASK 0xFFFF
37#define CAYMAN_MAX_SIMDS_PER_SE_MASK 0xFFF
38#define CAYMAN_MAX_PIPES 8
39#define CAYMAN_MAX_PIPES_MASK 0xFF
40#define CAYMAN_MAX_LDS_NUM 0xFFFF
41#define CAYMAN_MAX_TCC 16
42#define CAYMAN_MAX_TCC_MASK 0xFF
43
44#define DMIF_ADDR_CONFIG 0xBD4
Alex Deucher1b370782011-11-17 20:13:28 -050045#define SRBM_GFX_CNTL 0x0E44
46#define RINGID(x) (((x) & 0x3) << 0)
47#define VMID(x) (((x) & 0x7) << 0)
Alex Deucherb9952a82011-03-02 20:07:33 -050048#define SRBM_STATUS 0x0E50
Alex Deucherfecf1d02011-03-02 20:07:29 -050049
Alex Deucherfa8198e2011-03-02 20:07:30 -050050#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470
51#define REQUEST_TYPE(x) (((x) & 0xf) << 0)
52#define RESPONSE_TYPE_MASK 0x000000F0
53#define RESPONSE_TYPE_SHIFT 4
54#define VM_L2_CNTL 0x1400
55#define ENABLE_L2_CACHE (1 << 0)
56#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
57#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
58#define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10)
59#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14)
60#define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 18)
61/* CONTEXT1_IDENTITY_ACCESS_MODE
62 * 0 physical = logical
63 * 1 logical via context1 page table
64 * 2 inside identity aperture use translation, outside physical = logical
65 * 3 inside identity aperture physical = logical, outside use translation
66 */
67#define VM_L2_CNTL2 0x1404
68#define INVALIDATE_ALL_L1_TLBS (1 << 0)
69#define INVALIDATE_L2_CACHE (1 << 1)
70#define VM_L2_CNTL3 0x1408
71#define BANK_SELECT(x) ((x) << 0)
72#define CACHE_UPDATE_MODE(x) ((x) << 6)
73#define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20)
74#define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15)
75#define VM_L2_STATUS 0x140C
76#define L2_BUSY (1 << 0)
77#define VM_CONTEXT0_CNTL 0x1410
78#define ENABLE_CONTEXT (1 << 0)
79#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
80#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
81#define VM_CONTEXT1_CNTL 0x1414
82#define VM_CONTEXT0_CNTL2 0x1430
83#define VM_CONTEXT1_CNTL2 0x1434
84#define VM_INVALIDATE_REQUEST 0x1478
85#define VM_INVALIDATE_RESPONSE 0x147c
86#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
87#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c
88#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C
89#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C
90#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
91
Alex Deucherfecf1d02011-03-02 20:07:29 -050092#define MC_SHARED_CHMAP 0x2004
93#define NOOFCHAN_SHIFT 12
94#define NOOFCHAN_MASK 0x00003000
95#define MC_SHARED_CHREMAP 0x2008
Alex Deucherfa8198e2011-03-02 20:07:30 -050096
97#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
98#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
99#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
100#define MC_VM_MX_L1_TLB_CNTL 0x2064
101#define ENABLE_L1_TLB (1 << 0)
102#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
103#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
104#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
105#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
106#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
107#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
108#define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
109
Alex Deucher0af62b02011-01-06 21:19:31 -0500110#define MC_SHARED_BLACKOUT_CNTL 0x20ac
Alex Deucherfecf1d02011-03-02 20:07:29 -0500111#define MC_ARB_RAMCFG 0x2760
112#define NOOFBANK_SHIFT 0
113#define NOOFBANK_MASK 0x00000003
114#define NOOFRANK_SHIFT 2
115#define NOOFRANK_MASK 0x00000004
116#define NOOFROWS_SHIFT 3
117#define NOOFROWS_MASK 0x00000038
118#define NOOFCOLS_SHIFT 6
119#define NOOFCOLS_MASK 0x000000C0
120#define CHANSIZE_SHIFT 8
121#define CHANSIZE_MASK 0x00000100
122#define BURSTLENGTH_SHIFT 9
123#define BURSTLENGTH_MASK 0x00000200
124#define CHANSIZE_OVERRIDE (1 << 11)
Alex Deucher0af62b02011-01-06 21:19:31 -0500125#define MC_SEQ_SUP_CNTL 0x28c8
126#define RUN_MASK (1 << 0)
127#define MC_SEQ_SUP_PGM 0x28cc
128#define MC_IO_PAD_CNTL_D0 0x29d0
129#define MEM_FALL_OUT_CMD (1 << 8)
130#define MC_SEQ_MISC0 0x2a00
131#define MC_SEQ_MISC0_GDDR5_SHIFT 28
132#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
133#define MC_SEQ_MISC0_GDDR5_VALUE 5
134#define MC_SEQ_IO_DEBUG_INDEX 0x2a44
135#define MC_SEQ_IO_DEBUG_DATA 0x2a48
136
Alex Deucherfecf1d02011-03-02 20:07:29 -0500137#define HDP_HOST_PATH_CNTL 0x2C00
138#define HDP_NONSURFACE_BASE 0x2C04
139#define HDP_NONSURFACE_INFO 0x2C08
140#define HDP_NONSURFACE_SIZE 0x2C0C
141#define HDP_ADDR_CONFIG 0x2F48
Dave Airlie0b65f832011-05-19 14:14:42 +1000142#define HDP_MISC_CNTL 0x2F4C
143#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
Alex Deucherfecf1d02011-03-02 20:07:29 -0500144
145#define CC_SYS_RB_BACKEND_DISABLE 0x3F88
146#define GC_USER_SYS_RB_BACKEND_DISABLE 0x3F8C
147#define CGTS_SYS_TCC_DISABLE 0x3F90
148#define CGTS_USER_SYS_TCC_DISABLE 0x3F94
149
150#define CONFIG_MEMSIZE 0x5428
151
Alex Deucherfa8198e2011-03-02 20:07:30 -0500152#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
Alex Deucherfecf1d02011-03-02 20:07:29 -0500153#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
154
155#define GRBM_CNTL 0x8000
156#define GRBM_READ_TIMEOUT(x) ((x) << 0)
157#define GRBM_STATUS 0x8010
158#define CMDFIFO_AVAIL_MASK 0x0000000F
159#define RING2_RQ_PENDING (1 << 4)
160#define SRBM_RQ_PENDING (1 << 5)
161#define RING1_RQ_PENDING (1 << 6)
162#define CF_RQ_PENDING (1 << 7)
163#define PF_RQ_PENDING (1 << 8)
164#define GDS_DMA_RQ_PENDING (1 << 9)
165#define GRBM_EE_BUSY (1 << 10)
166#define SX_CLEAN (1 << 11)
167#define DB_CLEAN (1 << 12)
168#define CB_CLEAN (1 << 13)
169#define TA_BUSY (1 << 14)
170#define GDS_BUSY (1 << 15)
171#define VGT_BUSY_NO_DMA (1 << 16)
172#define VGT_BUSY (1 << 17)
173#define IA_BUSY_NO_DMA (1 << 18)
174#define IA_BUSY (1 << 19)
175#define SX_BUSY (1 << 20)
176#define SH_BUSY (1 << 21)
177#define SPI_BUSY (1 << 22)
178#define SC_BUSY (1 << 24)
179#define PA_BUSY (1 << 25)
180#define DB_BUSY (1 << 26)
181#define CP_COHERENCY_BUSY (1 << 28)
182#define CP_BUSY (1 << 29)
183#define CB_BUSY (1 << 30)
184#define GUI_ACTIVE (1 << 31)
185#define GRBM_STATUS_SE0 0x8014
186#define GRBM_STATUS_SE1 0x8018
187#define SE_SX_CLEAN (1 << 0)
188#define SE_DB_CLEAN (1 << 1)
189#define SE_CB_CLEAN (1 << 2)
190#define SE_VGT_BUSY (1 << 23)
191#define SE_PA_BUSY (1 << 24)
192#define SE_TA_BUSY (1 << 25)
193#define SE_SX_BUSY (1 << 26)
194#define SE_SPI_BUSY (1 << 27)
195#define SE_SH_BUSY (1 << 28)
196#define SE_SC_BUSY (1 << 29)
197#define SE_DB_BUSY (1 << 30)
198#define SE_CB_BUSY (1 << 31)
199#define GRBM_SOFT_RESET 0x8020
200#define SOFT_RESET_CP (1 << 0)
201#define SOFT_RESET_CB (1 << 1)
202#define SOFT_RESET_DB (1 << 3)
203#define SOFT_RESET_GDS (1 << 4)
204#define SOFT_RESET_PA (1 << 5)
205#define SOFT_RESET_SC (1 << 6)
206#define SOFT_RESET_SPI (1 << 8)
207#define SOFT_RESET_SH (1 << 9)
208#define SOFT_RESET_SX (1 << 10)
209#define SOFT_RESET_TC (1 << 11)
210#define SOFT_RESET_TA (1 << 12)
211#define SOFT_RESET_VGT (1 << 14)
212#define SOFT_RESET_IA (1 << 15)
213
Alex Deucher0c88a022011-03-02 20:07:31 -0500214#define SCRATCH_REG0 0x8500
215#define SCRATCH_REG1 0x8504
216#define SCRATCH_REG2 0x8508
217#define SCRATCH_REG3 0x850C
218#define SCRATCH_REG4 0x8510
219#define SCRATCH_REG5 0x8514
220#define SCRATCH_REG6 0x8518
221#define SCRATCH_REG7 0x851C
222#define SCRATCH_UMSK 0x8540
223#define SCRATCH_ADDR 0x8544
224#define CP_SEM_WAIT_TIMER 0x85BC
Alex Deucher11ef3f12012-01-20 14:47:43 -0500225#define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8
Jerome Glisse721604a2012-01-05 22:11:05 -0500226#define CP_COHER_CNTL2 0x85E8
Alex Deucher0c88a022011-03-02 20:07:31 -0500227#define CP_ME_CNTL 0x86D8
228#define CP_ME_HALT (1 << 28)
229#define CP_PFP_HALT (1 << 26)
230#define CP_RB2_RPTR 0x86f8
231#define CP_RB1_RPTR 0x86fc
232#define CP_RB0_RPTR 0x8700
233#define CP_RB_WPTR_DELAY 0x8704
Alex Deucherfecf1d02011-03-02 20:07:29 -0500234#define CP_MEQ_THRESHOLDS 0x8764
235#define MEQ1_START(x) ((x) << 0)
236#define MEQ2_START(x) ((x) << 8)
237#define CP_PERFMON_CNTL 0x87FC
238
239#define VGT_CACHE_INVALIDATION 0x88C4
240#define CACHE_INVALIDATION(x) ((x) << 0)
241#define VC_ONLY 0
242#define TC_ONLY 1
243#define VC_AND_TC 2
244#define AUTO_INVLD_EN(x) ((x) << 6)
245#define NO_AUTO 0
246#define ES_AUTO 1
247#define GS_AUTO 2
248#define ES_AND_GS_AUTO 3
249#define VGT_GS_VERTEX_REUSE 0x88D4
250
251#define CC_GC_SHADER_PIPE_CONFIG 0x8950
252#define GC_USER_SHADER_PIPE_CONFIG 0x8954
253#define INACTIVE_QD_PIPES(x) ((x) << 8)
254#define INACTIVE_QD_PIPES_MASK 0x0000FF00
255#define INACTIVE_QD_PIPES_SHIFT 8
256#define INACTIVE_SIMDS(x) ((x) << 16)
257#define INACTIVE_SIMDS_MASK 0xFFFF0000
258#define INACTIVE_SIMDS_SHIFT 16
259
260#define VGT_PRIMITIVE_TYPE 0x8958
261#define VGT_NUM_INSTANCES 0x8974
262#define VGT_TF_RING_SIZE 0x8988
263#define VGT_OFFCHIP_LDS_BASE 0x89b4
264
265#define PA_SC_LINE_STIPPLE_STATE 0x8B10
266#define PA_CL_ENHANCE 0x8A14
267#define CLIP_VTX_REORDER_ENA (1 << 0)
268#define NUM_CLIP_SEQ(x) ((x) << 1)
269#define PA_SC_FIFO_SIZE 0x8BCC
270#define SC_PRIM_FIFO_SIZE(x) ((x) << 0)
271#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
272#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
273#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
274#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
275#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
276
277#define SQ_CONFIG 0x8C00
278#define VC_ENABLE (1 << 0)
279#define EXPORT_SRC_C (1 << 1)
280#define GFX_PRIO(x) ((x) << 2)
281#define CS1_PRIO(x) ((x) << 4)
282#define CS2_PRIO(x) ((x) << 6)
283#define SQ_GPR_RESOURCE_MGMT_1 0x8C04
284#define NUM_PS_GPRS(x) ((x) << 0)
285#define NUM_VS_GPRS(x) ((x) << 16)
286#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
287#define SQ_ESGS_RING_SIZE 0x8c44
288#define SQ_GSVS_RING_SIZE 0x8c4c
289#define SQ_ESTMP_RING_BASE 0x8c50
290#define SQ_ESTMP_RING_SIZE 0x8c54
291#define SQ_GSTMP_RING_BASE 0x8c58
292#define SQ_GSTMP_RING_SIZE 0x8c5c
293#define SQ_VSTMP_RING_BASE 0x8c60
294#define SQ_VSTMP_RING_SIZE 0x8c64
295#define SQ_PSTMP_RING_BASE 0x8c68
296#define SQ_PSTMP_RING_SIZE 0x8c6c
297#define SQ_MS_FIFO_SIZES 0x8CF0
298#define CACHE_FIFO_SIZE(x) ((x) << 0)
299#define FETCH_FIFO_HIWATER(x) ((x) << 8)
300#define DONE_FIFO_HIWATER(x) ((x) << 16)
301#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
302#define SQ_LSTMP_RING_BASE 0x8e10
303#define SQ_LSTMP_RING_SIZE 0x8e14
304#define SQ_HSTMP_RING_BASE 0x8e18
305#define SQ_HSTMP_RING_SIZE 0x8e1c
306#define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C
307#define DYN_GPR_ENABLE (1 << 8)
308#define SQ_CONST_MEM_BASE 0x8df8
309
310#define SX_EXPORT_BUFFER_SIZES 0x900C
311#define COLOR_BUFFER_SIZE(x) ((x) << 0)
312#define POSITION_BUFFER_SIZE(x) ((x) << 8)
313#define SMX_BUFFER_SIZE(x) ((x) << 16)
314#define SX_DEBUG_1 0x9058
315#define ENABLE_NEW_SMX_ADDRESS (1 << 16)
316
317#define SPI_CONFIG_CNTL 0x9100
318#define GPR_WRITE_PRIORITY(x) ((x) << 0)
319#define SPI_CONFIG_CNTL_1 0x913C
320#define VTX_DONE_DELAY(x) ((x) << 0)
321#define INTERP_ONE_PRIM_PER_ROW (1 << 4)
322#define CRC_SIMD_ID_WADDR_DISABLE (1 << 8)
323
324#define CGTS_TCC_DISABLE 0x9148
325#define CGTS_USER_TCC_DISABLE 0x914C
326#define TCC_DISABLE_MASK 0xFFFF0000
327#define TCC_DISABLE_SHIFT 16
Alex Deucher2498c412011-07-01 12:58:54 -0400328#define CGTS_SM_CTRL_REG 0x9150
Alex Deucherfecf1d02011-03-02 20:07:29 -0500329#define OVERRIDE (1 << 21)
330
331#define TA_CNTL_AUX 0x9508
332#define DISABLE_CUBE_WRAP (1 << 0)
333#define DISABLE_CUBE_ANISO (1 << 1)
334
335#define TCP_CHAN_STEER_LO 0x960c
336#define TCP_CHAN_STEER_HI 0x9610
337
338#define CC_RB_BACKEND_DISABLE 0x98F4
339#define BACKEND_DISABLE(x) ((x) << 16)
340#define GB_ADDR_CONFIG 0x98F8
341#define NUM_PIPES(x) ((x) << 0)
342#define NUM_PIPES_MASK 0x00000007
343#define NUM_PIPES_SHIFT 0
344#define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
345#define PIPE_INTERLEAVE_SIZE_MASK 0x00000070
346#define PIPE_INTERLEAVE_SIZE_SHIFT 4
347#define BANK_INTERLEAVE_SIZE(x) ((x) << 8)
348#define NUM_SHADER_ENGINES(x) ((x) << 12)
349#define NUM_SHADER_ENGINES_MASK 0x00003000
350#define NUM_SHADER_ENGINES_SHIFT 12
351#define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
352#define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000
353#define SHADER_ENGINE_TILE_SIZE_SHIFT 16
354#define NUM_GPUS(x) ((x) << 20)
355#define NUM_GPUS_MASK 0x00700000
356#define NUM_GPUS_SHIFT 20
357#define MULTI_GPU_TILE_SIZE(x) ((x) << 24)
358#define MULTI_GPU_TILE_SIZE_MASK 0x03000000
359#define MULTI_GPU_TILE_SIZE_SHIFT 24
360#define ROW_SIZE(x) ((x) << 28)
Alex Deucherbb920912011-05-23 14:22:26 -0400361#define ROW_SIZE_MASK 0x30000000
Alex Deucherfecf1d02011-03-02 20:07:29 -0500362#define ROW_SIZE_SHIFT 28
363#define NUM_LOWER_PIPES(x) ((x) << 30)
364#define NUM_LOWER_PIPES_MASK 0x40000000
365#define NUM_LOWER_PIPES_SHIFT 30
366#define GB_BACKEND_MAP 0x98FC
367
368#define CB_PERF_CTR0_SEL_0 0x9A20
369#define CB_PERF_CTR0_SEL_1 0x9A24
370#define CB_PERF_CTR1_SEL_0 0x9A28
371#define CB_PERF_CTR1_SEL_1 0x9A2C
372#define CB_PERF_CTR2_SEL_0 0x9A30
373#define CB_PERF_CTR2_SEL_1 0x9A34
374#define CB_PERF_CTR3_SEL_0 0x9A38
375#define CB_PERF_CTR3_SEL_1 0x9A3C
376
377#define GC_USER_RB_BACKEND_DISABLE 0x9B7C
378#define BACKEND_DISABLE_MASK 0x00FF0000
379#define BACKEND_DISABLE_SHIFT 16
380
381#define SMX_DC_CTL0 0xA020
382#define USE_HASH_FUNCTION (1 << 0)
383#define NUMBER_OF_SETS(x) ((x) << 1)
384#define FLUSH_ALL_ON_EVENT (1 << 10)
385#define STALL_ON_EVENT (1 << 11)
386#define SMX_EVENT_CTL 0xA02C
387#define ES_FLUSH_CTL(x) ((x) << 0)
388#define GS_FLUSH_CTL(x) ((x) << 3)
389#define ACK_FLUSH_CTL(x) ((x) << 6)
390#define SYNC_FLUSH_CTL (1 << 8)
391
Alex Deucher0c88a022011-03-02 20:07:31 -0500392#define CP_RB0_BASE 0xC100
393#define CP_RB0_CNTL 0xC104
394#define RB_BUFSZ(x) ((x) << 0)
395#define RB_BLKSZ(x) ((x) << 8)
396#define RB_NO_UPDATE (1 << 27)
397#define RB_RPTR_WR_ENA (1 << 31)
398#define BUF_SWAP_32BIT (2 << 16)
399#define CP_RB0_RPTR_ADDR 0xC10C
400#define CP_RB0_RPTR_ADDR_HI 0xC110
401#define CP_RB0_WPTR 0xC114
Alex Deucher1b370782011-11-17 20:13:28 -0500402
403#define CP_INT_CNTL 0xC124
404# define CNTX_BUSY_INT_ENABLE (1 << 19)
405# define CNTX_EMPTY_INT_ENABLE (1 << 20)
406# define TIME_STAMP_INT_ENABLE (1 << 26)
407
Alex Deucher0c88a022011-03-02 20:07:31 -0500408#define CP_RB1_BASE 0xC180
409#define CP_RB1_CNTL 0xC184
410#define CP_RB1_RPTR_ADDR 0xC188
411#define CP_RB1_RPTR_ADDR_HI 0xC18C
412#define CP_RB1_WPTR 0xC190
413#define CP_RB2_BASE 0xC194
414#define CP_RB2_CNTL 0xC198
415#define CP_RB2_RPTR_ADDR 0xC19C
416#define CP_RB2_RPTR_ADDR_HI 0xC1A0
417#define CP_RB2_WPTR 0xC1A4
418#define CP_PFP_UCODE_ADDR 0xC150
419#define CP_PFP_UCODE_DATA 0xC154
420#define CP_ME_RAM_RADDR 0xC158
421#define CP_ME_RAM_WADDR 0xC15C
422#define CP_ME_RAM_DATA 0xC160
423#define CP_DEBUG 0xC1FC
424
Alex Deucherb40e7e12011-11-17 14:57:50 -0500425#define VGT_EVENT_INITIATOR 0x28a90
426# define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0)
427# define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0)
428
Alex Deucher0c88a022011-03-02 20:07:31 -0500429/*
430 * PM4
431 */
432#define PACKET_TYPE0 0
433#define PACKET_TYPE1 1
434#define PACKET_TYPE2 2
435#define PACKET_TYPE3 3
436
437#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
438#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
439#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
440#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
441#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
442 (((reg) >> 2) & 0xFFFF) | \
443 ((n) & 0x3FFF) << 16)
444#define CP_PACKET2 0x80000000
445#define PACKET2_PAD_SHIFT 0
446#define PACKET2_PAD_MASK (0x3fffffff << 0)
447
448#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
449
450#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
451 (((op) & 0xFF) << 8) | \
452 ((n) & 0x3FFF) << 16)
453
454/* Packet 3 types */
455#define PACKET3_NOP 0x10
456#define PACKET3_SET_BASE 0x11
457#define PACKET3_CLEAR_STATE 0x12
458#define PACKET3_INDEX_BUFFER_SIZE 0x13
459#define PACKET3_DEALLOC_STATE 0x14
460#define PACKET3_DISPATCH_DIRECT 0x15
461#define PACKET3_DISPATCH_INDIRECT 0x16
462#define PACKET3_INDIRECT_BUFFER_END 0x17
Jerome Glisse721604a2012-01-05 22:11:05 -0500463#define PACKET3_MODE_CONTROL 0x18
Alex Deucher0c88a022011-03-02 20:07:31 -0500464#define PACKET3_SET_PREDICATION 0x20
465#define PACKET3_REG_RMW 0x21
466#define PACKET3_COND_EXEC 0x22
467#define PACKET3_PRED_EXEC 0x23
468#define PACKET3_DRAW_INDIRECT 0x24
469#define PACKET3_DRAW_INDEX_INDIRECT 0x25
470#define PACKET3_INDEX_BASE 0x26
471#define PACKET3_DRAW_INDEX_2 0x27
472#define PACKET3_CONTEXT_CONTROL 0x28
473#define PACKET3_DRAW_INDEX_OFFSET 0x29
474#define PACKET3_INDEX_TYPE 0x2A
475#define PACKET3_DRAW_INDEX 0x2B
476#define PACKET3_DRAW_INDEX_AUTO 0x2D
477#define PACKET3_DRAW_INDEX_IMMD 0x2E
478#define PACKET3_NUM_INSTANCES 0x2F
479#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
480#define PACKET3_INDIRECT_BUFFER 0x32
481#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
482#define PACKET3_DRAW_INDEX_OFFSET_2 0x35
483#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
484#define PACKET3_WRITE_DATA 0x37
485#define PACKET3_MEM_SEMAPHORE 0x39
486#define PACKET3_MPEG_INDEX 0x3A
487#define PACKET3_WAIT_REG_MEM 0x3C
488#define PACKET3_MEM_WRITE 0x3D
489#define PACKET3_SURFACE_SYNC 0x43
490# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
491# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
492# define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
493# define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
494# define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
495# define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
496# define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
497# define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
498# define PACKET3_DB_DEST_BASE_ENA (1 << 14)
499# define PACKET3_CB8_DEST_BASE_ENA (1 << 15)
500# define PACKET3_CB9_DEST_BASE_ENA (1 << 16)
501# define PACKET3_CB10_DEST_BASE_ENA (1 << 17)
502# define PACKET3_CB11_DEST_BASE_ENA (1 << 18)
503# define PACKET3_FULL_CACHE_ENA (1 << 20)
504# define PACKET3_TC_ACTION_ENA (1 << 23)
505# define PACKET3_CB_ACTION_ENA (1 << 25)
506# define PACKET3_DB_ACTION_ENA (1 << 26)
507# define PACKET3_SH_ACTION_ENA (1 << 27)
508# define PACKET3_SX_ACTION_ENA (1 << 28)
509#define PACKET3_ME_INITIALIZE 0x44
510#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
511#define PACKET3_COND_WRITE 0x45
512#define PACKET3_EVENT_WRITE 0x46
Alex Deucherb40e7e12011-11-17 14:57:50 -0500513#define EVENT_TYPE(x) ((x) << 0)
514#define EVENT_INDEX(x) ((x) << 8)
515 /* 0 - any non-TS event
516 * 1 - ZPASS_DONE
517 * 2 - SAMPLE_PIPELINESTAT
518 * 3 - SAMPLE_STREAMOUTSTAT*
519 * 4 - *S_PARTIAL_FLUSH
520 * 5 - TS events
521 */
Alex Deucher0c88a022011-03-02 20:07:31 -0500522#define PACKET3_EVENT_WRITE_EOP 0x47
Alex Deucherb40e7e12011-11-17 14:57:50 -0500523#define DATA_SEL(x) ((x) << 29)
524 /* 0 - discard
525 * 1 - send low 32bit data
526 * 2 - send 64bit data
527 * 3 - send 64bit counter value
528 */
529#define INT_SEL(x) ((x) << 24)
530 /* 0 - none
531 * 1 - interrupt only (DATA_SEL = 0)
532 * 2 - interrupt when data write is confirmed
533 */
Alex Deucher0c88a022011-03-02 20:07:31 -0500534#define PACKET3_EVENT_WRITE_EOS 0x48
535#define PACKET3_PREAMBLE_CNTL 0x4A
536# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
537# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
538#define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C
539#define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D
540#define PACKET3_ALU_PS_CONST_UPDATE 0x4E
541#define PACKET3_ALU_VS_CONST_UPDATE 0x4F
542#define PACKET3_ONE_REG_WRITE 0x57
543#define PACKET3_SET_CONFIG_REG 0x68
544#define PACKET3_SET_CONFIG_REG_START 0x00008000
545#define PACKET3_SET_CONFIG_REG_END 0x0000ac00
546#define PACKET3_SET_CONTEXT_REG 0x69
547#define PACKET3_SET_CONTEXT_REG_START 0x00028000
548#define PACKET3_SET_CONTEXT_REG_END 0x00029000
549#define PACKET3_SET_ALU_CONST 0x6A
550/* alu const buffers only; no reg file */
551#define PACKET3_SET_BOOL_CONST 0x6B
552#define PACKET3_SET_BOOL_CONST_START 0x0003a500
553#define PACKET3_SET_BOOL_CONST_END 0x0003a518
554#define PACKET3_SET_LOOP_CONST 0x6C
555#define PACKET3_SET_LOOP_CONST_START 0x0003a200
556#define PACKET3_SET_LOOP_CONST_END 0x0003a500
557#define PACKET3_SET_RESOURCE 0x6D
558#define PACKET3_SET_RESOURCE_START 0x00030000
559#define PACKET3_SET_RESOURCE_END 0x00038000
560#define PACKET3_SET_SAMPLER 0x6E
561#define PACKET3_SET_SAMPLER_START 0x0003c000
562#define PACKET3_SET_SAMPLER_END 0x0003c600
563#define PACKET3_SET_CTL_CONST 0x6F
564#define PACKET3_SET_CTL_CONST_START 0x0003cff0
565#define PACKET3_SET_CTL_CONST_END 0x0003ff0c
566#define PACKET3_SET_RESOURCE_OFFSET 0x70
567#define PACKET3_SET_ALU_CONST_VS 0x71
568#define PACKET3_SET_ALU_CONST_DI 0x72
569#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
570#define PACKET3_SET_RESOURCE_INDIRECT 0x74
571#define PACKET3_SET_APPEND_CNT 0x75
572
Alex Deucher0af62b02011-01-06 21:19:31 -0500573#endif
574