Wu Zhangjin | d7edf47 | 2009-11-23 10:28:24 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Silicon Motion SM712 frame buffer device |
| 3 | * |
| 4 | * Copyright (C) 2006 Silicon Motion Technology Corp. |
| 5 | * Authors: Ge Wang, gewang@siliconmotion.com |
Javier Muñoz Mellid | d82f139 | 2010-03-29 19:35:24 +0200 | [diff] [blame] | 6 | * Boyod boyod.yang@siliconmotion.com.cn |
Wu Zhangjin | d7edf47 | 2009-11-23 10:28:24 +0800 | [diff] [blame] | 7 | * |
| 8 | * Copyright (C) 2009 Lemote, Inc. |
Wu Zhangjin | f7a904d | 2010-01-04 17:16:51 +0800 | [diff] [blame] | 9 | * Author: Wu Zhangjin, wuzhangjin@gmail.com |
Wu Zhangjin | d7edf47 | 2009-11-23 10:28:24 +0800 | [diff] [blame] | 10 | * |
| 11 | * This file is subject to the terms and conditions of the GNU General Public |
| 12 | * License. See the file COPYING in the main directory of this archive for |
| 13 | * more details. |
| 14 | */ |
| 15 | |
| 16 | #define SMTC_LINUX_FB_VERSION "version 0.11.2619.21.01 July 27, 2008" |
| 17 | |
| 18 | #define NR_PALETTE 256 |
| 19 | #define NR_RGB 2 |
| 20 | |
| 21 | #define FB_ACCEL_SMI_LYNX 88 |
| 22 | |
| 23 | #ifdef __BIG_ENDIAN |
| 24 | #define PC_VGA 0 |
| 25 | #else |
| 26 | #define PC_VGA 1 |
| 27 | #endif |
| 28 | |
| 29 | #define SCREEN_X_RES 1024 |
| 30 | #define SCREEN_Y_RES 600 |
| 31 | #define SCREEN_BPP 16 |
| 32 | |
| 33 | #ifndef FIELD_OFFSET |
| 34 | #define FIELD_OFSFET(type, field) \ |
| 35 | ((unsigned long) (PUCHAR) & (((type *)0)->field)) |
| 36 | #endif |
| 37 | |
| 38 | /*Assume SM712 graphics chip has 4MB VRAM */ |
| 39 | #define SM712_VIDEOMEMORYSIZE 0x00400000 |
| 40 | /*Assume SM722 graphics chip has 8MB VRAM */ |
| 41 | #define SM722_VIDEOMEMORYSIZE 0x00800000 |
| 42 | |
| 43 | #define dac_reg (0x3c8) |
| 44 | #define dac_val (0x3c9) |
| 45 | |
| 46 | extern char *smtc_RegBaseAddress; |
| 47 | #define smtc_mmiowb(dat, reg) writeb(dat, smtc_RegBaseAddress + reg) |
| 48 | #define smtc_mmioww(dat, reg) writew(dat, smtc_RegBaseAddress + reg) |
| 49 | #define smtc_mmiowl(dat, reg) writel(dat, smtc_RegBaseAddress + reg) |
| 50 | |
| 51 | #define smtc_mmiorb(reg) readb(smtc_RegBaseAddress + reg) |
| 52 | #define smtc_mmiorw(reg) readw(smtc_RegBaseAddress + reg) |
| 53 | #define smtc_mmiorl(reg) readl(smtc_RegBaseAddress + reg) |
| 54 | |
| 55 | #define SIZE_SR00_SR04 (0x04 - 0x00 + 1) |
| 56 | #define SIZE_SR10_SR24 (0x24 - 0x10 + 1) |
| 57 | #define SIZE_SR30_SR75 (0x75 - 0x30 + 1) |
| 58 | #define SIZE_SR80_SR93 (0x93 - 0x80 + 1) |
| 59 | #define SIZE_SRA0_SRAF (0xAF - 0xA0 + 1) |
| 60 | #define SIZE_GR00_GR08 (0x08 - 0x00 + 1) |
| 61 | #define SIZE_AR00_AR14 (0x14 - 0x00 + 1) |
| 62 | #define SIZE_CR00_CR18 (0x18 - 0x00 + 1) |
| 63 | #define SIZE_CR30_CR4D (0x4D - 0x30 + 1) |
| 64 | #define SIZE_CR90_CRA7 (0xA7 - 0x90 + 1) |
| 65 | #define SIZE_VPR (0x6C + 1) |
| 66 | #define SIZE_DPR (0x44 + 1) |
| 67 | |
| 68 | static inline void smtc_crtcw(int reg, int val) |
| 69 | { |
| 70 | smtc_mmiowb(reg, 0x3d4); |
| 71 | smtc_mmiowb(val, 0x3d5); |
| 72 | } |
| 73 | |
| 74 | static inline unsigned int smtc_crtcr(int reg) |
| 75 | { |
| 76 | smtc_mmiowb(reg, 0x3d4); |
| 77 | return smtc_mmiorb(0x3d5); |
| 78 | } |
| 79 | |
| 80 | static inline void smtc_grphw(int reg, int val) |
| 81 | { |
| 82 | smtc_mmiowb(reg, 0x3ce); |
| 83 | smtc_mmiowb(val, 0x3cf); |
| 84 | } |
| 85 | |
| 86 | static inline unsigned int smtc_grphr(int reg) |
| 87 | { |
| 88 | smtc_mmiowb(reg, 0x3ce); |
| 89 | return smtc_mmiorb(0x3cf); |
| 90 | } |
| 91 | |
| 92 | static inline void smtc_attrw(int reg, int val) |
| 93 | { |
| 94 | smtc_mmiorb(0x3da); |
| 95 | smtc_mmiowb(reg, 0x3c0); |
| 96 | smtc_mmiorb(0x3c1); |
| 97 | smtc_mmiowb(val, 0x3c0); |
| 98 | } |
| 99 | |
| 100 | static inline void smtc_seqw(int reg, int val) |
| 101 | { |
| 102 | smtc_mmiowb(reg, 0x3c4); |
| 103 | smtc_mmiowb(val, 0x3c5); |
| 104 | } |
| 105 | |
| 106 | static inline unsigned int smtc_seqr(int reg) |
| 107 | { |
| 108 | smtc_mmiowb(reg, 0x3c4); |
| 109 | return smtc_mmiorb(0x3c5); |
| 110 | } |
| 111 | |
| 112 | /* The next structure holds all information relevant for a specific video mode. |
| 113 | */ |
| 114 | |
| 115 | struct ModeInit { |
| 116 | int mmSizeX; |
| 117 | int mmSizeY; |
| 118 | int bpp; |
| 119 | int hz; |
| 120 | unsigned char Init_MISC; |
| 121 | unsigned char Init_SR00_SR04[SIZE_SR00_SR04]; |
| 122 | unsigned char Init_SR10_SR24[SIZE_SR10_SR24]; |
| 123 | unsigned char Init_SR30_SR75[SIZE_SR30_SR75]; |
| 124 | unsigned char Init_SR80_SR93[SIZE_SR80_SR93]; |
| 125 | unsigned char Init_SRA0_SRAF[SIZE_SRA0_SRAF]; |
| 126 | unsigned char Init_GR00_GR08[SIZE_GR00_GR08]; |
| 127 | unsigned char Init_AR00_AR14[SIZE_AR00_AR14]; |
| 128 | unsigned char Init_CR00_CR18[SIZE_CR00_CR18]; |
| 129 | unsigned char Init_CR30_CR4D[SIZE_CR30_CR4D]; |
| 130 | unsigned char Init_CR90_CRA7[SIZE_CR90_CRA7]; |
| 131 | }; |
| 132 | |
| 133 | /********************************************************************** |
| 134 | SM712 Mode table. |
| 135 | **********************************************************************/ |
| 136 | struct ModeInit VGAMode[] = { |
| 137 | { |
| 138 | /* mode#0: 640 x 480 16Bpp 60Hz */ |
| 139 | 640, 480, 16, 60, |
| 140 | /* Init_MISC */ |
| 141 | 0xE3, |
| 142 | { /* Init_SR0_SR4 */ |
| 143 | 0x03, 0x01, 0x0F, 0x00, 0x0E, |
| 144 | }, |
| 145 | { /* Init_SR10_SR24 */ |
| 146 | 0xFF, 0xBE, 0xEF, 0xFF, 0x00, 0x0E, 0x17, 0x2C, |
| 147 | 0x99, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 148 | 0xC4, 0x30, 0x02, 0x01, 0x01, |
| 149 | }, |
| 150 | { /* Init_SR30_SR75 */ |
| 151 | 0x32, 0x03, 0xA0, 0x09, 0xC0, 0x32, 0x32, 0x32, |
| 152 | 0x32, 0x32, 0x32, 0x32, 0x00, 0x00, 0x03, 0xFF, |
| 153 | 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC, |
| 154 | 0x20, 0x0C, 0x44, 0x20, 0x00, 0x32, 0x32, 0x32, |
| 155 | 0x04, 0x24, 0x63, 0x4F, 0x52, 0x0B, 0xDF, 0xEA, |
| 156 | 0x04, 0x50, 0x19, 0x32, 0x32, 0x00, 0x00, 0x32, |
| 157 | 0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00, |
| 158 | 0x50, 0x03, 0x74, 0x14, 0x07, 0x82, 0x07, 0x04, |
| 159 | 0x00, 0x45, 0x30, 0x30, 0x40, 0x30, |
| 160 | }, |
| 161 | { /* Init_SR80_SR93 */ |
| 162 | 0xFF, 0x07, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x32, |
| 163 | 0xF7, 0x00, 0x00, 0x00, 0xEF, 0xFF, 0x32, 0x32, |
| 164 | 0x00, 0x00, 0x00, 0x00, |
| 165 | }, |
| 166 | { /* Init_SRA0_SRAF */ |
| 167 | 0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED, |
| 168 | 0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xFF, 0xDF, |
| 169 | }, |
| 170 | { /* Init_GR00_GR08 */ |
| 171 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, |
| 172 | 0xFF, |
| 173 | }, |
| 174 | { /* Init_AR00_AR14 */ |
| 175 | 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, |
| 176 | 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, |
| 177 | 0x41, 0x00, 0x0F, 0x00, 0x00, |
| 178 | }, |
| 179 | { /* Init_CR00_CR18 */ |
| 180 | 0x5F, 0x4F, 0x4F, 0x00, 0x53, 0x1F, 0x0B, 0x3E, |
| 181 | 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 182 | 0xEA, 0x0C, 0xDF, 0x50, 0x40, 0xDF, 0x00, 0xE3, |
| 183 | 0xFF, |
| 184 | }, |
| 185 | { /* Init_CR30_CR4D */ |
| 186 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x03, 0x20, |
| 187 | 0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xFF, 0xFD, |
| 188 | 0x5F, 0x4F, 0x00, 0x54, 0x00, 0x0B, 0xDF, 0x00, |
| 189 | 0xEA, 0x0C, 0x2E, 0x00, 0x4F, 0xDF, |
| 190 | }, |
| 191 | { /* Init_CR90_CRA7 */ |
| 192 | 0x56, 0xDD, 0x5E, 0xEA, 0x87, 0x44, 0x8F, 0x55, |
| 193 | 0x0A, 0x8F, 0x55, 0x0A, 0x00, 0x00, 0x18, 0x00, |
| 194 | 0x11, 0x10, 0x0B, 0x0A, 0x0A, 0x0A, 0x0A, 0x00, |
| 195 | }, |
| 196 | }, |
| 197 | { |
| 198 | /* mode#1: 640 x 480 24Bpp 60Hz */ |
| 199 | 640, 480, 24, 60, |
| 200 | /* Init_MISC */ |
| 201 | 0xE3, |
| 202 | { /* Init_SR0_SR4 */ |
| 203 | 0x03, 0x01, 0x0F, 0x00, 0x0E, |
| 204 | }, |
| 205 | { /* Init_SR10_SR24 */ |
| 206 | 0xFF, 0xBE, 0xEF, 0xFF, 0x00, 0x0E, 0x17, 0x2C, |
| 207 | 0x99, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 208 | 0xC4, 0x30, 0x02, 0x01, 0x01, |
| 209 | }, |
| 210 | { /* Init_SR30_SR75 */ |
| 211 | 0x32, 0x03, 0xA0, 0x09, 0xC0, 0x32, 0x32, 0x32, |
| 212 | 0x32, 0x32, 0x32, 0x32, 0x00, 0x00, 0x03, 0xFF, |
| 213 | 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC, |
| 214 | 0x20, 0x0C, 0x44, 0x20, 0x00, 0x32, 0x32, 0x32, |
| 215 | 0x04, 0x24, 0x63, 0x4F, 0x52, 0x0B, 0xDF, 0xEA, |
| 216 | 0x04, 0x50, 0x19, 0x32, 0x32, 0x00, 0x00, 0x32, |
| 217 | 0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00, |
| 218 | 0x50, 0x03, 0x74, 0x14, 0x07, 0x82, 0x07, 0x04, |
| 219 | 0x00, 0x45, 0x30, 0x30, 0x40, 0x30, |
| 220 | }, |
| 221 | { /* Init_SR80_SR93 */ |
| 222 | 0xFF, 0x07, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x32, |
| 223 | 0xF7, 0x00, 0x00, 0x00, 0xEF, 0xFF, 0x32, 0x32, |
| 224 | 0x00, 0x00, 0x00, 0x00, |
| 225 | }, |
| 226 | { /* Init_SRA0_SRAF */ |
| 227 | 0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED, |
| 228 | 0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xFF, 0xDF, |
| 229 | }, |
| 230 | { /* Init_GR00_GR08 */ |
| 231 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, |
| 232 | 0xFF, |
| 233 | }, |
| 234 | { /* Init_AR00_AR14 */ |
| 235 | 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, |
| 236 | 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, |
| 237 | 0x41, 0x00, 0x0F, 0x00, 0x00, |
| 238 | }, |
| 239 | { /* Init_CR00_CR18 */ |
| 240 | 0x5F, 0x4F, 0x4F, 0x00, 0x53, 0x1F, 0x0B, 0x3E, |
| 241 | 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 242 | 0xEA, 0x0C, 0xDF, 0x50, 0x40, 0xDF, 0x00, 0xE3, |
| 243 | 0xFF, |
| 244 | }, |
| 245 | { /* Init_CR30_CR4D */ |
| 246 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x03, 0x20, |
| 247 | 0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xFF, 0xFD, |
| 248 | 0x5F, 0x4F, 0x00, 0x54, 0x00, 0x0B, 0xDF, 0x00, |
| 249 | 0xEA, 0x0C, 0x2E, 0x00, 0x4F, 0xDF, |
| 250 | }, |
| 251 | { /* Init_CR90_CRA7 */ |
| 252 | 0x56, 0xDD, 0x5E, 0xEA, 0x87, 0x44, 0x8F, 0x55, |
| 253 | 0x0A, 0x8F, 0x55, 0x0A, 0x00, 0x00, 0x18, 0x00, |
| 254 | 0x11, 0x10, 0x0B, 0x0A, 0x0A, 0x0A, 0x0A, 0x00, |
| 255 | }, |
| 256 | }, |
| 257 | { |
| 258 | /* mode#0: 640 x 480 32Bpp 60Hz */ |
| 259 | 640, 480, 32, 60, |
| 260 | /* Init_MISC */ |
| 261 | 0xE3, |
| 262 | { /* Init_SR0_SR4 */ |
| 263 | 0x03, 0x01, 0x0F, 0x00, 0x0E, |
| 264 | }, |
| 265 | { /* Init_SR10_SR24 */ |
| 266 | 0xFF, 0xBE, 0xEF, 0xFF, 0x00, 0x0E, 0x17, 0x2C, |
| 267 | 0x99, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 268 | 0xC4, 0x30, 0x02, 0x01, 0x01, |
| 269 | }, |
| 270 | { /* Init_SR30_SR75 */ |
| 271 | 0x32, 0x03, 0xA0, 0x09, 0xC0, 0x32, 0x32, 0x32, |
| 272 | 0x32, 0x32, 0x32, 0x32, 0x00, 0x00, 0x03, 0xFF, |
| 273 | 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC, |
| 274 | 0x20, 0x0C, 0x44, 0x20, 0x00, 0x32, 0x32, 0x32, |
| 275 | 0x04, 0x24, 0x63, 0x4F, 0x52, 0x0B, 0xDF, 0xEA, |
| 276 | 0x04, 0x50, 0x19, 0x32, 0x32, 0x00, 0x00, 0x32, |
| 277 | 0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00, |
| 278 | 0x50, 0x03, 0x74, 0x14, 0x07, 0x82, 0x07, 0x04, |
| 279 | 0x00, 0x45, 0x30, 0x30, 0x40, 0x30, |
| 280 | }, |
| 281 | { /* Init_SR80_SR93 */ |
| 282 | 0xFF, 0x07, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x32, |
| 283 | 0xF7, 0x00, 0x00, 0x00, 0xEF, 0xFF, 0x32, 0x32, |
| 284 | 0x00, 0x00, 0x00, 0x00, |
| 285 | }, |
| 286 | { /* Init_SRA0_SRAF */ |
| 287 | 0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED, |
| 288 | 0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xFF, 0xDF, |
| 289 | }, |
| 290 | { /* Init_GR00_GR08 */ |
| 291 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, |
| 292 | 0xFF, |
| 293 | }, |
| 294 | { /* Init_AR00_AR14 */ |
| 295 | 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, |
| 296 | 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, |
| 297 | 0x41, 0x00, 0x0F, 0x00, 0x00, |
| 298 | }, |
| 299 | { /* Init_CR00_CR18 */ |
| 300 | 0x5F, 0x4F, 0x4F, 0x00, 0x53, 0x1F, 0x0B, 0x3E, |
| 301 | 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 302 | 0xEA, 0x0C, 0xDF, 0x50, 0x40, 0xDF, 0x00, 0xE3, |
| 303 | 0xFF, |
| 304 | }, |
| 305 | { /* Init_CR30_CR4D */ |
| 306 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x03, 0x20, |
| 307 | 0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xFF, 0xFD, |
| 308 | 0x5F, 0x4F, 0x00, 0x54, 0x00, 0x0B, 0xDF, 0x00, |
| 309 | 0xEA, 0x0C, 0x2E, 0x00, 0x4F, 0xDF, |
| 310 | }, |
| 311 | { /* Init_CR90_CRA7 */ |
| 312 | 0x56, 0xDD, 0x5E, 0xEA, 0x87, 0x44, 0x8F, 0x55, |
| 313 | 0x0A, 0x8F, 0x55, 0x0A, 0x00, 0x00, 0x18, 0x00, |
| 314 | 0x11, 0x10, 0x0B, 0x0A, 0x0A, 0x0A, 0x0A, 0x00, |
| 315 | }, |
| 316 | }, |
| 317 | |
| 318 | { /* mode#2: 800 x 600 16Bpp 60Hz */ |
| 319 | 800, 600, 16, 60, |
| 320 | /* Init_MISC */ |
| 321 | 0x2B, |
| 322 | { /* Init_SR0_SR4 */ |
| 323 | 0x03, 0x01, 0x0F, 0x03, 0x0E, |
| 324 | }, |
| 325 | { /* Init_SR10_SR24 */ |
| 326 | 0xFF, 0xBE, 0xEE, 0xFF, 0x00, 0x0E, 0x17, 0x2C, |
| 327 | 0x99, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 328 | 0xC4, 0x30, 0x02, 0x01, 0x01, |
| 329 | }, |
| 330 | { /* Init_SR30_SR75 */ |
| 331 | 0x34, 0x03, 0x20, 0x09, 0xC0, 0x24, 0x24, 0x24, |
| 332 | 0x24, 0x24, 0x24, 0x24, 0x00, 0x00, 0x03, 0xFF, |
| 333 | 0x00, 0xFC, 0x00, 0x00, 0x20, 0x38, 0x00, 0xFC, |
| 334 | 0x20, 0x0C, 0x44, 0x20, 0x00, 0x24, 0x24, 0x24, |
| 335 | 0x04, 0x48, 0x83, 0x63, 0x68, 0x72, 0x57, 0x58, |
| 336 | 0x04, 0x55, 0x59, 0x24, 0x24, 0x00, 0x00, 0x24, |
| 337 | 0x01, 0x80, 0x7A, 0x1A, 0x1A, 0x00, 0x00, 0x00, |
| 338 | 0x50, 0x03, 0x74, 0x14, 0x1C, 0x85, 0x35, 0x13, |
| 339 | 0x02, 0x45, 0x30, 0x35, 0x40, 0x20, |
| 340 | }, |
| 341 | { /* Init_SR80_SR93 */ |
| 342 | 0x00, 0x00, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x24, |
| 343 | 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x24, 0x24, |
| 344 | 0x00, 0x00, 0x00, 0x00, |
| 345 | }, |
| 346 | { /* Init_SRA0_SRAF */ |
| 347 | 0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED, |
| 348 | 0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xBF, 0xDF, |
| 349 | }, |
| 350 | { /* Init_GR00_GR08 */ |
| 351 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, |
| 352 | 0xFF, |
| 353 | }, |
| 354 | { /* Init_AR00_AR14 */ |
| 355 | 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, |
| 356 | 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, |
| 357 | 0x41, 0x00, 0x0F, 0x00, 0x00, |
| 358 | }, |
| 359 | { /* Init_CR00_CR18 */ |
| 360 | 0x7F, 0x63, 0x63, 0x00, 0x68, 0x18, 0x72, 0xF0, |
| 361 | 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 362 | 0x58, 0x0C, 0x57, 0x64, 0x40, 0x57, 0x00, 0xE3, |
| 363 | 0xFF, |
| 364 | }, |
| 365 | { /* Init_CR30_CR4D */ |
| 366 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x03, 0x20, |
| 367 | 0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xBF, 0xFD, |
| 368 | 0x7F, 0x63, 0x00, 0x69, 0x18, 0x72, 0x57, 0x00, |
| 369 | 0x58, 0x0C, 0xE0, 0x20, 0x63, 0x57, |
| 370 | }, |
| 371 | { /* Init_CR90_CRA7 */ |
| 372 | 0x56, 0x4B, 0x5E, 0x55, 0x86, 0x9D, 0x8E, 0xAA, |
| 373 | 0xDB, 0x2A, 0xDF, 0x33, 0x00, 0x00, 0x18, 0x00, |
| 374 | 0x20, 0x1F, 0x1A, 0x19, 0x0F, 0x0F, 0x0F, 0x00, |
| 375 | }, |
| 376 | }, |
| 377 | { /* mode#3: 800 x 600 24Bpp 60Hz */ |
| 378 | 800, 600, 24, 60, |
| 379 | 0x2B, |
| 380 | { /* Init_SR0_SR4 */ |
| 381 | 0x03, 0x01, 0x0F, 0x03, 0x0E, |
| 382 | }, |
| 383 | { /* Init_SR10_SR24 */ |
| 384 | 0xFF, 0xBE, 0xEE, 0xFF, 0x00, 0x0E, 0x17, 0x2C, |
| 385 | 0x99, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 386 | 0xC4, 0x30, 0x02, 0x01, 0x01, |
| 387 | }, |
| 388 | { /* Init_SR30_SR75 */ |
| 389 | 0x36, 0x03, 0x20, 0x09, 0xC0, 0x36, 0x36, 0x36, |
| 390 | 0x36, 0x36, 0x36, 0x36, 0x00, 0x00, 0x03, 0xFF, |
| 391 | 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC, |
| 392 | 0x20, 0x0C, 0x44, 0x20, 0x00, 0x36, 0x36, 0x36, |
| 393 | 0x04, 0x48, 0x83, 0x63, 0x68, 0x72, 0x57, 0x58, |
| 394 | 0x04, 0x55, 0x59, 0x36, 0x36, 0x00, 0x00, 0x36, |
| 395 | 0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00, |
| 396 | 0x50, 0x03, 0x74, 0x14, 0x1C, 0x85, 0x35, 0x13, |
| 397 | 0x02, 0x45, 0x30, 0x30, 0x40, 0x20, |
| 398 | }, |
| 399 | { /* Init_SR80_SR93 */ |
| 400 | 0xFF, 0x07, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x36, |
| 401 | 0xF7, 0x00, 0x00, 0x00, 0xEF, 0xFF, 0x36, 0x36, |
| 402 | 0x00, 0x00, 0x00, 0x00, |
| 403 | }, |
| 404 | { /* Init_SRA0_SRAF */ |
| 405 | 0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED, |
| 406 | 0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xBF, 0xDF, |
| 407 | }, |
| 408 | { /* Init_GR00_GR08 */ |
| 409 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, |
| 410 | 0xFF, |
| 411 | }, |
| 412 | { /* Init_AR00_AR14 */ |
| 413 | 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, |
| 414 | 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, |
| 415 | 0x41, 0x00, 0x0F, 0x00, 0x00, |
| 416 | }, |
| 417 | { /* Init_CR00_CR18 */ |
| 418 | 0x7F, 0x63, 0x63, 0x00, 0x68, 0x18, 0x72, 0xF0, |
| 419 | 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 420 | 0x58, 0x0C, 0x57, 0x64, 0x40, 0x57, 0x00, 0xE3, |
| 421 | 0xFF, |
| 422 | }, |
| 423 | { /* Init_CR30_CR4D */ |
| 424 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x03, 0x20, |
| 425 | 0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xBF, 0xFD, |
| 426 | 0x7F, 0x63, 0x00, 0x69, 0x18, 0x72, 0x57, 0x00, |
| 427 | 0x58, 0x0C, 0xE0, 0x20, 0x63, 0x57, |
| 428 | }, |
| 429 | { /* Init_CR90_CRA7 */ |
| 430 | 0x56, 0x4B, 0x5E, 0x55, 0x86, 0x9D, 0x8E, 0xAA, |
| 431 | 0xDB, 0x2A, 0xDF, 0x33, 0x00, 0x00, 0x18, 0x00, |
| 432 | 0x20, 0x1F, 0x1A, 0x19, 0x0F, 0x0F, 0x0F, 0x00, |
| 433 | }, |
| 434 | }, |
| 435 | { /* mode#7: 800 x 600 32Bpp 60Hz */ |
| 436 | 800, 600, 32, 60, |
| 437 | /* Init_MISC */ |
| 438 | 0x2B, |
| 439 | { /* Init_SR0_SR4 */ |
| 440 | 0x03, 0x01, 0x0F, 0x03, 0x0E, |
| 441 | }, |
| 442 | { /* Init_SR10_SR24 */ |
| 443 | 0xFF, 0xBE, 0xEE, 0xFF, 0x00, 0x0E, 0x17, 0x2C, |
| 444 | 0x99, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 445 | 0xC4, 0x30, 0x02, 0x01, 0x01, |
| 446 | }, |
| 447 | { /* Init_SR30_SR75 */ |
| 448 | 0x34, 0x03, 0x20, 0x09, 0xC0, 0x24, 0x24, 0x24, |
| 449 | 0x24, 0x24, 0x24, 0x24, 0x00, 0x00, 0x03, 0xFF, |
| 450 | 0x00, 0xFC, 0x00, 0x00, 0x20, 0x38, 0x00, 0xFC, |
| 451 | 0x20, 0x0C, 0x44, 0x20, 0x00, 0x24, 0x24, 0x24, |
| 452 | 0x04, 0x48, 0x83, 0x63, 0x68, 0x72, 0x57, 0x58, |
| 453 | 0x04, 0x55, 0x59, 0x24, 0x24, 0x00, 0x00, 0x24, |
| 454 | 0x01, 0x80, 0x7A, 0x1A, 0x1A, 0x00, 0x00, 0x00, |
| 455 | 0x50, 0x03, 0x74, 0x14, 0x1C, 0x85, 0x35, 0x13, |
| 456 | 0x02, 0x45, 0x30, 0x35, 0x40, 0x20, |
| 457 | }, |
| 458 | { /* Init_SR80_SR93 */ |
| 459 | 0x00, 0x00, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x24, |
| 460 | 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x24, 0x24, |
| 461 | 0x00, 0x00, 0x00, 0x00, |
| 462 | }, |
| 463 | { /* Init_SRA0_SRAF */ |
| 464 | 0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED, |
| 465 | 0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xBF, 0xDF, |
| 466 | }, |
| 467 | { /* Init_GR00_GR08 */ |
| 468 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, |
| 469 | 0xFF, |
| 470 | }, |
| 471 | { /* Init_AR00_AR14 */ |
| 472 | 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, |
| 473 | 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, |
| 474 | 0x41, 0x00, 0x0F, 0x00, 0x00, |
| 475 | }, |
| 476 | { /* Init_CR00_CR18 */ |
| 477 | 0x7F, 0x63, 0x63, 0x00, 0x68, 0x18, 0x72, 0xF0, |
| 478 | 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 479 | 0x58, 0x0C, 0x57, 0x64, 0x40, 0x57, 0x00, 0xE3, |
| 480 | 0xFF, |
| 481 | }, |
| 482 | { /* Init_CR30_CR4D */ |
| 483 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x03, 0x20, |
| 484 | 0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xBF, 0xFD, |
| 485 | 0x7F, 0x63, 0x00, 0x69, 0x18, 0x72, 0x57, 0x00, |
| 486 | 0x58, 0x0C, 0xE0, 0x20, 0x63, 0x57, |
| 487 | }, |
| 488 | { /* Init_CR90_CRA7 */ |
| 489 | 0x56, 0x4B, 0x5E, 0x55, 0x86, 0x9D, 0x8E, 0xAA, |
| 490 | 0xDB, 0x2A, 0xDF, 0x33, 0x00, 0x00, 0x18, 0x00, |
| 491 | 0x20, 0x1F, 0x1A, 0x19, 0x0F, 0x0F, 0x0F, 0x00, |
| 492 | }, |
| 493 | }, |
| 494 | /* We use 1024x768 table to light 1024x600 panel for lemote */ |
| 495 | { /* mode#4: 1024 x 600 16Bpp 60Hz */ |
| 496 | 1024, 600, 16, 60, |
| 497 | /* Init_MISC */ |
| 498 | 0xEB, |
| 499 | { /* Init_SR0_SR4 */ |
| 500 | 0x03, 0x01, 0x0F, 0x00, 0x0E, |
| 501 | }, |
| 502 | { /* Init_SR10_SR24 */ |
| 503 | 0xC8, 0x40, 0x14, 0x60, 0x00, 0x0A, 0x17, 0x20, |
| 504 | 0x51, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 505 | 0xC4, 0x30, 0x02, 0x00, 0x01, |
| 506 | }, |
| 507 | { /* Init_SR30_SR75 */ |
| 508 | 0x22, 0x03, 0x24, 0x09, 0xC0, 0x22, 0x22, 0x22, |
| 509 | 0x22, 0x22, 0x22, 0x22, 0x00, 0x00, 0x03, 0xFF, |
| 510 | 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC, |
| 511 | 0x20, 0x0C, 0x44, 0x20, 0x00, 0x22, 0x22, 0x22, |
| 512 | 0x06, 0x68, 0xA7, 0x7F, 0x83, 0x24, 0xFF, 0x03, |
| 513 | 0x00, 0x60, 0x59, 0x22, 0x22, 0x00, 0x00, 0x22, |
| 514 | 0x01, 0x80, 0x7A, 0x1A, 0x1A, 0x00, 0x00, 0x00, |
| 515 | 0x50, 0x03, 0x16, 0x02, 0x0D, 0x82, 0x09, 0x02, |
| 516 | 0x04, 0x45, 0x3F, 0x30, 0x40, 0x20, |
| 517 | }, |
| 518 | { /* Init_SR80_SR93 */ |
| 519 | 0xFF, 0x07, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x3A, |
| 520 | 0xF7, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x3A, 0x3A, |
| 521 | 0x00, 0x00, 0x00, 0x00, |
| 522 | }, |
| 523 | { /* Init_SRA0_SRAF */ |
| 524 | 0x00, 0xFB, 0x9F, 0x01, 0x00, 0xED, 0xED, 0xED, |
| 525 | 0x7B, 0xFB, 0xFF, 0xFF, 0x97, 0xEF, 0xBF, 0xDF, |
| 526 | }, |
| 527 | { /* Init_GR00_GR08 */ |
| 528 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, |
| 529 | 0xFF, |
| 530 | }, |
| 531 | { /* Init_AR00_AR14 */ |
| 532 | 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, |
| 533 | 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, |
| 534 | 0x41, 0x00, 0x0F, 0x00, 0x00, |
| 535 | }, |
| 536 | { /* Init_CR00_CR18 */ |
| 537 | 0xA3, 0x7F, 0x7F, 0x00, 0x85, 0x16, 0x24, 0xF5, |
| 538 | 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 539 | 0x03, 0x09, 0xFF, 0x80, 0x40, 0xFF, 0x00, 0xE3, |
| 540 | 0xFF, |
| 541 | }, |
| 542 | { /* Init_CR30_CR4D */ |
| 543 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02, 0x20, |
| 544 | 0x00, 0x00, 0x00, 0x40, 0x00, 0xFF, 0xBF, 0xFF, |
| 545 | 0xA3, 0x7F, 0x00, 0x82, 0x0b, 0x6f, 0x57, 0x00, |
| 546 | 0x5c, 0x0f, 0xE0, 0xe0, 0x7F, 0x57, |
| 547 | }, |
| 548 | { /* Init_CR90_CRA7 */ |
| 549 | 0x55, 0xD9, 0x5D, 0xE1, 0x86, 0x1B, 0x8E, 0x26, |
| 550 | 0xDA, 0x8D, 0xDE, 0x94, 0x00, 0x00, 0x18, 0x00, |
| 551 | 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x15, 0x03, |
| 552 | }, |
| 553 | }, |
| 554 | { /* mode#5: 1024 x 768 24Bpp 60Hz */ |
| 555 | 1024, 768, 24, 60, |
| 556 | /* Init_MISC */ |
| 557 | 0xEB, |
| 558 | { /* Init_SR0_SR4 */ |
| 559 | 0x03, 0x01, 0x0F, 0x03, 0x0E, |
| 560 | }, |
| 561 | { /* Init_SR10_SR24 */ |
| 562 | 0xF3, 0xB6, 0xC0, 0xDD, 0x00, 0x0E, 0x17, 0x2C, |
| 563 | 0x99, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 564 | 0xC4, 0x30, 0x02, 0x01, 0x01, |
| 565 | }, |
| 566 | { /* Init_SR30_SR75 */ |
| 567 | 0x38, 0x03, 0x20, 0x09, 0xC0, 0x3A, 0x3A, 0x3A, |
| 568 | 0x3A, 0x3A, 0x3A, 0x3A, 0x00, 0x00, 0x03, 0xFF, |
| 569 | 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC, |
| 570 | 0x20, 0x0C, 0x44, 0x20, 0x00, 0x00, 0x00, 0x3A, |
| 571 | 0x06, 0x68, 0xA7, 0x7F, 0x83, 0x24, 0xFF, 0x03, |
| 572 | 0x00, 0x60, 0x59, 0x3A, 0x3A, 0x00, 0x00, 0x3A, |
| 573 | 0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00, |
| 574 | 0x50, 0x03, 0x74, 0x14, 0x3B, 0x0D, 0x09, 0x02, |
| 575 | 0x04, 0x45, 0x30, 0x30, 0x40, 0x20, |
| 576 | }, |
| 577 | { /* Init_SR80_SR93 */ |
| 578 | 0xFF, 0x07, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x3A, |
| 579 | 0xF7, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x3A, 0x3A, |
| 580 | 0x00, 0x00, 0x00, 0x00, |
| 581 | }, |
| 582 | { /* Init_SRA0_SRAF */ |
| 583 | 0x00, 0xFB, 0x9F, 0x01, 0x00, 0xED, 0xED, 0xED, |
| 584 | 0x7B, 0xFB, 0xFF, 0xFF, 0x97, 0xEF, 0xBF, 0xDF, |
| 585 | }, |
| 586 | { /* Init_GR00_GR08 */ |
| 587 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, |
| 588 | 0xFF, |
| 589 | }, |
| 590 | { /* Init_AR00_AR14 */ |
| 591 | 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, |
| 592 | 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, |
| 593 | 0x41, 0x00, 0x0F, 0x00, 0x00, |
| 594 | }, |
| 595 | { /* Init_CR00_CR18 */ |
| 596 | 0xA3, 0x7F, 0x7F, 0x00, 0x85, 0x16, 0x24, 0xF5, |
| 597 | 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 598 | 0x03, 0x09, 0xFF, 0x80, 0x40, 0xFF, 0x00, 0xE3, |
| 599 | 0xFF, |
| 600 | }, |
| 601 | { /* Init_CR30_CR4D */ |
| 602 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02, 0x20, |
| 603 | 0x00, 0x00, 0x00, 0x40, 0x00, 0xFF, 0xBF, 0xFF, |
| 604 | 0xA3, 0x7F, 0x00, 0x86, 0x15, 0x24, 0xFF, 0x00, |
| 605 | 0x01, 0x07, 0xE5, 0x20, 0x7F, 0xFF, |
| 606 | }, |
| 607 | { /* Init_CR90_CRA7 */ |
| 608 | 0x55, 0xD9, 0x5D, 0xE1, 0x86, 0x1B, 0x8E, 0x26, |
| 609 | 0xDA, 0x8D, 0xDE, 0x94, 0x00, 0x00, 0x18, 0x00, |
| 610 | 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x15, 0x03, |
| 611 | }, |
| 612 | }, |
| 613 | { /* mode#4: 1024 x 768 32Bpp 60Hz */ |
| 614 | 1024, 768, 32, 60, |
| 615 | /* Init_MISC */ |
| 616 | 0xEB, |
| 617 | { /* Init_SR0_SR4 */ |
| 618 | 0x03, 0x01, 0x0F, 0x03, 0x0E, |
| 619 | }, |
| 620 | { /* Init_SR10_SR24 */ |
| 621 | 0xF3, 0xB6, 0xC0, 0xDD, 0x00, 0x0E, 0x17, 0x2C, |
| 622 | 0x99, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 623 | 0xC4, 0x32, 0x02, 0x01, 0x01, |
| 624 | }, |
| 625 | { /* Init_SR30_SR75 */ |
| 626 | 0x38, 0x03, 0x20, 0x09, 0xC0, 0x3A, 0x3A, 0x3A, |
| 627 | 0x3A, 0x3A, 0x3A, 0x3A, 0x00, 0x00, 0x03, 0xFF, |
| 628 | 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC, |
| 629 | 0x20, 0x0C, 0x44, 0x20, 0x00, 0x00, 0x00, 0x3A, |
| 630 | 0x06, 0x68, 0xA7, 0x7F, 0x83, 0x24, 0xFF, 0x03, |
| 631 | 0x00, 0x60, 0x59, 0x3A, 0x3A, 0x00, 0x00, 0x3A, |
| 632 | 0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00, |
| 633 | 0x50, 0x03, 0x74, 0x14, 0x3B, 0x0D, 0x09, 0x02, |
| 634 | 0x04, 0x45, 0x30, 0x30, 0x40, 0x20, |
| 635 | }, |
| 636 | { /* Init_SR80_SR93 */ |
| 637 | 0xFF, 0x07, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x3A, |
| 638 | 0xF7, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x3A, 0x3A, |
| 639 | 0x00, 0x00, 0x00, 0x00, |
| 640 | }, |
| 641 | { /* Init_SRA0_SRAF */ |
| 642 | 0x00, 0xFB, 0x9F, 0x01, 0x00, 0xED, 0xED, 0xED, |
| 643 | 0x7B, 0xFB, 0xFF, 0xFF, 0x97, 0xEF, 0xBF, 0xDF, |
| 644 | }, |
| 645 | { /* Init_GR00_GR08 */ |
| 646 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, |
| 647 | 0xFF, |
| 648 | }, |
| 649 | { /* Init_AR00_AR14 */ |
| 650 | 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, |
| 651 | 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, |
| 652 | 0x41, 0x00, 0x0F, 0x00, 0x00, |
| 653 | }, |
| 654 | { /* Init_CR00_CR18 */ |
| 655 | 0xA3, 0x7F, 0x7F, 0x00, 0x85, 0x16, 0x24, 0xF5, |
| 656 | 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 657 | 0x03, 0x09, 0xFF, 0x80, 0x40, 0xFF, 0x00, 0xE3, |
| 658 | 0xFF, |
| 659 | }, |
| 660 | { /* Init_CR30_CR4D */ |
| 661 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02, 0x20, |
| 662 | 0x00, 0x00, 0x00, 0x40, 0x00, 0xFF, 0xBF, 0xFF, |
| 663 | 0xA3, 0x7F, 0x00, 0x86, 0x15, 0x24, 0xFF, 0x00, |
| 664 | 0x01, 0x07, 0xE5, 0x20, 0x7F, 0xFF, |
| 665 | }, |
| 666 | { /* Init_CR90_CRA7 */ |
| 667 | 0x55, 0xD9, 0x5D, 0xE1, 0x86, 0x1B, 0x8E, 0x26, |
| 668 | 0xDA, 0x8D, 0xDE, 0x94, 0x00, 0x00, 0x18, 0x00, |
| 669 | 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x15, 0x03, |
| 670 | }, |
| 671 | }, |
| 672 | { /* mode#6: 320 x 240 16Bpp 60Hz */ |
| 673 | 320, 240, 16, 60, |
| 674 | /* Init_MISC */ |
| 675 | 0xEB, |
| 676 | { /* Init_SR0_SR4 */ |
| 677 | 0x03, 0x01, 0x0F, 0x03, 0x0E, |
| 678 | }, |
| 679 | { /* Init_SR10_SR24 */ |
| 680 | 0xF3, 0xB6, 0xC0, 0xDD, 0x00, 0x0E, 0x17, 0x2C, |
| 681 | 0x99, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 682 | 0xC4, 0x32, 0x02, 0x01, 0x01, |
| 683 | }, |
| 684 | { /* Init_SR30_SR75 */ |
| 685 | 0x38, 0x03, 0x20, 0x09, 0xC0, 0x3A, 0x3A, 0x3A, |
| 686 | 0x3A, 0x3A, 0x3A, 0x3A, 0x00, 0x00, 0x03, 0xFF, |
| 687 | 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC, |
| 688 | 0x20, 0x0C, 0x44, 0x20, 0x00, 0x00, 0x00, 0x3A, |
| 689 | 0x06, 0x68, 0xA7, 0x7F, 0x83, 0x24, 0xFF, 0x03, |
| 690 | 0x00, 0x60, 0x59, 0x3A, 0x3A, 0x00, 0x00, 0x3A, |
| 691 | 0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00, |
| 692 | 0x50, 0x03, 0x74, 0x14, 0x08, 0x43, 0x08, 0x43, |
| 693 | 0x04, 0x45, 0x30, 0x30, 0x40, 0x20, |
| 694 | }, |
| 695 | { /* Init_SR80_SR93 */ |
| 696 | 0xFF, 0x07, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x3A, |
| 697 | 0xF7, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x3A, 0x3A, |
| 698 | 0x00, 0x00, 0x00, 0x00, |
| 699 | }, |
| 700 | { /* Init_SRA0_SRAF */ |
| 701 | 0x00, 0xFB, 0x9F, 0x01, 0x00, 0xED, 0xED, 0xED, |
| 702 | 0x7B, 0xFB, 0xFF, 0xFF, 0x97, 0xEF, 0xBF, 0xDF, |
| 703 | }, |
| 704 | { /* Init_GR00_GR08 */ |
| 705 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, |
| 706 | 0xFF, |
| 707 | }, |
| 708 | { /* Init_AR00_AR14 */ |
| 709 | 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, |
| 710 | 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, |
| 711 | 0x41, 0x00, 0x0F, 0x00, 0x00, |
| 712 | }, |
| 713 | { /* Init_CR00_CR18 */ |
| 714 | 0xA3, 0x7F, 0x7F, 0x00, 0x85, 0x16, 0x24, 0xF5, |
| 715 | 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 716 | 0x03, 0x09, 0xFF, 0x80, 0x40, 0xFF, 0x00, 0xE3, |
| 717 | 0xFF, |
| 718 | }, |
| 719 | { /* Init_CR30_CR4D */ |
| 720 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02, 0x20, |
| 721 | 0x00, 0x00, 0x30, 0x40, 0x00, 0xFF, 0xBF, 0xFF, |
| 722 | 0x2E, 0x27, 0x00, 0x2b, 0x0c, 0x0F, 0xEF, 0x00, |
| 723 | 0xFe, 0x0f, 0x01, 0xC0, 0x27, 0xEF, |
| 724 | }, |
| 725 | { /* Init_CR90_CRA7 */ |
| 726 | 0x55, 0xD9, 0x5D, 0xE1, 0x86, 0x1B, 0x8E, 0x26, |
| 727 | 0xDA, 0x8D, 0xDE, 0x94, 0x00, 0x00, 0x18, 0x00, |
| 728 | 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x15, 0x03, |
| 729 | }, |
| 730 | }, |
| 731 | |
| 732 | { /* mode#8: 320 x 240 32Bpp 60Hz */ |
| 733 | 320, 240, 32, 60, |
| 734 | /* Init_MISC */ |
| 735 | 0xEB, |
| 736 | { /* Init_SR0_SR4 */ |
| 737 | 0x03, 0x01, 0x0F, 0x03, 0x0E, |
| 738 | }, |
| 739 | { /* Init_SR10_SR24 */ |
| 740 | 0xF3, 0xB6, 0xC0, 0xDD, 0x00, 0x0E, 0x17, 0x2C, |
| 741 | 0x99, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 742 | 0xC4, 0x32, 0x02, 0x01, 0x01, |
| 743 | }, |
| 744 | { /* Init_SR30_SR75 */ |
| 745 | 0x38, 0x03, 0x20, 0x09, 0xC0, 0x3A, 0x3A, 0x3A, |
| 746 | 0x3A, 0x3A, 0x3A, 0x3A, 0x00, 0x00, 0x03, 0xFF, |
| 747 | 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC, |
| 748 | 0x20, 0x0C, 0x44, 0x20, 0x00, 0x00, 0x00, 0x3A, |
| 749 | 0x06, 0x68, 0xA7, 0x7F, 0x83, 0x24, 0xFF, 0x03, |
| 750 | 0x00, 0x60, 0x59, 0x3A, 0x3A, 0x00, 0x00, 0x3A, |
| 751 | 0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00, |
| 752 | 0x50, 0x03, 0x74, 0x14, 0x08, 0x43, 0x08, 0x43, |
| 753 | 0x04, 0x45, 0x30, 0x30, 0x40, 0x20, |
| 754 | }, |
| 755 | { /* Init_SR80_SR93 */ |
| 756 | 0xFF, 0x07, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x3A, |
| 757 | 0xF7, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x3A, 0x3A, |
| 758 | 0x00, 0x00, 0x00, 0x00, |
| 759 | }, |
| 760 | { /* Init_SRA0_SRAF */ |
| 761 | 0x00, 0xFB, 0x9F, 0x01, 0x00, 0xED, 0xED, 0xED, |
| 762 | 0x7B, 0xFB, 0xFF, 0xFF, 0x97, 0xEF, 0xBF, 0xDF, |
| 763 | }, |
| 764 | { /* Init_GR00_GR08 */ |
| 765 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, |
| 766 | 0xFF, |
| 767 | }, |
| 768 | { /* Init_AR00_AR14 */ |
| 769 | 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, |
| 770 | 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, |
| 771 | 0x41, 0x00, 0x0F, 0x00, 0x00, |
| 772 | }, |
| 773 | { /* Init_CR00_CR18 */ |
| 774 | 0xA3, 0x7F, 0x7F, 0x00, 0x85, 0x16, 0x24, 0xF5, |
| 775 | 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 776 | 0x03, 0x09, 0xFF, 0x80, 0x40, 0xFF, 0x00, 0xE3, |
| 777 | 0xFF, |
| 778 | }, |
| 779 | { /* Init_CR30_CR4D */ |
| 780 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02, 0x20, |
| 781 | 0x00, 0x00, 0x30, 0x40, 0x00, 0xFF, 0xBF, 0xFF, |
| 782 | 0x2E, 0x27, 0x00, 0x2b, 0x0c, 0x0F, 0xEF, 0x00, |
| 783 | 0xFe, 0x0f, 0x01, 0xC0, 0x27, 0xEF, |
| 784 | }, |
| 785 | { /* Init_CR90_CRA7 */ |
| 786 | 0x55, 0xD9, 0x5D, 0xE1, 0x86, 0x1B, 0x8E, 0x26, |
| 787 | 0xDA, 0x8D, 0xDE, 0x94, 0x00, 0x00, 0x18, 0x00, |
| 788 | 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x15, 0x03, |
| 789 | }, |
| 790 | }, |
| 791 | }; |
| 792 | |
| 793 | #define numVGAModes (sizeof(VGAMode) / sizeof(struct ModeInit)) |