Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Christian König. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Christian König |
| 25 | */ |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 26 | #include <drm/drmP.h> |
| 27 | #include <drm/radeon_drm.h> |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 28 | #include "radeon.h" |
Daniel Vetter | 3574dda | 2011-02-18 17:59:19 +0100 | [diff] [blame] | 29 | #include "radeon_asic.h" |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 30 | #include "r600d.h" |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 31 | #include "atom.h" |
| 32 | |
| 33 | /* |
| 34 | * HDMI color format |
| 35 | */ |
| 36 | enum r600_hdmi_color_format { |
| 37 | RGB = 0, |
| 38 | YCC_422 = 1, |
| 39 | YCC_444 = 2 |
| 40 | }; |
| 41 | |
| 42 | /* |
| 43 | * IEC60958 status bits |
| 44 | */ |
| 45 | enum r600_hdmi_iec_status_bits { |
| 46 | AUDIO_STATUS_DIG_ENABLE = 0x01, |
Rafał Miłecki | 3fe373d | 2010-03-06 13:03:38 +0000 | [diff] [blame] | 47 | AUDIO_STATUS_V = 0x02, |
| 48 | AUDIO_STATUS_VCFG = 0x04, |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 49 | AUDIO_STATUS_EMPHASIS = 0x08, |
| 50 | AUDIO_STATUS_COPYRIGHT = 0x10, |
| 51 | AUDIO_STATUS_NONAUDIO = 0x20, |
| 52 | AUDIO_STATUS_PROFESSIONAL = 0x40, |
Rafał Miłecki | 3fe373d | 2010-03-06 13:03:38 +0000 | [diff] [blame] | 53 | AUDIO_STATUS_LEVEL = 0x80 |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 54 | }; |
| 55 | |
Lauri Kasanen | 1109ca0 | 2012-08-31 13:43:50 -0400 | [diff] [blame] | 56 | static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = { |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 57 | /* 32kHz 44.1kHz 48kHz */ |
| 58 | /* Clock N CTS N CTS N CTS */ |
| 59 | { 25174, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */ |
| 60 | { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */ |
| 61 | { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */ |
| 62 | { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */ |
| 63 | { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */ |
| 64 | { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */ |
| 65 | { 74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */ |
| 66 | { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */ |
| 67 | { 148351, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */ |
| 68 | { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */ |
| 69 | { 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */ |
| 70 | }; |
| 71 | |
| 72 | /* |
| 73 | * calculate CTS value if it's not found in the table |
| 74 | */ |
Rafał Miłecki | 1b688d08 | 2012-04-30 15:44:54 +0200 | [diff] [blame] | 75 | static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int N, int freq) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 76 | { |
| 77 | if (*CTS == 0) |
Rafał Miłecki | 3fe373d | 2010-03-06 13:03:38 +0000 | [diff] [blame] | 78 | *CTS = clock * N / (128 * freq) * 1000; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 79 | DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n", |
| 80 | N, *CTS, freq); |
| 81 | } |
| 82 | |
Rafał Miłecki | 1b688d08 | 2012-04-30 15:44:54 +0200 | [diff] [blame] | 83 | struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock) |
| 84 | { |
| 85 | struct radeon_hdmi_acr res; |
| 86 | u8 i; |
| 87 | |
| 88 | for (i = 0; r600_hdmi_predefined_acr[i].clock != clock && |
| 89 | r600_hdmi_predefined_acr[i].clock != 0; i++) |
| 90 | ; |
| 91 | res = r600_hdmi_predefined_acr[i]; |
| 92 | |
| 93 | /* In case some CTS are missing */ |
| 94 | r600_hdmi_calc_cts(clock, &res.cts_32khz, res.n_32khz, 32000); |
| 95 | r600_hdmi_calc_cts(clock, &res.cts_44_1khz, res.n_44_1khz, 44100); |
| 96 | r600_hdmi_calc_cts(clock, &res.cts_48khz, res.n_48khz, 48000); |
| 97 | |
| 98 | return res; |
| 99 | } |
| 100 | |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 101 | /* |
| 102 | * update the N and CTS parameters for a given pixel clock rate |
| 103 | */ |
| 104 | static void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) |
| 105 | { |
| 106 | struct drm_device *dev = encoder->dev; |
| 107 | struct radeon_device *rdev = dev->dev_private; |
Rafał Miłecki | 1b688d08 | 2012-04-30 15:44:54 +0200 | [diff] [blame] | 108 | struct radeon_hdmi_acr acr = r600_hdmi_acr(clock); |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 109 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 110 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 111 | uint32_t offset = dig->afmt->offset; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 112 | |
Rafał Miłecki | 1b688d08 | 2012-04-30 15:44:54 +0200 | [diff] [blame] | 113 | WREG32(HDMI0_ACR_32_0 + offset, HDMI0_ACR_CTS_32(acr.cts_32khz)); |
| 114 | WREG32(HDMI0_ACR_32_1 + offset, acr.n_32khz); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 115 | |
Rafał Miłecki | 1b688d08 | 2012-04-30 15:44:54 +0200 | [diff] [blame] | 116 | WREG32(HDMI0_ACR_44_0 + offset, HDMI0_ACR_CTS_44(acr.cts_44_1khz)); |
| 117 | WREG32(HDMI0_ACR_44_1 + offset, acr.n_44_1khz); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 118 | |
Rafał Miłecki | 1b688d08 | 2012-04-30 15:44:54 +0200 | [diff] [blame] | 119 | WREG32(HDMI0_ACR_48_0 + offset, HDMI0_ACR_CTS_48(acr.cts_48khz)); |
| 120 | WREG32(HDMI0_ACR_48_1 + offset, acr.n_48khz); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 121 | } |
| 122 | |
| 123 | /* |
| 124 | * calculate the crc for a given info frame |
| 125 | */ |
| 126 | static void r600_hdmi_infoframe_checksum(uint8_t packetType, |
| 127 | uint8_t versionNumber, |
| 128 | uint8_t length, |
| 129 | uint8_t *frame) |
| 130 | { |
Rafał Miłecki | 3fe373d | 2010-03-06 13:03:38 +0000 | [diff] [blame] | 131 | int i; |
| 132 | frame[0] = packetType + versionNumber + length; |
| 133 | for (i = 1; i <= length; i++) |
| 134 | frame[0] += frame[i]; |
| 135 | frame[0] = 0x100 - frame[0]; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 136 | } |
| 137 | |
| 138 | /* |
| 139 | * build a HDMI Video Info Frame |
| 140 | */ |
| 141 | static void r600_hdmi_videoinfoframe( |
| 142 | struct drm_encoder *encoder, |
| 143 | enum r600_hdmi_color_format color_format, |
| 144 | int active_information_present, |
| 145 | uint8_t active_format_aspect_ratio, |
| 146 | uint8_t scan_information, |
| 147 | uint8_t colorimetry, |
| 148 | uint8_t ex_colorimetry, |
| 149 | uint8_t quantization, |
| 150 | int ITC, |
| 151 | uint8_t picture_aspect_ratio, |
| 152 | uint8_t video_format_identification, |
| 153 | uint8_t pixel_repetition, |
| 154 | uint8_t non_uniform_picture_scaling, |
| 155 | uint8_t bar_info_data_valid, |
| 156 | uint16_t top_bar, |
| 157 | uint16_t bottom_bar, |
| 158 | uint16_t left_bar, |
| 159 | uint16_t right_bar |
| 160 | ) |
| 161 | { |
| 162 | struct drm_device *dev = encoder->dev; |
| 163 | struct radeon_device *rdev = dev->dev_private; |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 164 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 165 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 166 | uint32_t offset = dig->afmt->offset; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 167 | |
| 168 | uint8_t frame[14]; |
| 169 | |
| 170 | frame[0x0] = 0; |
| 171 | frame[0x1] = |
| 172 | (scan_information & 0x3) | |
| 173 | ((bar_info_data_valid & 0x3) << 2) | |
| 174 | ((active_information_present & 0x1) << 4) | |
| 175 | ((color_format & 0x3) << 5); |
| 176 | frame[0x2] = |
| 177 | (active_format_aspect_ratio & 0xF) | |
| 178 | ((picture_aspect_ratio & 0x3) << 4) | |
| 179 | ((colorimetry & 0x3) << 6); |
| 180 | frame[0x3] = |
| 181 | (non_uniform_picture_scaling & 0x3) | |
| 182 | ((quantization & 0x3) << 2) | |
| 183 | ((ex_colorimetry & 0x7) << 4) | |
| 184 | ((ITC & 0x1) << 7); |
| 185 | frame[0x4] = (video_format_identification & 0x7F); |
| 186 | frame[0x5] = (pixel_repetition & 0xF); |
| 187 | frame[0x6] = (top_bar & 0xFF); |
| 188 | frame[0x7] = (top_bar >> 8); |
| 189 | frame[0x8] = (bottom_bar & 0xFF); |
| 190 | frame[0x9] = (bottom_bar >> 8); |
| 191 | frame[0xA] = (left_bar & 0xFF); |
| 192 | frame[0xB] = (left_bar >> 8); |
| 193 | frame[0xC] = (right_bar & 0xFF); |
| 194 | frame[0xD] = (right_bar >> 8); |
| 195 | |
| 196 | r600_hdmi_infoframe_checksum(0x82, 0x02, 0x0D, frame); |
Rafał Miłecki | 92db7f6 | 2011-12-23 20:32:18 +0100 | [diff] [blame] | 197 | /* Our header values (type, version, length) should be alright, Intel |
| 198 | * is using the same. Checksum function also seems to be OK, it works |
| 199 | * fine for audio infoframe. However calculated value is always lower |
| 200 | * by 2 in comparison to fglrx. It breaks displaying anything in case |
| 201 | * of TVs that strictly check the checksum. Hack it manually here to |
| 202 | * workaround this issue. */ |
| 203 | frame[0x0] += 2; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 204 | |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 205 | WREG32(HDMI0_AVI_INFO0 + offset, |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 206 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 207 | WREG32(HDMI0_AVI_INFO1 + offset, |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 208 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 209 | WREG32(HDMI0_AVI_INFO2 + offset, |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 210 | frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 211 | WREG32(HDMI0_AVI_INFO3 + offset, |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 212 | frame[0xC] | (frame[0xD] << 8)); |
| 213 | } |
| 214 | |
| 215 | /* |
| 216 | * build a Audio Info Frame |
| 217 | */ |
| 218 | static void r600_hdmi_audioinfoframe( |
| 219 | struct drm_encoder *encoder, |
| 220 | uint8_t channel_count, |
| 221 | uint8_t coding_type, |
| 222 | uint8_t sample_size, |
| 223 | uint8_t sample_frequency, |
| 224 | uint8_t format, |
| 225 | uint8_t channel_allocation, |
| 226 | uint8_t level_shift, |
| 227 | int downmix_inhibit |
| 228 | ) |
| 229 | { |
| 230 | struct drm_device *dev = encoder->dev; |
| 231 | struct radeon_device *rdev = dev->dev_private; |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 232 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 233 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 234 | uint32_t offset = dig->afmt->offset; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 235 | |
| 236 | uint8_t frame[11]; |
| 237 | |
| 238 | frame[0x0] = 0; |
| 239 | frame[0x1] = (channel_count & 0x7) | ((coding_type & 0xF) << 4); |
| 240 | frame[0x2] = (sample_size & 0x3) | ((sample_frequency & 0x7) << 2); |
| 241 | frame[0x3] = format; |
| 242 | frame[0x4] = channel_allocation; |
| 243 | frame[0x5] = ((level_shift & 0xF) << 3) | ((downmix_inhibit & 0x1) << 7); |
| 244 | frame[0x6] = 0; |
| 245 | frame[0x7] = 0; |
| 246 | frame[0x8] = 0; |
| 247 | frame[0x9] = 0; |
| 248 | frame[0xA] = 0; |
| 249 | |
| 250 | r600_hdmi_infoframe_checksum(0x84, 0x01, 0x0A, frame); |
| 251 | |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 252 | WREG32(HDMI0_AUDIO_INFO0 + offset, |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 253 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 254 | WREG32(HDMI0_AUDIO_INFO1 + offset, |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 255 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24)); |
| 256 | } |
| 257 | |
| 258 | /* |
| 259 | * test if audio buffer is filled enough to start playing |
| 260 | */ |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 261 | static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 262 | { |
| 263 | struct drm_device *dev = encoder->dev; |
| 264 | struct radeon_device *rdev = dev->dev_private; |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 265 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 266 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 267 | uint32_t offset = dig->afmt->offset; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 268 | |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 269 | return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 270 | } |
| 271 | |
| 272 | /* |
| 273 | * have buffer status changed since last call? |
| 274 | */ |
| 275 | int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder) |
| 276 | { |
| 277 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 278 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 279 | int status, result; |
| 280 | |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 281 | if (!dig->afmt || !dig->afmt->enabled) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 282 | return 0; |
| 283 | |
| 284 | status = r600_hdmi_is_audio_buffer_filled(encoder); |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 285 | result = dig->afmt->last_buffer_filled_status != status; |
| 286 | dig->afmt->last_buffer_filled_status = status; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 287 | |
| 288 | return result; |
| 289 | } |
| 290 | |
| 291 | /* |
| 292 | * write the audio workaround status to the hardware |
| 293 | */ |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 294 | static void r600_hdmi_audio_workaround(struct drm_encoder *encoder) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 295 | { |
| 296 | struct drm_device *dev = encoder->dev; |
| 297 | struct radeon_device *rdev = dev->dev_private; |
| 298 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 299 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 300 | uint32_t offset = dig->afmt->offset; |
| 301 | bool hdmi_audio_workaround = false; /* FIXME */ |
| 302 | u32 value; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 303 | |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 304 | if (!hdmi_audio_workaround || |
| 305 | r600_hdmi_is_audio_buffer_filled(encoder)) |
| 306 | value = 0; /* disable workaround */ |
| 307 | else |
| 308 | value = HDMI0_AUDIO_TEST_EN; /* enable workaround */ |
| 309 | WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, |
| 310 | value, ~HDMI0_AUDIO_TEST_EN); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 311 | } |
| 312 | |
| 313 | |
| 314 | /* |
| 315 | * update the info frames with the data from the current display mode |
| 316 | */ |
| 317 | void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) |
| 318 | { |
| 319 | struct drm_device *dev = encoder->dev; |
| 320 | struct radeon_device *rdev = dev->dev_private; |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 321 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 322 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 323 | uint32_t offset; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 324 | |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 325 | /* Silent, r600_hdmi_enable will raise WARN for us */ |
| 326 | if (!dig->afmt->enabled) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 327 | return; |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 328 | offset = dig->afmt->offset; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 329 | |
| 330 | r600_audio_set_clock(encoder, mode->clock); |
| 331 | |
Rafał Miłecki | 1c3439f | 2012-05-06 17:29:45 +0200 | [diff] [blame] | 332 | WREG32(HDMI0_VBI_PACKET_CONTROL + offset, |
| 333 | HDMI0_NULL_SEND); /* send null packets when required */ |
| 334 | |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 335 | WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000); |
Rafał Miłecki | a273a90 | 2012-04-30 15:44:52 +0200 | [diff] [blame] | 336 | |
Rafał Miłecki | 1c3439f | 2012-05-06 17:29:45 +0200 | [diff] [blame] | 337 | if (ASIC_IS_DCE32(rdev)) { |
| 338 | WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, |
| 339 | HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ |
| 340 | HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ |
| 341 | WREG32(AFMT_AUDIO_PACKET_CONTROL + offset, |
| 342 | AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */ |
| 343 | AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ |
| 344 | } else { |
| 345 | WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, |
| 346 | HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */ |
| 347 | HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ |
Rafał Miłecki | 1c3439f | 2012-05-06 17:29:45 +0200 | [diff] [blame] | 348 | HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */ |
| 349 | HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ |
| 350 | } |
Rafał Miłecki | a273a90 | 2012-04-30 15:44:52 +0200 | [diff] [blame] | 351 | |
Rafał Miłecki | 1c3439f | 2012-05-06 17:29:45 +0200 | [diff] [blame] | 352 | WREG32(HDMI0_ACR_PACKET_CONTROL + offset, |
| 353 | HDMI0_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */ |
| 354 | HDMI0_ACR_SOURCE); /* select SW CTS value */ |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 355 | |
Rafał Miłecki | 1c3439f | 2012-05-06 17:29:45 +0200 | [diff] [blame] | 356 | WREG32(HDMI0_VBI_PACKET_CONTROL + offset, |
| 357 | HDMI0_NULL_SEND | /* send null packets when required */ |
| 358 | HDMI0_GC_SEND | /* send general control packets */ |
| 359 | HDMI0_GC_CONT); /* send general control packets every frame */ |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 360 | |
Rafał Miłecki | 1c3439f | 2012-05-06 17:29:45 +0200 | [diff] [blame] | 361 | /* TODO: HDMI0_AUDIO_INFO_UPDATE */ |
| 362 | WREG32(HDMI0_INFOFRAME_CONTROL0 + offset, |
| 363 | HDMI0_AVI_INFO_SEND | /* enable AVI info frames */ |
| 364 | HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */ |
| 365 | HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ |
| 366 | HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */ |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 367 | |
Rafał Miłecki | 1c3439f | 2012-05-06 17:29:45 +0200 | [diff] [blame] | 368 | WREG32(HDMI0_INFOFRAME_CONTROL1 + offset, |
| 369 | HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */ |
| 370 | HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */ |
| 371 | |
| 372 | WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */ |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 373 | |
| 374 | r600_hdmi_videoinfoframe(encoder, RGB, 0, 0, 0, 0, |
| 375 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); |
| 376 | |
Rafał Miłecki | 1c3439f | 2012-05-06 17:29:45 +0200 | [diff] [blame] | 377 | r600_hdmi_update_ACR(encoder, mode->clock); |
| 378 | |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 379 | /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 380 | WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF); |
| 381 | WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF); |
| 382 | WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001); |
| 383 | WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 384 | |
| 385 | r600_hdmi_audio_workaround(encoder); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 386 | } |
| 387 | |
| 388 | /* |
| 389 | * update settings with current parameters from audio engine |
| 390 | */ |
Christian König | 58bd086 | 2010-04-05 22:14:55 +0200 | [diff] [blame] | 391 | void r600_hdmi_update_audio_settings(struct drm_encoder *encoder) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 392 | { |
| 393 | struct drm_device *dev = encoder->dev; |
| 394 | struct radeon_device *rdev = dev->dev_private; |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 395 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 396 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
Rafał Miłecki | 3299de9 | 2012-05-14 21:25:57 +0200 | [diff] [blame] | 397 | struct r600_audio audio = r600_audio_status(rdev); |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 398 | uint32_t offset; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 399 | uint32_t iec; |
| 400 | |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 401 | if (!dig->afmt || !dig->afmt->enabled) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 402 | return; |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 403 | offset = dig->afmt->offset; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 404 | |
| 405 | DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n", |
| 406 | r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped", |
Rafał Miłecki | 3299de9 | 2012-05-14 21:25:57 +0200 | [diff] [blame] | 407 | audio.channels, audio.rate, audio.bits_per_sample); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 408 | DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n", |
Rafał Miłecki | 3299de9 | 2012-05-14 21:25:57 +0200 | [diff] [blame] | 409 | (int)audio.status_bits, (int)audio.category_code); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 410 | |
| 411 | iec = 0; |
Rafał Miłecki | 3299de9 | 2012-05-14 21:25:57 +0200 | [diff] [blame] | 412 | if (audio.status_bits & AUDIO_STATUS_PROFESSIONAL) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 413 | iec |= 1 << 0; |
Rafał Miłecki | 3299de9 | 2012-05-14 21:25:57 +0200 | [diff] [blame] | 414 | if (audio.status_bits & AUDIO_STATUS_NONAUDIO) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 415 | iec |= 1 << 1; |
Rafał Miłecki | 3299de9 | 2012-05-14 21:25:57 +0200 | [diff] [blame] | 416 | if (audio.status_bits & AUDIO_STATUS_COPYRIGHT) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 417 | iec |= 1 << 2; |
Rafał Miłecki | 3299de9 | 2012-05-14 21:25:57 +0200 | [diff] [blame] | 418 | if (audio.status_bits & AUDIO_STATUS_EMPHASIS) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 419 | iec |= 1 << 3; |
| 420 | |
Rafał Miłecki | 3299de9 | 2012-05-14 21:25:57 +0200 | [diff] [blame] | 421 | iec |= HDMI0_60958_CS_CATEGORY_CODE(audio.category_code); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 422 | |
Rafał Miłecki | 3299de9 | 2012-05-14 21:25:57 +0200 | [diff] [blame] | 423 | switch (audio.rate) { |
Rafał Miłecki | a366e39 | 2012-05-06 17:29:46 +0200 | [diff] [blame] | 424 | case 32000: |
| 425 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x3); |
| 426 | break; |
| 427 | case 44100: |
| 428 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x0); |
| 429 | break; |
| 430 | case 48000: |
| 431 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x2); |
| 432 | break; |
| 433 | case 88200: |
| 434 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x8); |
| 435 | break; |
| 436 | case 96000: |
| 437 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xa); |
| 438 | break; |
| 439 | case 176400: |
| 440 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xc); |
| 441 | break; |
| 442 | case 192000: |
| 443 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xe); |
| 444 | break; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 445 | } |
| 446 | |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 447 | WREG32(HDMI0_60958_0 + offset, iec); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 448 | |
| 449 | iec = 0; |
Rafał Miłecki | 3299de9 | 2012-05-14 21:25:57 +0200 | [diff] [blame] | 450 | switch (audio.bits_per_sample) { |
Rafał Miłecki | a366e39 | 2012-05-06 17:29:46 +0200 | [diff] [blame] | 451 | case 16: |
| 452 | iec |= HDMI0_60958_CS_WORD_LENGTH(0x2); |
| 453 | break; |
| 454 | case 20: |
| 455 | iec |= HDMI0_60958_CS_WORD_LENGTH(0x3); |
| 456 | break; |
| 457 | case 24: |
| 458 | iec |= HDMI0_60958_CS_WORD_LENGTH(0xb); |
| 459 | break; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 460 | } |
Rafał Miłecki | 3299de9 | 2012-05-14 21:25:57 +0200 | [diff] [blame] | 461 | if (audio.status_bits & AUDIO_STATUS_V) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 462 | iec |= 0x5 << 16; |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 463 | WREG32_P(HDMI0_60958_1 + offset, iec, ~0x5000f); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 464 | |
Rafał Miłecki | 3299de9 | 2012-05-14 21:25:57 +0200 | [diff] [blame] | 465 | r600_hdmi_audioinfoframe(encoder, audio.channels - 1, 0, 0, 0, 0, 0, 0, |
| 466 | 0); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 467 | |
| 468 | r600_hdmi_audio_workaround(encoder); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 469 | } |
| 470 | |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 471 | /* |
Rafał Miłecki | 2cd6218c | 2010-03-08 22:14:01 +0000 | [diff] [blame] | 472 | * enable the HDMI engine |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 473 | */ |
Rafał Miłecki | 2cd6218c | 2010-03-08 22:14:01 +0000 | [diff] [blame] | 474 | void r600_hdmi_enable(struct drm_encoder *encoder) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 475 | { |
Rafał Miłecki | 2cd6218c | 2010-03-08 22:14:01 +0000 | [diff] [blame] | 476 | struct drm_device *dev = encoder->dev; |
| 477 | struct radeon_device *rdev = dev->dev_private; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 478 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 479 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 480 | uint32_t offset; |
Rafał Miłecki | 64fb4fb | 2012-04-30 15:44:53 +0200 | [diff] [blame] | 481 | u32 hdmi; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 482 | |
Rafał Miłecki | 6b53a05 | 2012-06-11 12:34:01 +0200 | [diff] [blame] | 483 | if (ASIC_IS_DCE6(rdev)) |
Alex Deucher | 16823d1 | 2010-04-16 11:35:30 -0400 | [diff] [blame] | 484 | return; |
| 485 | |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 486 | /* Silent, r600_hdmi_enable will raise WARN for us */ |
| 487 | if (dig->afmt->enabled) |
| 488 | return; |
| 489 | offset = dig->afmt->offset; |
Rafał Miłecki | 64fb4fb | 2012-04-30 15:44:53 +0200 | [diff] [blame] | 490 | |
| 491 | /* Older chipsets require setting HDMI and routing manually */ |
| 492 | if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) { |
| 493 | hdmi = HDMI0_ERROR_ACK | HDMI0_ENABLE; |
Rafał Miłecki | 5715f67 | 2010-03-06 13:03:35 +0000 | [diff] [blame] | 494 | switch (radeon_encoder->encoder_id) { |
| 495 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
Rafał Miłecki | 93a4ed8 | 2011-12-24 12:25:36 +0100 | [diff] [blame] | 496 | WREG32_P(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN, |
| 497 | ~AVIVO_TMDSA_CNTL_HDMI_EN); |
Rafał Miłecki | 64fb4fb | 2012-04-30 15:44:53 +0200 | [diff] [blame] | 498 | hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA); |
Rafał Miłecki | 5715f67 | 2010-03-06 13:03:35 +0000 | [diff] [blame] | 499 | break; |
| 500 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
Rafał Miłecki | 93a4ed8 | 2011-12-24 12:25:36 +0100 | [diff] [blame] | 501 | WREG32_P(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN, |
| 502 | ~AVIVO_LVTMA_CNTL_HDMI_EN); |
Rafał Miłecki | 64fb4fb | 2012-04-30 15:44:53 +0200 | [diff] [blame] | 503 | hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA); |
| 504 | break; |
| 505 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
| 506 | WREG32_P(DDIA_CNTL, DDIA_HDMI_EN, ~DDIA_HDMI_EN); |
| 507 | hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA); |
| 508 | break; |
| 509 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
| 510 | hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA); |
Rafał Miłecki | 5715f67 | 2010-03-06 13:03:35 +0000 | [diff] [blame] | 511 | break; |
| 512 | default: |
Rafał Miłecki | 64fb4fb | 2012-04-30 15:44:53 +0200 | [diff] [blame] | 513 | dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n", |
| 514 | radeon_encoder->encoder_id); |
Rafał Miłecki | 5715f67 | 2010-03-06 13:03:35 +0000 | [diff] [blame] | 515 | break; |
| 516 | } |
Rafał Miłecki | 64fb4fb | 2012-04-30 15:44:53 +0200 | [diff] [blame] | 517 | WREG32(HDMI0_CONTROL + offset, hdmi); |
Rafał Miłecki | 5715f67 | 2010-03-06 13:03:35 +0000 | [diff] [blame] | 518 | } |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 519 | |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 520 | if (rdev->irq.installed) { |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 521 | /* if irq is available use it */ |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 522 | radeon_irq_kms_enable_afmt(rdev, dig->afmt->id); |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 523 | } |
Christian König | 58bd086 | 2010-04-05 22:14:55 +0200 | [diff] [blame] | 524 | |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 525 | dig->afmt->enabled = true; |
| 526 | |
Rafał Miłecki | 2cd6218c | 2010-03-08 22:14:01 +0000 | [diff] [blame] | 527 | DRM_DEBUG("Enabling HDMI interface @ 0x%04X for encoder 0x%x\n", |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 528 | offset, radeon_encoder->encoder_id); |
Rafał Miłecki | 2cd6218c | 2010-03-08 22:14:01 +0000 | [diff] [blame] | 529 | } |
| 530 | |
| 531 | /* |
| 532 | * disable the HDMI engine |
| 533 | */ |
| 534 | void r600_hdmi_disable(struct drm_encoder *encoder) |
| 535 | { |
| 536 | struct drm_device *dev = encoder->dev; |
| 537 | struct radeon_device *rdev = dev->dev_private; |
| 538 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 539 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
Dave Airlie | 6698998 | 2010-05-19 10:35:02 +1000 | [diff] [blame] | 540 | uint32_t offset; |
Rafał Miłecki | 2cd6218c | 2010-03-08 22:14:01 +0000 | [diff] [blame] | 541 | |
Rafał Miłecki | 6b53a05 | 2012-06-11 12:34:01 +0200 | [diff] [blame] | 542 | if (ASIC_IS_DCE6(rdev)) |
Alex Deucher | 16823d1 | 2010-04-16 11:35:30 -0400 | [diff] [blame] | 543 | return; |
| 544 | |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 545 | /* Called for ATOM_ENCODER_MODE_HDMI only */ |
| 546 | if (!dig || !dig->afmt) { |
| 547 | WARN_ON(1); |
Rafał Miłecki | 2cd6218c | 2010-03-08 22:14:01 +0000 | [diff] [blame] | 548 | return; |
| 549 | } |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 550 | if (!dig->afmt->enabled) |
| 551 | return; |
| 552 | offset = dig->afmt->offset; |
Rafał Miłecki | 2cd6218c | 2010-03-08 22:14:01 +0000 | [diff] [blame] | 553 | |
| 554 | DRM_DEBUG("Disabling HDMI interface @ 0x%04X for encoder 0x%x\n", |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 555 | offset, radeon_encoder->encoder_id); |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 556 | |
| 557 | /* disable irq */ |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 558 | radeon_irq_kms_disable_afmt(rdev, dig->afmt->id); |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 559 | |
Rafał Miłecki | 64fb4fb | 2012-04-30 15:44:53 +0200 | [diff] [blame] | 560 | /* Older chipsets not handled by AtomBIOS */ |
| 561 | if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) { |
Rafał Miłecki | 5715f67 | 2010-03-06 13:03:35 +0000 | [diff] [blame] | 562 | switch (radeon_encoder->encoder_id) { |
| 563 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
Rafał Miłecki | 93a4ed8 | 2011-12-24 12:25:36 +0100 | [diff] [blame] | 564 | WREG32_P(AVIVO_TMDSA_CNTL, 0, |
| 565 | ~AVIVO_TMDSA_CNTL_HDMI_EN); |
Rafał Miłecki | 5715f67 | 2010-03-06 13:03:35 +0000 | [diff] [blame] | 566 | break; |
| 567 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
Rafał Miłecki | 93a4ed8 | 2011-12-24 12:25:36 +0100 | [diff] [blame] | 568 | WREG32_P(AVIVO_LVTMA_CNTL, 0, |
| 569 | ~AVIVO_LVTMA_CNTL_HDMI_EN); |
Rafał Miłecki | 64fb4fb | 2012-04-30 15:44:53 +0200 | [diff] [blame] | 570 | break; |
| 571 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
| 572 | WREG32_P(DDIA_CNTL, 0, ~DDIA_HDMI_EN); |
| 573 | break; |
| 574 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
Rafał Miłecki | 5715f67 | 2010-03-06 13:03:35 +0000 | [diff] [blame] | 575 | break; |
| 576 | default: |
Rafał Miłecki | 64fb4fb | 2012-04-30 15:44:53 +0200 | [diff] [blame] | 577 | dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n", |
| 578 | radeon_encoder->encoder_id); |
Rafał Miłecki | 5715f67 | 2010-03-06 13:03:35 +0000 | [diff] [blame] | 579 | break; |
| 580 | } |
Rafał Miłecki | 64fb4fb | 2012-04-30 15:44:53 +0200 | [diff] [blame] | 581 | WREG32(HDMI0_CONTROL + offset, HDMI0_ERROR_ACK); |
Rafał Miłecki | 5715f67 | 2010-03-06 13:03:35 +0000 | [diff] [blame] | 582 | } |
Rafał Miłecki | 2cd6218c | 2010-03-08 22:14:01 +0000 | [diff] [blame] | 583 | |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 584 | dig->afmt->enabled = false; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 585 | } |