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Andrei Konovalovae918c02007-07-17 04:04:11 -07001/*
2 * xilinx_spi.c
3 *
4 * Xilinx SPI controller driver (master mode only)
5 *
6 * Author: MontaVista Software, Inc.
7 * source@mvista.com
8 *
9 * 2002-2007 (c) MontaVista Software, Inc. This file is licensed under the
10 * terms of the GNU General Public License version 2. This program is licensed
11 * "as is" without any warranty of any kind, whether express or implied.
12 */
13
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
John Linnff82c582009-01-09 16:01:53 -070017
Andrei Konovalovae918c02007-07-17 04:04:11 -070018#include <linux/spi/spi.h>
19#include <linux/spi/spi_bitbang.h>
20#include <linux/io.h>
21
Richard Röjforsd5af91a2009-11-13 12:28:39 +010022#include "xilinx_spi.h"
23#include <linux/spi/xilinx_spi.h>
24
David Brownellfc3ba952007-08-30 23:56:24 -070025#define XILINX_SPI_NAME "xilinx_spi"
Andrei Konovalovae918c02007-07-17 04:04:11 -070026
27/* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
28 * Product Specification", DS464
29 */
Richard Röjforsc9da2e12009-11-13 12:28:55 +010030#define XSPI_CR_OFFSET 0x60 /* Control Register */
Andrei Konovalovae918c02007-07-17 04:04:11 -070031
32#define XSPI_CR_ENABLE 0x02
33#define XSPI_CR_MASTER_MODE 0x04
34#define XSPI_CR_CPOL 0x08
35#define XSPI_CR_CPHA 0x10
36#define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL)
37#define XSPI_CR_TXFIFO_RESET 0x20
38#define XSPI_CR_RXFIFO_RESET 0x40
39#define XSPI_CR_MANUAL_SSELECT 0x80
40#define XSPI_CR_TRANS_INHIBIT 0x100
Richard Röjforsc9da2e12009-11-13 12:28:55 +010041#define XSPI_CR_LSB_FIRST 0x200
Andrei Konovalovae918c02007-07-17 04:04:11 -070042
Richard Röjforsc9da2e12009-11-13 12:28:55 +010043#define XSPI_SR_OFFSET 0x64 /* Status Register */
Andrei Konovalovae918c02007-07-17 04:04:11 -070044
45#define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */
46#define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */
47#define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */
48#define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */
49#define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */
50
Richard Röjforsc9da2e12009-11-13 12:28:55 +010051#define XSPI_TXD_OFFSET 0x68 /* Data Transmit Register */
52#define XSPI_RXD_OFFSET 0x6c /* Data Receive Register */
Andrei Konovalovae918c02007-07-17 04:04:11 -070053
54#define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */
55
56/* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
57 * IPIF registers are 32 bit
58 */
59#define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */
60#define XIPIF_V123B_GINTR_ENABLE 0x80000000
61
62#define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */
63#define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */
64
65#define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */
66#define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while
67 * disabled */
68#define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */
69#define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */
70#define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */
71#define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */
Richard Röjforsc9da2e12009-11-13 12:28:55 +010072#define XSPI_INTR_TX_HALF_EMPTY 0x40 /* TxFIFO is half empty */
Andrei Konovalovae918c02007-07-17 04:04:11 -070073
74#define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */
75#define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */
76
77struct xilinx_spi {
78 /* bitbang has to be first */
79 struct spi_bitbang bitbang;
80 struct completion done;
Richard Röjforsd5af91a2009-11-13 12:28:39 +010081 struct resource mem; /* phys mem */
Andrei Konovalovae918c02007-07-17 04:04:11 -070082 void __iomem *regs; /* virt. address of the control registers */
83
84 u32 irq;
85
Andrei Konovalovae918c02007-07-17 04:04:11 -070086 u8 *rx_ptr; /* pointer in the Tx buffer */
87 const u8 *tx_ptr; /* pointer in the Rx buffer */
88 int remaining_bytes; /* the number of bytes left to transfer */
Richard Röjforsc9da2e12009-11-13 12:28:55 +010089 u8 bits_per_word;
Richard Röjfors86fc5932009-11-13 12:28:49 +010090 unsigned int (*read_fn) (void __iomem *);
91 void (*write_fn) (u32, void __iomem *);
Richard Röjforsc9da2e12009-11-13 12:28:55 +010092 void (*tx_fn) (struct xilinx_spi *);
93 void (*rx_fn) (struct xilinx_spi *);
Andrei Konovalovae918c02007-07-17 04:04:11 -070094};
95
Paul Mundt97782142010-01-20 13:49:45 -070096static void xspi_write32(u32 val, void __iomem *addr)
97{
98 iowrite32(val, addr);
99}
100
101static unsigned int xspi_read32(void __iomem *addr)
102{
103 return ioread32(addr);
104}
105
106static void xspi_write32_be(u32 val, void __iomem *addr)
107{
108 iowrite32be(val, addr);
109}
110
111static unsigned int xspi_read32_be(void __iomem *addr)
112{
113 return ioread32be(addr);
114}
115
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100116static void xspi_tx8(struct xilinx_spi *xspi)
117{
118 xspi->write_fn(*xspi->tx_ptr, xspi->regs + XSPI_TXD_OFFSET);
119 xspi->tx_ptr++;
120}
121
122static void xspi_tx16(struct xilinx_spi *xspi)
123{
124 xspi->write_fn(*(u16 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET);
125 xspi->tx_ptr += 2;
126}
127
128static void xspi_tx32(struct xilinx_spi *xspi)
129{
130 xspi->write_fn(*(u32 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET);
131 xspi->tx_ptr += 4;
132}
133
134static void xspi_rx8(struct xilinx_spi *xspi)
135{
136 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
137 if (xspi->rx_ptr) {
138 *xspi->rx_ptr = data & 0xff;
139 xspi->rx_ptr++;
140 }
141}
142
143static void xspi_rx16(struct xilinx_spi *xspi)
144{
145 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
146 if (xspi->rx_ptr) {
147 *(u16 *)(xspi->rx_ptr) = data & 0xffff;
148 xspi->rx_ptr += 2;
149 }
150}
151
152static void xspi_rx32(struct xilinx_spi *xspi)
153{
154 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
155 if (xspi->rx_ptr) {
156 *(u32 *)(xspi->rx_ptr) = data;
157 xspi->rx_ptr += 4;
158 }
159}
160
Richard Röjfors86fc5932009-11-13 12:28:49 +0100161static void xspi_init_hw(struct xilinx_spi *xspi)
Andrei Konovalovae918c02007-07-17 04:04:11 -0700162{
Richard Röjfors86fc5932009-11-13 12:28:49 +0100163 void __iomem *regs_base = xspi->regs;
164
Andrei Konovalovae918c02007-07-17 04:04:11 -0700165 /* Reset the SPI device */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100166 xspi->write_fn(XIPIF_V123B_RESET_MASK,
167 regs_base + XIPIF_V123B_RESETR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700168 /* Disable all the interrupts just in case */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100169 xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700170 /* Enable the global IPIF interrupt */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100171 xspi->write_fn(XIPIF_V123B_GINTR_ENABLE,
172 regs_base + XIPIF_V123B_DGIER_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700173 /* Deselect the slave on the SPI bus */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100174 xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700175 /* Disable the transmitter, enable Manual Slave Select Assertion,
176 * put SPI controller into master mode, and enable it */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100177 xspi->write_fn(XSPI_CR_TRANS_INHIBIT | XSPI_CR_MANUAL_SSELECT |
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100178 XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET |
179 XSPI_CR_RXFIFO_RESET, regs_base + XSPI_CR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700180}
181
182static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
183{
184 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
185
186 if (is_on == BITBANG_CS_INACTIVE) {
187 /* Deselect the slave on the SPI bus */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100188 xspi->write_fn(0xffff, xspi->regs + XSPI_SSR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700189 } else if (is_on == BITBANG_CS_ACTIVE) {
190 /* Set the SPI clock phase and polarity */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100191 u16 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET)
Andrei Konovalovae918c02007-07-17 04:04:11 -0700192 & ~XSPI_CR_MODE_MASK;
193 if (spi->mode & SPI_CPHA)
194 cr |= XSPI_CR_CPHA;
195 if (spi->mode & SPI_CPOL)
196 cr |= XSPI_CR_CPOL;
Richard Röjfors86fc5932009-11-13 12:28:49 +0100197 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700198
199 /* We do not check spi->max_speed_hz here as the SPI clock
200 * frequency is not software programmable (the IP block design
201 * parameter)
202 */
203
204 /* Activate the chip select */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100205 xspi->write_fn(~(0x0001 << spi->chip_select),
206 xspi->regs + XSPI_SSR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700207 }
208}
209
210/* spi_bitbang requires custom setup_transfer() to be defined if there is a
211 * custom txrx_bufs(). We have nothing to setup here as the SPI IP block
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100212 * supports 8 or 16 bits per word which cannot be changed in software.
213 * SPI clock can't be changed in software either.
214 * Check for correct bits per word. Chip select delay calculations could be
Andrei Konovalovae918c02007-07-17 04:04:11 -0700215 * added here as soon as bitbang_work() can be made aware of the delay value.
216 */
217static int xilinx_spi_setup_transfer(struct spi_device *spi,
218 struct spi_transfer *t)
219{
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100220 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700221 u8 bits_per_word;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700222
John Linn1a8d3b72009-09-14 08:17:05 +0000223 bits_per_word = (t && t->bits_per_word)
224 ? t->bits_per_word : spi->bits_per_word;
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100225 if (bits_per_word != xspi->bits_per_word) {
Andrei Konovalovae918c02007-07-17 04:04:11 -0700226 dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
Harvey Harrisonb687d2a2008-04-28 02:14:19 -0700227 __func__, bits_per_word);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700228 return -EINVAL;
229 }
230
Andrei Konovalovae918c02007-07-17 04:04:11 -0700231 return 0;
232}
233
Andrei Konovalovae918c02007-07-17 04:04:11 -0700234static int xilinx_spi_setup(struct spi_device *spi)
235{
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100236 /* always return 0, we can not check the number of bits.
237 * There are cases when SPI setup is called before any driver is
238 * there, in that case the SPI core defaults to 8 bits, which we
239 * do not support in some cases. But if we return an error, the
240 * SPI device would not be registered and no driver can get hold of it
241 * When the driver is there, it will call SPI setup again with the
242 * correct number of bits per transfer.
243 * If a driver setups with the wrong bit number, it will fail when
244 * it tries to do a transfer
245 */
Andrei Konovalovae918c02007-07-17 04:04:11 -0700246 return 0;
247}
248
249static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi)
250{
251 u8 sr;
252
253 /* Fill the Tx FIFO with as many bytes as possible */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100254 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700255 while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) {
Richard Röjfors86fc5932009-11-13 12:28:49 +0100256 if (xspi->tx_ptr)
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100257 xspi->tx_fn(xspi);
Richard Röjfors86fc5932009-11-13 12:28:49 +0100258 else
259 xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100260 xspi->remaining_bytes -= xspi->bits_per_word / 8;
Richard Röjfors86fc5932009-11-13 12:28:49 +0100261 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700262 }
263}
264
265static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
266{
267 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
268 u32 ipif_ier;
269 u16 cr;
270
271 /* We get here with transmitter inhibited */
272
273 xspi->tx_ptr = t->tx_buf;
274 xspi->rx_ptr = t->rx_buf;
275 xspi->remaining_bytes = t->len;
276 INIT_COMPLETION(xspi->done);
277
278 xilinx_spi_fill_tx_fifo(xspi);
279
280 /* Enable the transmit empty interrupt, which we use to determine
281 * progress on the transmission.
282 */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100283 ipif_ier = xspi->read_fn(xspi->regs + XIPIF_V123B_IIER_OFFSET);
284 xspi->write_fn(ipif_ier | XSPI_INTR_TX_EMPTY,
285 xspi->regs + XIPIF_V123B_IIER_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700286
287 /* Start the transfer by not inhibiting the transmitter any longer */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100288 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) &
289 ~XSPI_CR_TRANS_INHIBIT;
290 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700291
292 wait_for_completion(&xspi->done);
293
294 /* Disable the transmit empty interrupt */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100295 xspi->write_fn(ipif_ier, xspi->regs + XIPIF_V123B_IIER_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700296
297 return t->len - xspi->remaining_bytes;
298}
299
300
301/* This driver supports single master mode only. Hence Tx FIFO Empty
302 * is the only interrupt we care about.
303 * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode
304 * Fault are not to happen.
305 */
306static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
307{
308 struct xilinx_spi *xspi = dev_id;
309 u32 ipif_isr;
310
311 /* Get the IPIF interrupts, and clear them immediately */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100312 ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
313 xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700314
315 if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */
316 u16 cr;
317 u8 sr;
318
319 /* A transmit has just completed. Process received data and
320 * check for more data to transmit. Always inhibit the
321 * transmitter while the Isr refills the transmit register/FIFO,
322 * or make sure it is stopped if we're done.
323 */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100324 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
325 xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
326 xspi->regs + XSPI_CR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700327
328 /* Read out all the data from the Rx FIFO */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100329 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700330 while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) {
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100331 xspi->rx_fn(xspi);
Richard Röjfors86fc5932009-11-13 12:28:49 +0100332 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700333 }
334
335 /* See if there is more data to send */
336 if (xspi->remaining_bytes > 0) {
337 xilinx_spi_fill_tx_fifo(xspi);
338 /* Start the transfer by not inhibiting the
339 * transmitter any longer
340 */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100341 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700342 } else {
343 /* No more data to send.
344 * Indicate the transfer is completed.
345 */
346 complete(&xspi->done);
347 }
348 }
349
350 return IRQ_HANDLED;
351}
352
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100353struct spi_master *xilinx_spi_init(struct device *dev, struct resource *mem,
354 u32 irq, s16 bus_num)
Andrei Konovalovae918c02007-07-17 04:04:11 -0700355{
Andrei Konovalovae918c02007-07-17 04:04:11 -0700356 struct spi_master *master;
357 struct xilinx_spi *xspi;
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100358 struct xspi_platform_data *pdata = dev->platform_data;
359 int ret;
John Linnff82c582009-01-09 16:01:53 -0700360
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100361 if (!pdata) {
362 dev_err(dev, "No platform data attached\n");
363 return NULL;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700364 }
365
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100366 master = spi_alloc_master(dev, sizeof(struct xilinx_spi));
367 if (!master)
368 return NULL;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700369
David Brownelle7db06b2009-06-17 16:26:04 -0700370 /* the spi->mode bits understood by this driver: */
371 master->mode_bits = SPI_CPOL | SPI_CPHA;
372
Andrei Konovalovae918c02007-07-17 04:04:11 -0700373 xspi = spi_master_get_devdata(master);
374 xspi->bitbang.master = spi_master_get(master);
375 xspi->bitbang.chipselect = xilinx_spi_chipselect;
376 xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
377 xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
378 xspi->bitbang.master->setup = xilinx_spi_setup;
379 init_completion(&xspi->done);
380
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100381 if (!request_mem_region(mem->start, resource_size(mem),
382 XILINX_SPI_NAME))
Andrei Konovalovae918c02007-07-17 04:04:11 -0700383 goto put_master;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700384
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100385 xspi->regs = ioremap(mem->start, resource_size(mem));
Andrei Konovalovae918c02007-07-17 04:04:11 -0700386 if (xspi->regs == NULL) {
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100387 dev_warn(dev, "ioremap failure\n");
388 goto map_failed;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700389 }
390
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100391 master->bus_num = bus_num;
392 master->num_chipselect = pdata->num_chipselect;
Anatolij Gustschin12b15e82010-07-27 22:35:58 +0200393#ifdef CONFIG_OF
394 master->dev.of_node = dev->of_node;
395#endif
John Linnff82c582009-01-09 16:01:53 -0700396
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100397 xspi->mem = *mem;
398 xspi->irq = irq;
Richard Röjfors86fc5932009-11-13 12:28:49 +0100399 if (pdata->little_endian) {
Paul Mundt97782142010-01-20 13:49:45 -0700400 xspi->read_fn = xspi_read32;
401 xspi->write_fn = xspi_write32;
Richard Röjfors86fc5932009-11-13 12:28:49 +0100402 } else {
Paul Mundt97782142010-01-20 13:49:45 -0700403 xspi->read_fn = xspi_read32_be;
404 xspi->write_fn = xspi_write32_be;
Richard Röjfors86fc5932009-11-13 12:28:49 +0100405 }
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100406 xspi->bits_per_word = pdata->bits_per_word;
407 if (xspi->bits_per_word == 8) {
408 xspi->tx_fn = xspi_tx8;
409 xspi->rx_fn = xspi_rx8;
410 } else if (xspi->bits_per_word == 16) {
411 xspi->tx_fn = xspi_tx16;
412 xspi->rx_fn = xspi_rx16;
413 } else if (xspi->bits_per_word == 32) {
414 xspi->tx_fn = xspi_tx32;
415 xspi->rx_fn = xspi_rx32;
416 } else
417 goto unmap_io;
418
Andrei Konovalovae918c02007-07-17 04:04:11 -0700419
420 /* SPI controller initializations */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100421 xspi_init_hw(xspi);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700422
423 /* Register for SPI Interrupt */
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100424 ret = request_irq(xspi->irq, xilinx_spi_irq, 0, XILINX_SPI_NAME, xspi);
425 if (ret)
Andrei Konovalovae918c02007-07-17 04:04:11 -0700426 goto unmap_io;
427
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100428 ret = spi_bitbang_start(&xspi->bitbang);
429 if (ret) {
430 dev_err(dev, "spi_bitbang_start FAILED\n");
Andrei Konovalovae918c02007-07-17 04:04:11 -0700431 goto free_irq;
432 }
433
Grant Likely920712a2009-11-25 07:23:35 -0700434 dev_info(dev, "at 0x%08llX mapped to 0x%p, irq=%d\n",
435 (unsigned long long)mem->start, xspi->regs, xspi->irq);
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100436 return master;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700437
438free_irq:
439 free_irq(xspi->irq, xspi);
440unmap_io:
441 iounmap(xspi->regs);
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100442map_failed:
443 release_mem_region(mem->start, resource_size(mem));
Andrei Konovalovae918c02007-07-17 04:04:11 -0700444put_master:
445 spi_master_put(master);
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100446 return NULL;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700447}
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100448EXPORT_SYMBOL(xilinx_spi_init);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700449
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100450void xilinx_spi_deinit(struct spi_master *master)
Andrei Konovalovae918c02007-07-17 04:04:11 -0700451{
452 struct xilinx_spi *xspi;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700453
Andrei Konovalovae918c02007-07-17 04:04:11 -0700454 xspi = spi_master_get_devdata(master);
455
456 spi_bitbang_stop(&xspi->bitbang);
457 free_irq(xspi->irq, xspi);
458 iounmap(xspi->regs);
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100459
460 release_mem_region(xspi->mem.start, resource_size(&xspi->mem));
Andrei Konovalovae918c02007-07-17 04:04:11 -0700461 spi_master_put(xspi->bitbang.master);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700462}
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100463EXPORT_SYMBOL(xilinx_spi_deinit);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700464
Andrei Konovalovae918c02007-07-17 04:04:11 -0700465MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
466MODULE_DESCRIPTION("Xilinx SPI driver");
467MODULE_LICENSE("GPL");