blob: 88b9a663944f0afce886e3070677753282cad516 [file] [log] [blame]
Jesse Barnes317c35d2008-08-25 15:11:06 -07001/*
2 *
3 * Copyright 2008 (c) Intel Corporation
4 * Jesse Barnes <jbarnes@virtuousgeek.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 */
26
David Howells760285e2012-10-02 18:01:07 +010027#include <drm/drmP.h>
28#include <drm/i915_drm.h>
Eric Anholtf0217c42009-12-01 11:56:30 -080029#include "intel_drv.h"
Eugeni Dodonov5e5b7fa2012-01-07 23:40:34 -020030#include "i915_reg.h"
Jesse Barnes317c35d2008-08-25 15:11:06 -070031
Jesse Barnes317c35d2008-08-25 15:11:06 -070032static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
33{
34 struct drm_i915_private *dev_priv = dev->dev_private;
35
36 I915_WRITE8(index_port, reg);
37 return I915_READ8(data_port);
38}
39
40static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable)
41{
42 struct drm_i915_private *dev_priv = dev->dev_private;
43
44 I915_READ8(st01);
45 I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
46 return I915_READ8(VGA_AR_DATA_READ);
47}
48
49static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable)
50{
51 struct drm_i915_private *dev_priv = dev->dev_private;
52
53 I915_READ8(st01);
54 I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
55 I915_WRITE8(VGA_AR_DATA_WRITE, val);
56}
57
58static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val)
59{
60 struct drm_i915_private *dev_priv = dev->dev_private;
61
62 I915_WRITE8(index_port, reg);
63 I915_WRITE8(data_port, val);
64}
65
66static void i915_save_vga(struct drm_device *dev)
67{
68 struct drm_i915_private *dev_priv = dev->dev_private;
69 int i;
70 u16 cr_index, cr_data, st01;
71
Daniel Vetter44cec742013-01-25 17:53:21 +010072 /* VGA state */
73 dev_priv->regfile.saveVGA0 = I915_READ(VGA0);
74 dev_priv->regfile.saveVGA1 = I915_READ(VGA1);
75 dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);
Ville Syrjälä766aa1c2013-01-25 21:44:46 +020076 dev_priv->regfile.saveVGACNTRL = I915_READ(i915_vgacntrl_reg(dev));
Daniel Vetter44cec742013-01-25 17:53:21 +010077
Jesse Barnes317c35d2008-08-25 15:11:06 -070078 /* VGA color palette registers */
Daniel Vetterf4c956a2012-11-02 19:55:02 +010079 dev_priv->regfile.saveDACMASK = I915_READ8(VGA_DACMASK);
Jesse Barnes317c35d2008-08-25 15:11:06 -070080
81 /* MSR bits */
Daniel Vetterf4c956a2012-11-02 19:55:02 +010082 dev_priv->regfile.saveMSR = I915_READ8(VGA_MSR_READ);
83 if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
Jesse Barnes317c35d2008-08-25 15:11:06 -070084 cr_index = VGA_CR_INDEX_CGA;
85 cr_data = VGA_CR_DATA_CGA;
86 st01 = VGA_ST01_CGA;
87 } else {
88 cr_index = VGA_CR_INDEX_MDA;
89 cr_data = VGA_CR_DATA_MDA;
90 st01 = VGA_ST01_MDA;
91 }
92
93 /* CRT controller regs */
94 i915_write_indexed(dev, cr_index, cr_data, 0x11,
95 i915_read_indexed(dev, cr_index, cr_data, 0x11) &
96 (~0x80));
97 for (i = 0; i <= 0x24; i++)
Daniel Vetterf4c956a2012-11-02 19:55:02 +010098 dev_priv->regfile.saveCR[i] =
Jesse Barnes317c35d2008-08-25 15:11:06 -070099 i915_read_indexed(dev, cr_index, cr_data, i);
100 /* Make sure we don't turn off CR group 0 writes */
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100101 dev_priv->regfile.saveCR[0x11] &= ~0x80;
Jesse Barnes317c35d2008-08-25 15:11:06 -0700102
103 /* Attribute controller registers */
104 I915_READ8(st01);
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100105 dev_priv->regfile.saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
Jesse Barnes317c35d2008-08-25 15:11:06 -0700106 for (i = 0; i <= 0x14; i++)
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100107 dev_priv->regfile.saveAR[i] = i915_read_ar(dev, st01, i, 0);
Jesse Barnes317c35d2008-08-25 15:11:06 -0700108 I915_READ8(st01);
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100109 I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX);
Jesse Barnes317c35d2008-08-25 15:11:06 -0700110 I915_READ8(st01);
111
112 /* Graphics controller registers */
113 for (i = 0; i < 9; i++)
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100114 dev_priv->regfile.saveGR[i] =
Jesse Barnes317c35d2008-08-25 15:11:06 -0700115 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);
116
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100117 dev_priv->regfile.saveGR[0x10] =
Jesse Barnes317c35d2008-08-25 15:11:06 -0700118 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100119 dev_priv->regfile.saveGR[0x11] =
Jesse Barnes317c35d2008-08-25 15:11:06 -0700120 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100121 dev_priv->regfile.saveGR[0x18] =
Jesse Barnes317c35d2008-08-25 15:11:06 -0700122 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);
123
124 /* Sequencer registers */
125 for (i = 0; i < 8; i++)
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100126 dev_priv->regfile.saveSR[i] =
Jesse Barnes317c35d2008-08-25 15:11:06 -0700127 i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);
128}
129
130static void i915_restore_vga(struct drm_device *dev)
131{
132 struct drm_i915_private *dev_priv = dev->dev_private;
133 int i;
134 u16 cr_index, cr_data, st01;
135
Daniel Vetter44cec742013-01-25 17:53:21 +0100136 /* VGA state */
Ville Syrjälä766aa1c2013-01-25 21:44:46 +0200137 I915_WRITE(i915_vgacntrl_reg(dev), dev_priv->regfile.saveVGACNTRL);
Daniel Vetter44cec742013-01-25 17:53:21 +0100138
139 I915_WRITE(VGA0, dev_priv->regfile.saveVGA0);
140 I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);
141 I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);
142 POSTING_READ(VGA_PD);
143 udelay(150);
144
Jesse Barnes317c35d2008-08-25 15:11:06 -0700145 /* MSR bits */
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100146 I915_WRITE8(VGA_MSR_WRITE, dev_priv->regfile.saveMSR);
147 if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
Jesse Barnes317c35d2008-08-25 15:11:06 -0700148 cr_index = VGA_CR_INDEX_CGA;
149 cr_data = VGA_CR_DATA_CGA;
150 st01 = VGA_ST01_CGA;
151 } else {
152 cr_index = VGA_CR_INDEX_MDA;
153 cr_data = VGA_CR_DATA_MDA;
154 st01 = VGA_ST01_MDA;
155 }
156
157 /* Sequencer registers, don't write SR07 */
158 for (i = 0; i < 7; i++)
159 i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100160 dev_priv->regfile.saveSR[i]);
Jesse Barnes317c35d2008-08-25 15:11:06 -0700161
162 /* CRT controller regs */
163 /* Enable CR group 0 writes */
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100164 i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->regfile.saveCR[0x11]);
Jesse Barnes317c35d2008-08-25 15:11:06 -0700165 for (i = 0; i <= 0x24; i++)
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100166 i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->regfile.saveCR[i]);
Jesse Barnes317c35d2008-08-25 15:11:06 -0700167
168 /* Graphics controller regs */
169 for (i = 0; i < 9; i++)
170 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100171 dev_priv->regfile.saveGR[i]);
Jesse Barnes317c35d2008-08-25 15:11:06 -0700172
173 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100174 dev_priv->regfile.saveGR[0x10]);
Jesse Barnes317c35d2008-08-25 15:11:06 -0700175 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100176 dev_priv->regfile.saveGR[0x11]);
Jesse Barnes317c35d2008-08-25 15:11:06 -0700177 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100178 dev_priv->regfile.saveGR[0x18]);
Jesse Barnes317c35d2008-08-25 15:11:06 -0700179
180 /* Attribute controller registers */
181 I915_READ8(st01); /* switch back to index mode */
182 for (i = 0; i <= 0x14; i++)
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100183 i915_write_ar(dev, st01, i, dev_priv->regfile.saveAR[i], 0);
Jesse Barnes317c35d2008-08-25 15:11:06 -0700184 I915_READ8(st01); /* switch back to index mode */
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100185 I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX | 0x20);
Jesse Barnes317c35d2008-08-25 15:11:06 -0700186 I915_READ8(st01);
187
188 /* VGA color palette registers */
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100189 I915_WRITE8(VGA_DACMASK, dev_priv->regfile.saveDACMASK);
Jesse Barnes317c35d2008-08-25 15:11:06 -0700190}
191
Keith Packardd70bed12011-06-29 00:30:34 -0700192static void i915_save_display(struct drm_device *dev)
Zhao Yakuifccdaba2009-07-08 14:13:14 +0800193{
194 struct drm_i915_private *dev_priv = dev->dev_private;
Jani Nikula8ba2d182013-04-12 15:18:37 +0300195 unsigned long flags;
Zhao Yakuifccdaba2009-07-08 14:13:14 +0800196
197 /* Display arbitration control */
Paulo Zanoni8de0add2013-01-18 18:29:03 -0200198 if (INTEL_INFO(dev)->gen <= 4)
199 dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
Zhao Yakuifccdaba2009-07-08 14:13:14 +0800200
201 /* This is only meaningful in non-KMS mode */
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100202 /* Don't regfile.save them in KMS mode */
Daniel Vetter2e9723a2013-01-25 17:53:19 +0100203 if (!drm_core_check_feature(dev, DRIVER_MODESET))
Daniel Vetterd8157a32013-01-25 17:53:20 +0100204 i915_save_display_reg(dev);
Ben Gamari1341d652009-09-14 17:48:42 -0400205
Jani Nikula8ba2d182013-04-12 15:18:37 +0300206 spin_lock_irqsave(&dev_priv->backlight.lock, flags);
207
Jesse Barnes317c35d2008-08-25 15:11:06 -0700208 /* LVDS state */
Chris Wilson90eb77b2010-08-14 14:41:23 +0100209 if (HAS_PCH_SPLIT(dev)) {
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100210 dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
211 dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
212 dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
213 dev_priv->regfile.saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
214 dev_priv->regfile.saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
Paulo Zanoni4deb88a2013-03-06 20:03:20 -0300215 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
216 dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
Zhenyu Wang42048782009-10-21 15:27:01 +0800217 } else {
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100218 dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
219 dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
220 dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
221 dev_priv->regfile.saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100222 if (INTEL_INFO(dev)->gen >= 4)
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100223 dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
Zhenyu Wang42048782009-10-21 15:27:01 +0800224 if (IS_MOBILE(dev) && !IS_I830(dev))
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100225 dev_priv->regfile.saveLVDS = I915_READ(LVDS);
Zhenyu Wang42048782009-10-21 15:27:01 +0800226 }
227
Jani Nikula8ba2d182013-04-12 15:18:37 +0300228 spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
229
Chris Wilson90eb77b2010-08-14 14:41:23 +0100230 if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100231 dev_priv->regfile.savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
Zhenyu Wang42048782009-10-21 15:27:01 +0800232
Chris Wilson90eb77b2010-08-14 14:41:23 +0100233 if (HAS_PCH_SPLIT(dev)) {
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100234 dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
235 dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
236 dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
Zhenyu Wang42048782009-10-21 15:27:01 +0800237 } else {
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100238 dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
239 dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
240 dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR);
Zhenyu Wang42048782009-10-21 15:27:01 +0800241 }
Jesse Barnes317c35d2008-08-25 15:11:06 -0700242
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100243 /* Only regfile.save FBC state on the platform that supports FBC */
Zhao Yakuia2c459e2010-03-19 17:05:10 +0800244 if (I915_HAS_FBC(dev)) {
Chris Wilson90eb77b2010-08-14 14:41:23 +0100245 if (HAS_PCH_SPLIT(dev)) {
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100246 dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE);
Zhao Yakuib52eb4d2010-06-12 14:32:27 +0800247 } else if (IS_GM45(dev)) {
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100248 dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
Zhao Yakuia2c459e2010-03-19 17:05:10 +0800249 } else {
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100250 dev_priv->regfile.saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
251 dev_priv->regfile.saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
252 dev_priv->regfile.saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
253 dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
Zhao Yakuia2c459e2010-03-19 17:05:10 +0800254 }
Jesse Barnes06027f92009-10-05 13:47:26 -0700255 }
Jesse Barnes317c35d2008-08-25 15:11:06 -0700256
Daniel Vetter44cec742013-01-25 17:53:21 +0100257 if (!drm_core_check_feature(dev, DRIVER_MODESET))
258 i915_save_vga(dev);
Jesse Barnes317c35d2008-08-25 15:11:06 -0700259}
260
Keith Packardd70bed12011-06-29 00:30:34 -0700261static void i915_restore_display(struct drm_device *dev)
Jesse Barnes317c35d2008-08-25 15:11:06 -0700262{
263 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes2ec90662013-02-19 12:11:38 -0800264 u32 mask = 0xffffffff;
Jani Nikula8ba2d182013-04-12 15:18:37 +0300265 unsigned long flags;
Peng Li461cba22008-11-18 12:39:02 +0800266
Keith Packard881ee982008-11-02 23:08:44 -0800267 /* Display arbitration */
Paulo Zanoni8de0add2013-01-18 18:29:03 -0200268 if (INTEL_INFO(dev)->gen <= 4)
269 I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
Jesse Barnes317c35d2008-08-25 15:11:06 -0700270
Daniel Vetter2e9723a2013-01-25 17:53:19 +0100271 if (!drm_core_check_feature(dev, DRIVER_MODESET))
Daniel Vetterd8157a32013-01-25 17:53:20 +0100272 i915_restore_display_reg(dev);
Ben Gamari1341d652009-09-14 17:48:42 -0400273
Jani Nikula8ba2d182013-04-12 15:18:37 +0300274 spin_lock_irqsave(&dev_priv->backlight.lock, flags);
275
Jesse Barnes317c35d2008-08-25 15:11:06 -0700276 /* LVDS state */
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100277 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100278 I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
Zhenyu Wang42048782009-10-21 15:27:01 +0800279
Jesse Barnes2ec90662013-02-19 12:11:38 -0800280 if (drm_core_check_feature(dev, DRIVER_MODESET))
281 mask = ~LVDS_PORT_EN;
282
Paulo Zanoni4deb88a2013-03-06 20:03:20 -0300283 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
Jesse Barnes2ec90662013-02-19 12:11:38 -0800284 I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS & mask);
Paulo Zanoni4deb88a2013-03-06 20:03:20 -0300285 else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
Jesse Barnes2ec90662013-02-19 12:11:38 -0800286 I915_WRITE(LVDS, dev_priv->regfile.saveLVDS & mask);
Zhenyu Wang42048782009-10-21 15:27:01 +0800287
Chris Wilson90eb77b2010-08-14 14:41:23 +0100288 if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100289 I915_WRITE(PFIT_CONTROL, dev_priv->regfile.savePFIT_CONTROL);
Jesse Barnes317c35d2008-08-25 15:11:06 -0700290
Chris Wilson90eb77b2010-08-14 14:41:23 +0100291 if (HAS_PCH_SPLIT(dev)) {
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100292 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->regfile.saveBLC_PWM_CTL);
293 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
Takashi Iwai6db65cb2012-06-21 15:30:41 +0200294 /* NOTE: BLC_PWM_CPU_CTL must be written after BLC_PWM_CPU_CTL2;
295 * otherwise we get blank eDP screen after S3 on some machines
296 */
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100297 I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->regfile.saveBLC_CPU_PWM_CTL2);
298 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->regfile.saveBLC_CPU_PWM_CTL);
299 I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
300 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
301 I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
302 I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
Jesse Barnes88271da2011-01-05 12:01:24 -0800303 I915_WRITE(RSTDBYCTL,
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100304 dev_priv->regfile.saveMCHBAR_RENDER_STANDBY);
Zhenyu Wang42048782009-10-21 15:27:01 +0800305 } else {
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100306 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->regfile.savePFIT_PGM_RATIOS);
307 I915_WRITE(BLC_PWM_CTL, dev_priv->regfile.saveBLC_PWM_CTL);
308 I915_WRITE(BLC_HIST_CTL, dev_priv->regfile.saveBLC_HIST_CTL);
309 I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
310 I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
311 I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
312 I915_WRITE(PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
Zhenyu Wang42048782009-10-21 15:27:01 +0800313 }
Jesse Barnes317c35d2008-08-25 15:11:06 -0700314
Jani Nikula8ba2d182013-04-12 15:18:37 +0300315 spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
316
Zhao Yakuia2c459e2010-03-19 17:05:10 +0800317 /* only restore FBC info on the platform that supports FBC*/
Chris Wilson43a95392011-07-08 12:22:36 +0100318 intel_disable_fbc(dev);
Zhao Yakuia2c459e2010-03-19 17:05:10 +0800319 if (I915_HAS_FBC(dev)) {
Chris Wilson90eb77b2010-08-14 14:41:23 +0100320 if (HAS_PCH_SPLIT(dev)) {
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100321 I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
Zhao Yakuib52eb4d2010-06-12 14:32:27 +0800322 } else if (IS_GM45(dev)) {
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100323 I915_WRITE(DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
Zhao Yakuia2c459e2010-03-19 17:05:10 +0800324 } else {
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100325 I915_WRITE(FBC_CFB_BASE, dev_priv->regfile.saveFBC_CFB_BASE);
326 I915_WRITE(FBC_LL_BASE, dev_priv->regfile.saveFBC_LL_BASE);
327 I915_WRITE(FBC_CONTROL2, dev_priv->regfile.saveFBC_CONTROL2);
328 I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
Zhao Yakuia2c459e2010-03-19 17:05:10 +0800329 }
Jesse Barnes06027f92009-10-05 13:47:26 -0700330 }
Daniel Vettera65e8272013-01-25 17:53:22 +0100331
Daniel Vetter44cec742013-01-25 17:53:21 +0100332 if (!drm_core_check_feature(dev, DRIVER_MODESET))
333 i915_restore_vga(dev);
Zhenyu Wang42048782009-10-21 15:27:01 +0800334 else
Daniel Vetter44cec742013-01-25 17:53:21 +0100335 i915_redisable_vga(dev);
Ben Gamari1341d652009-09-14 17:48:42 -0400336}
337
338int i915_save_state(struct drm_device *dev)
339{
340 struct drm_i915_private *dev_priv = dev->dev_private;
341 int i;
342
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100343 pci_read_config_byte(dev->pdev, LBB, &dev_priv->regfile.saveLBB);
Ben Gamari1341d652009-09-14 17:48:42 -0400344
Keith Packardd70bed12011-06-29 00:30:34 -0700345 mutex_lock(&dev->struct_mutex);
346
Ben Gamari1341d652009-09-14 17:48:42 -0400347 i915_save_display(dev);
348
Daniel Vetter905c27b2012-10-17 11:32:56 +0200349 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
350 /* Interrupt state */
351 if (HAS_PCH_SPLIT(dev)) {
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100352 dev_priv->regfile.saveDEIER = I915_READ(DEIER);
353 dev_priv->regfile.saveDEIMR = I915_READ(DEIMR);
354 dev_priv->regfile.saveGTIER = I915_READ(GTIER);
355 dev_priv->regfile.saveGTIMR = I915_READ(GTIMR);
356 dev_priv->regfile.saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);
357 dev_priv->regfile.saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);
358 dev_priv->regfile.saveMCHBAR_RENDER_STANDBY =
Daniel Vetter905c27b2012-10-17 11:32:56 +0200359 I915_READ(RSTDBYCTL);
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100360 dev_priv->regfile.savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG);
Daniel Vetter905c27b2012-10-17 11:32:56 +0200361 } else {
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100362 dev_priv->regfile.saveIER = I915_READ(IER);
363 dev_priv->regfile.saveIMR = I915_READ(IMR);
Daniel Vetter905c27b2012-10-17 11:32:56 +0200364 }
Zhenyu Wang42048782009-10-21 15:27:01 +0800365 }
Ben Gamari1341d652009-09-14 17:48:42 -0400366
Daniel Vetter8090c6b2012-06-24 16:42:32 +0200367 intel_disable_gt_powersave(dev);
Jesse Barnesf97108d2010-01-29 11:27:07 -0800368
Ben Gamari1341d652009-09-14 17:48:42 -0400369 /* Cache mode state */
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100370 dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
Ben Gamari1341d652009-09-14 17:48:42 -0400371
372 /* Memory Arbitration state */
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100373 dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
Ben Gamari1341d652009-09-14 17:48:42 -0400374
375 /* Scratch space */
376 for (i = 0; i < 16; i++) {
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100377 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF00 + (i << 2));
378 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF10 + (i << 2));
Ben Gamari1341d652009-09-14 17:48:42 -0400379 }
380 for (i = 0; i < 3; i++)
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100381 dev_priv->regfile.saveSWF2[i] = I915_READ(SWF30 + (i << 2));
Ben Gamari1341d652009-09-14 17:48:42 -0400382
Keith Packardd70bed12011-06-29 00:30:34 -0700383 mutex_unlock(&dev->struct_mutex);
384
Ben Gamari1341d652009-09-14 17:48:42 -0400385 return 0;
386}
387
388int i915_restore_state(struct drm_device *dev)
389{
390 struct drm_i915_private *dev_priv = dev->dev_private;
391 int i;
392
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100393 pci_write_config_byte(dev->pdev, LBB, dev_priv->regfile.saveLBB);
Ben Gamari1341d652009-09-14 17:48:42 -0400394
Keith Packardd70bed12011-06-29 00:30:34 -0700395 mutex_lock(&dev->struct_mutex);
396
Ben Gamari1341d652009-09-14 17:48:42 -0400397 i915_restore_display(dev);
398
Daniel Vetter905c27b2012-10-17 11:32:56 +0200399 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
400 /* Interrupt state */
401 if (HAS_PCH_SPLIT(dev)) {
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100402 I915_WRITE(DEIER, dev_priv->regfile.saveDEIER);
403 I915_WRITE(DEIMR, dev_priv->regfile.saveDEIMR);
404 I915_WRITE(GTIER, dev_priv->regfile.saveGTIER);
405 I915_WRITE(GTIMR, dev_priv->regfile.saveGTIMR);
406 I915_WRITE(_FDI_RXA_IMR, dev_priv->regfile.saveFDI_RXA_IMR);
407 I915_WRITE(_FDI_RXB_IMR, dev_priv->regfile.saveFDI_RXB_IMR);
408 I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->regfile.savePCH_PORT_HOTPLUG);
Daniel Vetter905c27b2012-10-17 11:32:56 +0200409 } else {
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100410 I915_WRITE(IER, dev_priv->regfile.saveIER);
411 I915_WRITE(IMR, dev_priv->regfile.saveIMR);
Daniel Vetter905c27b2012-10-17 11:32:56 +0200412 }
Zhenyu Wang42048782009-10-21 15:27:01 +0800413 }
Keith Packardd70bed12011-06-29 00:30:34 -0700414
Jesse Barnes317c35d2008-08-25 15:11:06 -0700415 /* Cache mode state */
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100416 I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | 0xffff0000);
Jesse Barnes317c35d2008-08-25 15:11:06 -0700417
418 /* Memory arbitration state */
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100419 I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
Jesse Barnes317c35d2008-08-25 15:11:06 -0700420
421 for (i = 0; i < 16; i++) {
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100422 I915_WRITE(SWF00 + (i << 2), dev_priv->regfile.saveSWF0[i]);
423 I915_WRITE(SWF10 + (i << 2), dev_priv->regfile.saveSWF1[i]);
Jesse Barnes317c35d2008-08-25 15:11:06 -0700424 }
425 for (i = 0; i < 3; i++)
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100426 I915_WRITE(SWF30 + (i << 2), dev_priv->regfile.saveSWF2[i]);
Jesse Barnes317c35d2008-08-25 15:11:06 -0700427
Keith Packardd70bed12011-06-29 00:30:34 -0700428 mutex_unlock(&dev->struct_mutex);
429
Chris Wilsonf899fc62010-07-20 15:44:45 -0700430 intel_i2c_reset(dev);
Eric Anholtf0217c42009-12-01 11:56:30 -0800431
Jesse Barnes317c35d2008-08-25 15:11:06 -0700432 return 0;
433}