Vincent Guittot | c9018aa | 2011-08-08 13:21:59 +0100 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/kernel/topology.c |
| 3 | * |
| 4 | * Copyright (C) 2011 Linaro Limited. |
| 5 | * Written by: Vincent Guittot |
| 6 | * |
| 7 | * based on arch/sh/kernel/topology.c |
| 8 | * |
| 9 | * This file is subject to the terms and conditions of the GNU General Public |
| 10 | * License. See the file "COPYING" in the main directory of this archive |
| 11 | * for more details. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/cpu.h> |
| 15 | #include <linux/cpumask.h> |
| 16 | #include <linux/init.h> |
| 17 | #include <linux/percpu.h> |
| 18 | #include <linux/node.h> |
| 19 | #include <linux/nodemask.h> |
| 20 | #include <linux/sched.h> |
| 21 | |
| 22 | #include <asm/cputype.h> |
| 23 | #include <asm/topology.h> |
| 24 | |
Vincent Guittot | 130d9aa | 2012-07-10 14:08:40 +0100 | [diff] [blame^] | 25 | /* |
| 26 | * cpu power scale management |
| 27 | */ |
| 28 | |
| 29 | /* |
| 30 | * cpu power table |
| 31 | * This per cpu data structure describes the relative capacity of each core. |
| 32 | * On a heteregenous system, cores don't have the same computation capacity |
| 33 | * and we reflect that difference in the cpu_power field so the scheduler can |
| 34 | * take this difference into account during load balance. A per cpu structure |
| 35 | * is preferred because each CPU updates its own cpu_power field during the |
| 36 | * load balance except for idle cores. One idle core is selected to run the |
| 37 | * rebalance_domains for all idle cores and the cpu_power can be updated |
| 38 | * during this sequence. |
| 39 | */ |
| 40 | static DEFINE_PER_CPU(unsigned long, cpu_scale); |
| 41 | |
| 42 | unsigned long arch_scale_freq_power(struct sched_domain *sd, int cpu) |
| 43 | { |
| 44 | return per_cpu(cpu_scale, cpu); |
| 45 | } |
| 46 | |
| 47 | static void set_power_scale(unsigned int cpu, unsigned long power) |
| 48 | { |
| 49 | per_cpu(cpu_scale, cpu) = power; |
| 50 | } |
| 51 | |
| 52 | /* |
| 53 | * cpu topology management |
| 54 | */ |
| 55 | |
Vincent Guittot | c9018aa | 2011-08-08 13:21:59 +0100 | [diff] [blame] | 56 | #define MPIDR_SMP_BITMASK (0x3 << 30) |
| 57 | #define MPIDR_SMP_VALUE (0x2 << 30) |
| 58 | |
| 59 | #define MPIDR_MT_BITMASK (0x1 << 24) |
| 60 | |
| 61 | /* |
| 62 | * These masks reflect the current use of the affinity levels. |
| 63 | * The affinity level can be up to 16 bits according to ARM ARM |
| 64 | */ |
| 65 | |
| 66 | #define MPIDR_LEVEL0_MASK 0x3 |
| 67 | #define MPIDR_LEVEL0_SHIFT 0 |
| 68 | |
| 69 | #define MPIDR_LEVEL1_MASK 0xF |
| 70 | #define MPIDR_LEVEL1_SHIFT 8 |
| 71 | |
| 72 | #define MPIDR_LEVEL2_MASK 0xFF |
| 73 | #define MPIDR_LEVEL2_SHIFT 16 |
| 74 | |
Vincent Guittot | 130d9aa | 2012-07-10 14:08:40 +0100 | [diff] [blame^] | 75 | /* |
| 76 | * cpu topology table |
| 77 | */ |
Vincent Guittot | c9018aa | 2011-08-08 13:21:59 +0100 | [diff] [blame] | 78 | struct cputopo_arm cpu_topology[NR_CPUS]; |
| 79 | |
Vincent Guittot | 4cbd6b1 | 2011-11-29 15:50:20 +0100 | [diff] [blame] | 80 | const struct cpumask *cpu_coregroup_mask(int cpu) |
Vincent Guittot | c9018aa | 2011-08-08 13:21:59 +0100 | [diff] [blame] | 81 | { |
| 82 | return &cpu_topology[cpu].core_sibling; |
| 83 | } |
| 84 | |
| 85 | /* |
| 86 | * store_cpu_topology is called at boot when only one cpu is running |
| 87 | * and with the mutex cpu_hotplug.lock locked, when several cpus have booted, |
| 88 | * which prevents simultaneous write access to cpu_topology array |
| 89 | */ |
| 90 | void store_cpu_topology(unsigned int cpuid) |
| 91 | { |
| 92 | struct cputopo_arm *cpuid_topo = &cpu_topology[cpuid]; |
| 93 | unsigned int mpidr; |
| 94 | unsigned int cpu; |
| 95 | |
| 96 | /* If the cpu topology has been already set, just return */ |
| 97 | if (cpuid_topo->core_id != -1) |
| 98 | return; |
| 99 | |
| 100 | mpidr = read_cpuid_mpidr(); |
| 101 | |
| 102 | /* create cpu topology mapping */ |
| 103 | if ((mpidr & MPIDR_SMP_BITMASK) == MPIDR_SMP_VALUE) { |
| 104 | /* |
| 105 | * This is a multiprocessor system |
| 106 | * multiprocessor format & multiprocessor mode field are set |
| 107 | */ |
| 108 | |
| 109 | if (mpidr & MPIDR_MT_BITMASK) { |
| 110 | /* core performance interdependency */ |
| 111 | cpuid_topo->thread_id = (mpidr >> MPIDR_LEVEL0_SHIFT) |
| 112 | & MPIDR_LEVEL0_MASK; |
| 113 | cpuid_topo->core_id = (mpidr >> MPIDR_LEVEL1_SHIFT) |
| 114 | & MPIDR_LEVEL1_MASK; |
| 115 | cpuid_topo->socket_id = (mpidr >> MPIDR_LEVEL2_SHIFT) |
| 116 | & MPIDR_LEVEL2_MASK; |
| 117 | } else { |
| 118 | /* largely independent cores */ |
| 119 | cpuid_topo->thread_id = -1; |
| 120 | cpuid_topo->core_id = (mpidr >> MPIDR_LEVEL0_SHIFT) |
| 121 | & MPIDR_LEVEL0_MASK; |
| 122 | cpuid_topo->socket_id = (mpidr >> MPIDR_LEVEL1_SHIFT) |
| 123 | & MPIDR_LEVEL1_MASK; |
| 124 | } |
| 125 | } else { |
| 126 | /* |
| 127 | * This is an uniprocessor system |
| 128 | * we are in multiprocessor format but uniprocessor system |
| 129 | * or in the old uniprocessor format |
| 130 | */ |
| 131 | cpuid_topo->thread_id = -1; |
| 132 | cpuid_topo->core_id = 0; |
| 133 | cpuid_topo->socket_id = -1; |
| 134 | } |
| 135 | |
| 136 | /* update core and thread sibling masks */ |
| 137 | for_each_possible_cpu(cpu) { |
| 138 | struct cputopo_arm *cpu_topo = &cpu_topology[cpu]; |
| 139 | |
| 140 | if (cpuid_topo->socket_id == cpu_topo->socket_id) { |
| 141 | cpumask_set_cpu(cpuid, &cpu_topo->core_sibling); |
| 142 | if (cpu != cpuid) |
| 143 | cpumask_set_cpu(cpu, |
| 144 | &cpuid_topo->core_sibling); |
| 145 | |
| 146 | if (cpuid_topo->core_id == cpu_topo->core_id) { |
| 147 | cpumask_set_cpu(cpuid, |
| 148 | &cpu_topo->thread_sibling); |
| 149 | if (cpu != cpuid) |
| 150 | cpumask_set_cpu(cpu, |
| 151 | &cpuid_topo->thread_sibling); |
| 152 | } |
| 153 | } |
| 154 | } |
| 155 | smp_wmb(); |
| 156 | |
| 157 | printk(KERN_INFO "CPU%u: thread %d, cpu %d, socket %d, mpidr %x\n", |
| 158 | cpuid, cpu_topology[cpuid].thread_id, |
| 159 | cpu_topology[cpuid].core_id, |
| 160 | cpu_topology[cpuid].socket_id, mpidr); |
| 161 | } |
| 162 | |
| 163 | /* |
| 164 | * init_cpu_topology is called at boot when only one cpu is running |
| 165 | * which prevent simultaneous write access to cpu_topology array |
| 166 | */ |
| 167 | void init_cpu_topology(void) |
| 168 | { |
| 169 | unsigned int cpu; |
| 170 | |
Vincent Guittot | 130d9aa | 2012-07-10 14:08:40 +0100 | [diff] [blame^] | 171 | /* init core mask and power*/ |
Vincent Guittot | c9018aa | 2011-08-08 13:21:59 +0100 | [diff] [blame] | 172 | for_each_possible_cpu(cpu) { |
| 173 | struct cputopo_arm *cpu_topo = &(cpu_topology[cpu]); |
| 174 | |
| 175 | cpu_topo->thread_id = -1; |
| 176 | cpu_topo->core_id = -1; |
| 177 | cpu_topo->socket_id = -1; |
| 178 | cpumask_clear(&cpu_topo->core_sibling); |
| 179 | cpumask_clear(&cpu_topo->thread_sibling); |
Vincent Guittot | 130d9aa | 2012-07-10 14:08:40 +0100 | [diff] [blame^] | 180 | |
| 181 | set_power_scale(cpu, SCHED_POWER_SCALE); |
Vincent Guittot | c9018aa | 2011-08-08 13:21:59 +0100 | [diff] [blame] | 182 | } |
| 183 | smp_wmb(); |
| 184 | } |