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gerrit-public.fairphone.software / kernel / msm-4.9 / 13326e5a620df5063df2e87b38d923785066ee63 / . / arch / arm / boot / dts / kirkwood-6282.dtsi
blob: 4680eec990f0cd3bc92a985b57e954303ee2f0b4 [file] [log] [blame]
Andrew Lunn82bb2da2012-11-17 17:00:45 +0100[diff] [blame]1/ {
Ezequiel Garcia54397d82013-07-26 10:18:05 -0300[diff] [blame]2 mbus {
Sebastian Hesselbarth7b36efd2014-04-30 14:56:29 +0200[diff] [blame]3 pciec: pcie-controller {
Ezequiel Garcia54397d82013-07-26 10:18:05 -0300[diff] [blame]4 compatible = "marvell,kirkwood-pcie";
5 status = "disabled";
6 device_type = "pci";
7
8 #address-cells = <3>;
9 #size-cells = <2>;
10
11 bus-range = <0x00 0xff>;
12
13 ranges =
14 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
15 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
16 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
17 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
18 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
19 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */
20 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>;
21
Sebastian Hesselbarth7b36efd2014-04-30 14:56:29 +0200[diff] [blame]22 pcie0: pcie@1,0 {
Ezequiel Garcia54397d82013-07-26 10:18:05 -0300[diff] [blame]23 device_type = "pci";
24 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
25 reg = <0x0800 0 0 0 0>;
26 #address-cells = <3>;
27 #size-cells = <2>;
28 #interrupt-cells = <1>;
29 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
30 0x81000000 0 0 0x81000000 0x1 0 1 0>;
31 interrupt-map-mask = <0 0 0 0>;
32 interrupt-map = <0 0 0 0 &intc 9>;
33 marvell,pcie-port = <0>;
34 marvell,pcie-lane = <0>;
35 clocks = <&gate_clk 2>;
36 status = "disabled";
37 };
38
Sebastian Hesselbarth7b36efd2014-04-30 14:56:29 +0200[diff] [blame]39 pcie1: pcie@2,0 {
Ezequiel Garcia54397d82013-07-26 10:18:05 -0300[diff] [blame]40 device_type = "pci";
41 assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
42 reg = <0x1000 0 0 0 0>;
43 #address-cells = <3>;
44 #size-cells = <2>;
45 #interrupt-cells = <1>;
46 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
47 0x81000000 0 0 0x81000000 0x2 0 1 0>;
48 interrupt-map-mask = <0 0 0 0>;
49 interrupt-map = <0 0 0 0 &intc 10>;
50 marvell,pcie-port = <1>;
51 marvell,pcie-lane = <0>;
52 clocks = <&gate_clk 18>;
53 status = "disabled";
54 };
55 };
56 };
Andrew Lunn82bb2da2012-11-17 17:00:45 +0100[diff] [blame]57 ocp@f1000000 {
58
Sebastian Hesselbartha9483962014-04-30 14:56:32 +0200[diff] [blame]59 pinctrl: pin-controller@10000 {
Andrew Lunn82bb2da2012-11-17 17:00:45 +0100[diff] [blame]60 compatible = "marvell,88f6282-pinctrl";
Andrew Lunn82bb2da2012-11-17 17:00:45 +0100[diff] [blame]61
62 pmx_sata0: pmx-sata0 {
63 marvell,pins = "mpp5", "mpp21", "mpp23";
64 marvell,function = "sata0";
65 };
66 pmx_sata1: pmx-sata1 {
67 marvell,pins = "mpp4", "mpp20", "mpp22";
68 marvell,function = "sata1";
69 };
Nobuhiro Iwamatsu00211e92012-12-23 11:34:34 +0900[diff] [blame]70
Sebastian Hesselbarthd7e1c072014-04-30 14:56:40 +0200[diff] [blame]71 /*
72 * Default I2C1 pinctrl setting on mpp36/mpp37,
73 * overwrite marvell,pins on board level if required.
74 */
Nobuhiro Iwamatsu00211e92012-12-23 11:34:34 +0900[diff] [blame]75 pmx_twsi1: pmx-twsi1 {
76 marvell,pins = "mpp36", "mpp37";
77 marvell,function = "twsi1";
78 };
79
Thomas Petazzoni8059fc12012-12-21 15:49:13 +0100[diff] [blame]80 pmx_sdio: pmx-sdio {
81 marvell,pins = "mpp12", "mpp13", "mpp14",
82 "mpp15", "mpp16", "mpp17";
83 marvell,function = "sdio";
84 };
Andrew Lunn82bb2da2012-11-17 17:00:45 +0100[diff] [blame]85 };
Nobuhiro Iwamatsu083651f2012-11-23 06:58:34 +0900[diff] [blame]86
Sebastian Hesselbarth7b36efd2014-04-30 14:56:29 +0200[diff] [blame]87 thermal: thermal@10078 {
Jason Cooperd8e0a2b2013-12-22 17:16:36 +0000[diff] [blame]88 compatible = "marvell,kirkwood-thermal";
89 reg = <0x10078 0x4>;
90 status = "okay";
91 };
92
Sebastian Hesselbarth7b36efd2014-04-30 14:56:29 +0200[diff] [blame]93 rtc: rtc@10300 {
Valentin Longchampdf6bf2e2013-05-27 17:40:32 +0200[diff] [blame]94 compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
95 reg = <0x10300 0x20>;
96 interrupts = <53>;
97 clocks = <&gate_clk 7>;
98 };
99
Sebastian Hesselbarth7b36efd2014-04-30 14:56:29 +0200[diff] [blame]100 i2c1: i2c@11100 {
Jason Cooperd8e0a2b2013-12-22 17:16:36 +0000[diff] [blame]101 compatible = "marvell,mv64xxx-i2c";
102 reg = <0x11100 0x20>;
103 #address-cells = <1>;
104 #size-cells = <0>;
105 interrupts = <32>;
106 clock-frequency = <100000>;
107 clocks = <&gate_clk 7>;
Sebastian Hesselbarthd7e1c072014-04-30 14:56:40 +0200[diff] [blame]108 pinctrl-0 = <&pmx_twsi1>;
109 pinctrl-names = "default";
Jason Cooperd8e0a2b2013-12-22 17:16:36 +0000[diff] [blame]110 status = "disabled";
111 };
112
Sebastian Hesselbarth7b36efd2014-04-30 14:56:29 +0200[diff] [blame]113 sata: sata@80000 {
Valentin Longchampdf6bf2e2013-05-27 17:40:32 +0200[diff] [blame]114 compatible = "marvell,orion-sata";
115 reg = <0x80000 0x5000>;
116 interrupts = <21>;
117 clocks = <&gate_clk 14>, <&gate_clk 15>;
118 clock-names = "0", "1";
Andrew Lunn0ad82cd2013-12-17 21:21:52 +0100[diff] [blame]119 phys = <&sata_phy0>, <&sata_phy1>;
120 phy-names = "port0", "port1";
Valentin Longchampdf6bf2e2013-05-27 17:40:32 +0200[diff] [blame]121 status = "disabled";
122 };
123
Sebastian Hesselbarth7b36efd2014-04-30 14:56:29 +0200[diff] [blame]124 sdio: mvsdio@90000 {
Valentin Longchampdf6bf2e2013-05-27 17:40:32 +0200[diff] [blame]125 compatible = "marvell,orion-sdio";
126 reg = <0x90000 0x200>;
127 interrupts = <28>;
128 clocks = <&gate_clk 4>;
Sebastian Hesselbarth02423992013-11-15 15:20:24 +0100[diff] [blame]129 pinctrl-0 = <&pmx_sdio>;
130 pinctrl-names = "default";
Valentin Longchampdf6bf2e2013-05-27 17:40:32 +0200[diff] [blame]131 bus-width = <4>;
132 cap-sdio-irq;
133 cap-sd-highspeed;
134 cap-mmc-highspeed;
135 status = "disabled";
136 };
Andrew Lunn82bb2da2012-11-17 17:00:45 +0100[diff] [blame]137 };
Nobuhiro Iwamatsu083651f2012-11-23 06:58:34 +0900[diff] [blame]138};