Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> |
| 3 | * Copyright © 2006-2007 Intel Corporation |
| 4 | * Jesse Barnes <jesse.barnes@intel.com> |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice (including the next |
| 14 | * paragraph) shall be included in all copies or substantial portions of the |
| 15 | * Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 23 | * DEALINGS IN THE SOFTWARE. |
| 24 | * |
| 25 | * Authors: |
| 26 | * Eric Anholt <eric@anholt.net> |
| 27 | */ |
| 28 | #include <linux/i2c.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 29 | #include <linux/slab.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 30 | #include <linux/delay.h> |
| 31 | #include "drmP.h" |
| 32 | #include "drm.h" |
| 33 | #include "drm_crtc.h" |
ling.ma@intel.com | 2b8d33f7 | 2009-07-29 11:31:18 +0800 | [diff] [blame] | 34 | #include "drm_edid.h" |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 35 | #include "intel_drv.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 36 | #include "i915_drm.h" |
| 37 | #include "i915_drv.h" |
| 38 | #include "intel_sdvo_regs.h" |
| 39 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 40 | #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) |
| 41 | #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) |
| 42 | #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) |
| 43 | #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0) |
| 44 | |
| 45 | #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ |
| 46 | SDVO_TV_MASK) |
| 47 | |
| 48 | #define IS_TV(c) (c->output_flag & SDVO_TV_MASK) |
Chris Wilson | 13946743 | 2011-02-09 20:01:16 +0000 | [diff] [blame^] | 49 | #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 50 | #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 51 | #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 52 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 53 | |
Chris Wilson | 2e88e40 | 2010-08-07 11:01:27 +0100 | [diff] [blame] | 54 | static const char *tv_format_names[] = { |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 55 | "NTSC_M" , "NTSC_J" , "NTSC_443", |
| 56 | "PAL_B" , "PAL_D" , "PAL_G" , |
| 57 | "PAL_H" , "PAL_I" , "PAL_M" , |
| 58 | "PAL_N" , "PAL_NC" , "PAL_60" , |
| 59 | "SECAM_B" , "SECAM_D" , "SECAM_G" , |
| 60 | "SECAM_K" , "SECAM_K1", "SECAM_L" , |
| 61 | "SECAM_60" |
| 62 | }; |
| 63 | |
| 64 | #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names)) |
| 65 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 66 | struct intel_sdvo { |
| 67 | struct intel_encoder base; |
| 68 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 69 | struct i2c_adapter *i2c; |
Keith Packard | f9c10a9 | 2009-05-30 12:16:25 -0700 | [diff] [blame] | 70 | u8 slave_addr; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 71 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 72 | struct i2c_adapter ddc; |
| 73 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 74 | /* Register for the SDVO device: SDVOB or SDVOC */ |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 75 | int sdvo_reg; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 76 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 77 | /* Active outputs controlled by this SDVO output */ |
| 78 | uint16_t controlled_output; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 79 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 80 | /* |
| 81 | * Capabilities of the SDVO device returned by |
| 82 | * i830_sdvo_get_capabilities() |
| 83 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 84 | struct intel_sdvo_caps caps; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 85 | |
| 86 | /* Pixel clock limitations reported by the SDVO device, in kHz */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 87 | int pixel_clock_min, pixel_clock_max; |
| 88 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 89 | /* |
| 90 | * For multiple function SDVO device, |
| 91 | * this is for current attached outputs. |
| 92 | */ |
| 93 | uint16_t attached_output; |
| 94 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 95 | /** |
| 96 | * This is set if we're going to treat the device as TV-out. |
| 97 | * |
| 98 | * While we have these nice friendly flags for output types that ought |
| 99 | * to decide this for us, the S-Video output on our HDMI+S-Video card |
| 100 | * shows up as RGB1 (VGA). |
| 101 | */ |
| 102 | bool is_tv; |
| 103 | |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 104 | /* This is for current tv format name */ |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 105 | int tv_format_index; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 106 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 107 | /** |
| 108 | * This is set if we treat the device as HDMI, instead of DVI. |
| 109 | */ |
| 110 | bool is_hdmi; |
Chris Wilson | da79de9 | 2010-11-22 11:12:46 +0000 | [diff] [blame] | 111 | bool has_hdmi_monitor; |
| 112 | bool has_hdmi_audio; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 113 | |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 114 | /** |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 115 | * This is set if we detect output of sdvo device as LVDS and |
| 116 | * have a valid fixed mode to use with the panel. |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 117 | */ |
| 118 | bool is_lvds; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 119 | |
| 120 | /** |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 121 | * This is sdvo fixed pannel mode pointer |
| 122 | */ |
| 123 | struct drm_display_mode *sdvo_lvds_fixed_mode; |
| 124 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 125 | /* DDC bus used by this SDVO encoder */ |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 126 | uint8_t ddc_bus; |
| 127 | |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 128 | /* Input timings for adjusted_mode */ |
| 129 | struct intel_sdvo_dtd input_dtd; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 130 | }; |
| 131 | |
| 132 | struct intel_sdvo_connector { |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 133 | struct intel_connector base; |
| 134 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 135 | /* Mark the type of connector */ |
| 136 | uint16_t output_flag; |
| 137 | |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 138 | int force_audio; |
| 139 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 140 | /* This contains all current supported TV format */ |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 141 | u8 tv_format_supported[TV_FORMAT_NUM]; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 142 | int format_supported_num; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 143 | struct drm_property *tv_format; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 144 | |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 145 | struct drm_property *force_audio_property; |
| 146 | |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 147 | /* add the property for the SDVO-TV */ |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 148 | struct drm_property *left; |
| 149 | struct drm_property *right; |
| 150 | struct drm_property *top; |
| 151 | struct drm_property *bottom; |
| 152 | struct drm_property *hpos; |
| 153 | struct drm_property *vpos; |
| 154 | struct drm_property *contrast; |
| 155 | struct drm_property *saturation; |
| 156 | struct drm_property *hue; |
| 157 | struct drm_property *sharpness; |
| 158 | struct drm_property *flicker_filter; |
| 159 | struct drm_property *flicker_filter_adaptive; |
| 160 | struct drm_property *flicker_filter_2d; |
| 161 | struct drm_property *tv_chroma_filter; |
| 162 | struct drm_property *tv_luma_filter; |
Chris Wilson | e044218 | 2010-08-04 13:50:29 +0100 | [diff] [blame] | 163 | struct drm_property *dot_crawl; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 164 | |
| 165 | /* add the property for the SDVO-TV/LVDS */ |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 166 | struct drm_property *brightness; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 167 | |
| 168 | /* Add variable to record current setting for the above property */ |
| 169 | u32 left_margin, right_margin, top_margin, bottom_margin; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 170 | |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 171 | /* this is to get the range of margin.*/ |
| 172 | u32 max_hscan, max_vscan; |
| 173 | u32 max_hpos, cur_hpos; |
| 174 | u32 max_vpos, cur_vpos; |
| 175 | u32 cur_brightness, max_brightness; |
| 176 | u32 cur_contrast, max_contrast; |
| 177 | u32 cur_saturation, max_saturation; |
| 178 | u32 cur_hue, max_hue; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 179 | u32 cur_sharpness, max_sharpness; |
| 180 | u32 cur_flicker_filter, max_flicker_filter; |
| 181 | u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive; |
| 182 | u32 cur_flicker_filter_2d, max_flicker_filter_2d; |
| 183 | u32 cur_tv_chroma_filter, max_tv_chroma_filter; |
| 184 | u32 cur_tv_luma_filter, max_tv_luma_filter; |
Chris Wilson | e044218 | 2010-08-04 13:50:29 +0100 | [diff] [blame] | 185 | u32 cur_dot_crawl, max_dot_crawl; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 186 | }; |
| 187 | |
Chris Wilson | 890f335 | 2010-09-14 16:46:59 +0100 | [diff] [blame] | 188 | static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 189 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 190 | return container_of(encoder, struct intel_sdvo, base.base); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 191 | } |
| 192 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 193 | static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector) |
| 194 | { |
| 195 | return container_of(intel_attached_encoder(connector), |
| 196 | struct intel_sdvo, base); |
| 197 | } |
| 198 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 199 | static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector) |
| 200 | { |
| 201 | return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base); |
| 202 | } |
| 203 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 204 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 205 | intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 206 | static bool |
| 207 | intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, |
| 208 | struct intel_sdvo_connector *intel_sdvo_connector, |
| 209 | int type); |
| 210 | static bool |
| 211 | intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, |
| 212 | struct intel_sdvo_connector *intel_sdvo_connector); |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 213 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 214 | /** |
| 215 | * Writes the SDVOB or SDVOC with the given value, but always writes both |
| 216 | * SDVOB and SDVOC to work around apparent hardware issues (according to |
| 217 | * comments in the BIOS). |
| 218 | */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 219 | static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 220 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 221 | struct drm_device *dev = intel_sdvo->base.base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 222 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 223 | u32 bval = val, cval = val; |
| 224 | int i; |
| 225 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 226 | if (intel_sdvo->sdvo_reg == PCH_SDVOB) { |
| 227 | I915_WRITE(intel_sdvo->sdvo_reg, val); |
| 228 | I915_READ(intel_sdvo->sdvo_reg); |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 229 | return; |
| 230 | } |
| 231 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 232 | if (intel_sdvo->sdvo_reg == SDVOB) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 233 | cval = I915_READ(SDVOC); |
| 234 | } else { |
| 235 | bval = I915_READ(SDVOB); |
| 236 | } |
| 237 | /* |
| 238 | * Write the registers twice for luck. Sometimes, |
| 239 | * writing them only once doesn't appear to 'stick'. |
| 240 | * The BIOS does this too. Yay, magic |
| 241 | */ |
| 242 | for (i = 0; i < 2; i++) |
| 243 | { |
| 244 | I915_WRITE(SDVOB, bval); |
| 245 | I915_READ(SDVOB); |
| 246 | I915_WRITE(SDVOC, cval); |
| 247 | I915_READ(SDVOC); |
| 248 | } |
| 249 | } |
| 250 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 251 | static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 252 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 253 | struct i2c_msg msgs[] = { |
| 254 | { |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 255 | .addr = intel_sdvo->slave_addr, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 256 | .flags = 0, |
| 257 | .len = 1, |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 258 | .buf = &addr, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 259 | }, |
| 260 | { |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 261 | .addr = intel_sdvo->slave_addr, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 262 | .flags = I2C_M_RD, |
| 263 | .len = 1, |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 264 | .buf = ch, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 265 | } |
| 266 | }; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 267 | int ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 268 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 269 | if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 270 | return true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 271 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 272 | DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 273 | return false; |
| 274 | } |
| 275 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 276 | #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd} |
| 277 | /** Mapping of command numbers to names, for debug output */ |
Tobias Klauser | 005568b | 2009-02-09 22:02:42 +0100 | [diff] [blame] | 278 | static const struct _sdvo_cmd_name { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 279 | u8 cmd; |
Chris Wilson | 2e88e40 | 2010-08-07 11:01:27 +0100 | [diff] [blame] | 280 | const char *name; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 281 | } sdvo_cmd_names[] = { |
| 282 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), |
| 283 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), |
| 284 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV), |
| 285 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS), |
| 286 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS), |
| 287 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS), |
| 288 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP), |
| 289 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP), |
| 290 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS), |
| 291 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT), |
| 292 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG), |
| 293 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG), |
| 294 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE), |
| 295 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT), |
| 296 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT), |
| 297 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1), |
| 298 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2), |
| 299 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), |
| 300 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2), |
| 301 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), |
| 302 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1), |
| 303 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2), |
| 304 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1), |
| 305 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2), |
| 306 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING), |
| 307 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1), |
| 308 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2), |
| 309 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE), |
| 310 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE), |
| 311 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS), |
| 312 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT), |
| 313 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT), |
| 314 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS), |
| 315 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT), |
| 316 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT), |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 317 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES), |
| 318 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE), |
| 319 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE), |
| 320 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE), |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 321 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH), |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 322 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT), |
| 323 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT), |
| 324 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS), |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 325 | |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 326 | /* Add the op code for SDVO enhancements */ |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 327 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS), |
| 328 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS), |
| 329 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS), |
| 330 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS), |
| 331 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS), |
| 332 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS), |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 333 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION), |
| 334 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION), |
| 335 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION), |
| 336 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE), |
| 337 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE), |
| 338 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE), |
| 339 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST), |
| 340 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST), |
| 341 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST), |
| 342 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS), |
| 343 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS), |
| 344 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS), |
| 345 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H), |
| 346 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H), |
| 347 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H), |
| 348 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V), |
| 349 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V), |
| 350 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V), |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 351 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER), |
| 352 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER), |
| 353 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER), |
| 354 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE), |
| 355 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE), |
| 356 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE), |
| 357 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D), |
| 358 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D), |
| 359 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D), |
| 360 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS), |
| 361 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS), |
| 362 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS), |
| 363 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL), |
| 364 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL), |
| 365 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER), |
| 366 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER), |
| 367 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER), |
| 368 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER), |
| 369 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER), |
| 370 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER), |
| 371 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 372 | /* HDMI op code */ |
| 373 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE), |
| 374 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE), |
| 375 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE), |
| 376 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI), |
| 377 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI), |
| 378 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP), |
| 379 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY), |
| 380 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY), |
| 381 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER), |
| 382 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT), |
| 383 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT), |
| 384 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX), |
| 385 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX), |
| 386 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO), |
| 387 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT), |
| 388 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT), |
| 389 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE), |
| 390 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE), |
| 391 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA), |
| 392 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA), |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 393 | }; |
| 394 | |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 395 | #define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 396 | #define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC") |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 397 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 398 | static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 399 | const void *args, int args_len) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 400 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 401 | int i; |
| 402 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 403 | DRM_DEBUG_KMS("%s: W: %02X ", |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 404 | SDVO_NAME(intel_sdvo), cmd); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 405 | for (i = 0; i < args_len; i++) |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 406 | DRM_LOG_KMS("%02X ", ((u8 *)args)[i]); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 407 | for (; i < 8; i++) |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 408 | DRM_LOG_KMS(" "); |
Kulikov Vasiliy | 04ad327 | 2010-06-28 15:54:56 +0400 | [diff] [blame] | 409 | for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 410 | if (cmd == sdvo_cmd_names[i].cmd) { |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 411 | DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 412 | break; |
| 413 | } |
| 414 | } |
Kulikov Vasiliy | 04ad327 | 2010-06-28 15:54:56 +0400 | [diff] [blame] | 415 | if (i == ARRAY_SIZE(sdvo_cmd_names)) |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 416 | DRM_LOG_KMS("(%02X)", cmd); |
| 417 | DRM_LOG_KMS("\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 418 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 419 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 420 | static const char *cmd_status_names[] = { |
| 421 | "Power on", |
| 422 | "Success", |
| 423 | "Not supported", |
| 424 | "Invalid arg", |
| 425 | "Pending", |
| 426 | "Target not specified", |
| 427 | "Scaling not supported" |
| 428 | }; |
| 429 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 430 | static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, |
| 431 | const void *args, int args_len) |
| 432 | { |
| 433 | u8 buf[args_len*2 + 2], status; |
| 434 | struct i2c_msg msgs[args_len + 3]; |
| 435 | int i, ret; |
| 436 | |
| 437 | intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); |
| 438 | |
| 439 | for (i = 0; i < args_len; i++) { |
| 440 | msgs[i].addr = intel_sdvo->slave_addr; |
| 441 | msgs[i].flags = 0; |
| 442 | msgs[i].len = 2; |
| 443 | msgs[i].buf = buf + 2 *i; |
| 444 | buf[2*i + 0] = SDVO_I2C_ARG_0 - i; |
| 445 | buf[2*i + 1] = ((u8*)args)[i]; |
| 446 | } |
| 447 | msgs[i].addr = intel_sdvo->slave_addr; |
| 448 | msgs[i].flags = 0; |
| 449 | msgs[i].len = 2; |
| 450 | msgs[i].buf = buf + 2*i; |
| 451 | buf[2*i + 0] = SDVO_I2C_OPCODE; |
| 452 | buf[2*i + 1] = cmd; |
| 453 | |
| 454 | /* the following two are to read the response */ |
| 455 | status = SDVO_I2C_CMD_STATUS; |
| 456 | msgs[i+1].addr = intel_sdvo->slave_addr; |
| 457 | msgs[i+1].flags = 0; |
| 458 | msgs[i+1].len = 1; |
| 459 | msgs[i+1].buf = &status; |
| 460 | |
| 461 | msgs[i+2].addr = intel_sdvo->slave_addr; |
| 462 | msgs[i+2].flags = I2C_M_RD; |
| 463 | msgs[i+2].len = 1; |
| 464 | msgs[i+2].buf = &status; |
| 465 | |
| 466 | ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3); |
| 467 | if (ret < 0) { |
| 468 | DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); |
| 469 | return false; |
| 470 | } |
| 471 | if (ret != i+3) { |
| 472 | /* failure in I2C transfer */ |
| 473 | DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3); |
| 474 | return false; |
| 475 | } |
| 476 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 477 | return true; |
| 478 | } |
| 479 | |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 480 | static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, |
| 481 | void *response, int response_len) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 482 | { |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 483 | u8 retry = 5; |
| 484 | u8 status; |
Zhenyu Wang | 33b5296 | 2009-03-24 14:02:40 +0800 | [diff] [blame] | 485 | int i; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 486 | |
Chris Wilson | d121a5d | 2011-01-25 15:00:01 +0000 | [diff] [blame] | 487 | DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo)); |
| 488 | |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 489 | /* |
| 490 | * The documentation states that all commands will be |
| 491 | * processed within 15µs, and that we need only poll |
| 492 | * the status byte a maximum of 3 times in order for the |
| 493 | * command to be complete. |
| 494 | * |
| 495 | * Check 5 times in case the hardware failed to read the docs. |
| 496 | */ |
Chris Wilson | d121a5d | 2011-01-25 15:00:01 +0000 | [diff] [blame] | 497 | if (!intel_sdvo_read_byte(intel_sdvo, |
| 498 | SDVO_I2C_CMD_STATUS, |
| 499 | &status)) |
| 500 | goto log_fail; |
| 501 | |
| 502 | while (status == SDVO_CMD_STATUS_PENDING && retry--) { |
| 503 | udelay(15); |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 504 | if (!intel_sdvo_read_byte(intel_sdvo, |
| 505 | SDVO_I2C_CMD_STATUS, |
| 506 | &status)) |
Chris Wilson | d121a5d | 2011-01-25 15:00:01 +0000 | [diff] [blame] | 507 | goto log_fail; |
| 508 | } |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 509 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 510 | if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP) |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 511 | DRM_LOG_KMS("(%s)", cmd_status_names[status]); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 512 | else |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 513 | DRM_LOG_KMS("(??? %d)", status); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 514 | |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 515 | if (status != SDVO_CMD_STATUS_SUCCESS) |
| 516 | goto log_fail; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 517 | |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 518 | /* Read the command response */ |
| 519 | for (i = 0; i < response_len; i++) { |
| 520 | if (!intel_sdvo_read_byte(intel_sdvo, |
| 521 | SDVO_I2C_RETURN_0 + i, |
| 522 | &((u8 *)response)[i])) |
| 523 | goto log_fail; |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 524 | DRM_LOG_KMS(" %02X", ((u8 *)response)[i]); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 525 | } |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 526 | DRM_LOG_KMS("\n"); |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 527 | return true; |
| 528 | |
| 529 | log_fail: |
Chris Wilson | d121a5d | 2011-01-25 15:00:01 +0000 | [diff] [blame] | 530 | DRM_LOG_KMS("... failed\n"); |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 531 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 532 | } |
| 533 | |
Hannes Eder | b358d0a | 2008-12-18 21:18:47 +0100 | [diff] [blame] | 534 | static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 535 | { |
| 536 | if (mode->clock >= 100000) |
| 537 | return 1; |
| 538 | else if (mode->clock >= 50000) |
| 539 | return 2; |
| 540 | else |
| 541 | return 4; |
| 542 | } |
| 543 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 544 | static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, |
| 545 | u8 ddc_bus) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 546 | { |
Chris Wilson | d121a5d | 2011-01-25 15:00:01 +0000 | [diff] [blame] | 547 | /* This must be the immediately preceding write before the i2c xfer */ |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 548 | return intel_sdvo_write_cmd(intel_sdvo, |
| 549 | SDVO_CMD_SET_CONTROL_BUS_SWITCH, |
| 550 | &ddc_bus, 1); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 551 | } |
| 552 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 553 | static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) |
| 554 | { |
Chris Wilson | d121a5d | 2011-01-25 15:00:01 +0000 | [diff] [blame] | 555 | if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) |
| 556 | return false; |
| 557 | |
| 558 | return intel_sdvo_read_response(intel_sdvo, NULL, 0); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 559 | } |
| 560 | |
| 561 | static bool |
| 562 | intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) |
| 563 | { |
| 564 | if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) |
| 565 | return false; |
| 566 | |
| 567 | return intel_sdvo_read_response(intel_sdvo, value, len); |
| 568 | } |
| 569 | |
| 570 | static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 571 | { |
| 572 | struct intel_sdvo_set_target_input_args targets = {0}; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 573 | return intel_sdvo_set_value(intel_sdvo, |
| 574 | SDVO_CMD_SET_TARGET_INPUT, |
| 575 | &targets, sizeof(targets)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 576 | } |
| 577 | |
| 578 | /** |
| 579 | * Return whether each input is trained. |
| 580 | * |
| 581 | * This function is making an assumption about the layout of the response, |
| 582 | * which should be checked against the docs. |
| 583 | */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 584 | static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 585 | { |
| 586 | struct intel_sdvo_get_trained_inputs_response response; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 587 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 588 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, |
| 589 | &response, sizeof(response))) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 590 | return false; |
| 591 | |
| 592 | *input_1 = response.input0_trained; |
| 593 | *input_2 = response.input1_trained; |
| 594 | return true; |
| 595 | } |
| 596 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 597 | static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 598 | u16 outputs) |
| 599 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 600 | return intel_sdvo_set_value(intel_sdvo, |
| 601 | SDVO_CMD_SET_ACTIVE_OUTPUTS, |
| 602 | &outputs, sizeof(outputs)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 603 | } |
| 604 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 605 | static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 606 | int mode) |
| 607 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 608 | u8 state = SDVO_ENCODER_STATE_ON; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 609 | |
| 610 | switch (mode) { |
| 611 | case DRM_MODE_DPMS_ON: |
| 612 | state = SDVO_ENCODER_STATE_ON; |
| 613 | break; |
| 614 | case DRM_MODE_DPMS_STANDBY: |
| 615 | state = SDVO_ENCODER_STATE_STANDBY; |
| 616 | break; |
| 617 | case DRM_MODE_DPMS_SUSPEND: |
| 618 | state = SDVO_ENCODER_STATE_SUSPEND; |
| 619 | break; |
| 620 | case DRM_MODE_DPMS_OFF: |
| 621 | state = SDVO_ENCODER_STATE_OFF; |
| 622 | break; |
| 623 | } |
| 624 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 625 | return intel_sdvo_set_value(intel_sdvo, |
| 626 | SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 627 | } |
| 628 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 629 | static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 630 | int *clock_min, |
| 631 | int *clock_max) |
| 632 | { |
| 633 | struct intel_sdvo_pixel_clock_range clocks; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 634 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 635 | if (!intel_sdvo_get_value(intel_sdvo, |
| 636 | SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, |
| 637 | &clocks, sizeof(clocks))) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 638 | return false; |
| 639 | |
| 640 | /* Convert the values from units of 10 kHz to kHz. */ |
| 641 | *clock_min = clocks.min * 10; |
| 642 | *clock_max = clocks.max * 10; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 643 | return true; |
| 644 | } |
| 645 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 646 | static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 647 | u16 outputs) |
| 648 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 649 | return intel_sdvo_set_value(intel_sdvo, |
| 650 | SDVO_CMD_SET_TARGET_OUTPUT, |
| 651 | &outputs, sizeof(outputs)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 652 | } |
| 653 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 654 | static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 655 | struct intel_sdvo_dtd *dtd) |
| 656 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 657 | return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && |
| 658 | intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 659 | } |
| 660 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 661 | static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 662 | struct intel_sdvo_dtd *dtd) |
| 663 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 664 | return intel_sdvo_set_timing(intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 665 | SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); |
| 666 | } |
| 667 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 668 | static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 669 | struct intel_sdvo_dtd *dtd) |
| 670 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 671 | return intel_sdvo_set_timing(intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 672 | SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); |
| 673 | } |
| 674 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 675 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 676 | intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 677 | uint16_t clock, |
| 678 | uint16_t width, |
| 679 | uint16_t height) |
| 680 | { |
| 681 | struct intel_sdvo_preferred_input_timing_args args; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 682 | |
Zhenyu Wang | e642c6f | 2009-03-24 14:02:42 +0800 | [diff] [blame] | 683 | memset(&args, 0, sizeof(args)); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 684 | args.clock = clock; |
| 685 | args.width = width; |
| 686 | args.height = height; |
Zhenyu Wang | e642c6f | 2009-03-24 14:02:42 +0800 | [diff] [blame] | 687 | args.interlace = 0; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 688 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 689 | if (intel_sdvo->is_lvds && |
| 690 | (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width || |
| 691 | intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height)) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 692 | args.scaled = 1; |
| 693 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 694 | return intel_sdvo_set_value(intel_sdvo, |
| 695 | SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, |
| 696 | &args, sizeof(args)); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 697 | } |
| 698 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 699 | static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 700 | struct intel_sdvo_dtd *dtd) |
| 701 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 702 | return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, |
| 703 | &dtd->part1, sizeof(dtd->part1)) && |
| 704 | intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, |
| 705 | &dtd->part2, sizeof(dtd->part2)); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 706 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 707 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 708 | static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 709 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 710 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 711 | } |
| 712 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 713 | static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 714 | const struct drm_display_mode *mode) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 715 | { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 716 | uint16_t width, height; |
| 717 | uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len; |
| 718 | uint16_t h_sync_offset, v_sync_offset; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 719 | |
| 720 | width = mode->crtc_hdisplay; |
| 721 | height = mode->crtc_vdisplay; |
| 722 | |
| 723 | /* do some mode translations */ |
| 724 | h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start; |
| 725 | h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; |
| 726 | |
| 727 | v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start; |
| 728 | v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; |
| 729 | |
| 730 | h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start; |
| 731 | v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start; |
| 732 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 733 | dtd->part1.clock = mode->clock / 10; |
| 734 | dtd->part1.h_active = width & 0xff; |
| 735 | dtd->part1.h_blank = h_blank_len & 0xff; |
| 736 | dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 737 | ((h_blank_len >> 8) & 0xf); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 738 | dtd->part1.v_active = height & 0xff; |
| 739 | dtd->part1.v_blank = v_blank_len & 0xff; |
| 740 | dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 741 | ((v_blank_len >> 8) & 0xf); |
| 742 | |
Zhenyu Wang | 171a9e9 | 2009-03-24 14:02:41 +0800 | [diff] [blame] | 743 | dtd->part2.h_sync_off = h_sync_offset & 0xff; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 744 | dtd->part2.h_sync_width = h_sync_len & 0xff; |
| 745 | dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 746 | (v_sync_len & 0xf); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 747 | dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 748 | ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | |
| 749 | ((v_sync_len & 0x30) >> 4); |
| 750 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 751 | dtd->part2.dtd_flags = 0x18; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 752 | if (mode->flags & DRM_MODE_FLAG_PHSYNC) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 753 | dtd->part2.dtd_flags |= 0x2; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 754 | if (mode->flags & DRM_MODE_FLAG_PVSYNC) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 755 | dtd->part2.dtd_flags |= 0x4; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 756 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 757 | dtd->part2.sdvo_flags = 0; |
| 758 | dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; |
| 759 | dtd->part2.reserved = 0; |
| 760 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 761 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 762 | static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode, |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 763 | const struct intel_sdvo_dtd *dtd) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 764 | { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 765 | mode->hdisplay = dtd->part1.h_active; |
| 766 | mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; |
| 767 | mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off; |
Zhenyu Wang | 171a9e9 | 2009-03-24 14:02:41 +0800 | [diff] [blame] | 768 | mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 769 | mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width; |
| 770 | mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; |
| 771 | mode->htotal = mode->hdisplay + dtd->part1.h_blank; |
| 772 | mode->htotal += (dtd->part1.h_high & 0xf) << 8; |
| 773 | |
| 774 | mode->vdisplay = dtd->part1.v_active; |
| 775 | mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; |
| 776 | mode->vsync_start = mode->vdisplay; |
| 777 | mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; |
Zhenyu Wang | 171a9e9 | 2009-03-24 14:02:41 +0800 | [diff] [blame] | 778 | mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 779 | mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0; |
| 780 | mode->vsync_end = mode->vsync_start + |
| 781 | (dtd->part2.v_sync_off_width & 0xf); |
| 782 | mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; |
| 783 | mode->vtotal = mode->vdisplay + dtd->part1.v_blank; |
| 784 | mode->vtotal += (dtd->part1.v_high & 0xf) << 8; |
| 785 | |
| 786 | mode->clock = dtd->part1.clock * 10; |
| 787 | |
Zhenyu Wang | 171a9e9 | 2009-03-24 14:02:41 +0800 | [diff] [blame] | 788 | mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 789 | if (dtd->part2.dtd_flags & 0x2) |
| 790 | mode->flags |= DRM_MODE_FLAG_PHSYNC; |
| 791 | if (dtd->part2.dtd_flags & 0x4) |
| 792 | mode->flags |= DRM_MODE_FLAG_PVSYNC; |
| 793 | } |
| 794 | |
Chris Wilson | e27d853 | 2010-10-22 09:15:22 +0100 | [diff] [blame] | 795 | static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 796 | { |
Chris Wilson | e27d853 | 2010-10-22 09:15:22 +0100 | [diff] [blame] | 797 | struct intel_sdvo_encode encode; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 798 | |
Chris Wilson | e27d853 | 2010-10-22 09:15:22 +0100 | [diff] [blame] | 799 | return intel_sdvo_get_value(intel_sdvo, |
| 800 | SDVO_CMD_GET_SUPP_ENCODE, |
| 801 | &encode, sizeof(encode)); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 802 | } |
| 803 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 804 | static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 805 | uint8_t mode) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 806 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 807 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 808 | } |
| 809 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 810 | static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 811 | uint8_t mode) |
| 812 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 813 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 814 | } |
| 815 | |
| 816 | #if 0 |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 817 | static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 818 | { |
| 819 | int i, j; |
| 820 | uint8_t set_buf_index[2]; |
| 821 | uint8_t av_split; |
| 822 | uint8_t buf_size; |
| 823 | uint8_t buf[48]; |
| 824 | uint8_t *pos; |
| 825 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 826 | intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 827 | |
| 828 | for (i = 0; i <= av_split; i++) { |
| 829 | set_buf_index[0] = i; set_buf_index[1] = 0; |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 830 | intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 831 | set_buf_index, 2); |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 832 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); |
| 833 | intel_sdvo_read_response(encoder, &buf_size, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 834 | |
| 835 | pos = buf; |
| 836 | for (j = 0; j <= buf_size; j += 8) { |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 837 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 838 | NULL, 0); |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 839 | intel_sdvo_read_response(encoder, pos, 8); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 840 | pos += 8; |
| 841 | } |
| 842 | } |
| 843 | } |
| 844 | #endif |
| 845 | |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 846 | static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 847 | { |
| 848 | struct dip_infoframe avi_if = { |
| 849 | .type = DIP_TYPE_AVI, |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 850 | .ver = DIP_VERSION_AVI, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 851 | .len = DIP_LEN_AVI, |
| 852 | }; |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 853 | uint8_t tx_rate = SDVO_HBUF_TX_VSYNC; |
| 854 | uint8_t set_buf_index[2] = { 1, 0 }; |
| 855 | uint64_t *data = (uint64_t *)&avi_if; |
| 856 | unsigned i; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 857 | |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 858 | intel_dip_infoframe_csum(&avi_if); |
| 859 | |
Chris Wilson | d121a5d | 2011-01-25 15:00:01 +0000 | [diff] [blame] | 860 | if (!intel_sdvo_set_value(intel_sdvo, |
| 861 | SDVO_CMD_SET_HBUF_INDEX, |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 862 | set_buf_index, 2)) |
| 863 | return false; |
| 864 | |
| 865 | for (i = 0; i < sizeof(avi_if); i += 8) { |
Chris Wilson | d121a5d | 2011-01-25 15:00:01 +0000 | [diff] [blame] | 866 | if (!intel_sdvo_set_value(intel_sdvo, |
| 867 | SDVO_CMD_SET_HBUF_DATA, |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 868 | data, 8)) |
| 869 | return false; |
| 870 | data++; |
| 871 | } |
| 872 | |
Chris Wilson | d121a5d | 2011-01-25 15:00:01 +0000 | [diff] [blame] | 873 | return intel_sdvo_set_value(intel_sdvo, |
| 874 | SDVO_CMD_SET_HBUF_TXRATE, |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 875 | &tx_rate, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 876 | } |
| 877 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 878 | static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo) |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 879 | { |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 880 | struct intel_sdvo_tv_format format; |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 881 | uint32_t format_map; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 882 | |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 883 | format_map = 1 << intel_sdvo->tv_format_index; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 884 | memset(&format, 0, sizeof(format)); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 885 | memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 886 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 887 | BUILD_BUG_ON(sizeof(format) != 6); |
| 888 | return intel_sdvo_set_value(intel_sdvo, |
| 889 | SDVO_CMD_SET_TV_FORMAT, |
| 890 | &format, sizeof(format)); |
| 891 | } |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 892 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 893 | static bool |
| 894 | intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, |
| 895 | struct drm_display_mode *mode) |
| 896 | { |
| 897 | struct intel_sdvo_dtd output_dtd; |
| 898 | |
| 899 | if (!intel_sdvo_set_target_output(intel_sdvo, |
| 900 | intel_sdvo->attached_output)) |
| 901 | return false; |
| 902 | |
| 903 | intel_sdvo_get_dtd_from_mode(&output_dtd, mode); |
| 904 | if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) |
| 905 | return false; |
| 906 | |
| 907 | return true; |
| 908 | } |
| 909 | |
| 910 | static bool |
| 911 | intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo, |
| 912 | struct drm_display_mode *mode, |
| 913 | struct drm_display_mode *adjusted_mode) |
| 914 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 915 | /* Reset the input timing to the screen. Assume always input 0. */ |
| 916 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
| 917 | return false; |
| 918 | |
| 919 | if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, |
| 920 | mode->clock / 10, |
| 921 | mode->hdisplay, |
| 922 | mode->vdisplay)) |
| 923 | return false; |
| 924 | |
| 925 | if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 926 | &intel_sdvo->input_dtd)) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 927 | return false; |
| 928 | |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 929 | intel_sdvo_get_mode_from_dtd(adjusted_mode, &intel_sdvo->input_dtd); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 930 | |
| 931 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 932 | return true; |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 933 | } |
| 934 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 935 | static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder, |
| 936 | struct drm_display_mode *mode, |
| 937 | struct drm_display_mode *adjusted_mode) |
| 938 | { |
Chris Wilson | 890f335 | 2010-09-14 16:46:59 +0100 | [diff] [blame] | 939 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder); |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 940 | int multiplier; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 941 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 942 | /* We need to construct preferred input timings based on our |
| 943 | * output timings. To do that, we have to set the output |
| 944 | * timings, even though this isn't really the right place in |
| 945 | * the sequence to do it. Oh well. |
| 946 | */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 947 | if (intel_sdvo->is_tv) { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 948 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 949 | return false; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 950 | |
Pavel Roskin | c74696b | 2010-09-02 14:46:34 -0400 | [diff] [blame] | 951 | (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo, |
| 952 | mode, |
| 953 | adjusted_mode); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 954 | } else if (intel_sdvo->is_lvds) { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 955 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 956 | intel_sdvo->sdvo_lvds_fixed_mode)) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 957 | return false; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 958 | |
Pavel Roskin | c74696b | 2010-09-02 14:46:34 -0400 | [diff] [blame] | 959 | (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo, |
| 960 | mode, |
| 961 | adjusted_mode); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 962 | } |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 963 | |
| 964 | /* Make the CRTC code factor in the SDVO pixel multiplier. The |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 965 | * SDVO device will factor out the multiplier during mode_set. |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 966 | */ |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 967 | multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode); |
| 968 | intel_mode_set_pixel_multiplier(adjusted_mode, multiplier); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 969 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 970 | return true; |
| 971 | } |
| 972 | |
| 973 | static void intel_sdvo_mode_set(struct drm_encoder *encoder, |
| 974 | struct drm_display_mode *mode, |
| 975 | struct drm_display_mode *adjusted_mode) |
| 976 | { |
| 977 | struct drm_device *dev = encoder->dev; |
| 978 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 979 | struct drm_crtc *crtc = encoder->crtc; |
| 980 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Chris Wilson | 890f335 | 2010-09-14 16:46:59 +0100 | [diff] [blame] | 981 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder); |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 982 | u32 sdvox; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 983 | struct intel_sdvo_in_out_map in_out; |
| 984 | struct intel_sdvo_dtd input_dtd; |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 985 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
| 986 | int rate; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 987 | |
| 988 | if (!mode) |
| 989 | return; |
| 990 | |
| 991 | /* First, set the input mapping for the first input to our controlled |
| 992 | * output. This is only correct if we're a single-input device, in |
| 993 | * which case the first input is the output from the appropriate SDVO |
| 994 | * channel on the motherboard. In a two-input device, the first input |
| 995 | * will be SDVOB and the second SDVOC. |
| 996 | */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 997 | in_out.in0 = intel_sdvo->attached_output; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 998 | in_out.in1 = 0; |
| 999 | |
Pavel Roskin | c74696b | 2010-09-02 14:46:34 -0400 | [diff] [blame] | 1000 | intel_sdvo_set_value(intel_sdvo, |
| 1001 | SDVO_CMD_SET_IN_OUT_MAP, |
| 1002 | &in_out, sizeof(in_out)); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1003 | |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1004 | /* Set the output timings to the screen */ |
| 1005 | if (!intel_sdvo_set_target_output(intel_sdvo, |
| 1006 | intel_sdvo->attached_output)) |
| 1007 | return; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1008 | |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1009 | /* We have tried to get input timing in mode_fixup, and filled into |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1010 | * adjusted_mode. |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1011 | */ |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1012 | if (intel_sdvo->is_tv || intel_sdvo->is_lvds) { |
| 1013 | input_dtd = intel_sdvo->input_dtd; |
| 1014 | } else { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1015 | /* Set the output timing to the screen */ |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1016 | if (!intel_sdvo_set_target_output(intel_sdvo, |
| 1017 | intel_sdvo->attached_output)) |
| 1018 | return; |
| 1019 | |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1020 | intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); |
Pavel Roskin | c74696b | 2010-09-02 14:46:34 -0400 | [diff] [blame] | 1021 | (void) intel_sdvo_set_output_timing(intel_sdvo, &input_dtd); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1022 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1023 | |
| 1024 | /* Set the input timing to the screen. Assume always input 0. */ |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1025 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
| 1026 | return; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1027 | |
Chris Wilson | 97aaf91 | 2011-01-04 20:10:52 +0000 | [diff] [blame] | 1028 | if (intel_sdvo->has_hdmi_monitor) { |
| 1029 | intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); |
| 1030 | intel_sdvo_set_colorimetry(intel_sdvo, |
| 1031 | SDVO_COLORIMETRY_RGB256); |
| 1032 | intel_sdvo_set_avi_infoframe(intel_sdvo); |
| 1033 | } else |
| 1034 | intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI); |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1035 | |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1036 | if (intel_sdvo->is_tv && |
| 1037 | !intel_sdvo_set_tv_format(intel_sdvo)) |
| 1038 | return; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1039 | |
Pavel Roskin | c74696b | 2010-09-02 14:46:34 -0400 | [diff] [blame] | 1040 | (void) intel_sdvo_set_input_timing(intel_sdvo, &input_dtd); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1041 | |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1042 | switch (pixel_multiplier) { |
| 1043 | default: |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1044 | case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; |
| 1045 | case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; |
| 1046 | case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1047 | } |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1048 | if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) |
| 1049 | return; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1050 | |
| 1051 | /* Set the SDVO control regs. */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1052 | if (INTEL_INFO(dev)->gen >= 4) { |
Chris Wilson | 6714afb | 2010-12-17 04:10:51 +0000 | [diff] [blame] | 1053 | sdvox = 0; |
| 1054 | if (INTEL_INFO(dev)->gen < 5) |
| 1055 | sdvox |= SDVO_BORDER_ENABLE; |
Adam Jackson | 81a14b4 | 2010-07-16 14:46:32 -0400 | [diff] [blame] | 1056 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 1057 | sdvox |= SDVO_VSYNC_ACTIVE_HIGH; |
| 1058 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 1059 | sdvox |= SDVO_HSYNC_ACTIVE_HIGH; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1060 | } else { |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1061 | sdvox = I915_READ(intel_sdvo->sdvo_reg); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1062 | switch (intel_sdvo->sdvo_reg) { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1063 | case SDVOB: |
| 1064 | sdvox &= SDVOB_PRESERVE_MASK; |
| 1065 | break; |
| 1066 | case SDVOC: |
| 1067 | sdvox &= SDVOC_PRESERVE_MASK; |
| 1068 | break; |
| 1069 | } |
| 1070 | sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; |
| 1071 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1072 | if (intel_crtc->pipe == 1) |
| 1073 | sdvox |= SDVO_PIPE_B_SELECT; |
Chris Wilson | da79de9 | 2010-11-22 11:12:46 +0000 | [diff] [blame] | 1074 | if (intel_sdvo->has_hdmi_audio) |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1075 | sdvox |= SDVO_AUDIO_ENABLE; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1076 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1077 | if (INTEL_INFO(dev)->gen >= 4) { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1078 | /* done in crtc_mode_set as the dpll_md reg must be written early */ |
| 1079 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
| 1080 | /* done in crtc_mode_set as it lives inside the dpll register */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1081 | } else { |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1082 | sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1083 | } |
| 1084 | |
Chris Wilson | 6714afb | 2010-12-17 04:10:51 +0000 | [diff] [blame] | 1085 | if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && |
| 1086 | INTEL_INFO(dev)->gen < 5) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1087 | sdvox |= SDVO_STALL_SELECT; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1088 | intel_sdvo_write_sdvox(intel_sdvo, sdvox); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1089 | } |
| 1090 | |
| 1091 | static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode) |
| 1092 | { |
| 1093 | struct drm_device *dev = encoder->dev; |
| 1094 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 890f335 | 2010-09-14 16:46:59 +0100 | [diff] [blame] | 1095 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder); |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 1096 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1097 | u32 temp; |
| 1098 | |
| 1099 | if (mode != DRM_MODE_DPMS_ON) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1100 | intel_sdvo_set_active_outputs(intel_sdvo, 0); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1101 | if (0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1102 | intel_sdvo_set_encoder_power_state(intel_sdvo, mode); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1103 | |
| 1104 | if (mode == DRM_MODE_DPMS_OFF) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1105 | temp = I915_READ(intel_sdvo->sdvo_reg); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1106 | if ((temp & SDVO_ENABLE) != 0) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1107 | intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1108 | } |
| 1109 | } |
| 1110 | } else { |
| 1111 | bool input1, input2; |
| 1112 | int i; |
| 1113 | u8 status; |
| 1114 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1115 | temp = I915_READ(intel_sdvo->sdvo_reg); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1116 | if ((temp & SDVO_ENABLE) == 0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1117 | intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1118 | for (i = 0; i < 2; i++) |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 1119 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1120 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1121 | status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1122 | /* Warn if the device reported failure to sync. |
| 1123 | * A lot of SDVO devices fail to notify of sync, but it's |
| 1124 | * a given it the status is a success, we succeeded. |
| 1125 | */ |
| 1126 | if (status == SDVO_CMD_STATUS_SUCCESS && !input1) { |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 1127 | DRM_DEBUG_KMS("First %s output reported failure to " |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1128 | "sync\n", SDVO_NAME(intel_sdvo)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1129 | } |
| 1130 | |
| 1131 | if (0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1132 | intel_sdvo_set_encoder_power_state(intel_sdvo, mode); |
| 1133 | intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1134 | } |
| 1135 | return; |
| 1136 | } |
| 1137 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1138 | static int intel_sdvo_mode_valid(struct drm_connector *connector, |
| 1139 | struct drm_display_mode *mode) |
| 1140 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1141 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1142 | |
| 1143 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 1144 | return MODE_NO_DBLESCAN; |
| 1145 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1146 | if (intel_sdvo->pixel_clock_min > mode->clock) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1147 | return MODE_CLOCK_LOW; |
| 1148 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1149 | if (intel_sdvo->pixel_clock_max < mode->clock) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1150 | return MODE_CLOCK_HIGH; |
| 1151 | |
Chris Wilson | 8545423 | 2010-08-08 14:28:23 +0100 | [diff] [blame] | 1152 | if (intel_sdvo->is_lvds) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1153 | if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1154 | return MODE_PANEL; |
| 1155 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1156 | if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1157 | return MODE_PANEL; |
| 1158 | } |
| 1159 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1160 | return MODE_OK; |
| 1161 | } |
| 1162 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1163 | static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1164 | { |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1165 | if (!intel_sdvo_get_value(intel_sdvo, |
| 1166 | SDVO_CMD_GET_DEVICE_CAPS, |
| 1167 | caps, sizeof(*caps))) |
| 1168 | return false; |
| 1169 | |
| 1170 | DRM_DEBUG_KMS("SDVO capabilities:\n" |
| 1171 | " vendor_id: %d\n" |
| 1172 | " device_id: %d\n" |
| 1173 | " device_rev_id: %d\n" |
| 1174 | " sdvo_version_major: %d\n" |
| 1175 | " sdvo_version_minor: %d\n" |
| 1176 | " sdvo_inputs_mask: %d\n" |
| 1177 | " smooth_scaling: %d\n" |
| 1178 | " sharp_scaling: %d\n" |
| 1179 | " up_scaling: %d\n" |
| 1180 | " down_scaling: %d\n" |
| 1181 | " stall_support: %d\n" |
| 1182 | " output_flags: %d\n", |
| 1183 | caps->vendor_id, |
| 1184 | caps->device_id, |
| 1185 | caps->device_rev_id, |
| 1186 | caps->sdvo_version_major, |
| 1187 | caps->sdvo_version_minor, |
| 1188 | caps->sdvo_inputs_mask, |
| 1189 | caps->smooth_scaling, |
| 1190 | caps->sharp_scaling, |
| 1191 | caps->up_scaling, |
| 1192 | caps->down_scaling, |
| 1193 | caps->stall_support, |
| 1194 | caps->output_flags); |
| 1195 | |
| 1196 | return true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1197 | } |
| 1198 | |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1199 | /* No use! */ |
| 1200 | #if 0 |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1201 | struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB) |
| 1202 | { |
| 1203 | struct drm_connector *connector = NULL; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1204 | struct intel_sdvo *iout = NULL; |
| 1205 | struct intel_sdvo *sdvo; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1206 | |
| 1207 | /* find the sdvo connector */ |
| 1208 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1209 | iout = to_intel_sdvo(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1210 | |
| 1211 | if (iout->type != INTEL_OUTPUT_SDVO) |
| 1212 | continue; |
| 1213 | |
| 1214 | sdvo = iout->dev_priv; |
| 1215 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1216 | if (sdvo->sdvo_reg == SDVOB && sdvoB) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1217 | return connector; |
| 1218 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1219 | if (sdvo->sdvo_reg == SDVOC && !sdvoB) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1220 | return connector; |
| 1221 | |
| 1222 | } |
| 1223 | |
| 1224 | return NULL; |
| 1225 | } |
| 1226 | |
| 1227 | int intel_sdvo_supports_hotplug(struct drm_connector *connector) |
| 1228 | { |
| 1229 | u8 response[2]; |
| 1230 | u8 status; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1231 | struct intel_sdvo *intel_sdvo; |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 1232 | DRM_DEBUG_KMS("\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1233 | |
| 1234 | if (!connector) |
| 1235 | return 0; |
| 1236 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1237 | intel_sdvo = to_intel_sdvo(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1238 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1239 | return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, |
| 1240 | &response, 2) && response[0]; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1241 | } |
| 1242 | |
| 1243 | void intel_sdvo_set_hotplug(struct drm_connector *connector, int on) |
| 1244 | { |
| 1245 | u8 response[2]; |
| 1246 | u8 status; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1247 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1248 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1249 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0); |
| 1250 | intel_sdvo_read_response(intel_sdvo, &response, 2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1251 | |
| 1252 | if (on) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1253 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0); |
| 1254 | status = intel_sdvo_read_response(intel_sdvo, &response, 2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1255 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1256 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1257 | } else { |
| 1258 | response[0] = 0; |
| 1259 | response[1] = 0; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1260 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1261 | } |
| 1262 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1263 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0); |
| 1264 | intel_sdvo_read_response(intel_sdvo, &response, 2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1265 | } |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1266 | #endif |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1267 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1268 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1269 | intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo) |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1270 | { |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1271 | int caps = 0; |
| 1272 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1273 | if (intel_sdvo->caps.output_flags & |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1274 | (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) |
| 1275 | caps++; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1276 | if (intel_sdvo->caps.output_flags & |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1277 | (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)) |
| 1278 | caps++; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1279 | if (intel_sdvo->caps.output_flags & |
Roel Kluin | 19e1f88 | 2009-08-09 13:50:53 +0200 | [diff] [blame] | 1280 | (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1)) |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1281 | caps++; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1282 | if (intel_sdvo->caps.output_flags & |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1283 | (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1)) |
| 1284 | caps++; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1285 | if (intel_sdvo->caps.output_flags & |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1286 | (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1)) |
| 1287 | caps++; |
| 1288 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1289 | if (intel_sdvo->caps.output_flags & |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1290 | (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1)) |
| 1291 | caps++; |
| 1292 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1293 | if (intel_sdvo->caps.output_flags & |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1294 | (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)) |
| 1295 | caps++; |
| 1296 | |
| 1297 | return (caps > 1); |
| 1298 | } |
| 1299 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1300 | static struct edid * |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1301 | intel_sdvo_get_edid(struct drm_connector *connector) |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1302 | { |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1303 | struct intel_sdvo *sdvo = intel_attached_sdvo(connector); |
| 1304 | return drm_get_edid(connector, &sdvo->ddc); |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1305 | } |
| 1306 | |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1307 | /* Mac mini hack -- use the same DDC as the analog connector */ |
| 1308 | static struct edid * |
| 1309 | intel_sdvo_get_analog_edid(struct drm_connector *connector) |
| 1310 | { |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1311 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1312 | |
Chris Wilson | 0c1dab8 | 2010-11-23 22:37:01 +0000 | [diff] [blame] | 1313 | return drm_get_edid(connector, |
| 1314 | &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter); |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1315 | } |
| 1316 | |
ling.ma@intel.com | 2b8d33f7 | 2009-07-29 11:31:18 +0800 | [diff] [blame] | 1317 | enum drm_connector_status |
Adam Jackson | 149c36a | 2010-04-29 14:05:18 -0400 | [diff] [blame] | 1318 | intel_sdvo_hdmi_sink_detect(struct drm_connector *connector) |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 1319 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1320 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1321 | enum drm_connector_status status; |
| 1322 | struct edid *edid; |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 1323 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1324 | edid = intel_sdvo_get_edid(connector); |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1325 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1326 | if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) { |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1327 | u8 ddc, saved_ddc = intel_sdvo->ddc_bus; |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1328 | |
Zhao Yakui | 7c3f0a2 | 2010-01-08 10:58:20 +0800 | [diff] [blame] | 1329 | /* |
| 1330 | * Don't use the 1 as the argument of DDC bus switch to get |
| 1331 | * the EDID. It is used for SDVO SPD ROM. |
| 1332 | */ |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1333 | for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) { |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1334 | intel_sdvo->ddc_bus = ddc; |
| 1335 | edid = intel_sdvo_get_edid(connector); |
| 1336 | if (edid) |
Zhao Yakui | 7c3f0a2 | 2010-01-08 10:58:20 +0800 | [diff] [blame] | 1337 | break; |
Zhao Yakui | 7c3f0a2 | 2010-01-08 10:58:20 +0800 | [diff] [blame] | 1338 | } |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1339 | /* |
| 1340 | * If we found the EDID on the other bus, |
| 1341 | * assume that is the correct DDC bus. |
| 1342 | */ |
| 1343 | if (edid == NULL) |
| 1344 | intel_sdvo->ddc_bus = saved_ddc; |
Zhao Yakui | 7c3f0a2 | 2010-01-08 10:58:20 +0800 | [diff] [blame] | 1345 | } |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1346 | |
| 1347 | /* |
| 1348 | * When there is no edid and no monitor is connected with VGA |
| 1349 | * port, try to use the CRT ddc to read the EDID for DVI-connector. |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1350 | */ |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1351 | if (edid == NULL) |
| 1352 | edid = intel_sdvo_get_analog_edid(connector); |
Adam Jackson | 149c36a | 2010-04-29 14:05:18 -0400 | [diff] [blame] | 1353 | |
Chris Wilson | 2f551c8 | 2010-09-15 10:42:50 +0100 | [diff] [blame] | 1354 | status = connector_status_unknown; |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 1355 | if (edid != NULL) { |
Adam Jackson | 149c36a | 2010-04-29 14:05:18 -0400 | [diff] [blame] | 1356 | /* DDC bus is shared, match EDID to connector type */ |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1357 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
| 1358 | status = connector_status_connected; |
Chris Wilson | da79de9 | 2010-11-22 11:12:46 +0000 | [diff] [blame] | 1359 | if (intel_sdvo->is_hdmi) { |
| 1360 | intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid); |
| 1361 | intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid); |
| 1362 | } |
Chris Wilson | 13946743 | 2011-02-09 20:01:16 +0000 | [diff] [blame^] | 1363 | } else |
| 1364 | status = connector_status_disconnected; |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1365 | connector->display_info.raw_edid = NULL; |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1366 | kfree(edid); |
| 1367 | } |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 1368 | |
| 1369 | if (status == connector_status_connected) { |
| 1370 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
| 1371 | if (intel_sdvo_connector->force_audio) |
Chris Wilson | da79de9 | 2010-11-22 11:12:46 +0000 | [diff] [blame] | 1372 | intel_sdvo->has_hdmi_audio = intel_sdvo_connector->force_audio > 0; |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 1373 | } |
| 1374 | |
ling.ma@intel.com | 2b8d33f7 | 2009-07-29 11:31:18 +0800 | [diff] [blame] | 1375 | return status; |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 1376 | } |
| 1377 | |
Chris Wilson | 7b334fc | 2010-09-09 23:51:02 +0100 | [diff] [blame] | 1378 | static enum drm_connector_status |
Chris Wilson | 930a9e2 | 2010-09-14 11:07:23 +0100 | [diff] [blame] | 1379 | intel_sdvo_detect(struct drm_connector *connector, bool force) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1380 | { |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1381 | uint16_t response; |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1382 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1383 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1384 | enum drm_connector_status ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1385 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1386 | if (!intel_sdvo_write_cmd(intel_sdvo, |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1387 | SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0)) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1388 | return connector_status_unknown; |
Chris Wilson | ba84cd1 | 2010-11-24 17:37:17 +0000 | [diff] [blame] | 1389 | |
| 1390 | /* add 30ms delay when the output type might be TV */ |
| 1391 | if (intel_sdvo->caps.output_flags & |
| 1392 | (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_CVBS0)) |
Zhao Yakui | d09c23d | 2009-11-06 15:39:56 +0800 | [diff] [blame] | 1393 | mdelay(30); |
Chris Wilson | ba84cd1 | 2010-11-24 17:37:17 +0000 | [diff] [blame] | 1394 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1395 | if (!intel_sdvo_read_response(intel_sdvo, &response, 2)) |
| 1396 | return connector_status_unknown; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1397 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1398 | DRM_DEBUG_KMS("SDVO response %d %d [%x]\n", |
| 1399 | response & 0xff, response >> 8, |
| 1400 | intel_sdvo_connector->output_flag); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1401 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1402 | if (response == 0) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1403 | return connector_status_disconnected; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1404 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1405 | intel_sdvo->attached_output = response; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1406 | |
Chris Wilson | 97aaf91 | 2011-01-04 20:10:52 +0000 | [diff] [blame] | 1407 | intel_sdvo->has_hdmi_monitor = false; |
| 1408 | intel_sdvo->has_hdmi_audio = false; |
| 1409 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1410 | if ((intel_sdvo_connector->output_flag & response) == 0) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1411 | ret = connector_status_disconnected; |
Chris Wilson | 13946743 | 2011-02-09 20:01:16 +0000 | [diff] [blame^] | 1412 | else if (IS_TMDS(intel_sdvo_connector)) |
Adam Jackson | 149c36a | 2010-04-29 14:05:18 -0400 | [diff] [blame] | 1413 | ret = intel_sdvo_hdmi_sink_detect(connector); |
Chris Wilson | 13946743 | 2011-02-09 20:01:16 +0000 | [diff] [blame^] | 1414 | else { |
| 1415 | struct edid *edid; |
| 1416 | |
| 1417 | /* if we have an edid check it matches the connection */ |
| 1418 | edid = intel_sdvo_get_edid(connector); |
| 1419 | if (edid == NULL) |
| 1420 | edid = intel_sdvo_get_analog_edid(connector); |
| 1421 | if (edid != NULL) { |
| 1422 | if (edid->input & DRM_EDID_INPUT_DIGITAL) |
| 1423 | ret = connector_status_disconnected; |
| 1424 | else |
| 1425 | ret = connector_status_connected; |
| 1426 | connector->display_info.raw_edid = NULL; |
| 1427 | kfree(edid); |
| 1428 | } else |
| 1429 | ret = connector_status_connected; |
| 1430 | } |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1431 | |
| 1432 | /* May update encoder flag for like clock for SDVO TV, etc.*/ |
| 1433 | if (ret == connector_status_connected) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1434 | intel_sdvo->is_tv = false; |
| 1435 | intel_sdvo->is_lvds = false; |
| 1436 | intel_sdvo->base.needs_tv_clock = false; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1437 | |
| 1438 | if (response & SDVO_TV_MASK) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1439 | intel_sdvo->is_tv = true; |
| 1440 | intel_sdvo->base.needs_tv_clock = true; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1441 | } |
| 1442 | if (response & SDVO_LVDS_MASK) |
Chris Wilson | 8545423 | 2010-08-08 14:28:23 +0100 | [diff] [blame] | 1443 | intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1444 | } |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1445 | |
| 1446 | return ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1447 | } |
| 1448 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1449 | static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1450 | { |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1451 | struct edid *edid; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1452 | |
| 1453 | /* set the bus switch and get the modes */ |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1454 | edid = intel_sdvo_get_edid(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1455 | |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1456 | /* |
| 1457 | * Mac mini hack. On this device, the DVI-I connector shares one DDC |
| 1458 | * link between analog and digital outputs. So, if the regular SDVO |
| 1459 | * DDC fails, check to see if the analog output is disconnected, in |
| 1460 | * which case we'll look there for the digital DDC data. |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1461 | */ |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1462 | if (edid == NULL) |
| 1463 | edid = intel_sdvo_get_analog_edid(connector); |
| 1464 | |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1465 | if (edid != NULL) { |
Chris Wilson | 13946743 | 2011-02-09 20:01:16 +0000 | [diff] [blame^] | 1466 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
| 1467 | bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); |
| 1468 | bool connector_is_digital = !!IS_TMDS(intel_sdvo_connector); |
| 1469 | |
| 1470 | if (connector_is_digital == monitor_is_digital) { |
Chris Wilson | 0c1dab8 | 2010-11-23 22:37:01 +0000 | [diff] [blame] | 1471 | drm_mode_connector_update_edid_property(connector, edid); |
| 1472 | drm_add_edid_modes(connector, edid); |
| 1473 | } |
Chris Wilson | 13946743 | 2011-02-09 20:01:16 +0000 | [diff] [blame^] | 1474 | |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1475 | connector->display_info.raw_edid = NULL; |
| 1476 | kfree(edid); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1477 | } |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1478 | } |
| 1479 | |
| 1480 | /* |
| 1481 | * Set of SDVO TV modes. |
| 1482 | * Note! This is in reply order (see loop in get_tv_modes). |
| 1483 | * XXX: all 60Hz refresh? |
| 1484 | */ |
| 1485 | struct drm_display_mode sdvo_tv_modes[] = { |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1486 | { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, |
| 1487 | 416, 0, 200, 201, 232, 233, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1488 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1489 | { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, |
| 1490 | 416, 0, 240, 241, 272, 273, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1491 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1492 | { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, |
| 1493 | 496, 0, 300, 301, 332, 333, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1494 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1495 | { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, |
| 1496 | 736, 0, 350, 351, 382, 383, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1497 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1498 | { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, |
| 1499 | 736, 0, 400, 401, 432, 433, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1500 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1501 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, |
| 1502 | 736, 0, 480, 481, 512, 513, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1503 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1504 | { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, |
| 1505 | 800, 0, 480, 481, 512, 513, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1506 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1507 | { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, |
| 1508 | 800, 0, 576, 577, 608, 609, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1509 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1510 | { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, |
| 1511 | 816, 0, 350, 351, 382, 383, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1512 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1513 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, |
| 1514 | 816, 0, 400, 401, 432, 433, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1515 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1516 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, |
| 1517 | 816, 0, 480, 481, 512, 513, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1518 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1519 | { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, |
| 1520 | 816, 0, 540, 541, 572, 573, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1521 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1522 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, |
| 1523 | 816, 0, 576, 577, 608, 609, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1524 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1525 | { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, |
| 1526 | 864, 0, 576, 577, 608, 609, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1527 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1528 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, |
| 1529 | 896, 0, 600, 601, 632, 633, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1530 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1531 | { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, |
| 1532 | 928, 0, 624, 625, 656, 657, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1533 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1534 | { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, |
| 1535 | 1016, 0, 766, 767, 798, 799, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1536 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1537 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, |
| 1538 | 1120, 0, 768, 769, 800, 801, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1539 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1540 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, |
| 1541 | 1376, 0, 1024, 1025, 1056, 1057, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1542 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
| 1543 | }; |
| 1544 | |
| 1545 | static void intel_sdvo_get_tv_modes(struct drm_connector *connector) |
| 1546 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1547 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1548 | struct intel_sdvo_sdtv_resolution_request tv_res; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1549 | uint32_t reply = 0, format_map = 0; |
| 1550 | int i; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1551 | |
| 1552 | /* Read the list of supported input resolutions for the selected TV |
| 1553 | * format. |
| 1554 | */ |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 1555 | format_map = 1 << intel_sdvo->tv_format_index; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1556 | memcpy(&tv_res, &format_map, |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1557 | min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1558 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1559 | if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output)) |
| 1560 | return; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1561 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1562 | BUILD_BUG_ON(sizeof(tv_res) != 3); |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1563 | if (!intel_sdvo_write_cmd(intel_sdvo, |
| 1564 | SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1565 | &tv_res, sizeof(tv_res))) |
| 1566 | return; |
| 1567 | if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1568 | return; |
| 1569 | |
| 1570 | for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1571 | if (reply & (1 << i)) { |
| 1572 | struct drm_display_mode *nmode; |
| 1573 | nmode = drm_mode_duplicate(connector->dev, |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1574 | &sdvo_tv_modes[i]); |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1575 | if (nmode) |
| 1576 | drm_mode_probed_add(connector, nmode); |
| 1577 | } |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1578 | } |
| 1579 | |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1580 | static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) |
| 1581 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1582 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1583 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1584 | struct drm_display_mode *newmode; |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1585 | |
| 1586 | /* |
| 1587 | * Attempt to get the mode list from DDC. |
| 1588 | * Assume that the preferred modes are |
| 1589 | * arranged in priority order. |
| 1590 | */ |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1591 | intel_ddc_get_modes(connector, intel_sdvo->i2c); |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1592 | if (list_empty(&connector->probed_modes) == false) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1593 | goto end; |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1594 | |
| 1595 | /* Fetch modes from VBT */ |
| 1596 | if (dev_priv->sdvo_lvds_vbt_mode != NULL) { |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1597 | newmode = drm_mode_duplicate(connector->dev, |
| 1598 | dev_priv->sdvo_lvds_vbt_mode); |
| 1599 | if (newmode != NULL) { |
| 1600 | /* Guarantee the mode is preferred */ |
| 1601 | newmode->type = (DRM_MODE_TYPE_PREFERRED | |
| 1602 | DRM_MODE_TYPE_DRIVER); |
| 1603 | drm_mode_probed_add(connector, newmode); |
| 1604 | } |
| 1605 | } |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1606 | |
| 1607 | end: |
| 1608 | list_for_each_entry(newmode, &connector->probed_modes, head) { |
| 1609 | if (newmode->type & DRM_MODE_TYPE_PREFERRED) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1610 | intel_sdvo->sdvo_lvds_fixed_mode = |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1611 | drm_mode_duplicate(connector->dev, newmode); |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1612 | |
| 1613 | drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode, |
| 1614 | 0); |
| 1615 | |
Chris Wilson | 8545423 | 2010-08-08 14:28:23 +0100 | [diff] [blame] | 1616 | intel_sdvo->is_lvds = true; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1617 | break; |
| 1618 | } |
| 1619 | } |
| 1620 | |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1621 | } |
| 1622 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1623 | static int intel_sdvo_get_modes(struct drm_connector *connector) |
| 1624 | { |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1625 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1626 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1627 | if (IS_TV(intel_sdvo_connector)) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1628 | intel_sdvo_get_tv_modes(connector); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1629 | else if (IS_LVDS(intel_sdvo_connector)) |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1630 | intel_sdvo_get_lvds_modes(connector); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1631 | else |
| 1632 | intel_sdvo_get_ddc_modes(connector); |
| 1633 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1634 | return !list_empty(&connector->probed_modes); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1635 | } |
| 1636 | |
Chris Wilson | fcc8d67 | 2010-08-04 13:50:27 +0100 | [diff] [blame] | 1637 | static void |
| 1638 | intel_sdvo_destroy_enhance_property(struct drm_connector *connector) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1639 | { |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1640 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1641 | struct drm_device *dev = connector->dev; |
| 1642 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1643 | if (intel_sdvo_connector->left) |
| 1644 | drm_property_destroy(dev, intel_sdvo_connector->left); |
| 1645 | if (intel_sdvo_connector->right) |
| 1646 | drm_property_destroy(dev, intel_sdvo_connector->right); |
| 1647 | if (intel_sdvo_connector->top) |
| 1648 | drm_property_destroy(dev, intel_sdvo_connector->top); |
| 1649 | if (intel_sdvo_connector->bottom) |
| 1650 | drm_property_destroy(dev, intel_sdvo_connector->bottom); |
| 1651 | if (intel_sdvo_connector->hpos) |
| 1652 | drm_property_destroy(dev, intel_sdvo_connector->hpos); |
| 1653 | if (intel_sdvo_connector->vpos) |
| 1654 | drm_property_destroy(dev, intel_sdvo_connector->vpos); |
| 1655 | if (intel_sdvo_connector->saturation) |
| 1656 | drm_property_destroy(dev, intel_sdvo_connector->saturation); |
| 1657 | if (intel_sdvo_connector->contrast) |
| 1658 | drm_property_destroy(dev, intel_sdvo_connector->contrast); |
| 1659 | if (intel_sdvo_connector->hue) |
| 1660 | drm_property_destroy(dev, intel_sdvo_connector->hue); |
| 1661 | if (intel_sdvo_connector->sharpness) |
| 1662 | drm_property_destroy(dev, intel_sdvo_connector->sharpness); |
| 1663 | if (intel_sdvo_connector->flicker_filter) |
| 1664 | drm_property_destroy(dev, intel_sdvo_connector->flicker_filter); |
| 1665 | if (intel_sdvo_connector->flicker_filter_2d) |
| 1666 | drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d); |
| 1667 | if (intel_sdvo_connector->flicker_filter_adaptive) |
| 1668 | drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive); |
| 1669 | if (intel_sdvo_connector->tv_luma_filter) |
| 1670 | drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter); |
| 1671 | if (intel_sdvo_connector->tv_chroma_filter) |
| 1672 | drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter); |
Chris Wilson | e044218 | 2010-08-04 13:50:29 +0100 | [diff] [blame] | 1673 | if (intel_sdvo_connector->dot_crawl) |
| 1674 | drm_property_destroy(dev, intel_sdvo_connector->dot_crawl); |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1675 | if (intel_sdvo_connector->brightness) |
| 1676 | drm_property_destroy(dev, intel_sdvo_connector->brightness); |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1677 | } |
| 1678 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1679 | static void intel_sdvo_destroy(struct drm_connector *connector) |
| 1680 | { |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1681 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1682 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1683 | if (intel_sdvo_connector->tv_format) |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1684 | drm_property_destroy(connector->dev, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1685 | intel_sdvo_connector->tv_format); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1686 | |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1687 | intel_sdvo_destroy_enhance_property(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1688 | drm_sysfs_connector_remove(connector); |
| 1689 | drm_connector_cleanup(connector); |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1690 | kfree(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1691 | } |
| 1692 | |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1693 | static int |
| 1694 | intel_sdvo_set_property(struct drm_connector *connector, |
| 1695 | struct drm_property *property, |
| 1696 | uint64_t val) |
| 1697 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1698 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1699 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1700 | uint16_t temp_value; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1701 | uint8_t cmd; |
| 1702 | int ret; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1703 | |
| 1704 | ret = drm_connector_property_set_value(connector, property, val); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1705 | if (ret) |
| 1706 | return ret; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1707 | |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 1708 | if (property == intel_sdvo_connector->force_audio_property) { |
| 1709 | if (val == intel_sdvo_connector->force_audio) |
| 1710 | return 0; |
| 1711 | |
| 1712 | intel_sdvo_connector->force_audio = val; |
| 1713 | |
Chris Wilson | da79de9 | 2010-11-22 11:12:46 +0000 | [diff] [blame] | 1714 | if (val > 0 && intel_sdvo->has_hdmi_audio) |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 1715 | return 0; |
Chris Wilson | da79de9 | 2010-11-22 11:12:46 +0000 | [diff] [blame] | 1716 | if (val < 0 && !intel_sdvo->has_hdmi_audio) |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 1717 | return 0; |
| 1718 | |
Chris Wilson | da79de9 | 2010-11-22 11:12:46 +0000 | [diff] [blame] | 1719 | intel_sdvo->has_hdmi_audio = val > 0; |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 1720 | goto done; |
| 1721 | } |
| 1722 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1723 | #define CHECK_PROPERTY(name, NAME) \ |
| 1724 | if (intel_sdvo_connector->name == property) { \ |
| 1725 | if (intel_sdvo_connector->cur_##name == temp_value) return 0; \ |
| 1726 | if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \ |
| 1727 | cmd = SDVO_CMD_SET_##NAME; \ |
| 1728 | intel_sdvo_connector->cur_##name = temp_value; \ |
| 1729 | goto set_value; \ |
| 1730 | } |
| 1731 | |
| 1732 | if (property == intel_sdvo_connector->tv_format) { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1733 | if (val >= TV_FORMAT_NUM) |
| 1734 | return -EINVAL; |
| 1735 | |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 1736 | if (intel_sdvo->tv_format_index == |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1737 | intel_sdvo_connector->tv_format_supported[val]) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1738 | return 0; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1739 | |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 1740 | intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val]; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1741 | goto done; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1742 | } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1743 | temp_value = val; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1744 | if (intel_sdvo_connector->left == property) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1745 | drm_connector_property_set_value(connector, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1746 | intel_sdvo_connector->right, val); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1747 | if (intel_sdvo_connector->left_margin == temp_value) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1748 | return 0; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1749 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1750 | intel_sdvo_connector->left_margin = temp_value; |
| 1751 | intel_sdvo_connector->right_margin = temp_value; |
| 1752 | temp_value = intel_sdvo_connector->max_hscan - |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1753 | intel_sdvo_connector->left_margin; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1754 | cmd = SDVO_CMD_SET_OVERSCAN_H; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1755 | goto set_value; |
| 1756 | } else if (intel_sdvo_connector->right == property) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1757 | drm_connector_property_set_value(connector, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1758 | intel_sdvo_connector->left, val); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1759 | if (intel_sdvo_connector->right_margin == temp_value) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1760 | return 0; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1761 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1762 | intel_sdvo_connector->left_margin = temp_value; |
| 1763 | intel_sdvo_connector->right_margin = temp_value; |
| 1764 | temp_value = intel_sdvo_connector->max_hscan - |
| 1765 | intel_sdvo_connector->left_margin; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1766 | cmd = SDVO_CMD_SET_OVERSCAN_H; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1767 | goto set_value; |
| 1768 | } else if (intel_sdvo_connector->top == property) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1769 | drm_connector_property_set_value(connector, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1770 | intel_sdvo_connector->bottom, val); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1771 | if (intel_sdvo_connector->top_margin == temp_value) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1772 | return 0; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1773 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1774 | intel_sdvo_connector->top_margin = temp_value; |
| 1775 | intel_sdvo_connector->bottom_margin = temp_value; |
| 1776 | temp_value = intel_sdvo_connector->max_vscan - |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1777 | intel_sdvo_connector->top_margin; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1778 | cmd = SDVO_CMD_SET_OVERSCAN_V; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1779 | goto set_value; |
| 1780 | } else if (intel_sdvo_connector->bottom == property) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1781 | drm_connector_property_set_value(connector, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1782 | intel_sdvo_connector->top, val); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1783 | if (intel_sdvo_connector->bottom_margin == temp_value) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1784 | return 0; |
| 1785 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1786 | intel_sdvo_connector->top_margin = temp_value; |
| 1787 | intel_sdvo_connector->bottom_margin = temp_value; |
| 1788 | temp_value = intel_sdvo_connector->max_vscan - |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1789 | intel_sdvo_connector->top_margin; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1790 | cmd = SDVO_CMD_SET_OVERSCAN_V; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1791 | goto set_value; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1792 | } |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1793 | CHECK_PROPERTY(hpos, HPOS) |
| 1794 | CHECK_PROPERTY(vpos, VPOS) |
| 1795 | CHECK_PROPERTY(saturation, SATURATION) |
| 1796 | CHECK_PROPERTY(contrast, CONTRAST) |
| 1797 | CHECK_PROPERTY(hue, HUE) |
| 1798 | CHECK_PROPERTY(brightness, BRIGHTNESS) |
| 1799 | CHECK_PROPERTY(sharpness, SHARPNESS) |
| 1800 | CHECK_PROPERTY(flicker_filter, FLICKER_FILTER) |
| 1801 | CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D) |
| 1802 | CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE) |
| 1803 | CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER) |
| 1804 | CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER) |
Chris Wilson | e044218 | 2010-08-04 13:50:29 +0100 | [diff] [blame] | 1805 | CHECK_PROPERTY(dot_crawl, DOT_CRAWL) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1806 | } |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1807 | |
| 1808 | return -EINVAL; /* unknown property */ |
| 1809 | |
| 1810 | set_value: |
| 1811 | if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2)) |
| 1812 | return -EIO; |
| 1813 | |
| 1814 | |
| 1815 | done: |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1816 | if (intel_sdvo->base.base.crtc) { |
| 1817 | struct drm_crtc *crtc = intel_sdvo->base.base.crtc; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1818 | drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1819 | crtc->y, crtc->fb); |
| 1820 | } |
| 1821 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1822 | return 0; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1823 | #undef CHECK_PROPERTY |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1824 | } |
| 1825 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1826 | static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = { |
| 1827 | .dpms = intel_sdvo_dpms, |
| 1828 | .mode_fixup = intel_sdvo_mode_fixup, |
| 1829 | .prepare = intel_encoder_prepare, |
| 1830 | .mode_set = intel_sdvo_mode_set, |
| 1831 | .commit = intel_encoder_commit, |
| 1832 | }; |
| 1833 | |
| 1834 | static const struct drm_connector_funcs intel_sdvo_connector_funcs = { |
Keith Packard | c9fb15f | 2009-05-30 20:42:28 -0700 | [diff] [blame] | 1835 | .dpms = drm_helper_connector_dpms, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1836 | .detect = intel_sdvo_detect, |
| 1837 | .fill_modes = drm_helper_probe_single_connector_modes, |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1838 | .set_property = intel_sdvo_set_property, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1839 | .destroy = intel_sdvo_destroy, |
| 1840 | }; |
| 1841 | |
| 1842 | static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { |
| 1843 | .get_modes = intel_sdvo_get_modes, |
| 1844 | .mode_valid = intel_sdvo_mode_valid, |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1845 | .best_encoder = intel_best_encoder, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1846 | }; |
| 1847 | |
Hannes Eder | b358d0a | 2008-12-18 21:18:47 +0100 | [diff] [blame] | 1848 | static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1849 | { |
Chris Wilson | 890f335 | 2010-09-14 16:46:59 +0100 | [diff] [blame] | 1850 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder); |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1851 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1852 | if (intel_sdvo->sdvo_lvds_fixed_mode != NULL) |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1853 | drm_mode_destroy(encoder->dev, |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1854 | intel_sdvo->sdvo_lvds_fixed_mode); |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1855 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1856 | i2c_del_adapter(&intel_sdvo->ddc); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1857 | intel_encoder_destroy(encoder); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1858 | } |
| 1859 | |
| 1860 | static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { |
| 1861 | .destroy = intel_sdvo_enc_destroy, |
| 1862 | }; |
| 1863 | |
Chris Wilson | b66d842 | 2010-08-12 15:26:41 +0100 | [diff] [blame] | 1864 | static void |
| 1865 | intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo) |
| 1866 | { |
| 1867 | uint16_t mask = 0; |
| 1868 | unsigned int num_bits; |
| 1869 | |
| 1870 | /* Make a mask of outputs less than or equal to our own priority in the |
| 1871 | * list. |
| 1872 | */ |
| 1873 | switch (sdvo->controlled_output) { |
| 1874 | case SDVO_OUTPUT_LVDS1: |
| 1875 | mask |= SDVO_OUTPUT_LVDS1; |
| 1876 | case SDVO_OUTPUT_LVDS0: |
| 1877 | mask |= SDVO_OUTPUT_LVDS0; |
| 1878 | case SDVO_OUTPUT_TMDS1: |
| 1879 | mask |= SDVO_OUTPUT_TMDS1; |
| 1880 | case SDVO_OUTPUT_TMDS0: |
| 1881 | mask |= SDVO_OUTPUT_TMDS0; |
| 1882 | case SDVO_OUTPUT_RGB1: |
| 1883 | mask |= SDVO_OUTPUT_RGB1; |
| 1884 | case SDVO_OUTPUT_RGB0: |
| 1885 | mask |= SDVO_OUTPUT_RGB0; |
| 1886 | break; |
| 1887 | } |
| 1888 | |
| 1889 | /* Count bits to find what number we are in the priority list. */ |
| 1890 | mask &= sdvo->caps.output_flags; |
| 1891 | num_bits = hweight16(mask); |
| 1892 | /* If more than 3 outputs, default to DDC bus 3 for now. */ |
| 1893 | if (num_bits > 3) |
| 1894 | num_bits = 3; |
| 1895 | |
| 1896 | /* Corresponds to SDVO_CONTROL_BUS_DDCx */ |
| 1897 | sdvo->ddc_bus = 1 << num_bits; |
| 1898 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1899 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1900 | /** |
| 1901 | * Choose the appropriate DDC bus for control bus switch command for this |
| 1902 | * SDVO output based on the controlled output. |
| 1903 | * |
| 1904 | * DDC bus number assignment is in a priority order of RGB outputs, then TMDS |
| 1905 | * outputs, then LVDS outputs. |
| 1906 | */ |
| 1907 | static void |
Adam Jackson | b108333 | 2010-04-23 16:07:40 -0400 | [diff] [blame] | 1908 | intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1909 | struct intel_sdvo *sdvo, u32 reg) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1910 | { |
Adam Jackson | b108333 | 2010-04-23 16:07:40 -0400 | [diff] [blame] | 1911 | struct sdvo_device_mapping *mapping; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1912 | |
Adam Jackson | b108333 | 2010-04-23 16:07:40 -0400 | [diff] [blame] | 1913 | if (IS_SDVOB(reg)) |
| 1914 | mapping = &(dev_priv->sdvo_mappings[0]); |
| 1915 | else |
| 1916 | mapping = &(dev_priv->sdvo_mappings[1]); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1917 | |
Chris Wilson | b66d842 | 2010-08-12 15:26:41 +0100 | [diff] [blame] | 1918 | if (mapping->initialized) |
| 1919 | sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); |
| 1920 | else |
| 1921 | intel_sdvo_guess_ddc_bus(sdvo); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1922 | } |
| 1923 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1924 | static void |
| 1925 | intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv, |
| 1926 | struct intel_sdvo *sdvo, u32 reg) |
| 1927 | { |
| 1928 | struct sdvo_device_mapping *mapping; |
| 1929 | u8 pin, speed; |
| 1930 | |
| 1931 | if (IS_SDVOB(reg)) |
| 1932 | mapping = &dev_priv->sdvo_mappings[0]; |
| 1933 | else |
| 1934 | mapping = &dev_priv->sdvo_mappings[1]; |
| 1935 | |
| 1936 | pin = GMBUS_PORT_DPB; |
| 1937 | speed = GMBUS_RATE_1MHZ >> 8; |
| 1938 | if (mapping->initialized) { |
| 1939 | pin = mapping->i2c_pin; |
| 1940 | speed = mapping->i2c_speed; |
| 1941 | } |
| 1942 | |
Chris Wilson | 63abf3e | 2010-12-08 16:48:21 +0000 | [diff] [blame] | 1943 | if (pin < GMBUS_NUM_PORTS) { |
| 1944 | sdvo->i2c = &dev_priv->gmbus[pin].adapter; |
| 1945 | intel_gmbus_set_speed(sdvo->i2c, speed); |
| 1946 | intel_gmbus_force_bit(sdvo->i2c, true); |
| 1947 | } else |
| 1948 | sdvo->i2c = &dev_priv->gmbus[GMBUS_PORT_DPB].adapter; |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1949 | } |
| 1950 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1951 | static bool |
Chris Wilson | e27d853 | 2010-10-22 09:15:22 +0100 | [diff] [blame] | 1952 | intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1953 | { |
Chris Wilson | 97aaf91 | 2011-01-04 20:10:52 +0000 | [diff] [blame] | 1954 | return intel_sdvo_check_supp_encode(intel_sdvo); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1955 | } |
| 1956 | |
yakui_zhao | 714605e | 2009-05-31 17:18:07 +0800 | [diff] [blame] | 1957 | static u8 |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1958 | intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg) |
yakui_zhao | 714605e | 2009-05-31 17:18:07 +0800 | [diff] [blame] | 1959 | { |
| 1960 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1961 | struct sdvo_device_mapping *my_mapping, *other_mapping; |
| 1962 | |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 1963 | if (IS_SDVOB(sdvo_reg)) { |
yakui_zhao | 714605e | 2009-05-31 17:18:07 +0800 | [diff] [blame] | 1964 | my_mapping = &dev_priv->sdvo_mappings[0]; |
| 1965 | other_mapping = &dev_priv->sdvo_mappings[1]; |
| 1966 | } else { |
| 1967 | my_mapping = &dev_priv->sdvo_mappings[1]; |
| 1968 | other_mapping = &dev_priv->sdvo_mappings[0]; |
| 1969 | } |
| 1970 | |
| 1971 | /* If the BIOS described our SDVO device, take advantage of it. */ |
| 1972 | if (my_mapping->slave_addr) |
| 1973 | return my_mapping->slave_addr; |
| 1974 | |
| 1975 | /* If the BIOS only described a different SDVO device, use the |
| 1976 | * address that it isn't using. |
| 1977 | */ |
| 1978 | if (other_mapping->slave_addr) { |
| 1979 | if (other_mapping->slave_addr == 0x70) |
| 1980 | return 0x72; |
| 1981 | else |
| 1982 | return 0x70; |
| 1983 | } |
| 1984 | |
| 1985 | /* No SDVO device info is found for another DVO port, |
| 1986 | * so use mapping assumption we had before BIOS parsing. |
| 1987 | */ |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 1988 | if (IS_SDVOB(sdvo_reg)) |
yakui_zhao | 714605e | 2009-05-31 17:18:07 +0800 | [diff] [blame] | 1989 | return 0x70; |
| 1990 | else |
| 1991 | return 0x72; |
| 1992 | } |
| 1993 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1994 | static void |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1995 | intel_sdvo_connector_init(struct intel_sdvo_connector *connector, |
| 1996 | struct intel_sdvo *encoder) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1997 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1998 | drm_connector_init(encoder->base.base.dev, |
| 1999 | &connector->base.base, |
| 2000 | &intel_sdvo_connector_funcs, |
| 2001 | connector->base.base.connector_type); |
Zhao Yakui | 6070a4a | 2010-02-08 21:35:12 +0800 | [diff] [blame] | 2002 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2003 | drm_connector_helper_add(&connector->base.base, |
| 2004 | &intel_sdvo_connector_helper_funcs); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2005 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2006 | connector->base.base.interlace_allowed = 0; |
| 2007 | connector->base.base.doublescan_allowed = 0; |
| 2008 | connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2009 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2010 | intel_connector_attach_encoder(&connector->base, &encoder->base); |
| 2011 | drm_sysfs_connector_add(&connector->base.base); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2012 | } |
| 2013 | |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2014 | static void |
| 2015 | intel_sdvo_add_hdmi_properties(struct intel_sdvo_connector *connector) |
| 2016 | { |
| 2017 | struct drm_device *dev = connector->base.base.dev; |
| 2018 | |
| 2019 | connector->force_audio_property = |
| 2020 | drm_property_create(dev, DRM_MODE_PROP_RANGE, "force_audio", 2); |
| 2021 | if (connector->force_audio_property) { |
| 2022 | connector->force_audio_property->values[0] = -1; |
| 2023 | connector->force_audio_property->values[1] = 1; |
| 2024 | drm_connector_attach_property(&connector->base.base, |
| 2025 | connector->force_audio_property, 0); |
| 2026 | } |
| 2027 | } |
| 2028 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2029 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2030 | intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2031 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2032 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2033 | struct drm_connector *connector; |
| 2034 | struct intel_connector *intel_connector; |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2035 | struct intel_sdvo_connector *intel_sdvo_connector; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2036 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2037 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); |
| 2038 | if (!intel_sdvo_connector) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2039 | return false; |
| 2040 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2041 | if (device == 0) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2042 | intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0; |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2043 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2044 | } else if (device == 1) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2045 | intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1; |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2046 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2047 | } |
| 2048 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2049 | intel_connector = &intel_sdvo_connector->base; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2050 | connector = &intel_connector->base; |
Dave Airlie | eb1f8e4 | 2010-05-07 06:42:51 +0000 | [diff] [blame] | 2051 | connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2052 | encoder->encoder_type = DRM_MODE_ENCODER_TMDS; |
| 2053 | connector->connector_type = DRM_MODE_CONNECTOR_DVID; |
| 2054 | |
Chris Wilson | e27d853 | 2010-10-22 09:15:22 +0100 | [diff] [blame] | 2055 | if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) { |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2056 | connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; |
Chris Wilson | e27d853 | 2010-10-22 09:15:22 +0100 | [diff] [blame] | 2057 | intel_sdvo->is_hdmi = true; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2058 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2059 | intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) | |
| 2060 | (1 << INTEL_ANALOG_CLONE_BIT)); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2061 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2062 | intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); |
Chris Wilson | f797d22 | 2010-12-23 09:43:48 +0000 | [diff] [blame] | 2063 | if (intel_sdvo->is_hdmi) |
| 2064 | intel_sdvo_add_hdmi_properties(intel_sdvo_connector); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2065 | |
| 2066 | return true; |
| 2067 | } |
| 2068 | |
| 2069 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2070 | intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2071 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2072 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
| 2073 | struct drm_connector *connector; |
| 2074 | struct intel_connector *intel_connector; |
| 2075 | struct intel_sdvo_connector *intel_sdvo_connector; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2076 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2077 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); |
| 2078 | if (!intel_sdvo_connector) |
| 2079 | return false; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2080 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2081 | intel_connector = &intel_sdvo_connector->base; |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2082 | connector = &intel_connector->base; |
| 2083 | encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; |
| 2084 | connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2085 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2086 | intel_sdvo->controlled_output |= type; |
| 2087 | intel_sdvo_connector->output_flag = type; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2088 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2089 | intel_sdvo->is_tv = true; |
| 2090 | intel_sdvo->base.needs_tv_clock = true; |
| 2091 | intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2092 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2093 | intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2094 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2095 | if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2096 | goto err; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2097 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2098 | if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2099 | goto err; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2100 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2101 | return true; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2102 | |
| 2103 | err: |
Chris Wilson | 123d5c0 | 2010-09-23 16:15:21 +0100 | [diff] [blame] | 2104 | intel_sdvo_destroy(connector); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2105 | return false; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2106 | } |
| 2107 | |
| 2108 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2109 | intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2110 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2111 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
| 2112 | struct drm_connector *connector; |
| 2113 | struct intel_connector *intel_connector; |
| 2114 | struct intel_sdvo_connector *intel_sdvo_connector; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2115 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2116 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); |
| 2117 | if (!intel_sdvo_connector) |
| 2118 | return false; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2119 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2120 | intel_connector = &intel_sdvo_connector->base; |
| 2121 | connector = &intel_connector->base; |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2122 | connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
| 2123 | encoder->encoder_type = DRM_MODE_ENCODER_DAC; |
| 2124 | connector->connector_type = DRM_MODE_CONNECTOR_VGA; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2125 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2126 | if (device == 0) { |
| 2127 | intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0; |
| 2128 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0; |
| 2129 | } else if (device == 1) { |
| 2130 | intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1; |
| 2131 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; |
| 2132 | } |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2133 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2134 | intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) | |
| 2135 | (1 << INTEL_ANALOG_CLONE_BIT)); |
| 2136 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2137 | intel_sdvo_connector_init(intel_sdvo_connector, |
| 2138 | intel_sdvo); |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2139 | return true; |
| 2140 | } |
| 2141 | |
| 2142 | static bool |
| 2143 | intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device) |
| 2144 | { |
| 2145 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
| 2146 | struct drm_connector *connector; |
| 2147 | struct intel_connector *intel_connector; |
| 2148 | struct intel_sdvo_connector *intel_sdvo_connector; |
| 2149 | |
| 2150 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); |
| 2151 | if (!intel_sdvo_connector) |
| 2152 | return false; |
| 2153 | |
| 2154 | intel_connector = &intel_sdvo_connector->base; |
| 2155 | connector = &intel_connector->base; |
| 2156 | encoder->encoder_type = DRM_MODE_ENCODER_LVDS; |
| 2157 | connector->connector_type = DRM_MODE_CONNECTOR_LVDS; |
| 2158 | |
| 2159 | if (device == 0) { |
| 2160 | intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0; |
| 2161 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0; |
| 2162 | } else if (device == 1) { |
| 2163 | intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1; |
| 2164 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; |
| 2165 | } |
| 2166 | |
| 2167 | intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2168 | (1 << INTEL_SDVO_LVDS_CLONE_BIT)); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2169 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2170 | intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2171 | if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2172 | goto err; |
| 2173 | |
| 2174 | return true; |
| 2175 | |
| 2176 | err: |
Chris Wilson | 123d5c0 | 2010-09-23 16:15:21 +0100 | [diff] [blame] | 2177 | intel_sdvo_destroy(connector); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2178 | return false; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2179 | } |
Zhao Yakui | 6070a4a | 2010-02-08 21:35:12 +0800 | [diff] [blame] | 2180 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2181 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2182 | intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags) |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2183 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2184 | intel_sdvo->is_tv = false; |
| 2185 | intel_sdvo->base.needs_tv_clock = false; |
| 2186 | intel_sdvo->is_lvds = false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2187 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2188 | /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2189 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2190 | if (flags & SDVO_OUTPUT_TMDS0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2191 | if (!intel_sdvo_dvi_init(intel_sdvo, 0)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2192 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2193 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2194 | if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2195 | if (!intel_sdvo_dvi_init(intel_sdvo, 1)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2196 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2197 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2198 | /* TV has no XXX1 function block */ |
Zhenyu Wang | a1f4b7ff | 2010-03-29 23:16:13 +0800 | [diff] [blame] | 2199 | if (flags & SDVO_OUTPUT_SVID0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2200 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2201 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2202 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2203 | if (flags & SDVO_OUTPUT_CVBS0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2204 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2205 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2206 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2207 | if (flags & SDVO_OUTPUT_RGB0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2208 | if (!intel_sdvo_analog_init(intel_sdvo, 0)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2209 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2210 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2211 | if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2212 | if (!intel_sdvo_analog_init(intel_sdvo, 1)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2213 | return false; |
Zhao Yakui | 2dd8738 | 2010-01-27 16:32:46 +0800 | [diff] [blame] | 2214 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2215 | if (flags & SDVO_OUTPUT_LVDS0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2216 | if (!intel_sdvo_lvds_init(intel_sdvo, 0)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2217 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2218 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2219 | if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2220 | if (!intel_sdvo_lvds_init(intel_sdvo, 1)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2221 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2222 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2223 | if ((flags & SDVO_OUTPUT_MASK) == 0) { |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2224 | unsigned char bytes[2]; |
| 2225 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2226 | intel_sdvo->controlled_output = 0; |
| 2227 | memcpy(bytes, &intel_sdvo->caps.output_flags, 2); |
Dave Airlie | 51c8b40 | 2009-08-20 13:38:04 +1000 | [diff] [blame] | 2228 | DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2229 | SDVO_NAME(intel_sdvo), |
Dave Airlie | 51c8b40 | 2009-08-20 13:38:04 +1000 | [diff] [blame] | 2230 | bytes[0], bytes[1]); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2231 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2232 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2233 | intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1); |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2234 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2235 | return true; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2236 | } |
| 2237 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2238 | static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, |
| 2239 | struct intel_sdvo_connector *intel_sdvo_connector, |
| 2240 | int type) |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2241 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2242 | struct drm_device *dev = intel_sdvo->base.base.dev; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2243 | struct intel_sdvo_tv_format format; |
| 2244 | uint32_t format_map, i; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2245 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2246 | if (!intel_sdvo_set_target_output(intel_sdvo, type)) |
| 2247 | return false; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2248 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2249 | if (!intel_sdvo_get_value(intel_sdvo, |
| 2250 | SDVO_CMD_GET_SUPPORTED_TV_FORMATS, |
| 2251 | &format, sizeof(format))) |
| 2252 | return false; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2253 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2254 | memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2255 | |
| 2256 | if (format_map == 0) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2257 | return false; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2258 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2259 | intel_sdvo_connector->format_supported_num = 0; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2260 | for (i = 0 ; i < TV_FORMAT_NUM; i++) |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 2261 | if (format_map & (1 << i)) |
| 2262 | intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2263 | |
| 2264 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2265 | intel_sdvo_connector->tv_format = |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2266 | drm_property_create(dev, DRM_MODE_PROP_ENUM, |
| 2267 | "mode", intel_sdvo_connector->format_supported_num); |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2268 | if (!intel_sdvo_connector->tv_format) |
Chris Wilson | fcc8d67 | 2010-08-04 13:50:27 +0100 | [diff] [blame] | 2269 | return false; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2270 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2271 | for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2272 | drm_property_add_enum( |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2273 | intel_sdvo_connector->tv_format, i, |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 2274 | i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2275 | |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 2276 | intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0]; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2277 | drm_connector_attach_property(&intel_sdvo_connector->base.base, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2278 | intel_sdvo_connector->tv_format, 0); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2279 | return true; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2280 | |
| 2281 | } |
| 2282 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2283 | #define ENHANCEMENT(name, NAME) do { \ |
| 2284 | if (enhancements.name) { \ |
| 2285 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ |
| 2286 | !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ |
| 2287 | return false; \ |
| 2288 | intel_sdvo_connector->max_##name = data_value[0]; \ |
| 2289 | intel_sdvo_connector->cur_##name = response; \ |
| 2290 | intel_sdvo_connector->name = \ |
| 2291 | drm_property_create(dev, DRM_MODE_PROP_RANGE, #name, 2); \ |
| 2292 | if (!intel_sdvo_connector->name) return false; \ |
| 2293 | intel_sdvo_connector->name->values[0] = 0; \ |
| 2294 | intel_sdvo_connector->name->values[1] = data_value[0]; \ |
| 2295 | drm_connector_attach_property(connector, \ |
| 2296 | intel_sdvo_connector->name, \ |
| 2297 | intel_sdvo_connector->cur_##name); \ |
| 2298 | DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ |
| 2299 | data_value[0], data_value[1], response); \ |
| 2300 | } \ |
| 2301 | } while(0) |
| 2302 | |
| 2303 | static bool |
| 2304 | intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, |
| 2305 | struct intel_sdvo_connector *intel_sdvo_connector, |
| 2306 | struct intel_sdvo_enhancements_reply enhancements) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2307 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2308 | struct drm_device *dev = intel_sdvo->base.base.dev; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2309 | struct drm_connector *connector = &intel_sdvo_connector->base.base; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2310 | uint16_t response, data_value[2]; |
| 2311 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2312 | /* when horizontal overscan is supported, Add the left/right property */ |
| 2313 | if (enhancements.overscan_h) { |
| 2314 | if (!intel_sdvo_get_value(intel_sdvo, |
| 2315 | SDVO_CMD_GET_MAX_OVERSCAN_H, |
| 2316 | &data_value, 4)) |
| 2317 | return false; |
| 2318 | |
| 2319 | if (!intel_sdvo_get_value(intel_sdvo, |
| 2320 | SDVO_CMD_GET_OVERSCAN_H, |
| 2321 | &response, 2)) |
| 2322 | return false; |
| 2323 | |
| 2324 | intel_sdvo_connector->max_hscan = data_value[0]; |
| 2325 | intel_sdvo_connector->left_margin = data_value[0] - response; |
| 2326 | intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin; |
| 2327 | intel_sdvo_connector->left = |
| 2328 | drm_property_create(dev, DRM_MODE_PROP_RANGE, |
| 2329 | "left_margin", 2); |
| 2330 | if (!intel_sdvo_connector->left) |
| 2331 | return false; |
| 2332 | |
| 2333 | intel_sdvo_connector->left->values[0] = 0; |
| 2334 | intel_sdvo_connector->left->values[1] = data_value[0]; |
| 2335 | drm_connector_attach_property(connector, |
| 2336 | intel_sdvo_connector->left, |
| 2337 | intel_sdvo_connector->left_margin); |
| 2338 | |
| 2339 | intel_sdvo_connector->right = |
| 2340 | drm_property_create(dev, DRM_MODE_PROP_RANGE, |
| 2341 | "right_margin", 2); |
| 2342 | if (!intel_sdvo_connector->right) |
| 2343 | return false; |
| 2344 | |
| 2345 | intel_sdvo_connector->right->values[0] = 0; |
| 2346 | intel_sdvo_connector->right->values[1] = data_value[0]; |
| 2347 | drm_connector_attach_property(connector, |
| 2348 | intel_sdvo_connector->right, |
| 2349 | intel_sdvo_connector->right_margin); |
| 2350 | DRM_DEBUG_KMS("h_overscan: max %d, " |
| 2351 | "default %d, current %d\n", |
| 2352 | data_value[0], data_value[1], response); |
| 2353 | } |
| 2354 | |
| 2355 | if (enhancements.overscan_v) { |
| 2356 | if (!intel_sdvo_get_value(intel_sdvo, |
| 2357 | SDVO_CMD_GET_MAX_OVERSCAN_V, |
| 2358 | &data_value, 4)) |
| 2359 | return false; |
| 2360 | |
| 2361 | if (!intel_sdvo_get_value(intel_sdvo, |
| 2362 | SDVO_CMD_GET_OVERSCAN_V, |
| 2363 | &response, 2)) |
| 2364 | return false; |
| 2365 | |
| 2366 | intel_sdvo_connector->max_vscan = data_value[0]; |
| 2367 | intel_sdvo_connector->top_margin = data_value[0] - response; |
| 2368 | intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin; |
| 2369 | intel_sdvo_connector->top = |
| 2370 | drm_property_create(dev, DRM_MODE_PROP_RANGE, |
| 2371 | "top_margin", 2); |
| 2372 | if (!intel_sdvo_connector->top) |
| 2373 | return false; |
| 2374 | |
| 2375 | intel_sdvo_connector->top->values[0] = 0; |
| 2376 | intel_sdvo_connector->top->values[1] = data_value[0]; |
| 2377 | drm_connector_attach_property(connector, |
| 2378 | intel_sdvo_connector->top, |
| 2379 | intel_sdvo_connector->top_margin); |
| 2380 | |
| 2381 | intel_sdvo_connector->bottom = |
| 2382 | drm_property_create(dev, DRM_MODE_PROP_RANGE, |
| 2383 | "bottom_margin", 2); |
| 2384 | if (!intel_sdvo_connector->bottom) |
| 2385 | return false; |
| 2386 | |
| 2387 | intel_sdvo_connector->bottom->values[0] = 0; |
| 2388 | intel_sdvo_connector->bottom->values[1] = data_value[0]; |
| 2389 | drm_connector_attach_property(connector, |
| 2390 | intel_sdvo_connector->bottom, |
| 2391 | intel_sdvo_connector->bottom_margin); |
| 2392 | DRM_DEBUG_KMS("v_overscan: max %d, " |
| 2393 | "default %d, current %d\n", |
| 2394 | data_value[0], data_value[1], response); |
| 2395 | } |
| 2396 | |
| 2397 | ENHANCEMENT(hpos, HPOS); |
| 2398 | ENHANCEMENT(vpos, VPOS); |
| 2399 | ENHANCEMENT(saturation, SATURATION); |
| 2400 | ENHANCEMENT(contrast, CONTRAST); |
| 2401 | ENHANCEMENT(hue, HUE); |
| 2402 | ENHANCEMENT(sharpness, SHARPNESS); |
| 2403 | ENHANCEMENT(brightness, BRIGHTNESS); |
| 2404 | ENHANCEMENT(flicker_filter, FLICKER_FILTER); |
| 2405 | ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); |
| 2406 | ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D); |
| 2407 | ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER); |
| 2408 | ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER); |
| 2409 | |
Chris Wilson | e044218 | 2010-08-04 13:50:29 +0100 | [diff] [blame] | 2410 | if (enhancements.dot_crawl) { |
| 2411 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) |
| 2412 | return false; |
| 2413 | |
| 2414 | intel_sdvo_connector->max_dot_crawl = 1; |
| 2415 | intel_sdvo_connector->cur_dot_crawl = response & 0x1; |
| 2416 | intel_sdvo_connector->dot_crawl = |
| 2417 | drm_property_create(dev, DRM_MODE_PROP_RANGE, "dot_crawl", 2); |
| 2418 | if (!intel_sdvo_connector->dot_crawl) |
| 2419 | return false; |
| 2420 | |
| 2421 | intel_sdvo_connector->dot_crawl->values[0] = 0; |
| 2422 | intel_sdvo_connector->dot_crawl->values[1] = 1; |
| 2423 | drm_connector_attach_property(connector, |
| 2424 | intel_sdvo_connector->dot_crawl, |
| 2425 | intel_sdvo_connector->cur_dot_crawl); |
| 2426 | DRM_DEBUG_KMS("dot crawl: current %d\n", response); |
| 2427 | } |
| 2428 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2429 | return true; |
| 2430 | } |
| 2431 | |
| 2432 | static bool |
| 2433 | intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, |
| 2434 | struct intel_sdvo_connector *intel_sdvo_connector, |
| 2435 | struct intel_sdvo_enhancements_reply enhancements) |
| 2436 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2437 | struct drm_device *dev = intel_sdvo->base.base.dev; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2438 | struct drm_connector *connector = &intel_sdvo_connector->base.base; |
| 2439 | uint16_t response, data_value[2]; |
| 2440 | |
| 2441 | ENHANCEMENT(brightness, BRIGHTNESS); |
| 2442 | |
| 2443 | return true; |
| 2444 | } |
| 2445 | #undef ENHANCEMENT |
| 2446 | |
| 2447 | static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, |
| 2448 | struct intel_sdvo_connector *intel_sdvo_connector) |
| 2449 | { |
| 2450 | union { |
| 2451 | struct intel_sdvo_enhancements_reply reply; |
| 2452 | uint16_t response; |
| 2453 | } enhancements; |
| 2454 | |
Chris Wilson | cf9a2f3 | 2010-09-23 16:17:33 +0100 | [diff] [blame] | 2455 | enhancements.response = 0; |
| 2456 | intel_sdvo_get_value(intel_sdvo, |
| 2457 | SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, |
| 2458 | &enhancements, sizeof(enhancements)); |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2459 | if (enhancements.response == 0) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2460 | DRM_DEBUG_KMS("No enhancement is supported\n"); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2461 | return true; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2462 | } |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2463 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2464 | if (IS_TV(intel_sdvo_connector)) |
| 2465 | return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); |
| 2466 | else if(IS_LVDS(intel_sdvo_connector)) |
| 2467 | return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); |
| 2468 | else |
| 2469 | return true; |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 2470 | } |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2471 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 2472 | static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, |
| 2473 | struct i2c_msg *msgs, |
| 2474 | int num) |
| 2475 | { |
| 2476 | struct intel_sdvo *sdvo = adapter->algo_data; |
| 2477 | |
| 2478 | if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) |
| 2479 | return -EIO; |
| 2480 | |
| 2481 | return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num); |
| 2482 | } |
| 2483 | |
| 2484 | static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter) |
| 2485 | { |
| 2486 | struct intel_sdvo *sdvo = adapter->algo_data; |
| 2487 | return sdvo->i2c->algo->functionality(sdvo->i2c); |
| 2488 | } |
| 2489 | |
| 2490 | static const struct i2c_algorithm intel_sdvo_ddc_proxy = { |
| 2491 | .master_xfer = intel_sdvo_ddc_proxy_xfer, |
| 2492 | .functionality = intel_sdvo_ddc_proxy_func |
| 2493 | }; |
| 2494 | |
| 2495 | static bool |
| 2496 | intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo, |
| 2497 | struct drm_device *dev) |
| 2498 | { |
| 2499 | sdvo->ddc.owner = THIS_MODULE; |
| 2500 | sdvo->ddc.class = I2C_CLASS_DDC; |
| 2501 | snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy"); |
| 2502 | sdvo->ddc.dev.parent = &dev->pdev->dev; |
| 2503 | sdvo->ddc.algo_data = sdvo; |
| 2504 | sdvo->ddc.algo = &intel_sdvo_ddc_proxy; |
| 2505 | |
| 2506 | return i2c_add_adapter(&sdvo->ddc) == 0; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2507 | } |
| 2508 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 2509 | bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2510 | { |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 2511 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2512 | struct intel_encoder *intel_encoder; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2513 | struct intel_sdvo *intel_sdvo; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2514 | int i; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2515 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2516 | intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL); |
| 2517 | if (!intel_sdvo) |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 2518 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2519 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 2520 | if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) { |
| 2521 | kfree(intel_sdvo); |
| 2522 | return false; |
| 2523 | } |
| 2524 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2525 | intel_sdvo->sdvo_reg = sdvo_reg; |
Keith Packard | 308cd3a | 2009-06-14 11:56:18 -0700 | [diff] [blame] | 2526 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2527 | intel_encoder = &intel_sdvo->base; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2528 | intel_encoder->type = INTEL_OUTPUT_SDVO; |
Chris Wilson | 373a3cf | 2010-09-15 12:03:59 +0100 | [diff] [blame] | 2529 | /* encoder type will be decided later */ |
| 2530 | drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2531 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 2532 | intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg) >> 1; |
| 2533 | intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2534 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2535 | /* Read the regs to test if we can talk to the device */ |
| 2536 | for (i = 0; i < 0x40; i++) { |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2537 | u8 byte; |
| 2538 | |
| 2539 | if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 2540 | DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n", |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 2541 | IS_SDVOB(sdvo_reg) ? 'B' : 'C'); |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2542 | goto err; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2543 | } |
| 2544 | } |
| 2545 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2546 | if (IS_SDVOB(sdvo_reg)) |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 2547 | dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS; |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2548 | else |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 2549 | dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS; |
Ma Ling | 619ac3b | 2009-05-18 16:12:46 +0800 | [diff] [blame] | 2550 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2551 | drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2552 | |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 2553 | /* In default case sdvo lvds is false */ |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2554 | if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2555 | goto err; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2556 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2557 | if (intel_sdvo_output_setup(intel_sdvo, |
| 2558 | intel_sdvo->caps.output_flags) != true) { |
Dave Airlie | 51c8b40 | 2009-08-20 13:38:04 +1000 | [diff] [blame] | 2559 | DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n", |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 2560 | IS_SDVOB(sdvo_reg) ? 'B' : 'C'); |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2561 | goto err; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2562 | } |
| 2563 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2564 | intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2565 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2566 | /* Set the input timing to the screen. Assume always input 0. */ |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2567 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2568 | goto err; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2569 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2570 | if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, |
| 2571 | &intel_sdvo->pixel_clock_min, |
| 2572 | &intel_sdvo->pixel_clock_max)) |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2573 | goto err; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2574 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 2575 | DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 2576 | "clock range %dMHz - %dMHz, " |
| 2577 | "input 1: %c, input 2: %c, " |
| 2578 | "output 1: %c, output 2: %c\n", |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2579 | SDVO_NAME(intel_sdvo), |
| 2580 | intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, |
| 2581 | intel_sdvo->caps.device_rev_id, |
| 2582 | intel_sdvo->pixel_clock_min / 1000, |
| 2583 | intel_sdvo->pixel_clock_max / 1000, |
| 2584 | (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', |
| 2585 | (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 2586 | /* check currently supported outputs */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2587 | intel_sdvo->caps.output_flags & |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2588 | (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2589 | intel_sdvo->caps.output_flags & |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2590 | (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 2591 | return true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2592 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2593 | err: |
Chris Wilson | 373a3cf | 2010-09-15 12:03:59 +0100 | [diff] [blame] | 2594 | drm_encoder_cleanup(&intel_encoder->base); |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 2595 | i2c_del_adapter(&intel_sdvo->ddc); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2596 | kfree(intel_sdvo); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2597 | |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 2598 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2599 | } |