blob: 7f040f5ba01832da9a3851c1c7a0856791996424 [file] [log] [blame]
Bryan Wu1394f032007-05-06 14:50:22 -07001
2/*
3 * File: include/asm-blackfin/mach-bf537/anomaly.h
4 * Based on:
5 * Author:
6 *
7 * Created:
8 * Description:
9 *
10 * Rev:
11 *
12 * Modified:
13 *
14 *
15 * Bugs: Enter bugs at http://blackfin.uclinux.org/
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License as published by
19 * the Free Software Foundation; either version 2, or (at your option)
20 * any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; see the file COPYING.
29 * If not, write to the Free Software Foundation,
30 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
31 */
32
33/* This file shoule be up to date with:
34 * - Revision J, June 1, 2006; ADSP-BF537 Blackfin Processor Anomaly List
35 * - Revision I, June 1, 2006; ADSP-BF536 Blackfin Processor Anomaly List
36 * - Revision J, June 1, 2006; ADSP-BF534 Blackfin Processor Anomaly List
37 */
38
39#ifndef _MACH_ANOMALY_H_
40#define _MACH_ANOMALY_H_
41
42/* We do not support 0.1 silicon - sorry */
43#if (defined(CONFIG_BF_REV_0_1))
44#error Kernel will not work on BF537/6/4 Version 0.1
45#endif
46
47#if (defined(CONFIG_BF_REV_0_3) || defined(CONFIG_BF_REV_0_2))
48#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
49 slot1 and store of a P register in slot 2 is not
50 supported */
51#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
52 Channel DMA stops */
53#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
54 registers. */
55#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
56 upper bits*/
57#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
58 syncs */
59#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
60#define ANOMALY_05000247 /* CLKIN Buffer Output Enable Reset Behavior Is
61 Changed */
62#endif
63#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
64 SPORT external receive and transmit clocks. */
65#define ANOMALY_05000272 /* Certain data cache write through modes fail for
66 VDDint <=0.9V */
67#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */
68#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
69 an edge is detected may clear interrupt */
70#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
71 not restored */
72#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
73 control */
74#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
75 killed in a particular stage*/
76#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC
77 registers are interrupted */
78#endif
79
80#if defined(CONFIG_BF_REV_0_2)
81#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or
82 IDLE around a Change of Control causes
83 unpredictable results */
84#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
85 (TDM) */
86#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
87#define ANOMALY_05000252 /* EMAC Tx DMA error after an early frame abort */
88#endif
89#define ANOMALY_05000253 /* Maximum external clock speed for Timers */
90#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
91 interrupt not functional */
92#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
93#define ANOMALY_05000256 /* EMAC MDIO input latched on wrong MDC edge */
94#endif
95#define ANOMALY_05000257 /* An interrupt or exception during short Hardware
96 loops may cause the instruction fetch unit to
97 malfunction */
98#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of
99 the ICPLB Data registers differ */
100#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
101#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
102#define ANOMALY_05000262 /* Stores to data cache may be lost */
103#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */
104#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE
105 instruction will cause an infinite stall in the
106 second to last instruction in a hardware loop */
107#define ANOMALY_05000268 /* Memory DMA error when peripheral DMA is running
108 and non-zero DEB_TRAFFIC_PERIOD value */
109#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
110 internal voltage regulator (VDDint) to decrease */
111#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
112 an edge is detected may clear interrupt */
113#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
114 DMA system instability */
115#define ANOMALY_05000280 /* SPI Master boot mode does not work well with
116 Atmel Dataflash devices */
117
118#endif /* CONFIG_BF_REV_0_2 */
119
120#endif /* _MACH_ANOMALY_H_ */