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Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -07001/*
2 * Copyright (c) 2006, Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
16 *
17 * Copyright (C) Ashok Raj <ashok.raj@intel.com>
18 * Copyright (C) Shaohua Li <shaohua.li@intel.com>
19 */
20
21#ifndef __DMAR_H__
22#define __DMAR_H__
23
24#include <linux/acpi.h>
25#include <linux/types.h>
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -070026#include <linux/msi.h>
Suresh Siddha1531a6a2009-03-16 17:04:57 -070027#include <linux/irqreturn.h>
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -070028
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -070029struct intel_iommu;
Suresh Siddha29b61be2009-03-16 17:05:02 -070030#if defined(CONFIG_DMAR) || defined(CONFIG_INTR_REMAP)
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -070031struct dmar_drhd_unit {
32 struct list_head list; /* list of drhd units */
Suresh Siddha1886e8a2008-07-10 11:16:37 -070033 struct acpi_dmar_header *hdr; /* ACPI header */
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -070034 u64 reg_base_addr; /* register base address*/
35 struct pci_dev **devices; /* target device array */
36 int devices_cnt; /* target device count */
David Woodhouse276dbf992009-04-04 01:45:37 +010037 u16 segment; /* PCI domain */
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -070038 u8 ignored:1; /* ignore drhd */
39 u8 include_all:1;
40 struct intel_iommu *iommu;
41};
42
Suresh Siddha2ae21012008-07-10 11:16:43 -070043extern struct list_head dmar_drhd_units;
44
45#define for_each_drhd_unit(drhd) \
46 list_for_each_entry(drhd, &dmar_drhd_units, list)
47
David Woodhouse8f912ba2009-04-03 15:19:32 +010048#define for_each_active_iommu(i, drhd) \
49 list_for_each_entry(drhd, &dmar_drhd_units, list) \
50 if (i=drhd->iommu, drhd->ignored) {} else
51
52#define for_each_iommu(i, drhd) \
53 list_for_each_entry(drhd, &dmar_drhd_units, list) \
54 if (i=drhd->iommu, 0) {} else
55
Suresh Siddha2ae21012008-07-10 11:16:43 -070056extern int dmar_table_init(void);
Suresh Siddha2ae21012008-07-10 11:16:43 -070057extern int dmar_dev_scope_init(void);
58
59/* Intel IOMMU detection */
Konrad Rzeszutek Wilk480125b2010-08-26 13:57:57 -040060extern int detect_intel_iommu(void);
Suresh Siddha9d783ba2009-03-16 17:04:55 -070061extern int enable_drhd_fault_handling(void);
Suresh Siddha2ae21012008-07-10 11:16:43 -070062
Suresh Siddha2ae21012008-07-10 11:16:43 -070063extern int parse_ioapics_under_ir(void);
64extern int alloc_iommu(struct dmar_drhd_unit *);
65#else
Konrad Rzeszutek Wilk480125b2010-08-26 13:57:57 -040066static inline int detect_intel_iommu(void)
Suresh Siddha2ae21012008-07-10 11:16:43 -070067{
Konrad Rzeszutek Wilk480125b2010-08-26 13:57:57 -040068 return -ENODEV;
Suresh Siddha2ae21012008-07-10 11:16:43 -070069}
70
71static inline int dmar_table_init(void)
72{
73 return -ENODEV;
74}
Suresh Siddha29b61be2009-03-16 17:05:02 -070075static inline int enable_drhd_fault_handling(void)
76{
77 return -1;
78}
Suresh Siddha2ae21012008-07-10 11:16:43 -070079#endif /* !CONFIG_DMAR && !CONFIG_INTR_REMAP */
80
Suresh Siddha2ae21012008-07-10 11:16:43 -070081struct irte {
82 union {
83 struct {
84 __u64 present : 1,
85 fpd : 1,
86 dst_mode : 1,
87 redir_hint : 1,
88 trigger_mode : 1,
89 dlvry_mode : 3,
90 avail : 4,
91 __reserved_1 : 4,
92 vector : 8,
93 __reserved_2 : 8,
94 dest_id : 32;
95 };
96 __u64 low;
97 };
98
99 union {
100 struct {
101 __u64 sid : 16,
102 sq : 2,
103 svt : 2,
104 __reserved_3 : 44;
105 };
106 __u64 high;
107 };
108};
Thomas Gleixner423f0852010-10-10 11:39:09 +0200109
Suresh Siddha29b61be2009-03-16 17:05:02 -0700110#ifdef CONFIG_INTR_REMAP
111extern int intr_remapping_enabled;
Weidong Han93758232009-04-17 16:42:14 +0800112extern int intr_remapping_supported(void);
Suresh Siddha29b61be2009-03-16 17:05:02 -0700113extern int enable_intr_remapping(int);
Fenghua Yub24696b2009-03-27 14:22:44 -0700114extern void disable_intr_remapping(void);
115extern int reenable_intr_remapping(int);
Suresh Siddha29b61be2009-03-16 17:05:02 -0700116
Suresh Siddhab6fcb332008-07-10 11:16:44 -0700117extern int get_irte(int irq, struct irte *entry);
118extern int modify_irte(int irq, struct irte *irte_modified);
119extern int alloc_irte(struct intel_iommu *iommu, int irq, u16 count);
120extern int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index,
121 u16 sub_handle);
122extern int map_irq_to_irte_handle(int irq, u16 *sub_handle);
Suresh Siddhab6fcb332008-07-10 11:16:44 -0700123extern int free_irte(int irq);
124
Suresh Siddha75c46fa2008-07-10 11:16:57 -0700125extern struct intel_iommu *map_dev_to_ir(struct pci_dev *dev);
Suresh Siddha89027d32008-07-10 11:16:56 -0700126extern struct intel_iommu *map_ioapic_to_ir(int apic);
Suresh Siddha20f30972009-08-04 12:07:08 -0700127extern struct intel_iommu *map_hpet_to_ir(u8 id);
Weidong Hanf007e992009-05-23 00:41:15 +0800128extern int set_ioapic_sid(struct irte *irte, int apic);
Suresh Siddha20f30972009-08-04 12:07:08 -0700129extern int set_hpet_sid(struct irte *irte, u8 id);
Weidong Hanf007e992009-05-23 00:41:15 +0800130extern int set_msi_sid(struct irte *irte, struct pci_dev *dev);
Suresh Siddha2ae21012008-07-10 11:16:43 -0700131#else
Suresh Siddha29b61be2009-03-16 17:05:02 -0700132static inline int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
133{
134 return -1;
135}
136static inline int modify_irte(int irq, struct irte *irte_modified)
137{
138 return -1;
139}
140static inline int free_irte(int irq)
141{
142 return -1;
143}
144static inline int map_irq_to_irte_handle(int irq, u16 *sub_handle)
145{
146 return -1;
147}
148static inline int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index,
149 u16 sub_handle)
150{
151 return -1;
152}
153static inline struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
154{
155 return NULL;
156}
157static inline struct intel_iommu *map_ioapic_to_ir(int apic)
158{
159 return NULL;
160}
Suresh Siddha20f30972009-08-04 12:07:08 -0700161static inline struct intel_iommu *map_hpet_to_ir(unsigned int hpet_id)
162{
163 return NULL;
164}
Weidong Hanf007e992009-05-23 00:41:15 +0800165static inline int set_ioapic_sid(struct irte *irte, int apic)
166{
167 return 0;
168}
Suresh Siddha20f30972009-08-04 12:07:08 -0700169static inline int set_hpet_sid(struct irte *irte, u8 id)
170{
171 return -1;
172}
Weidong Hanf007e992009-05-23 00:41:15 +0800173static inline int set_msi_sid(struct irte *irte, struct pci_dev *dev)
174{
175 return 0;
176}
177
Suresh Siddha2ae21012008-07-10 11:16:43 -0700178#define enable_intr_remapping(mode) (-1)
Suresh Siddhafc1edaf2009-04-20 13:02:27 -0700179#define disable_intr_remapping() (0)
180#define reenable_intr_remapping(mode) (0)
Suresh Siddha2ae21012008-07-10 11:16:43 -0700181#define intr_remapping_enabled (0)
182#endif
183
Suresh Siddha2ae21012008-07-10 11:16:43 -0700184/* Can't use the common MSI interrupt functions
185 * since DMAR is not a pci device
186 */
Thomas Gleixner5c2837f2010-09-28 17:15:11 +0200187struct irq_data;
188extern void dmar_msi_unmask(struct irq_data *data);
189extern void dmar_msi_mask(struct irq_data *data);
Suresh Siddha2ae21012008-07-10 11:16:43 -0700190extern void dmar_msi_read(int irq, struct msi_msg *msg);
191extern void dmar_msi_write(int irq, struct msi_msg *msg);
192extern int dmar_set_interrupt(struct intel_iommu *iommu);
Suresh Siddha1531a6a2009-03-16 17:04:57 -0700193extern irqreturn_t dmar_fault(int irq, void *dev_id);
Suresh Siddha2ae21012008-07-10 11:16:43 -0700194extern int arch_setup_dmar_msi(unsigned int irq);
195
Suresh Siddha9d783ba2009-03-16 17:04:55 -0700196#ifdef CONFIG_DMAR
Suresh Siddha2ae21012008-07-10 11:16:43 -0700197extern int iommu_detected, no_iommu;
198extern struct list_head dmar_rmrr_units;
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -0700199struct dmar_rmrr_unit {
200 struct list_head list; /* list of rmrr units */
Suresh Siddha1886e8a2008-07-10 11:16:37 -0700201 struct acpi_dmar_header *hdr; /* ACPI header */
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -0700202 u64 base_address; /* reserved base address*/
203 u64 end_address; /* reserved end address */
204 struct pci_dev **devices; /* target devices */
205 int devices_cnt; /* target device count */
206};
207
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -0700208#define for_each_rmrr_units(rmrr) \
209 list_for_each_entry(rmrr, &dmar_rmrr_units, list)
Yu Zhaoaa5d2b52009-05-18 13:51:34 +0800210
211struct dmar_atsr_unit {
212 struct list_head list; /* list of ATSR units */
213 struct acpi_dmar_header *hdr; /* ACPI header */
214 struct pci_dev **devices; /* target devices */
215 int devices_cnt; /* target device count */
216 u8 include_all:1; /* include all ports */
217};
218
Suresh Siddha2ae21012008-07-10 11:16:43 -0700219extern int intel_iommu_init(void);
FUJITA Tomonori9d5ce732009-11-10 19:46:16 +0900220#else /* !CONFIG_DMAR: */
221static inline int intel_iommu_init(void) { return -ENODEV; }
222#endif /* CONFIG_DMAR */
223
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -0700224#endif /* __DMAR_H__ */