blob: c2d23cae95155d5c78fefa8995c672c5b30643a7 [file] [log] [blame]
Ben Gardnere3291132006-01-09 20:51:29 -08001/*
2 * AMD CS5535/CS5536 GPIO driver.
3 * Allows a user space process to play with the GPIO pins.
4 *
5 * Copyright (c) 2005 Ben Gardner <bgardner@wabtec.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the smems of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 */
11
12#include <linux/fs.h>
13#include <linux/module.h>
14#include <linux/errno.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/cdev.h>
18#include <linux/ioport.h>
19#include <linux/pci.h>
20#include <asm/uaccess.h>
21#include <asm/io.h>
22
23
24#define NAME "cs5535_gpio"
25
26MODULE_AUTHOR("Ben Gardner <bgardner@wabtec.com>");
27MODULE_DESCRIPTION("AMD CS5535/CS5536 GPIO Pin Driver");
28MODULE_LICENSE("GPL");
29
30static int major;
31module_param(major, int, 0);
32MODULE_PARM_DESC(major, "Major device number");
33
34static ulong mask;
35module_param(mask, ulong, 0);
36MODULE_PARM_DESC(mask, "GPIO channel mask");
37
38#define MSR_LBAR_GPIO 0x5140000C
39
40static u32 gpio_base;
41
42static struct pci_device_id divil_pci[] = {
43 { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_CS5535_ISA) },
44 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA) },
45 { } /* NULL entry */
46};
Jiri Slaby524e6752007-05-08 00:27:07 -070047MODULE_DEVICE_TABLE(pci, divil_pci);
Ben Gardnere3291132006-01-09 20:51:29 -080048
49static struct cdev cs5535_gpio_cdev;
50
51/* reserve 32 entries even though some aren't usable */
52#define CS5535_GPIO_COUNT 32
53
54/* IO block size */
55#define CS5535_GPIO_SIZE 256
56
57struct gpio_regmap {
58 u32 rd_offset;
59 u32 wr_offset;
60 char on;
61 char off;
62};
63static struct gpio_regmap rm[] =
64{
65 { 0x30, 0x00, '1', '0' }, /* GPIOx_READ_BACK / GPIOx_OUT_VAL */
66 { 0x20, 0x20, 'I', 'i' }, /* GPIOx_IN_EN */
67 { 0x04, 0x04, 'O', 'o' }, /* GPIOx_OUT_EN */
68 { 0x08, 0x08, 't', 'T' }, /* GPIOx_OUT_OD_EN */
69 { 0x18, 0x18, 'P', 'p' }, /* GPIOx_OUT_PU_EN */
70 { 0x1c, 0x1c, 'D', 'd' }, /* GPIOx_OUT_PD_EN */
71};
72
73
74/**
75 * Gets the register offset for the GPIO bank.
76 * Low (0-15) starts at 0x00, high (16-31) starts at 0x80
77 */
78static inline u32 cs5535_lowhigh_base(int reg)
79{
80 return (reg & 0x10) << 3;
81}
82
83static ssize_t cs5535_gpio_write(struct file *file, const char __user *data,
84 size_t len, loff_t *ppos)
85{
Josef Sipeka7113a92006-12-08 02:36:55 -080086 u32 m = iminor(file->f_path.dentry->d_inode);
Ben Gardnere3291132006-01-09 20:51:29 -080087 int i, j;
88 u32 base = gpio_base + cs5535_lowhigh_base(m);
89 u32 m0, m1;
90 char c;
91
92 /**
93 * Creates the mask for atomic bit programming.
94 * The high 16 bits and the low 16 bits are used to set the mask.
95 * For example, GPIO 15 maps to 31,15: 0,1 => On; 1,0=> Off
96 */
97 m1 = 1 << (m & 0x0F);
98 m0 = m1 << 16;
99
100 for (i = 0; i < len; ++i) {
101 if (get_user(c, data+i))
102 return -EFAULT;
103
104 for (j = 0; j < ARRAY_SIZE(rm); j++) {
105 if (c == rm[j].on) {
106 outl(m1, base + rm[j].wr_offset);
Ben Gardner4670df82007-12-04 23:45:24 -0800107 /* If enabling output, turn off AUX 1 and AUX 2 */
108 if (c == 'O') {
109 outl(m0, base + 0x10);
110 outl(m0, base + 0x14);
111 }
Ben Gardnere3291132006-01-09 20:51:29 -0800112 break;
113 } else if (c == rm[j].off) {
114 outl(m0, base + rm[j].wr_offset);
115 break;
116 }
117 }
118 }
119 *ppos = 0;
120 return len;
121}
122
123static ssize_t cs5535_gpio_read(struct file *file, char __user *buf,
124 size_t len, loff_t *ppos)
125{
Josef Sipeka7113a92006-12-08 02:36:55 -0800126 u32 m = iminor(file->f_path.dentry->d_inode);
Ben Gardnere3291132006-01-09 20:51:29 -0800127 u32 base = gpio_base + cs5535_lowhigh_base(m);
128 int rd_bit = 1 << (m & 0x0f);
129 int i;
130 char ch;
131 ssize_t count = 0;
132
133 if (*ppos >= ARRAY_SIZE(rm))
134 return 0;
135
136 for (i = *ppos; (i < (*ppos + len)) && (i < ARRAY_SIZE(rm)); i++) {
137 ch = (inl(base + rm[i].rd_offset) & rd_bit) ?
138 rm[i].on : rm[i].off;
139
140 if (put_user(ch, buf+count))
141 return -EFAULT;
142
143 count++;
144 }
145
146 /* add a line-feed if there is room */
147 if ((i == ARRAY_SIZE(rm)) && (count < len)) {
148 put_user('\n', buf + count);
149 count++;
150 }
151
152 *ppos += count;
153 return count;
154}
155
156static int cs5535_gpio_open(struct inode *inode, struct file *file)
157{
158 u32 m = iminor(inode);
159
160 /* the mask says which pins are usable by this driver */
161 if ((mask & (1 << m)) == 0)
162 return -EINVAL;
163
164 return nonseekable_open(inode, file);
165}
166
Arjan van de Ven62322d22006-07-03 00:24:21 -0700167static const struct file_operations cs5535_gpio_fops = {
Ben Gardnere3291132006-01-09 20:51:29 -0800168 .owner = THIS_MODULE,
169 .write = cs5535_gpio_write,
170 .read = cs5535_gpio_read,
171 .open = cs5535_gpio_open
172};
173
174static int __init cs5535_gpio_init(void)
175{
176 dev_t dev_id;
177 u32 low, hi;
178 int retval;
179
180 if (pci_dev_present(divil_pci) == 0) {
181 printk(KERN_WARNING NAME ": DIVIL not found\n");
182 return -ENODEV;
183 }
184
185 /* Grab the GPIO I/O range */
186 rdmsr(MSR_LBAR_GPIO, low, hi);
187
188 /* Check the mask and whether GPIO is enabled (sanity check) */
189 if (hi != 0x0000f001) {
190 printk(KERN_WARNING NAME ": GPIO not enabled\n");
191 return -ENODEV;
192 }
193
194 /* Mask off the IO base address */
195 gpio_base = low & 0x0000ff00;
196
197 /**
198 * Some GPIO pins
199 * 31-29,23 : reserved (always mask out)
200 * 28 : Power Button
201 * 26 : PME#
202 * 22-16 : LPC
203 * 14,15 : SMBus
204 * 9,8 : UART1
205 * 7 : PCI INTB
206 * 3,4 : UART2/DDC
207 * 2 : IDE_IRQ0
208 * 0 : PCI INTA
209 *
210 * If a mask was not specified, be conservative and only allow:
211 * 1,2,5,6,10-13,24,25,27
212 */
213 if (mask != 0)
214 mask &= 0x1f7fffff;
215 else
216 mask = 0x0b003c66;
217
218 if (request_region(gpio_base, CS5535_GPIO_SIZE, NAME) == 0) {
219 printk(KERN_ERR NAME ": can't allocate I/O for GPIO\n");
220 return -ENODEV;
221 }
222
223 if (major) {
224 dev_id = MKDEV(major, 0);
225 retval = register_chrdev_region(dev_id, CS5535_GPIO_COUNT,
226 NAME);
227 } else {
228 retval = alloc_chrdev_region(&dev_id, 0, CS5535_GPIO_COUNT,
229 NAME);
230 major = MAJOR(dev_id);
231 }
232
233 if (retval) {
234 release_region(gpio_base, CS5535_GPIO_SIZE);
235 return -1;
236 }
237
238 printk(KERN_DEBUG NAME ": base=%#x mask=%#lx major=%d\n",
239 gpio_base, mask, major);
240
241 cdev_init(&cs5535_gpio_cdev, &cs5535_gpio_fops);
242 cdev_add(&cs5535_gpio_cdev, dev_id, CS5535_GPIO_COUNT);
243
244 return 0;
245}
246
247static void __exit cs5535_gpio_cleanup(void)
248{
249 dev_t dev_id = MKDEV(major, 0);
Thayumanavar Sachithanantham03246802006-04-20 02:43:15 -0700250
251 cdev_del(&cs5535_gpio_cdev);
Ben Gardnere3291132006-01-09 20:51:29 -0800252 unregister_chrdev_region(dev_id, CS5535_GPIO_COUNT);
Thayumanavar Sachithanantham03246802006-04-20 02:43:15 -0700253 release_region(gpio_base, CS5535_GPIO_SIZE);
Ben Gardnere3291132006-01-09 20:51:29 -0800254}
255
256module_init(cs5535_gpio_init);
257module_exit(cs5535_gpio_cleanup);