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Graf Yangc51b4482009-01-07 23:14:39 +08001/*
Robin Getz96f10502009-09-24 14:11:24 +00002 * Copyright 2007-2009 Analog Devices Inc.
3 * Philippe Gerum <rpm@xenomai.org>
Graf Yangc51b4482009-01-07 23:14:39 +08004 *
Robin Getz96f10502009-09-24 14:11:24 +00005 * Licensed under the GPL-2 or later.
Graf Yangc51b4482009-01-07 23:14:39 +08006 */
7
8#include <linux/init.h>
9#include <linux/kernel.h>
10#include <linux/sched.h>
11#include <linux/delay.h>
12#include <asm/smp.h>
13#include <asm/dma.h>
Yi Li0d152c22009-12-28 10:21:49 +000014#include <asm/time.h>
Graf Yangc51b4482009-01-07 23:14:39 +080015
Graf Yangc51b4482009-01-07 23:14:39 +080016static DEFINE_SPINLOCK(boot_lock);
17
Graf Yangc51b4482009-01-07 23:14:39 +080018/*
19 * platform_init_cpus() - Tell the world about how many cores we
20 * have. This is called while setting up the architecture support
21 * (setup_arch()), so don't be too demanding here with respect to
22 * available kernel services.
23 */
24
25void __init platform_init_cpus(void)
26{
KOSAKI Motohiro3cb8a392011-04-26 10:55:41 +090027 struct cpumask mask;
28
29 cpumask_set_cpu(0, &mask); /* CoreA */
30 cpumask_set_cpu(1, &mask); /* CoreB */
31 init_cpu_possible(&mask);
Graf Yangc51b4482009-01-07 23:14:39 +080032}
33
34void __init platform_prepare_cpus(unsigned int max_cpus)
35{
KOSAKI Motohiro3cb8a392011-04-26 10:55:41 +090036 struct cpumask mask;
37
Sonic Zhangc6345ab2010-08-05 07:49:26 +000038 bfin_relocate_coreb_l1_mem();
Graf Yangc51b4482009-01-07 23:14:39 +080039
40 /* Both cores ought to be present on a bf561! */
KOSAKI Motohiro3cb8a392011-04-26 10:55:41 +090041 cpumask_set_cpu(0, &mask); /* CoreA */
42 cpumask_set_cpu(1, &mask); /* CoreB */
43 init_cpu_present(&mask);
Graf Yangc51b4482009-01-07 23:14:39 +080044}
45
46int __init setup_profiling_timer(unsigned int multiplier) /* not supported */
47{
48 return -EINVAL;
49}
50
Paul Gortmaker13dff622013-06-18 16:56:21 -040051void platform_secondary_init(unsigned int cpu)
Graf Yangc51b4482009-01-07 23:14:39 +080052{
Graf Yangc51b4482009-01-07 23:14:39 +080053 /* Clone setup for peripheral interrupt sources from CoreA. */
Mike Frysinger39c99962010-10-19 18:44:23 +000054 bfin_write_SICB_IMASK0(bfin_read_SIC_IMASK0());
55 bfin_write_SICB_IMASK1(bfin_read_SIC_IMASK1());
Graf Yangc51b4482009-01-07 23:14:39 +080056 SSYNC();
57
58 /* Clone setup for IARs from CoreA. */
Mike Frysinger39c99962010-10-19 18:44:23 +000059 bfin_write_SICB_IAR0(bfin_read_SIC_IAR0());
60 bfin_write_SICB_IAR1(bfin_read_SIC_IAR1());
61 bfin_write_SICB_IAR2(bfin_read_SIC_IAR2());
62 bfin_write_SICB_IAR3(bfin_read_SIC_IAR3());
63 bfin_write_SICB_IAR4(bfin_read_SIC_IAR4());
64 bfin_write_SICB_IAR5(bfin_read_SIC_IAR5());
65 bfin_write_SICB_IAR6(bfin_read_SIC_IAR6());
66 bfin_write_SICB_IAR7(bfin_read_SIC_IAR7());
Graf Yang0b39db22009-12-28 11:13:51 +000067 bfin_write_SICB_IWR0(IWR_DISABLE_ALL);
68 bfin_write_SICB_IWR1(IWR_DISABLE_ALL);
Graf Yangc51b4482009-01-07 23:14:39 +080069 SSYNC();
70
Graf Yangc51b4482009-01-07 23:14:39 +080071 /* We are done with local CPU inits, unblock the boot CPU. */
Graf Yangc51b4482009-01-07 23:14:39 +080072 spin_lock(&boot_lock);
73 spin_unlock(&boot_lock);
74}
75
Paul Gortmaker13dff622013-06-18 16:56:21 -040076int platform_boot_secondary(unsigned int cpu, struct task_struct *idle)
Graf Yangc51b4482009-01-07 23:14:39 +080077{
78 unsigned long timeout;
79
Graf Yangc51b4482009-01-07 23:14:39 +080080 printk(KERN_INFO "Booting Core B.\n");
81
82 spin_lock(&boot_lock);
83
Mike Frysinger94a038c2010-10-27 10:06:32 -040084 if ((bfin_read_SYSCR() & COREB_SRAM_INIT) == 0) {
Graf Yang0b39db22009-12-28 11:13:51 +000085 /* CoreB already running, sending ipi to wakeup it */
Bob Liud0014be2011-12-12 11:04:05 +080086 smp_send_reschedule(cpu);
Graf Yang0b39db22009-12-28 11:13:51 +000087 } else {
88 /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */
Mike Frysinger94a038c2010-10-27 10:06:32 -040089 bfin_write_SYSCR(bfin_read_SYSCR() & ~COREB_SRAM_INIT);
Graf Yang0b39db22009-12-28 11:13:51 +000090 SSYNC();
91 }
Graf Yangc51b4482009-01-07 23:14:39 +080092
Steven Miao150382a2013-07-09 15:39:53 +080093 timeout = jiffies + HZ;
94 /* release the lock and let coreb run */
95 spin_unlock(&boot_lock);
Graf Yangc51b4482009-01-07 23:14:39 +080096 while (time_before(jiffies, timeout)) {
Graf Yang682f5dc2009-12-28 09:27:27 +000097 if (cpu_online(cpu))
Graf Yangc51b4482009-01-07 23:14:39 +080098 break;
99 udelay(100);
100 barrier();
101 }
102
Graf Yang682f5dc2009-12-28 09:27:27 +0000103 if (cpu_online(cpu)) {
Yi Li578d36f2009-12-02 07:58:12 +0000104 return 0;
105 } else
106 panic("CPU%u: processor failed to boot\n", cpu);
Graf Yangc51b4482009-01-07 23:14:39 +0800107}
108
Yi Li73a40062009-12-17 08:20:32 +0000109static const char supple0[] = "IRQ_SUPPLE_0";
110static const char supple1[] = "IRQ_SUPPLE_1";
111void __init platform_request_ipi(int irq, void *handler)
Graf Yangc51b4482009-01-07 23:14:39 +0800112{
113 int ret;
Yi Li73a40062009-12-17 08:20:32 +0000114 const char *name = (irq == IRQ_SUPPLE_0) ? supple0 : supple1;
Graf Yangc51b4482009-01-07 23:14:39 +0800115
Bob Liu16df3662011-12-12 10:59:48 +0800116 ret = request_irq(irq, handler, IRQF_PERCPU | IRQF_NO_SUSPEND |
117 IRQF_FORCE_RESUME, name, handler);
Graf Yangc51b4482009-01-07 23:14:39 +0800118 if (ret)
Yi Li73a40062009-12-17 08:20:32 +0000119 panic("Cannot request %s for IPI service", name);
Graf Yangc51b4482009-01-07 23:14:39 +0800120}
121
Yi Li73a40062009-12-17 08:20:32 +0000122void platform_send_ipi(cpumask_t callmap, int irq)
Graf Yangc51b4482009-01-07 23:14:39 +0800123{
124 unsigned int cpu;
Yi Li73a40062009-12-17 08:20:32 +0000125 int offset = (irq == IRQ_SUPPLE_0) ? 6 : 8;
Graf Yangc51b4482009-01-07 23:14:39 +0800126
127 for_each_cpu_mask(cpu, callmap) {
128 BUG_ON(cpu >= 2);
129 SSYNC();
Yi Li73a40062009-12-17 08:20:32 +0000130 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
Graf Yangc51b4482009-01-07 23:14:39 +0800131 SSYNC();
132 }
133}
134
Yi Li73a40062009-12-17 08:20:32 +0000135void platform_send_ipi_cpu(unsigned int cpu, int irq)
Graf Yangc51b4482009-01-07 23:14:39 +0800136{
Yi Li73a40062009-12-17 08:20:32 +0000137 int offset = (irq == IRQ_SUPPLE_0) ? 6 : 8;
Graf Yangc51b4482009-01-07 23:14:39 +0800138 BUG_ON(cpu >= 2);
139 SSYNC();
Yi Li73a40062009-12-17 08:20:32 +0000140 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
Graf Yangc51b4482009-01-07 23:14:39 +0800141 SSYNC();
142}
143
Yi Li73a40062009-12-17 08:20:32 +0000144void platform_clear_ipi(unsigned int cpu, int irq)
Graf Yangc51b4482009-01-07 23:14:39 +0800145{
Yi Li73a40062009-12-17 08:20:32 +0000146 int offset = (irq == IRQ_SUPPLE_0) ? 10 : 12;
Graf Yangc51b4482009-01-07 23:14:39 +0800147 BUG_ON(cpu >= 2);
148 SSYNC();
Yi Li73a40062009-12-17 08:20:32 +0000149 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
Graf Yangc51b4482009-01-07 23:14:39 +0800150 SSYNC();
151}
Yi Li0d152c22009-12-28 10:21:49 +0000152
153/*
154 * Setup core B's local core timer.
155 * In SMP, core timer is used for clock event device.
156 */
Paul Gortmaker13dff622013-06-18 16:56:21 -0400157void bfin_local_timer_setup(void)
Yi Li0d152c22009-12-28 10:21:49 +0000158{
159#if defined(CONFIG_TICKSOURCE_CORETMR)
Thomas Gleixner1907d8b2011-03-24 17:21:01 +0100160 struct irq_data *data = irq_get_irq_data(IRQ_CORETMR);
161 struct irq_chip *chip = irq_data_get_irq_chip(data);
Mike Frysinger91796c22011-03-18 03:03:23 -0400162
Yi Li0d152c22009-12-28 10:21:49 +0000163 bfin_coretmr_init();
164 bfin_coretmr_clockevent_init();
Mike Frysinger91796c22011-03-18 03:03:23 -0400165
Thomas Gleixner1907d8b2011-03-24 17:21:01 +0100166 chip->irq_unmask(data);
Yi Li0d152c22009-12-28 10:21:49 +0000167#else
168 /* Power down the core timer, just to play safe. */
169 bfin_write_TCNTL(0);
170#endif
171
172}