Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2010 Marvell International Ltd. |
| 3 | * Zhangfei Gao <zhangfei.gao@marvell.com> |
| 4 | * Kevin Wang <dwang4@marvell.com> |
| 5 | * Mingwei Wang <mwwang@marvell.com> |
| 6 | * Philip Rakity <prakity@marvell.com> |
| 7 | * Mark Brown <markb@marvell.com> |
| 8 | * |
| 9 | * This software is licensed under the terms of the GNU General Public |
| 10 | * License version 2, as published by the Free Software Foundation, and |
| 11 | * may be copied, distributed, and modified under those terms. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | */ |
| 19 | #include <linux/err.h> |
| 20 | #include <linux/init.h> |
| 21 | #include <linux/platform_device.h> |
| 22 | #include <linux/clk.h> |
| 23 | #include <linux/io.h> |
| 24 | #include <linux/gpio.h> |
| 25 | #include <linux/mmc/card.h> |
| 26 | #include <linux/mmc/host.h> |
Chris Ball | 8f63795 | 2012-09-19 16:29:12 +0800 | [diff] [blame] | 27 | #include <linux/mmc/slot-gpio.h> |
Zhangfei Gao | bfed345 | 2011-06-20 22:11:52 +0800 | [diff] [blame] | 28 | #include <linux/platform_data/pxa_sdhci.h> |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 29 | #include <linux/slab.h> |
| 30 | #include <linux/delay.h> |
Paul Gortmaker | 88b4767 | 2011-07-03 15:15:51 -0400 | [diff] [blame] | 31 | #include <linux/module.h> |
Chris Ball | b650352 | 2012-04-10 22:34:33 -0400 | [diff] [blame] | 32 | #include <linux/of.h> |
| 33 | #include <linux/of_device.h> |
Chris Ball | 8f63795 | 2012-09-19 16:29:12 +0800 | [diff] [blame] | 34 | #include <linux/of_gpio.h> |
Kevin Liu | bb691ae | 2013-02-01 17:48:30 +0800 | [diff] [blame] | 35 | #include <linux/pm.h> |
| 36 | #include <linux/pm_runtime.h> |
Marcin Wojtas | 5491ce3 | 2014-02-18 16:08:29 +0100 | [diff] [blame] | 37 | #include <linux/mbus.h> |
Chris Ball | b650352 | 2012-04-10 22:34:33 -0400 | [diff] [blame] | 38 | |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 39 | #include "sdhci.h" |
| 40 | #include "sdhci-pltfm.h" |
| 41 | |
Kevin Liu | bb691ae | 2013-02-01 17:48:30 +0800 | [diff] [blame] | 42 | #define PXAV3_RPM_DELAY_MS 50 |
| 43 | |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 44 | #define SD_CLOCK_BURST_SIZE_SETUP 0x10A |
| 45 | #define SDCLK_SEL 0x100 |
| 46 | #define SDCLK_DELAY_SHIFT 9 |
| 47 | #define SDCLK_DELAY_MASK 0x1f |
| 48 | |
| 49 | #define SD_CFG_FIFO_PARAM 0x100 |
| 50 | #define SDCFG_GEN_PAD_CLK_ON (1<<6) |
| 51 | #define SDCFG_GEN_PAD_CLK_CNT_MASK 0xFF |
| 52 | #define SDCFG_GEN_PAD_CLK_CNT_SHIFT 24 |
| 53 | |
| 54 | #define SD_SPI_MODE 0x108 |
| 55 | #define SD_CE_ATA_1 0x10C |
| 56 | |
| 57 | #define SD_CE_ATA_2 0x10E |
| 58 | #define SDCE_MISC_INT (1<<2) |
| 59 | #define SDCE_MISC_INT_EN (1<<1) |
| 60 | |
Sebastian Hesselbarth | cc9571e | 2014-10-21 11:22:35 +0200 | [diff] [blame] | 61 | struct sdhci_pxa { |
Sebastian Hesselbarth | 8afdc9c | 2014-10-21 11:22:40 +0200 | [diff] [blame] | 62 | struct clk *clk_core; |
Sebastian Hesselbarth | 8c96a7a | 2014-10-21 11:22:38 +0200 | [diff] [blame] | 63 | struct clk *clk_io; |
Sebastian Hesselbarth | cc9571e | 2014-10-21 11:22:35 +0200 | [diff] [blame] | 64 | u8 power_mode; |
| 65 | }; |
| 66 | |
Marcin Wojtas | 5491ce3 | 2014-02-18 16:08:29 +0100 | [diff] [blame] | 67 | /* |
| 68 | * These registers are relative to the second register region, for the |
| 69 | * MBus bridge. |
| 70 | */ |
| 71 | #define SDHCI_WINDOW_CTRL(i) (0x80 + ((i) << 3)) |
| 72 | #define SDHCI_WINDOW_BASE(i) (0x84 + ((i) << 3)) |
| 73 | #define SDHCI_MAX_WIN_NUM 8 |
| 74 | |
| 75 | static int mv_conf_mbus_windows(struct platform_device *pdev, |
| 76 | const struct mbus_dram_target_info *dram) |
| 77 | { |
| 78 | int i; |
| 79 | void __iomem *regs; |
| 80 | struct resource *res; |
| 81 | |
| 82 | if (!dram) { |
| 83 | dev_err(&pdev->dev, "no mbus dram info\n"); |
| 84 | return -EINVAL; |
| 85 | } |
| 86 | |
| 87 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
| 88 | if (!res) { |
| 89 | dev_err(&pdev->dev, "cannot get mbus registers\n"); |
| 90 | return -EINVAL; |
| 91 | } |
| 92 | |
| 93 | regs = ioremap(res->start, resource_size(res)); |
| 94 | if (!regs) { |
| 95 | dev_err(&pdev->dev, "cannot map mbus registers\n"); |
| 96 | return -ENOMEM; |
| 97 | } |
| 98 | |
| 99 | for (i = 0; i < SDHCI_MAX_WIN_NUM; i++) { |
| 100 | writel(0, regs + SDHCI_WINDOW_CTRL(i)); |
| 101 | writel(0, regs + SDHCI_WINDOW_BASE(i)); |
| 102 | } |
| 103 | |
| 104 | for (i = 0; i < dram->num_cs; i++) { |
| 105 | const struct mbus_dram_window *cs = dram->cs + i; |
| 106 | |
| 107 | /* Write size, attributes and target id to control register */ |
| 108 | writel(((cs->size - 1) & 0xffff0000) | |
| 109 | (cs->mbus_attr << 8) | |
| 110 | (dram->mbus_dram_target_id << 4) | 1, |
| 111 | regs + SDHCI_WINDOW_CTRL(i)); |
| 112 | /* Write base address to base register */ |
| 113 | writel(cs->base, regs + SDHCI_WINDOW_BASE(i)); |
| 114 | } |
| 115 | |
| 116 | iounmap(regs); |
| 117 | |
| 118 | return 0; |
| 119 | } |
| 120 | |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 121 | static void pxav3_reset(struct sdhci_host *host, u8 mask) |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 122 | { |
| 123 | struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc)); |
| 124 | struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; |
| 125 | |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 126 | sdhci_reset(host, mask); |
| 127 | |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 128 | if (mask == SDHCI_RESET_ALL) { |
| 129 | /* |
| 130 | * tune timing of read data/command when crc error happen |
| 131 | * no performance impact |
| 132 | */ |
| 133 | if (pdata && 0 != pdata->clk_delay_cycles) { |
| 134 | u16 tmp; |
| 135 | |
| 136 | tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); |
| 137 | tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK) |
| 138 | << SDCLK_DELAY_SHIFT; |
| 139 | tmp |= SDCLK_SEL; |
| 140 | writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); |
| 141 | } |
| 142 | } |
| 143 | } |
| 144 | |
| 145 | #define MAX_WAIT_COUNT 5 |
| 146 | static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode) |
| 147 | { |
| 148 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 149 | struct sdhci_pxa *pxa = pltfm_host->priv; |
| 150 | u16 tmp; |
| 151 | int count; |
| 152 | |
| 153 | if (pxa->power_mode == MMC_POWER_UP |
| 154 | && power_mode == MMC_POWER_ON) { |
| 155 | |
| 156 | dev_dbg(mmc_dev(host->mmc), |
| 157 | "%s: slot->power_mode = %d," |
| 158 | "ios->power_mode = %d\n", |
| 159 | __func__, |
| 160 | pxa->power_mode, |
| 161 | power_mode); |
| 162 | |
| 163 | /* set we want notice of when 74 clocks are sent */ |
| 164 | tmp = readw(host->ioaddr + SD_CE_ATA_2); |
| 165 | tmp |= SDCE_MISC_INT_EN; |
| 166 | writew(tmp, host->ioaddr + SD_CE_ATA_2); |
| 167 | |
| 168 | /* start sending the 74 clocks */ |
| 169 | tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM); |
| 170 | tmp |= SDCFG_GEN_PAD_CLK_ON; |
| 171 | writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM); |
| 172 | |
| 173 | /* slowest speed is about 100KHz or 10usec per clock */ |
| 174 | udelay(740); |
| 175 | count = 0; |
| 176 | |
| 177 | while (count++ < MAX_WAIT_COUNT) { |
| 178 | if ((readw(host->ioaddr + SD_CE_ATA_2) |
| 179 | & SDCE_MISC_INT) == 0) |
| 180 | break; |
| 181 | udelay(10); |
| 182 | } |
| 183 | |
| 184 | if (count == MAX_WAIT_COUNT) |
| 185 | dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n"); |
| 186 | |
| 187 | /* clear the interrupt bit if posted */ |
| 188 | tmp = readw(host->ioaddr + SD_CE_ATA_2); |
| 189 | tmp |= SDCE_MISC_INT; |
| 190 | writew(tmp, host->ioaddr + SD_CE_ATA_2); |
| 191 | } |
| 192 | pxa->power_mode = power_mode; |
| 193 | } |
| 194 | |
Russell King | 13e6450 | 2014-04-25 12:59:20 +0100 | [diff] [blame] | 195 | static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 196 | { |
| 197 | u16 ctrl_2; |
| 198 | |
| 199 | /* |
| 200 | * Set V18_EN -- UHS modes do not work without this. |
| 201 | * does not change signaling voltage |
| 202 | */ |
| 203 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 204 | |
| 205 | /* Select Bus Speed Mode for host */ |
| 206 | ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; |
| 207 | switch (uhs) { |
| 208 | case MMC_TIMING_UHS_SDR12: |
| 209 | ctrl_2 |= SDHCI_CTRL_UHS_SDR12; |
| 210 | break; |
| 211 | case MMC_TIMING_UHS_SDR25: |
| 212 | ctrl_2 |= SDHCI_CTRL_UHS_SDR25; |
| 213 | break; |
| 214 | case MMC_TIMING_UHS_SDR50: |
| 215 | ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180; |
| 216 | break; |
| 217 | case MMC_TIMING_UHS_SDR104: |
| 218 | ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180; |
| 219 | break; |
Sebastian Hesselbarth | 668e84b | 2014-10-21 11:22:34 +0200 | [diff] [blame] | 220 | case MMC_TIMING_MMC_DDR52: |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 221 | case MMC_TIMING_UHS_DDR50: |
| 222 | ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180; |
| 223 | break; |
| 224 | } |
| 225 | |
| 226 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); |
| 227 | dev_dbg(mmc_dev(host->mmc), |
| 228 | "%s uhs = %d, ctrl_2 = %04X\n", |
| 229 | __func__, uhs, ctrl_2); |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 230 | } |
| 231 | |
Lars-Peter Clausen | c915568 | 2013-03-13 19:26:05 +0100 | [diff] [blame] | 232 | static const struct sdhci_ops pxav3_sdhci_ops = { |
Russell King | 1771059 | 2014-04-25 12:58:55 +0100 | [diff] [blame] | 233 | .set_clock = sdhci_set_clock, |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 234 | .platform_send_init_74_clocks = pxav3_gen_init_74_clocks, |
Lars-Peter Clausen | d005d94 | 2013-01-28 19:27:12 +0100 | [diff] [blame] | 235 | .get_max_clock = sdhci_pltfm_clk_get_max_clock, |
Russell King | 2317f56 | 2014-04-25 12:57:07 +0100 | [diff] [blame] | 236 | .set_bus_width = sdhci_set_bus_width, |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 237 | .reset = pxav3_reset, |
Peter Griffin | b315376 | 2014-08-15 14:02:15 +0100 | [diff] [blame] | 238 | .set_uhs_signaling = pxav3_set_uhs_signaling, |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 239 | }; |
| 240 | |
Kevin Liu | 73b7afb | 2013-03-25 17:42:56 +0800 | [diff] [blame] | 241 | static struct sdhci_pltfm_data sdhci_pxav3_pdata = { |
Kevin Liu | e065162 | 2013-03-25 17:42:59 +0800 | [diff] [blame] | 242 | .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
Kevin Liu | 73b7afb | 2013-03-25 17:42:56 +0800 | [diff] [blame] | 243 | | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
| 244 | | SDHCI_QUIRK_32BIT_ADMA_SIZE |
| 245 | | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, |
| 246 | .ops = &pxav3_sdhci_ops, |
| 247 | }; |
| 248 | |
Chris Ball | b650352 | 2012-04-10 22:34:33 -0400 | [diff] [blame] | 249 | #ifdef CONFIG_OF |
| 250 | static const struct of_device_id sdhci_pxav3_of_match[] = { |
| 251 | { |
| 252 | .compatible = "mrvl,pxav3-mmc", |
| 253 | }, |
Marcin Wojtas | 5491ce3 | 2014-02-18 16:08:29 +0100 | [diff] [blame] | 254 | { |
| 255 | .compatible = "marvell,armada-380-sdhci", |
| 256 | }, |
Chris Ball | b650352 | 2012-04-10 22:34:33 -0400 | [diff] [blame] | 257 | {}, |
| 258 | }; |
| 259 | MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match); |
| 260 | |
| 261 | static struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev) |
| 262 | { |
| 263 | struct sdhci_pxa_platdata *pdata; |
| 264 | struct device_node *np = dev->of_node; |
Chris Ball | b650352 | 2012-04-10 22:34:33 -0400 | [diff] [blame] | 265 | u32 clk_delay_cycles; |
| 266 | |
| 267 | pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); |
| 268 | if (!pdata) |
| 269 | return NULL; |
| 270 | |
Chris Ball | b650352 | 2012-04-10 22:34:33 -0400 | [diff] [blame] | 271 | of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles); |
| 272 | if (clk_delay_cycles > 0) |
| 273 | pdata->clk_delay_cycles = clk_delay_cycles; |
| 274 | |
| 275 | return pdata; |
| 276 | } |
| 277 | #else |
| 278 | static inline struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev) |
| 279 | { |
| 280 | return NULL; |
| 281 | } |
| 282 | #endif |
| 283 | |
Bill Pemberton | c3be1ef | 2012-11-19 13:23:06 -0500 | [diff] [blame] | 284 | static int sdhci_pxav3_probe(struct platform_device *pdev) |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 285 | { |
| 286 | struct sdhci_pltfm_host *pltfm_host; |
| 287 | struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; |
| 288 | struct device *dev = &pdev->dev; |
Marcin Wojtas | 5491ce3 | 2014-02-18 16:08:29 +0100 | [diff] [blame] | 289 | struct device_node *np = pdev->dev.of_node; |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 290 | struct sdhci_host *host = NULL; |
| 291 | struct sdhci_pxa *pxa = NULL; |
Chris Ball | b650352 | 2012-04-10 22:34:33 -0400 | [diff] [blame] | 292 | const struct of_device_id *match; |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 293 | int ret; |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 294 | |
Laurent Pinchart | 3df5b28 | 2014-07-16 11:53:42 +0200 | [diff] [blame] | 295 | pxa = devm_kzalloc(&pdev->dev, sizeof(struct sdhci_pxa), GFP_KERNEL); |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 296 | if (!pxa) |
| 297 | return -ENOMEM; |
| 298 | |
Christian Daudt | 0e74823 | 2013-05-29 13:50:05 -0700 | [diff] [blame] | 299 | host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, 0); |
Laurent Pinchart | 3df5b28 | 2014-07-16 11:53:42 +0200 | [diff] [blame] | 300 | if (IS_ERR(host)) |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 301 | return PTR_ERR(host); |
Marcin Wojtas | 5491ce3 | 2014-02-18 16:08:29 +0100 | [diff] [blame] | 302 | |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 303 | pltfm_host = sdhci_priv(host); |
| 304 | pltfm_host->priv = pxa; |
| 305 | |
Sebastian Hesselbarth | 01ae107 | 2014-10-21 11:22:39 +0200 | [diff] [blame] | 306 | pxa->clk_io = devm_clk_get(dev, "io"); |
| 307 | if (IS_ERR(pxa->clk_io)) |
| 308 | pxa->clk_io = devm_clk_get(dev, NULL); |
Sebastian Hesselbarth | 8c96a7a | 2014-10-21 11:22:38 +0200 | [diff] [blame] | 309 | if (IS_ERR(pxa->clk_io)) { |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 310 | dev_err(dev, "failed to get io clock\n"); |
Sebastian Hesselbarth | 8c96a7a | 2014-10-21 11:22:38 +0200 | [diff] [blame] | 311 | ret = PTR_ERR(pxa->clk_io); |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 312 | goto err_clk_get; |
| 313 | } |
Sebastian Hesselbarth | 8c96a7a | 2014-10-21 11:22:38 +0200 | [diff] [blame] | 314 | pltfm_host->clk = pxa->clk_io; |
| 315 | clk_prepare_enable(pxa->clk_io); |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 316 | |
Sebastian Hesselbarth | 8afdc9c | 2014-10-21 11:22:40 +0200 | [diff] [blame] | 317 | pxa->clk_core = devm_clk_get(dev, "core"); |
| 318 | if (!IS_ERR(pxa->clk_core)) |
| 319 | clk_prepare_enable(pxa->clk_core); |
| 320 | |
Thomas Petazzoni | aa8165f | 2014-12-31 11:54:10 +0100 | [diff] [blame] | 321 | if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) { |
| 322 | ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info()); |
| 323 | if (ret < 0) |
| 324 | goto err_mbus_win; |
| 325 | } |
| 326 | |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 327 | /* enable 1/8V DDR capable */ |
| 328 | host->mmc->caps |= MMC_CAP_1_8V_DDR; |
| 329 | |
Chris Ball | b650352 | 2012-04-10 22:34:33 -0400 | [diff] [blame] | 330 | match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev); |
Kevin Liu | 943647f | 2013-03-25 17:42:58 +0800 | [diff] [blame] | 331 | if (match) { |
Simon Baatz | d2cf607 | 2013-06-09 22:14:15 +0200 | [diff] [blame] | 332 | ret = mmc_of_parse(host->mmc); |
| 333 | if (ret) |
| 334 | goto err_of_parse; |
Kevin Liu | 943647f | 2013-03-25 17:42:58 +0800 | [diff] [blame] | 335 | sdhci_get_of_property(pdev); |
Chris Ball | b650352 | 2012-04-10 22:34:33 -0400 | [diff] [blame] | 336 | pdata = pxav3_get_mmc_pdata(dev); |
Kevin Liu | 943647f | 2013-03-25 17:42:58 +0800 | [diff] [blame] | 337 | } else if (pdata) { |
Kevin Liu | c844a46 | 2013-03-25 17:42:57 +0800 | [diff] [blame] | 338 | /* on-chip device */ |
| 339 | if (pdata->flags & PXA_FLAG_CARD_PERMANENT) |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 340 | host->mmc->caps |= MMC_CAP_NONREMOVABLE; |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 341 | |
| 342 | /* If slot design supports 8 bit data, indicate this to MMC. */ |
| 343 | if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT) |
| 344 | host->mmc->caps |= MMC_CAP_8_BIT_DATA; |
| 345 | |
| 346 | if (pdata->quirks) |
| 347 | host->quirks |= pdata->quirks; |
Kevin Liu | 7c52d7bb | 2012-10-17 19:04:48 +0800 | [diff] [blame] | 348 | if (pdata->quirks2) |
| 349 | host->quirks2 |= pdata->quirks2; |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 350 | if (pdata->host_caps) |
| 351 | host->mmc->caps |= pdata->host_caps; |
Chris Ball | 8f63795 | 2012-09-19 16:29:12 +0800 | [diff] [blame] | 352 | if (pdata->host_caps2) |
| 353 | host->mmc->caps2 |= pdata->host_caps2; |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 354 | if (pdata->pm_caps) |
| 355 | host->mmc->pm_caps |= pdata->pm_caps; |
Chris Ball | 8f63795 | 2012-09-19 16:29:12 +0800 | [diff] [blame] | 356 | |
| 357 | if (gpio_is_valid(pdata->ext_cd_gpio)) { |
Laurent Pinchart | 214fc30 | 2013-08-08 12:38:31 +0200 | [diff] [blame] | 358 | ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio, |
| 359 | 0); |
Chris Ball | 8f63795 | 2012-09-19 16:29:12 +0800 | [diff] [blame] | 360 | if (ret) { |
| 361 | dev_err(mmc_dev(host->mmc), |
| 362 | "failed to allocate card detect gpio\n"); |
| 363 | goto err_cd_req; |
| 364 | } |
| 365 | } |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 366 | } |
| 367 | |
Jisheng Zhang | 62cf983 | 2015-01-04 23:15:47 +0800 | [diff] [blame] | 368 | pm_runtime_get_noresume(&pdev->dev); |
| 369 | pm_runtime_set_active(&pdev->dev); |
Kevin Liu | bb691ae | 2013-02-01 17:48:30 +0800 | [diff] [blame] | 370 | pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS); |
| 371 | pm_runtime_use_autosuspend(&pdev->dev); |
Jisheng Zhang | 62cf983 | 2015-01-04 23:15:47 +0800 | [diff] [blame] | 372 | pm_runtime_enable(&pdev->dev); |
Kevin Liu | bb691ae | 2013-02-01 17:48:30 +0800 | [diff] [blame] | 373 | pm_suspend_ignore_children(&pdev->dev, 1); |
Kevin Liu | bb691ae | 2013-02-01 17:48:30 +0800 | [diff] [blame] | 374 | |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 375 | ret = sdhci_add_host(host); |
| 376 | if (ret) { |
| 377 | dev_err(&pdev->dev, "failed to add host\n"); |
| 378 | goto err_add_host; |
| 379 | } |
| 380 | |
| 381 | platform_set_drvdata(pdev, host); |
| 382 | |
Kevin Liu | 943647f | 2013-03-25 17:42:58 +0800 | [diff] [blame] | 383 | if (host->mmc->pm_caps & MMC_PM_KEEP_POWER) { |
Kevin Liu | 740b7a4 | 2013-01-14 14:38:53 -0500 | [diff] [blame] | 384 | device_init_wakeup(&pdev->dev, 1); |
| 385 | host->mmc->pm_flags |= MMC_PM_WAKE_SDIO_IRQ; |
| 386 | } else { |
| 387 | device_init_wakeup(&pdev->dev, 0); |
| 388 | } |
| 389 | |
Kevin Liu | bb691ae | 2013-02-01 17:48:30 +0800 | [diff] [blame] | 390 | pm_runtime_put_autosuspend(&pdev->dev); |
| 391 | |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 392 | return 0; |
| 393 | |
| 394 | err_add_host: |
Daniel Drake | 0dcaa24 | 2013-06-27 11:46:29 -0400 | [diff] [blame] | 395 | pm_runtime_disable(&pdev->dev); |
Jisheng Zhang | 62cf983 | 2015-01-04 23:15:47 +0800 | [diff] [blame] | 396 | pm_runtime_put_noidle(&pdev->dev); |
Xiang Wang | 87d2163 | 2014-07-16 15:50:09 +0800 | [diff] [blame] | 397 | err_of_parse: |
| 398 | err_cd_req: |
Thomas Petazzoni | aa8165f | 2014-12-31 11:54:10 +0100 | [diff] [blame] | 399 | err_mbus_win: |
Sebastian Hesselbarth | 8c96a7a | 2014-10-21 11:22:38 +0200 | [diff] [blame] | 400 | clk_disable_unprepare(pxa->clk_io); |
Jisheng Zhang | c25d9e1 | 2015-01-05 15:59:19 +0800 | [diff] [blame] | 401 | clk_disable_unprepare(pxa->clk_core); |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 402 | err_clk_get: |
| 403 | sdhci_pltfm_free(pdev); |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 404 | return ret; |
| 405 | } |
| 406 | |
Bill Pemberton | 6e0ee71 | 2012-11-19 13:26:03 -0500 | [diff] [blame] | 407 | static int sdhci_pxav3_remove(struct platform_device *pdev) |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 408 | { |
| 409 | struct sdhci_host *host = platform_get_drvdata(pdev); |
| 410 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
Sebastian Hesselbarth | 8c96a7a | 2014-10-21 11:22:38 +0200 | [diff] [blame] | 411 | struct sdhci_pxa *pxa = pltfm_host->priv; |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 412 | |
Kevin Liu | bb691ae | 2013-02-01 17:48:30 +0800 | [diff] [blame] | 413 | pm_runtime_get_sync(&pdev->dev); |
Kevin Liu | bb691ae | 2013-02-01 17:48:30 +0800 | [diff] [blame] | 414 | pm_runtime_disable(&pdev->dev); |
Jisheng Zhang | 20f1f2d | 2015-01-04 23:15:48 +0800 | [diff] [blame] | 415 | pm_runtime_put_noidle(&pdev->dev); |
| 416 | |
| 417 | sdhci_remove_host(host, 1); |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 418 | |
Sebastian Hesselbarth | 8c96a7a | 2014-10-21 11:22:38 +0200 | [diff] [blame] | 419 | clk_disable_unprepare(pxa->clk_io); |
Jisheng Zhang | c25d9e1 | 2015-01-05 15:59:19 +0800 | [diff] [blame] | 420 | clk_disable_unprepare(pxa->clk_core); |
Chris Ball | 8f63795 | 2012-09-19 16:29:12 +0800 | [diff] [blame] | 421 | |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 422 | sdhci_pltfm_free(pdev); |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 423 | |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 424 | return 0; |
| 425 | } |
| 426 | |
Kevin Liu | bb691ae | 2013-02-01 17:48:30 +0800 | [diff] [blame] | 427 | #ifdef CONFIG_PM_SLEEP |
| 428 | static int sdhci_pxav3_suspend(struct device *dev) |
| 429 | { |
| 430 | int ret; |
| 431 | struct sdhci_host *host = dev_get_drvdata(dev); |
| 432 | |
| 433 | pm_runtime_get_sync(dev); |
| 434 | ret = sdhci_suspend_host(host); |
| 435 | pm_runtime_mark_last_busy(dev); |
| 436 | pm_runtime_put_autosuspend(dev); |
| 437 | |
| 438 | return ret; |
| 439 | } |
| 440 | |
| 441 | static int sdhci_pxav3_resume(struct device *dev) |
| 442 | { |
| 443 | int ret; |
| 444 | struct sdhci_host *host = dev_get_drvdata(dev); |
| 445 | |
| 446 | pm_runtime_get_sync(dev); |
| 447 | ret = sdhci_resume_host(host); |
| 448 | pm_runtime_mark_last_busy(dev); |
| 449 | pm_runtime_put_autosuspend(dev); |
| 450 | |
| 451 | return ret; |
| 452 | } |
| 453 | #endif |
| 454 | |
Rafael J. Wysocki | 162d6f9 | 2014-12-05 03:05:33 +0100 | [diff] [blame] | 455 | #ifdef CONFIG_PM |
Kevin Liu | bb691ae | 2013-02-01 17:48:30 +0800 | [diff] [blame] | 456 | static int sdhci_pxav3_runtime_suspend(struct device *dev) |
| 457 | { |
| 458 | struct sdhci_host *host = dev_get_drvdata(dev); |
| 459 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
Sebastian Hesselbarth | 8c96a7a | 2014-10-21 11:22:38 +0200 | [diff] [blame] | 460 | struct sdhci_pxa *pxa = pltfm_host->priv; |
Jisheng Zhang | 3bb10f6 | 2015-01-23 18:08:21 +0800 | [diff] [blame] | 461 | int ret; |
Kevin Liu | bb691ae | 2013-02-01 17:48:30 +0800 | [diff] [blame] | 462 | |
Jisheng Zhang | 3bb10f6 | 2015-01-23 18:08:21 +0800 | [diff] [blame] | 463 | ret = sdhci_runtime_suspend_host(host); |
| 464 | if (ret) |
| 465 | return ret; |
Kevin Liu | bb691ae | 2013-02-01 17:48:30 +0800 | [diff] [blame] | 466 | |
Sebastian Hesselbarth | 8c96a7a | 2014-10-21 11:22:38 +0200 | [diff] [blame] | 467 | clk_disable_unprepare(pxa->clk_io); |
Sebastian Hesselbarth | 8afdc9c | 2014-10-21 11:22:40 +0200 | [diff] [blame] | 468 | if (!IS_ERR(pxa->clk_core)) |
| 469 | clk_disable_unprepare(pxa->clk_core); |
Kevin Liu | bb691ae | 2013-02-01 17:48:30 +0800 | [diff] [blame] | 470 | |
| 471 | return 0; |
| 472 | } |
| 473 | |
| 474 | static int sdhci_pxav3_runtime_resume(struct device *dev) |
| 475 | { |
| 476 | struct sdhci_host *host = dev_get_drvdata(dev); |
| 477 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
Sebastian Hesselbarth | 8c96a7a | 2014-10-21 11:22:38 +0200 | [diff] [blame] | 478 | struct sdhci_pxa *pxa = pltfm_host->priv; |
Kevin Liu | bb691ae | 2013-02-01 17:48:30 +0800 | [diff] [blame] | 479 | |
Sebastian Hesselbarth | 8c96a7a | 2014-10-21 11:22:38 +0200 | [diff] [blame] | 480 | clk_prepare_enable(pxa->clk_io); |
Sebastian Hesselbarth | 8afdc9c | 2014-10-21 11:22:40 +0200 | [diff] [blame] | 481 | if (!IS_ERR(pxa->clk_core)) |
| 482 | clk_prepare_enable(pxa->clk_core); |
Kevin Liu | bb691ae | 2013-02-01 17:48:30 +0800 | [diff] [blame] | 483 | |
Jisheng Zhang | 3bb10f6 | 2015-01-23 18:08:21 +0800 | [diff] [blame] | 484 | return sdhci_runtime_resume_host(host); |
Kevin Liu | bb691ae | 2013-02-01 17:48:30 +0800 | [diff] [blame] | 485 | } |
| 486 | #endif |
| 487 | |
| 488 | #ifdef CONFIG_PM |
| 489 | static const struct dev_pm_ops sdhci_pxav3_pmops = { |
| 490 | SET_SYSTEM_SLEEP_PM_OPS(sdhci_pxav3_suspend, sdhci_pxav3_resume) |
| 491 | SET_RUNTIME_PM_OPS(sdhci_pxav3_runtime_suspend, |
| 492 | sdhci_pxav3_runtime_resume, NULL) |
| 493 | }; |
| 494 | |
| 495 | #define SDHCI_PXAV3_PMOPS (&sdhci_pxav3_pmops) |
| 496 | |
| 497 | #else |
| 498 | #define SDHCI_PXAV3_PMOPS NULL |
| 499 | #endif |
| 500 | |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 501 | static struct platform_driver sdhci_pxav3_driver = { |
| 502 | .driver = { |
| 503 | .name = "sdhci-pxav3", |
Chris Ball | b650352 | 2012-04-10 22:34:33 -0400 | [diff] [blame] | 504 | #ifdef CONFIG_OF |
| 505 | .of_match_table = sdhci_pxav3_of_match, |
| 506 | #endif |
Kevin Liu | bb691ae | 2013-02-01 17:48:30 +0800 | [diff] [blame] | 507 | .pm = SDHCI_PXAV3_PMOPS, |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 508 | }, |
| 509 | .probe = sdhci_pxav3_probe, |
Bill Pemberton | 0433c14 | 2012-11-19 13:20:26 -0500 | [diff] [blame] | 510 | .remove = sdhci_pxav3_remove, |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 511 | }; |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 512 | |
Axel Lin | d1f81a6 | 2011-11-26 12:55:43 +0800 | [diff] [blame] | 513 | module_platform_driver(sdhci_pxav3_driver); |
Zhangfei Gao | a702c8a | 2011-06-08 17:41:57 +0800 | [diff] [blame] | 514 | |
| 515 | MODULE_DESCRIPTION("SDHCI driver for pxav3"); |
| 516 | MODULE_AUTHOR("Marvell International Ltd."); |
| 517 | MODULE_LICENSE("GPL v2"); |
| 518 | |