Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
| 2 | */ |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 3 | /* |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 4 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 6 | * All Rights Reserved. |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 7 | * |
| 8 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 9 | * copy of this software and associated documentation files (the |
| 10 | * "Software"), to deal in the Software without restriction, including |
| 11 | * without limitation the rights to use, copy, modify, merge, publish, |
| 12 | * distribute, sub license, and/or sell copies of the Software, and to |
| 13 | * permit persons to whom the Software is furnished to do so, subject to |
| 14 | * the following conditions: |
| 15 | * |
| 16 | * The above copyright notice and this permission notice (including the |
| 17 | * next paragraph) shall be included in all copies or substantial portions |
| 18 | * of the Software. |
| 19 | * |
| 20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 27 | * |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 28 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | |
| 30 | #ifndef _I915_DRV_H_ |
| 31 | #define _I915_DRV_H_ |
| 32 | |
Chris Wilson | e9b73c6 | 2012-12-03 21:03:14 +0000 | [diff] [blame] | 33 | #include <uapi/drm/i915_drm.h> |
| 34 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 35 | #include "i915_reg.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 36 | #include "intel_bios.h" |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 37 | #include "intel_ringbuffer.h" |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 38 | #include <linux/io-mapping.h> |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 39 | #include <linux/i2c.h> |
Daniel Vetter | c167a6f | 2012-02-28 00:43:09 +0100 | [diff] [blame] | 40 | #include <linux/i2c-algo-bit.h> |
Daniel Vetter | 0ade638 | 2010-08-24 22:18:41 +0200 | [diff] [blame] | 41 | #include <drm/intel-gtt.h> |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 42 | #include <linux/backlight.h> |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 43 | #include <linux/intel-iommu.h> |
Daniel Vetter | 742cbee | 2012-04-27 15:17:39 +0200 | [diff] [blame] | 44 | #include <linux/kref.h> |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 45 | #include <linux/pm_qos.h> |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 46 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 47 | /* General customization: |
| 48 | */ |
| 49 | |
| 50 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." |
| 51 | |
| 52 | #define DRIVER_NAME "i915" |
| 53 | #define DRIVER_DESC "Intel Graphics" |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 54 | #define DRIVER_DATE "20080730" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 55 | |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 56 | enum pipe { |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 57 | INVALID_PIPE = -1, |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 58 | PIPE_A = 0, |
| 59 | PIPE_B, |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 60 | PIPE_C, |
| 61 | I915_MAX_PIPES |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 62 | }; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 63 | #define pipe_name(p) ((p) + 'A') |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 64 | |
Paulo Zanoni | a5c961d | 2012-10-24 15:59:34 -0200 | [diff] [blame] | 65 | enum transcoder { |
| 66 | TRANSCODER_A = 0, |
| 67 | TRANSCODER_B, |
| 68 | TRANSCODER_C, |
| 69 | TRANSCODER_EDP = 0xF, |
| 70 | }; |
| 71 | #define transcoder_name(t) ((t) + 'A') |
| 72 | |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 73 | enum plane { |
| 74 | PLANE_A = 0, |
| 75 | PLANE_B, |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 76 | PLANE_C, |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 77 | }; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 78 | #define plane_name(p) ((p) + 'A') |
Keith Packard | 5244021 | 2008-11-18 09:30:25 -0800 | [diff] [blame] | 79 | |
Ville Syrjälä | 06da8da | 2013-04-17 17:48:51 +0300 | [diff] [blame] | 80 | #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A') |
| 81 | |
Eugeni Dodonov | 2b13952 | 2012-03-29 12:32:22 -0300 | [diff] [blame] | 82 | enum port { |
| 83 | PORT_A = 0, |
| 84 | PORT_B, |
| 85 | PORT_C, |
| 86 | PORT_D, |
| 87 | PORT_E, |
| 88 | I915_MAX_PORTS |
| 89 | }; |
| 90 | #define port_name(p) ((p) + 'A') |
| 91 | |
Paulo Zanoni | b97186f | 2013-05-03 12:15:36 -0300 | [diff] [blame] | 92 | enum intel_display_power_domain { |
| 93 | POWER_DOMAIN_PIPE_A, |
| 94 | POWER_DOMAIN_PIPE_B, |
| 95 | POWER_DOMAIN_PIPE_C, |
| 96 | POWER_DOMAIN_PIPE_A_PANEL_FITTER, |
| 97 | POWER_DOMAIN_PIPE_B_PANEL_FITTER, |
| 98 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, |
| 99 | POWER_DOMAIN_TRANSCODER_A, |
| 100 | POWER_DOMAIN_TRANSCODER_B, |
| 101 | POWER_DOMAIN_TRANSCODER_C, |
Imre Deak | f52e353 | 2013-10-16 17:25:48 +0300 | [diff] [blame] | 102 | POWER_DOMAIN_TRANSCODER_EDP, |
Ville Syrjälä | cdf8dd7 | 2013-09-16 17:38:30 +0300 | [diff] [blame] | 103 | POWER_DOMAIN_VGA, |
Imre Deak | baa7070 | 2013-10-25 17:36:48 +0300 | [diff] [blame] | 104 | POWER_DOMAIN_INIT, |
Imre Deak | bddc764 | 2013-10-16 17:25:49 +0300 | [diff] [blame] | 105 | |
| 106 | POWER_DOMAIN_NUM, |
Paulo Zanoni | b97186f | 2013-05-03 12:15:36 -0300 | [diff] [blame] | 107 | }; |
| 108 | |
Imre Deak | bddc764 | 2013-10-16 17:25:49 +0300 | [diff] [blame] | 109 | #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1) |
| 110 | |
Paulo Zanoni | b97186f | 2013-05-03 12:15:36 -0300 | [diff] [blame] | 111 | #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) |
| 112 | #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ |
| 113 | ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) |
Imre Deak | f52e353 | 2013-10-16 17:25:48 +0300 | [diff] [blame] | 114 | #define POWER_DOMAIN_TRANSCODER(tran) \ |
| 115 | ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ |
| 116 | (tran) + POWER_DOMAIN_TRANSCODER_A) |
Paulo Zanoni | b97186f | 2013-05-03 12:15:36 -0300 | [diff] [blame] | 117 | |
Imre Deak | bddc764 | 2013-10-16 17:25:49 +0300 | [diff] [blame] | 118 | #define HSW_ALWAYS_ON_POWER_DOMAINS ( \ |
| 119 | BIT(POWER_DOMAIN_PIPE_A) | \ |
| 120 | BIT(POWER_DOMAIN_TRANSCODER_EDP)) |
Paulo Zanoni | 6745a2c | 2013-11-02 21:07:34 -0700 | [diff] [blame] | 121 | #define BDW_ALWAYS_ON_POWER_DOMAINS ( \ |
| 122 | BIT(POWER_DOMAIN_PIPE_A) | \ |
| 123 | BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ |
| 124 | BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER)) |
Imre Deak | bddc764 | 2013-10-16 17:25:49 +0300 | [diff] [blame] | 125 | |
Egbert Eich | 1d843f9 | 2013-02-25 12:06:49 -0500 | [diff] [blame] | 126 | enum hpd_pin { |
| 127 | HPD_NONE = 0, |
| 128 | HPD_PORT_A = HPD_NONE, /* PORT_A is internal */ |
| 129 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ |
| 130 | HPD_CRT, |
| 131 | HPD_SDVO_B, |
| 132 | HPD_SDVO_C, |
| 133 | HPD_PORT_B, |
| 134 | HPD_PORT_C, |
| 135 | HPD_PORT_D, |
| 136 | HPD_NUM_PINS |
| 137 | }; |
| 138 | |
Chris Wilson | 2a2d548 | 2012-12-03 11:49:06 +0000 | [diff] [blame] | 139 | #define I915_GEM_GPU_DOMAINS \ |
| 140 | (I915_GEM_DOMAIN_RENDER | \ |
| 141 | I915_GEM_DOMAIN_SAMPLER | \ |
| 142 | I915_GEM_DOMAIN_COMMAND | \ |
| 143 | I915_GEM_DOMAIN_INSTRUCTION | \ |
| 144 | I915_GEM_DOMAIN_VERTEX) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 145 | |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 146 | #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++) |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 147 | |
Daniel Vetter | 6c2b7c12 | 2012-07-05 09:50:24 +0200 | [diff] [blame] | 148 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
| 149 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ |
| 150 | if ((intel_encoder)->base.crtc == (__crtc)) |
| 151 | |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 152 | struct drm_i915_private; |
| 153 | |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 154 | enum intel_dpll_id { |
| 155 | DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ |
| 156 | /* real shared dpll ids must be >= 0 */ |
| 157 | DPLL_ID_PCH_PLL_A, |
| 158 | DPLL_ID_PCH_PLL_B, |
| 159 | }; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 160 | #define I915_NUM_PLLS 2 |
| 161 | |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 162 | struct intel_dpll_hw_state { |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 163 | uint32_t dpll; |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 164 | uint32_t dpll_md; |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 165 | uint32_t fp0; |
| 166 | uint32_t fp1; |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 167 | }; |
| 168 | |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 169 | struct intel_shared_dpll { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 170 | int refcount; /* count of number of CRTCs sharing this PLL */ |
| 171 | int active; /* count of number of active CRTCs (i.e. DPMS on) */ |
| 172 | bool on; /* is the PLL actually active? Disabled during modeset */ |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 173 | const char *name; |
| 174 | /* should match the index in the dev_priv->shared_dplls array */ |
| 175 | enum intel_dpll_id id; |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 176 | struct intel_dpll_hw_state hw_state; |
Daniel Vetter | 15bdd4c | 2013-06-05 13:34:23 +0200 | [diff] [blame] | 177 | void (*mode_set)(struct drm_i915_private *dev_priv, |
| 178 | struct intel_shared_dpll *pll); |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 179 | void (*enable)(struct drm_i915_private *dev_priv, |
| 180 | struct intel_shared_dpll *pll); |
| 181 | void (*disable)(struct drm_i915_private *dev_priv, |
| 182 | struct intel_shared_dpll *pll); |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 183 | bool (*get_hw_state)(struct drm_i915_private *dev_priv, |
| 184 | struct intel_shared_dpll *pll, |
| 185 | struct intel_dpll_hw_state *hw_state); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 186 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 187 | |
Daniel Vetter | e69d0bc | 2012-11-29 15:59:36 +0100 | [diff] [blame] | 188 | /* Used by dp and fdi links */ |
| 189 | struct intel_link_m_n { |
| 190 | uint32_t tu; |
| 191 | uint32_t gmch_m; |
| 192 | uint32_t gmch_n; |
| 193 | uint32_t link_m; |
| 194 | uint32_t link_n; |
| 195 | }; |
| 196 | |
| 197 | void intel_link_compute_m_n(int bpp, int nlanes, |
| 198 | int pixel_clock, int link_clock, |
| 199 | struct intel_link_m_n *m_n); |
| 200 | |
Paulo Zanoni | 6441ab5 | 2012-10-05 12:05:58 -0300 | [diff] [blame] | 201 | struct intel_ddi_plls { |
| 202 | int spll_refcount; |
| 203 | int wrpll1_refcount; |
| 204 | int wrpll2_refcount; |
| 205 | }; |
| 206 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 207 | /* Interface history: |
| 208 | * |
| 209 | * 1.1: Original. |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 210 | * 1.2: Add Power Management |
| 211 | * 1.3: Add vblank support |
Dave Airlie | de227f5 | 2006-01-25 15:31:43 +1100 | [diff] [blame] | 212 | * 1.4: Fix cmdbuffer path, add heap destroy |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 213 | * 1.5: Add vblank pipe configuration |
=?utf-8?q?Michel_D=C3=A4nzer?= | 2228ed6 | 2006-10-25 01:05:09 +1000 | [diff] [blame] | 214 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
| 215 | * - Support vertical blank on secondary display pipe |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 216 | */ |
| 217 | #define DRIVER_MAJOR 1 |
=?utf-8?q?Michel_D=C3=A4nzer?= | 2228ed6 | 2006-10-25 01:05:09 +1000 | [diff] [blame] | 218 | #define DRIVER_MINOR 6 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 219 | #define DRIVER_PATCHLEVEL 0 |
| 220 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 221 | #define WATCH_LISTS 0 |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 222 | #define WATCH_GTT 0 |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 223 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 224 | #define I915_GEM_PHYS_CURSOR_0 1 |
| 225 | #define I915_GEM_PHYS_CURSOR_1 2 |
| 226 | #define I915_GEM_PHYS_OVERLAY_REGS 3 |
| 227 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) |
| 228 | |
| 229 | struct drm_i915_gem_phys_object { |
| 230 | int id; |
| 231 | struct page **page_list; |
| 232 | drm_dma_handle_t *handle; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 233 | struct drm_i915_gem_object *cur_obj; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 234 | }; |
| 235 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 236 | struct opregion_header; |
| 237 | struct opregion_acpi; |
| 238 | struct opregion_swsci; |
| 239 | struct opregion_asle; |
| 240 | |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 241 | struct intel_opregion { |
Ben Widawsky | 5bc4418 | 2012-04-16 14:07:42 -0700 | [diff] [blame] | 242 | struct opregion_header __iomem *header; |
| 243 | struct opregion_acpi __iomem *acpi; |
| 244 | struct opregion_swsci __iomem *swsci; |
Jani Nikula | ebde53c | 2013-09-02 10:38:59 +0300 | [diff] [blame] | 245 | u32 swsci_gbda_sub_functions; |
| 246 | u32 swsci_sbcb_sub_functions; |
Ben Widawsky | 5bc4418 | 2012-04-16 14:07:42 -0700 | [diff] [blame] | 247 | struct opregion_asle __iomem *asle; |
| 248 | void __iomem *vbt; |
Chris Wilson | 01fe9db | 2011-01-16 19:37:30 +0000 | [diff] [blame] | 249 | u32 __iomem *lid_state; |
Jani Nikula | 91a60f2 | 2013-10-31 18:55:48 +0200 | [diff] [blame] | 250 | struct work_struct asle_work; |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 251 | }; |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 252 | #define OPREGION_SIZE (8*1024) |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 253 | |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 254 | struct intel_overlay; |
| 255 | struct intel_overlay_error_state; |
| 256 | |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 257 | struct drm_i915_master_private { |
| 258 | drm_local_map_t *sarea; |
| 259 | struct _drm_i915_sarea *sarea_priv; |
| 260 | }; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 261 | #define I915_FENCE_REG_NONE -1 |
Ville Syrjälä | 42b5aea | 2013-04-09 13:02:47 +0300 | [diff] [blame] | 262 | #define I915_MAX_NUM_FENCES 32 |
| 263 | /* 32 fences + sign bit for FENCE_REG_NONE */ |
| 264 | #define I915_MAX_NUM_FENCE_BITS 6 |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 265 | |
| 266 | struct drm_i915_fence_reg { |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 267 | struct list_head lru_list; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 268 | struct drm_i915_gem_object *obj; |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 269 | int pin_count; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 270 | }; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 271 | |
yakui_zhao | 9b9d172 | 2009-05-31 17:17:17 +0800 | [diff] [blame] | 272 | struct sdvo_device_mapping { |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 273 | u8 initialized; |
yakui_zhao | 9b9d172 | 2009-05-31 17:17:17 +0800 | [diff] [blame] | 274 | u8 dvo_port; |
| 275 | u8 slave_addr; |
| 276 | u8 dvo_wiring; |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 277 | u8 i2c_pin; |
Adam Jackson | b108333 | 2010-04-23 16:07:40 -0400 | [diff] [blame] | 278 | u8 ddc_pin; |
yakui_zhao | 9b9d172 | 2009-05-31 17:17:17 +0800 | [diff] [blame] | 279 | }; |
| 280 | |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 281 | struct intel_display_error_state; |
| 282 | |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 283 | struct drm_i915_error_state { |
Daniel Vetter | 742cbee | 2012-04-27 15:17:39 +0200 | [diff] [blame] | 284 | struct kref ref; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 285 | u32 eir; |
| 286 | u32 pgtbl_er; |
Ben Widawsky | be998e2 | 2012-04-26 16:03:00 -0700 | [diff] [blame] | 287 | u32 ier; |
Ben Widawsky | b9a3906 | 2012-06-04 14:42:52 -0700 | [diff] [blame] | 288 | u32 ccid; |
Chris Wilson | 0f3b684 | 2013-01-15 12:05:55 +0000 | [diff] [blame] | 289 | u32 derrmr; |
| 290 | u32 forcewake; |
Ben Widawsky | 9574b3f | 2012-04-26 16:03:01 -0700 | [diff] [blame] | 291 | bool waiting[I915_NUM_RINGS]; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 292 | u32 pipestat[I915_MAX_PIPES]; |
Daniel Vetter | c1cd90e | 2011-12-14 13:57:02 +0100 | [diff] [blame] | 293 | u32 tail[I915_NUM_RINGS]; |
| 294 | u32 head[I915_NUM_RINGS]; |
Chris Wilson | 0f3b684 | 2013-01-15 12:05:55 +0000 | [diff] [blame] | 295 | u32 ctl[I915_NUM_RINGS]; |
Daniel Vetter | d27b1e0 | 2011-12-14 13:57:01 +0100 | [diff] [blame] | 296 | u32 ipeir[I915_NUM_RINGS]; |
| 297 | u32 ipehr[I915_NUM_RINGS]; |
| 298 | u32 instdone[I915_NUM_RINGS]; |
| 299 | u32 acthd[I915_NUM_RINGS]; |
Daniel Vetter | 7e3b873 | 2012-02-01 22:26:45 +0100 | [diff] [blame] | 300 | u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; |
Chris Wilson | df2b23d | 2012-11-27 17:06:54 +0000 | [diff] [blame] | 301 | u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1]; |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 302 | u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */ |
Daniel Vetter | 7e3b873 | 2012-02-01 22:26:45 +0100 | [diff] [blame] | 303 | /* our own tracking of ring head and tail */ |
| 304 | u32 cpu_ring_head[I915_NUM_RINGS]; |
| 305 | u32 cpu_ring_tail[I915_NUM_RINGS]; |
Chris Wilson | 1d8f38f | 2010-10-29 19:00:51 +0100 | [diff] [blame] | 306 | u32 error; /* gen6+ */ |
Ben Widawsky | 71e172e | 2012-08-20 16:15:13 -0700 | [diff] [blame] | 307 | u32 err_int; /* gen7 */ |
Chris Wilson | 94e39e2 | 2013-10-30 09:28:22 +0000 | [diff] [blame] | 308 | u32 bbstate[I915_NUM_RINGS]; |
Daniel Vetter | c1cd90e | 2011-12-14 13:57:02 +0100 | [diff] [blame] | 309 | u32 instpm[I915_NUM_RINGS]; |
| 310 | u32 instps[I915_NUM_RINGS]; |
Ben Widawsky | 050ee91 | 2012-08-22 11:32:15 -0700 | [diff] [blame] | 311 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; |
Daniel Vetter | d27b1e0 | 2011-12-14 13:57:01 +0100 | [diff] [blame] | 312 | u32 seqno[I915_NUM_RINGS]; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 313 | u64 bbaddr; |
Daniel Vetter | 33f3f51 | 2011-12-14 13:57:39 +0100 | [diff] [blame] | 314 | u32 fault_reg[I915_NUM_RINGS]; |
| 315 | u32 done_reg; |
Daniel Vetter | c1cd90e | 2011-12-14 13:57:02 +0100 | [diff] [blame] | 316 | u32 faddr[I915_NUM_RINGS]; |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 317 | u64 fence[I915_MAX_NUM_FENCES]; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 318 | struct timeval time; |
Chris Wilson | 52d39a2 | 2012-02-15 11:25:37 +0000 | [diff] [blame] | 319 | struct drm_i915_error_ring { |
| 320 | struct drm_i915_error_object { |
| 321 | int page_count; |
| 322 | u32 gtt_offset; |
| 323 | u32 *pages[0]; |
Ben Widawsky | 8c123e5 | 2013-03-04 17:00:29 -0800 | [diff] [blame] | 324 | } *ringbuffer, *batchbuffer, *ctx; |
Chris Wilson | 52d39a2 | 2012-02-15 11:25:37 +0000 | [diff] [blame] | 325 | struct drm_i915_error_request { |
| 326 | long jiffies; |
| 327 | u32 seqno; |
Chris Wilson | ee4f42b | 2012-02-15 11:25:38 +0000 | [diff] [blame] | 328 | u32 tail; |
Chris Wilson | 52d39a2 | 2012-02-15 11:25:37 +0000 | [diff] [blame] | 329 | } *requests; |
| 330 | int num_requests; |
| 331 | } ring[I915_NUM_RINGS]; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 332 | struct drm_i915_error_buffer { |
Chris Wilson | a779e5a | 2011-01-09 21:07:49 +0000 | [diff] [blame] | 333 | u32 size; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 334 | u32 name; |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 335 | u32 rseqno, wseqno; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 336 | u32 gtt_offset; |
| 337 | u32 read_domains; |
| 338 | u32 write_domain; |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 339 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 340 | s32 pinned:2; |
| 341 | u32 tiling:2; |
| 342 | u32 dirty:1; |
| 343 | u32 purgeable:1; |
Daniel Vetter | 5d1333f | 2012-02-16 11:03:29 +0100 | [diff] [blame] | 344 | s32 ring:4; |
Chris Wilson | f56383c | 2013-09-25 10:23:19 +0100 | [diff] [blame] | 345 | u32 cache_level:3; |
Ben Widawsky | 95f5301 | 2013-07-31 17:00:15 -0700 | [diff] [blame] | 346 | } **active_bo, **pinned_bo; |
| 347 | u32 *active_bo_count, *pinned_bo_count; |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 348 | struct intel_overlay_error_state *overlay; |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 349 | struct intel_display_error_state *display; |
Mika Kuoppala | da66146 | 2013-09-06 16:03:28 +0300 | [diff] [blame] | 350 | int hangcheck_score[I915_NUM_RINGS]; |
| 351 | enum intel_ring_hangcheck_action hangcheck_action[I915_NUM_RINGS]; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 352 | }; |
| 353 | |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 354 | struct intel_crtc_config; |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 355 | struct intel_crtc; |
Daniel Vetter | ee9300b | 2013-06-03 22:40:22 +0200 | [diff] [blame] | 356 | struct intel_limit; |
| 357 | struct dpll; |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 358 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 359 | struct drm_i915_display_funcs { |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 360 | bool (*fbc_enabled)(struct drm_device *dev); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 361 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
| 362 | void (*disable_fbc)(struct drm_device *dev); |
| 363 | int (*get_display_clock_speed)(struct drm_device *dev); |
| 364 | int (*get_fifo_size)(struct drm_device *dev, int plane); |
Daniel Vetter | ee9300b | 2013-06-03 22:40:22 +0200 | [diff] [blame] | 365 | /** |
| 366 | * find_dpll() - Find the best values for the PLL |
| 367 | * @limit: limits for the PLL |
| 368 | * @crtc: current CRTC |
| 369 | * @target: target frequency in kHz |
| 370 | * @refclk: reference clock frequency in kHz |
| 371 | * @match_clock: if provided, @best_clock P divider must |
| 372 | * match the P divider from @match_clock |
| 373 | * used for LVDS downclocking |
| 374 | * @best_clock: best PLL values found |
| 375 | * |
| 376 | * Returns true on success, false on failure. |
| 377 | */ |
| 378 | bool (*find_dpll)(const struct intel_limit *limit, |
| 379 | struct drm_crtc *crtc, |
| 380 | int target, int refclk, |
| 381 | struct dpll *match_clock, |
| 382 | struct dpll *best_clock); |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 383 | void (*update_wm)(struct drm_crtc *crtc); |
Ville Syrjälä | adf3d35 | 2013-08-06 22:24:11 +0300 | [diff] [blame] | 384 | void (*update_sprite_wm)(struct drm_plane *plane, |
| 385 | struct drm_crtc *crtc, |
Paulo Zanoni | 4c4ff43 | 2013-05-24 11:59:17 -0300 | [diff] [blame] | 386 | uint32_t sprite_width, int pixel_size, |
Ville Syrjälä | bdd57d0 | 2013-07-05 11:57:13 +0300 | [diff] [blame] | 387 | bool enable, bool scaled); |
Daniel Vetter | 47fab73 | 2012-10-26 10:58:18 +0200 | [diff] [blame] | 388 | void (*modeset_global_resources)(struct drm_device *dev); |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 389 | /* Returns the active state of the crtc, and if the crtc is active, |
| 390 | * fills out the pipe-config with the hw state. */ |
| 391 | bool (*get_pipe_config)(struct intel_crtc *, |
| 392 | struct intel_crtc_config *); |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 393 | int (*crtc_mode_set)(struct drm_crtc *crtc, |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 394 | int x, int y, |
| 395 | struct drm_framebuffer *old_fb); |
Daniel Vetter | 76e5a89 | 2012-06-29 22:39:33 +0200 | [diff] [blame] | 396 | void (*crtc_enable)(struct drm_crtc *crtc); |
| 397 | void (*crtc_disable)(struct drm_crtc *crtc); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 398 | void (*off)(struct drm_crtc *crtc); |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 399 | void (*write_eld)(struct drm_connector *connector, |
Jani Nikula | 3442705 | 2013-10-16 12:34:47 +0300 | [diff] [blame] | 400 | struct drm_crtc *crtc, |
| 401 | struct drm_display_mode *mode); |
Jesse Barnes | 674cf96 | 2011-04-28 14:27:04 -0700 | [diff] [blame] | 402 | void (*fdi_link_train)(struct drm_crtc *crtc); |
Jesse Barnes | 6067aae | 2011-04-28 15:04:31 -0700 | [diff] [blame] | 403 | void (*init_clock_gating)(struct drm_device *dev); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 404 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
| 405 | struct drm_framebuffer *fb, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 406 | struct drm_i915_gem_object *obj, |
| 407 | uint32_t flags); |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 408 | int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
| 409 | int x, int y); |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 410 | void (*hpd_irq_setup)(struct drm_device *dev); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 411 | /* clock updates for mode set */ |
| 412 | /* cursor updates */ |
| 413 | /* render clock increase/decrease */ |
| 414 | /* display clock increase/decrease */ |
| 415 | /* pll clock increase/decrease */ |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 416 | }; |
| 417 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 418 | struct intel_uncore_funcs { |
Chris Wilson | 990bbda | 2012-07-02 11:51:02 -0300 | [diff] [blame] | 419 | void (*force_wake_get)(struct drm_i915_private *dev_priv); |
| 420 | void (*force_wake_put)(struct drm_i915_private *dev_priv); |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 421 | |
| 422 | uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace); |
| 423 | uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace); |
| 424 | uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace); |
| 425 | uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace); |
| 426 | |
| 427 | void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset, |
| 428 | uint8_t val, bool trace); |
| 429 | void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset, |
| 430 | uint16_t val, bool trace); |
| 431 | void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset, |
| 432 | uint32_t val, bool trace); |
| 433 | void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset, |
| 434 | uint64_t val, bool trace); |
Chris Wilson | 990bbda | 2012-07-02 11:51:02 -0300 | [diff] [blame] | 435 | }; |
| 436 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 437 | struct intel_uncore { |
| 438 | spinlock_t lock; /** lock is also taken in irq contexts. */ |
| 439 | |
| 440 | struct intel_uncore_funcs funcs; |
| 441 | |
| 442 | unsigned fifo_count; |
| 443 | unsigned forcewake_count; |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 444 | |
| 445 | struct delayed_work force_wake_work; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 446 | }; |
| 447 | |
Damien Lespiau | 79fc46d | 2013-04-23 16:37:17 +0100 | [diff] [blame] | 448 | #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ |
| 449 | func(is_mobile) sep \ |
| 450 | func(is_i85x) sep \ |
| 451 | func(is_i915g) sep \ |
| 452 | func(is_i945gm) sep \ |
| 453 | func(is_g33) sep \ |
| 454 | func(need_gfx_hws) sep \ |
| 455 | func(is_g4x) sep \ |
| 456 | func(is_pineview) sep \ |
| 457 | func(is_broadwater) sep \ |
| 458 | func(is_crestline) sep \ |
| 459 | func(is_ivybridge) sep \ |
| 460 | func(is_valleyview) sep \ |
| 461 | func(is_haswell) sep \ |
Ben Widawsky | b833d68 | 2013-08-23 16:00:07 -0700 | [diff] [blame] | 462 | func(is_preliminary) sep \ |
Damien Lespiau | 79fc46d | 2013-04-23 16:37:17 +0100 | [diff] [blame] | 463 | func(has_fbc) sep \ |
| 464 | func(has_pipe_cxsr) sep \ |
| 465 | func(has_hotplug) sep \ |
| 466 | func(cursor_needs_physical) sep \ |
| 467 | func(has_overlay) sep \ |
| 468 | func(overlay_needs_physical) sep \ |
| 469 | func(supports_tv) sep \ |
Damien Lespiau | dd93be5 | 2013-04-22 18:40:39 +0100 | [diff] [blame] | 470 | func(has_llc) sep \ |
Damien Lespiau | 30568c4 | 2013-04-22 18:40:41 +0100 | [diff] [blame] | 471 | func(has_ddi) sep \ |
| 472 | func(has_fpga_dbg) |
Daniel Vetter | c96ea64 | 2012-08-08 22:01:51 +0200 | [diff] [blame] | 473 | |
Damien Lespiau | a587f77 | 2013-04-22 18:40:38 +0100 | [diff] [blame] | 474 | #define DEFINE_FLAG(name) u8 name:1 |
| 475 | #define SEP_SEMICOLON ; |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 476 | |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 477 | struct intel_device_info { |
Ville Syrjälä | 10fce67 | 2013-01-24 15:29:28 +0200 | [diff] [blame] | 478 | u32 display_mmio_offset; |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 479 | u8 num_pipes:3; |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 480 | u8 gen; |
Ben Widawsky | 73ae478 | 2013-10-15 10:02:57 -0700 | [diff] [blame] | 481 | u8 ring_mask; /* Rings supported by the HW */ |
Damien Lespiau | a587f77 | 2013-04-22 18:40:38 +0100 | [diff] [blame] | 482 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 483 | }; |
| 484 | |
Damien Lespiau | a587f77 | 2013-04-22 18:40:38 +0100 | [diff] [blame] | 485 | #undef DEFINE_FLAG |
| 486 | #undef SEP_SEMICOLON |
| 487 | |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 488 | enum i915_cache_level { |
| 489 | I915_CACHE_NONE = 0, |
Chris Wilson | 350ec88 | 2013-08-06 13:17:02 +0100 | [diff] [blame] | 490 | I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ |
| 491 | I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc |
| 492 | caches, eg sampler/render caches, and the |
| 493 | large Last-Level-Cache. LLC is coherent with |
| 494 | the CPU, but L3 is only visible to the GPU. */ |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 495 | I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 496 | }; |
| 497 | |
Kenneth Graunke | 2d04bef | 2013-04-22 00:53:49 -0700 | [diff] [blame] | 498 | typedef uint32_t gen6_gtt_pte_t; |
| 499 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 500 | struct i915_address_space { |
Ben Widawsky | 93bd864 | 2013-07-16 16:50:06 -0700 | [diff] [blame] | 501 | struct drm_mm mm; |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 502 | struct drm_device *dev; |
Ben Widawsky | a7bbbd6 | 2013-07-16 16:50:07 -0700 | [diff] [blame] | 503 | struct list_head global_link; |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 504 | unsigned long start; /* Start offset always 0 for dri2 */ |
| 505 | size_t total; /* size addr space maps (ex. 2GB for ggtt) */ |
| 506 | |
| 507 | struct { |
| 508 | dma_addr_t addr; |
| 509 | struct page *page; |
| 510 | } scratch; |
| 511 | |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 512 | /** |
| 513 | * List of objects currently involved in rendering. |
| 514 | * |
| 515 | * Includes buffers having the contents of their GPU caches |
| 516 | * flushed, not necessarily primitives. last_rendering_seqno |
| 517 | * represents when the rendering involved will be completed. |
| 518 | * |
| 519 | * A reference is held on the buffer while on this list. |
| 520 | */ |
| 521 | struct list_head active_list; |
| 522 | |
| 523 | /** |
| 524 | * LRU list of objects which are not in the ringbuffer and |
| 525 | * are ready to unbind, but are still in the GTT. |
| 526 | * |
| 527 | * last_rendering_seqno is 0 while an object is in this list. |
| 528 | * |
| 529 | * A reference is not held on the buffer while on this list, |
| 530 | * as merely being GTT-bound shouldn't prevent its being |
| 531 | * freed, and we'll pull it off the list in the free path. |
| 532 | */ |
| 533 | struct list_head inactive_list; |
| 534 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 535 | /* FIXME: Need a more generic return type */ |
| 536 | gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr, |
Ben Widawsky | b35b380 | 2013-10-16 09:18:21 -0700 | [diff] [blame] | 537 | enum i915_cache_level level, |
| 538 | bool valid); /* Create a valid PTE */ |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 539 | void (*clear_range)(struct i915_address_space *vm, |
| 540 | unsigned int first_entry, |
Ben Widawsky | 828c790 | 2013-10-16 09:21:30 -0700 | [diff] [blame] | 541 | unsigned int num_entries, |
| 542 | bool use_scratch); |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 543 | void (*insert_entries)(struct i915_address_space *vm, |
| 544 | struct sg_table *st, |
| 545 | unsigned int first_entry, |
| 546 | enum i915_cache_level cache_level); |
| 547 | void (*cleanup)(struct i915_address_space *vm); |
| 548 | }; |
| 549 | |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 550 | /* The Graphics Translation Table is the way in which GEN hardware translates a |
| 551 | * Graphics Virtual Address into a Physical Address. In addition to the normal |
| 552 | * collateral associated with any va->pa translations GEN hardware also has a |
| 553 | * portion of the GTT which can be mapped by the CPU and remain both coherent |
| 554 | * and correct (in cases like swizzling). That region is referred to as GMADR in |
| 555 | * the spec. |
| 556 | */ |
| 557 | struct i915_gtt { |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 558 | struct i915_address_space base; |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 559 | size_t stolen_size; /* Total size of stolen memory */ |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 560 | |
| 561 | unsigned long mappable_end; /* End offset that we can CPU map */ |
| 562 | struct io_mapping *mappable; /* Mapping to our CPU mappable region */ |
| 563 | phys_addr_t mappable_base; /* PA of our GMADR */ |
| 564 | |
| 565 | /** "Graphics Stolen Memory" holds the global PTEs */ |
| 566 | void __iomem *gsm; |
Ben Widawsky | a81cc00 | 2013-01-18 12:30:31 -0800 | [diff] [blame] | 567 | |
| 568 | bool do_idle_maps; |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 569 | |
Ben Widawsky | 911bdf0 | 2013-06-27 16:30:23 -0700 | [diff] [blame] | 570 | int mtrr; |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 571 | |
| 572 | /* global gtt ops */ |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 573 | int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total, |
Ben Widawsky | 41907dd | 2013-02-08 11:32:47 -0800 | [diff] [blame] | 574 | size_t *stolen, phys_addr_t *mappable_base, |
| 575 | unsigned long *mappable_end); |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 576 | }; |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 577 | #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT) |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 578 | |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 579 | struct i915_hw_ppgtt { |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 580 | struct i915_address_space base; |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 581 | unsigned num_pd_entries; |
Ben Widawsky | 37aca44 | 2013-11-04 20:47:32 -0800 | [diff] [blame] | 582 | union { |
| 583 | struct page **pt_pages; |
| 584 | struct page *gen8_pt_pages; |
| 585 | }; |
| 586 | struct page *pd_pages; |
| 587 | int num_pd_pages; |
| 588 | int num_pt_pages; |
| 589 | union { |
| 590 | uint32_t pd_offset; |
| 591 | dma_addr_t pd_dma_addr[4]; |
| 592 | }; |
| 593 | union { |
| 594 | dma_addr_t *pt_dma_addr; |
| 595 | dma_addr_t *gen8_pt_dma_addr[4]; |
| 596 | }; |
Ben Widawsky | b7c36d2 | 2013-04-08 18:43:56 -0700 | [diff] [blame] | 597 | int (*enable)(struct drm_device *dev); |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 598 | }; |
| 599 | |
Ben Widawsky | 0b02e79 | 2013-07-31 17:00:08 -0700 | [diff] [blame] | 600 | /** |
| 601 | * A VMA represents a GEM BO that is bound into an address space. Therefore, a |
| 602 | * VMA's presence cannot be guaranteed before binding, or after unbinding the |
| 603 | * object into/from the address space. |
| 604 | * |
| 605 | * To make things as simple as possible (ie. no refcounting), a VMA's lifetime |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 606 | * will always be <= an objects lifetime. So object refcounting should cover us. |
| 607 | */ |
| 608 | struct i915_vma { |
| 609 | struct drm_mm_node node; |
| 610 | struct drm_i915_gem_object *obj; |
| 611 | struct i915_address_space *vm; |
| 612 | |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 613 | /** This object's place on the active/inactive lists */ |
| 614 | struct list_head mm_list; |
| 615 | |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 616 | struct list_head vma_link; /* Link in the object's VMA list */ |
Ben Widawsky | 82a55ad | 2013-08-14 11:38:34 +0200 | [diff] [blame] | 617 | |
| 618 | /** This vma's place in the batchbuffer or on the eviction list */ |
| 619 | struct list_head exec_list; |
| 620 | |
Ben Widawsky | 27173f1 | 2013-08-14 11:38:36 +0200 | [diff] [blame] | 621 | /** |
| 622 | * Used for performing relocations during execbuffer insertion. |
| 623 | */ |
| 624 | struct hlist_node exec_node; |
| 625 | unsigned long exec_handle; |
| 626 | struct drm_i915_gem_exec_object2 *exec_entry; |
| 627 | |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 628 | }; |
| 629 | |
Mika Kuoppala | e59ec13 | 2013-06-12 12:35:28 +0300 | [diff] [blame] | 630 | struct i915_ctx_hang_stats { |
| 631 | /* This context had batch pending when hang was declared */ |
| 632 | unsigned batch_pending; |
| 633 | |
| 634 | /* This context had batch active when hang was declared */ |
| 635 | unsigned batch_active; |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 636 | |
| 637 | /* Time when this context was last blamed for a GPU reset */ |
| 638 | unsigned long guilty_ts; |
| 639 | |
| 640 | /* This context is banned to submit more work */ |
| 641 | bool banned; |
Mika Kuoppala | e59ec13 | 2013-06-12 12:35:28 +0300 | [diff] [blame] | 642 | }; |
Ben Widawsky | 4052105 | 2012-06-04 14:42:43 -0700 | [diff] [blame] | 643 | |
| 644 | /* This must match up with the value previously used for execbuf2.rsvd1. */ |
| 645 | #define DEFAULT_CONTEXT_ID 0 |
| 646 | struct i915_hw_context { |
Mika Kuoppala | dce3271 | 2013-04-30 13:30:33 +0300 | [diff] [blame] | 647 | struct kref ref; |
Ben Widawsky | 4052105 | 2012-06-04 14:42:43 -0700 | [diff] [blame] | 648 | int id; |
Ben Widawsky | e055684 | 2012-06-04 14:42:46 -0700 | [diff] [blame] | 649 | bool is_initialized; |
Ben Widawsky | 3ccfd19 | 2013-09-18 19:03:18 -0700 | [diff] [blame] | 650 | uint8_t remap_slice; |
Ben Widawsky | 4052105 | 2012-06-04 14:42:43 -0700 | [diff] [blame] | 651 | struct drm_i915_file_private *file_priv; |
| 652 | struct intel_ring_buffer *ring; |
| 653 | struct drm_i915_gem_object *obj; |
Mika Kuoppala | e59ec13 | 2013-06-12 12:35:28 +0300 | [diff] [blame] | 654 | struct i915_ctx_hang_stats hang_stats; |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 655 | |
| 656 | struct list_head link; |
Ben Widawsky | 4052105 | 2012-06-04 14:42:43 -0700 | [diff] [blame] | 657 | }; |
| 658 | |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 659 | struct i915_fbc { |
| 660 | unsigned long size; |
| 661 | unsigned int fb_id; |
| 662 | enum plane plane; |
| 663 | int y; |
| 664 | |
| 665 | struct drm_mm_node *compressed_fb; |
| 666 | struct drm_mm_node *compressed_llb; |
| 667 | |
| 668 | struct intel_fbc_work { |
| 669 | struct delayed_work work; |
| 670 | struct drm_crtc *crtc; |
| 671 | struct drm_framebuffer *fb; |
| 672 | int interval; |
| 673 | } *fbc_work; |
| 674 | |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 675 | enum no_fbc_reason { |
| 676 | FBC_OK, /* FBC is enabled */ |
| 677 | FBC_UNSUPPORTED, /* FBC is not supported by this chipset */ |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 678 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
| 679 | FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */ |
| 680 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ |
| 681 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ |
| 682 | FBC_BAD_PLANE, /* fbc not supported on plane */ |
| 683 | FBC_NOT_TILED, /* buffer not tiled */ |
| 684 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ |
| 685 | FBC_MODULE_PARAM, |
| 686 | FBC_CHIP_DEFAULT, /* disabled by default on this chip */ |
| 687 | } no_fbc_reason; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 688 | }; |
| 689 | |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 690 | struct i915_psr { |
| 691 | bool sink_support; |
| 692 | bool source_ok; |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 693 | }; |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 694 | |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 695 | enum intel_pch { |
Paulo Zanoni | f035083 | 2012-07-03 18:48:16 -0300 | [diff] [blame] | 696 | PCH_NONE = 0, /* No PCH present */ |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 697 | PCH_IBX, /* Ibexpeak PCH */ |
| 698 | PCH_CPT, /* Cougarpoint PCH */ |
Eugeni Dodonov | eb877eb | 2012-03-29 12:32:20 -0300 | [diff] [blame] | 699 | PCH_LPT, /* Lynxpoint PCH */ |
Ben Widawsky | 40c7ead | 2013-04-05 13:12:40 -0700 | [diff] [blame] | 700 | PCH_NOP, |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 701 | }; |
| 702 | |
Paulo Zanoni | 988d6ee | 2012-12-01 12:04:24 -0200 | [diff] [blame] | 703 | enum intel_sbi_destination { |
| 704 | SBI_ICLK, |
| 705 | SBI_MPHY, |
| 706 | }; |
| 707 | |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 708 | #define QUIRK_PIPEA_FORCE (1<<0) |
Keith Packard | 435793d | 2011-07-12 14:56:22 -0700 | [diff] [blame] | 709 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
Carsten Emde | 4dca20e | 2012-03-15 15:56:26 +0100 | [diff] [blame] | 710 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
Kamal Mostafa | e85843b | 2013-07-19 15:02:01 -0700 | [diff] [blame] | 711 | #define QUIRK_NO_PCH_PWM_ENABLE (1<<3) |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 712 | |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 713 | struct intel_fbdev; |
Chris Wilson | 1630fe7 | 2011-07-08 12:22:42 +0100 | [diff] [blame] | 714 | struct intel_fbc_work; |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 715 | |
Daniel Vetter | c2b9152 | 2012-02-14 22:37:19 +0100 | [diff] [blame] | 716 | struct intel_gmbus { |
| 717 | struct i2c_adapter adapter; |
Chris Wilson | f2ce9fa | 2012-11-10 15:58:21 +0000 | [diff] [blame] | 718 | u32 force_bit; |
Daniel Vetter | c2b9152 | 2012-02-14 22:37:19 +0100 | [diff] [blame] | 719 | u32 reg0; |
Daniel Vetter | 36c785f | 2012-02-14 22:37:22 +0100 | [diff] [blame] | 720 | u32 gpio_reg; |
Daniel Vetter | c167a6f | 2012-02-28 00:43:09 +0100 | [diff] [blame] | 721 | struct i2c_algo_bit_data bit_algo; |
Daniel Vetter | c2b9152 | 2012-02-14 22:37:19 +0100 | [diff] [blame] | 722 | struct drm_i915_private *dev_priv; |
| 723 | }; |
| 724 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 725 | struct i915_suspend_saved_registers { |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 726 | u8 saveLBB; |
| 727 | u32 saveDSPACNTR; |
| 728 | u32 saveDSPBCNTR; |
Keith Packard | e948e99 | 2008-05-07 12:27:53 +1000 | [diff] [blame] | 729 | u32 saveDSPARB; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 730 | u32 savePIPEACONF; |
| 731 | u32 savePIPEBCONF; |
| 732 | u32 savePIPEASRC; |
| 733 | u32 savePIPEBSRC; |
| 734 | u32 saveFPA0; |
| 735 | u32 saveFPA1; |
| 736 | u32 saveDPLL_A; |
| 737 | u32 saveDPLL_A_MD; |
| 738 | u32 saveHTOTAL_A; |
| 739 | u32 saveHBLANK_A; |
| 740 | u32 saveHSYNC_A; |
| 741 | u32 saveVTOTAL_A; |
| 742 | u32 saveVBLANK_A; |
| 743 | u32 saveVSYNC_A; |
| 744 | u32 saveBCLRPAT_A; |
Zhenyu Wang | 5586c8b | 2009-11-06 02:13:02 +0000 | [diff] [blame] | 745 | u32 saveTRANSACONF; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 746 | u32 saveTRANS_HTOTAL_A; |
| 747 | u32 saveTRANS_HBLANK_A; |
| 748 | u32 saveTRANS_HSYNC_A; |
| 749 | u32 saveTRANS_VTOTAL_A; |
| 750 | u32 saveTRANS_VBLANK_A; |
| 751 | u32 saveTRANS_VSYNC_A; |
Jesse Barnes | 0da3ea1 | 2008-02-20 09:39:58 +1000 | [diff] [blame] | 752 | u32 savePIPEASTAT; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 753 | u32 saveDSPASTRIDE; |
| 754 | u32 saveDSPASIZE; |
| 755 | u32 saveDSPAPOS; |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 756 | u32 saveDSPAADDR; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 757 | u32 saveDSPASURF; |
| 758 | u32 saveDSPATILEOFF; |
| 759 | u32 savePFIT_PGM_RATIOS; |
Jesse Barnes | 0eb96d6 | 2009-10-14 12:33:41 -0700 | [diff] [blame] | 760 | u32 saveBLC_HIST_CTL; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 761 | u32 saveBLC_PWM_CTL; |
| 762 | u32 saveBLC_PWM_CTL2; |
Jesse Barnes | 07bf139 | 2013-10-31 18:55:50 +0200 | [diff] [blame] | 763 | u32 saveBLC_HIST_CTL_B; |
| 764 | u32 saveBLC_PWM_CTL_B; |
| 765 | u32 saveBLC_PWM_CTL2_B; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 766 | u32 saveBLC_CPU_PWM_CTL; |
| 767 | u32 saveBLC_CPU_PWM_CTL2; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 768 | u32 saveFPB0; |
| 769 | u32 saveFPB1; |
| 770 | u32 saveDPLL_B; |
| 771 | u32 saveDPLL_B_MD; |
| 772 | u32 saveHTOTAL_B; |
| 773 | u32 saveHBLANK_B; |
| 774 | u32 saveHSYNC_B; |
| 775 | u32 saveVTOTAL_B; |
| 776 | u32 saveVBLANK_B; |
| 777 | u32 saveVSYNC_B; |
| 778 | u32 saveBCLRPAT_B; |
Zhenyu Wang | 5586c8b | 2009-11-06 02:13:02 +0000 | [diff] [blame] | 779 | u32 saveTRANSBCONF; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 780 | u32 saveTRANS_HTOTAL_B; |
| 781 | u32 saveTRANS_HBLANK_B; |
| 782 | u32 saveTRANS_HSYNC_B; |
| 783 | u32 saveTRANS_VTOTAL_B; |
| 784 | u32 saveTRANS_VBLANK_B; |
| 785 | u32 saveTRANS_VSYNC_B; |
Jesse Barnes | 0da3ea1 | 2008-02-20 09:39:58 +1000 | [diff] [blame] | 786 | u32 savePIPEBSTAT; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 787 | u32 saveDSPBSTRIDE; |
| 788 | u32 saveDSPBSIZE; |
| 789 | u32 saveDSPBPOS; |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 790 | u32 saveDSPBADDR; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 791 | u32 saveDSPBSURF; |
| 792 | u32 saveDSPBTILEOFF; |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 793 | u32 saveVGA0; |
| 794 | u32 saveVGA1; |
| 795 | u32 saveVGA_PD; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 796 | u32 saveVGACNTRL; |
| 797 | u32 saveADPA; |
| 798 | u32 saveLVDS; |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 799 | u32 savePP_ON_DELAYS; |
| 800 | u32 savePP_OFF_DELAYS; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 801 | u32 saveDVOA; |
| 802 | u32 saveDVOB; |
| 803 | u32 saveDVOC; |
| 804 | u32 savePP_ON; |
| 805 | u32 savePP_OFF; |
| 806 | u32 savePP_CONTROL; |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 807 | u32 savePP_DIVISOR; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 808 | u32 savePFIT_CONTROL; |
| 809 | u32 save_palette_a[256]; |
| 810 | u32 save_palette_b[256]; |
Jesse Barnes | 06027f9 | 2009-10-05 13:47:26 -0700 | [diff] [blame] | 811 | u32 saveDPFC_CB_BASE; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 812 | u32 saveFBC_CFB_BASE; |
| 813 | u32 saveFBC_LL_BASE; |
| 814 | u32 saveFBC_CONTROL; |
| 815 | u32 saveFBC_CONTROL2; |
Jesse Barnes | 0da3ea1 | 2008-02-20 09:39:58 +1000 | [diff] [blame] | 816 | u32 saveIER; |
| 817 | u32 saveIIR; |
| 818 | u32 saveIMR; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 819 | u32 saveDEIER; |
| 820 | u32 saveDEIMR; |
| 821 | u32 saveGTIER; |
| 822 | u32 saveGTIMR; |
| 823 | u32 saveFDI_RXA_IMR; |
| 824 | u32 saveFDI_RXB_IMR; |
Keith Packard | 1f84e55 | 2008-02-16 19:19:29 -0800 | [diff] [blame] | 825 | u32 saveCACHE_MODE_0; |
Keith Packard | 1f84e55 | 2008-02-16 19:19:29 -0800 | [diff] [blame] | 826 | u32 saveMI_ARB_STATE; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 827 | u32 saveSWF0[16]; |
| 828 | u32 saveSWF1[16]; |
| 829 | u32 saveSWF2[3]; |
| 830 | u8 saveMSR; |
| 831 | u8 saveSR[8]; |
Jesse Barnes | 123f794 | 2008-02-07 11:15:20 -0800 | [diff] [blame] | 832 | u8 saveGR[25]; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 833 | u8 saveAR_INDEX; |
Jesse Barnes | a59e122 | 2008-05-07 12:25:46 +1000 | [diff] [blame] | 834 | u8 saveAR[21]; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 835 | u8 saveDACMASK; |
Jesse Barnes | a59e122 | 2008-05-07 12:25:46 +1000 | [diff] [blame] | 836 | u8 saveCR[37]; |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 837 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
Eric Anholt | 1fd1c62 | 2009-06-03 07:26:58 +0000 | [diff] [blame] | 838 | u32 saveCURACNTR; |
| 839 | u32 saveCURAPOS; |
| 840 | u32 saveCURABASE; |
| 841 | u32 saveCURBCNTR; |
| 842 | u32 saveCURBPOS; |
| 843 | u32 saveCURBBASE; |
| 844 | u32 saveCURSIZE; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 845 | u32 saveDP_B; |
| 846 | u32 saveDP_C; |
| 847 | u32 saveDP_D; |
| 848 | u32 savePIPEA_GMCH_DATA_M; |
| 849 | u32 savePIPEB_GMCH_DATA_M; |
| 850 | u32 savePIPEA_GMCH_DATA_N; |
| 851 | u32 savePIPEB_GMCH_DATA_N; |
| 852 | u32 savePIPEA_DP_LINK_M; |
| 853 | u32 savePIPEB_DP_LINK_M; |
| 854 | u32 savePIPEA_DP_LINK_N; |
| 855 | u32 savePIPEB_DP_LINK_N; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 856 | u32 saveFDI_RXA_CTL; |
| 857 | u32 saveFDI_TXA_CTL; |
| 858 | u32 saveFDI_RXB_CTL; |
| 859 | u32 saveFDI_TXB_CTL; |
| 860 | u32 savePFA_CTL_1; |
| 861 | u32 savePFB_CTL_1; |
| 862 | u32 savePFA_WIN_SZ; |
| 863 | u32 savePFB_WIN_SZ; |
| 864 | u32 savePFA_WIN_POS; |
| 865 | u32 savePFB_WIN_POS; |
Zhenyu Wang | 5586c8b | 2009-11-06 02:13:02 +0000 | [diff] [blame] | 866 | u32 savePCH_DREF_CONTROL; |
| 867 | u32 saveDISP_ARB_CTL; |
| 868 | u32 savePIPEA_DATA_M1; |
| 869 | u32 savePIPEA_DATA_N1; |
| 870 | u32 savePIPEA_LINK_M1; |
| 871 | u32 savePIPEA_LINK_N1; |
| 872 | u32 savePIPEB_DATA_M1; |
| 873 | u32 savePIPEB_DATA_N1; |
| 874 | u32 savePIPEB_LINK_M1; |
| 875 | u32 savePIPEB_LINK_N1; |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 876 | u32 saveMCHBAR_RENDER_STANDBY; |
Adam Jackson | cda2bb7 | 2011-07-26 16:53:06 -0400 | [diff] [blame] | 877 | u32 savePCH_PORT_HOTPLUG; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 878 | }; |
Daniel Vetter | c85aa88 | 2012-11-02 19:55:03 +0100 | [diff] [blame] | 879 | |
| 880 | struct intel_gen6_power_mgmt { |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 881 | /* work and pm_iir are protected by dev_priv->irq_lock */ |
Daniel Vetter | c85aa88 | 2012-11-02 19:55:03 +0100 | [diff] [blame] | 882 | struct work_struct work; |
| 883 | u32 pm_iir; |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 884 | |
Daniel Vetter | c85aa88 | 2012-11-02 19:55:03 +0100 | [diff] [blame] | 885 | /* The below variables an all the rps hw state are protected by |
| 886 | * dev->struct mutext. */ |
| 887 | u8 cur_delay; |
| 888 | u8 min_delay; |
| 889 | u8 max_delay; |
Jesse Barnes | 52ceb90 | 2013-04-23 10:09:26 -0700 | [diff] [blame] | 890 | u8 rpe_delay; |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 891 | u8 rp1_delay; |
| 892 | u8 rp0_delay; |
Ben Widawsky | 31c7738 | 2013-04-05 14:29:22 -0700 | [diff] [blame] | 893 | u8 hw_max; |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 894 | |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 895 | int last_adj; |
| 896 | enum { LOW_POWER, BETWEEN, HIGH_POWER } power; |
| 897 | |
Chris Wilson | c0951f0 | 2013-10-10 21:58:50 +0100 | [diff] [blame] | 898 | bool enabled; |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 899 | struct delayed_work delayed_resume_work; |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 900 | |
| 901 | /* |
| 902 | * Protects RPS/RC6 register access and PCU communication. |
| 903 | * Must be taken after struct_mutex if nested. |
| 904 | */ |
| 905 | struct mutex hw_lock; |
Daniel Vetter | c85aa88 | 2012-11-02 19:55:03 +0100 | [diff] [blame] | 906 | }; |
| 907 | |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 908 | /* defined intel_pm.c */ |
| 909 | extern spinlock_t mchdev_lock; |
| 910 | |
Daniel Vetter | c85aa88 | 2012-11-02 19:55:03 +0100 | [diff] [blame] | 911 | struct intel_ilk_power_mgmt { |
| 912 | u8 cur_delay; |
| 913 | u8 min_delay; |
| 914 | u8 max_delay; |
| 915 | u8 fmax; |
| 916 | u8 fstart; |
| 917 | |
| 918 | u64 last_count1; |
| 919 | unsigned long last_time1; |
| 920 | unsigned long chipset_power; |
| 921 | u64 last_count2; |
| 922 | struct timespec last_time2; |
| 923 | unsigned long gfx_power; |
| 924 | u8 corr; |
| 925 | |
| 926 | int c_m; |
| 927 | int r_t; |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 928 | |
| 929 | struct drm_i915_gem_object *pwrctx; |
| 930 | struct drm_i915_gem_object *renderctx; |
Daniel Vetter | c85aa88 | 2012-11-02 19:55:03 +0100 | [diff] [blame] | 931 | }; |
| 932 | |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 933 | /* Power well structure for haswell */ |
| 934 | struct i915_power_well { |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 935 | /* power well enable/disable usage count */ |
| 936 | int count; |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 937 | }; |
| 938 | |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 939 | #define I915_MAX_POWER_WELLS 1 |
| 940 | |
| 941 | struct i915_power_domains { |
Imre Deak | baa7070 | 2013-10-25 17:36:48 +0300 | [diff] [blame] | 942 | /* |
| 943 | * Power wells needed for initialization at driver init and suspend |
| 944 | * time are on. They are kept on until after the first modeset. |
| 945 | */ |
| 946 | bool init_power_on; |
| 947 | |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 948 | struct mutex lock; |
| 949 | struct i915_power_well power_wells[I915_MAX_POWER_WELLS]; |
| 950 | }; |
| 951 | |
Daniel Vetter | 231f42a | 2012-11-02 19:55:05 +0100 | [diff] [blame] | 952 | struct i915_dri1_state { |
| 953 | unsigned allow_batchbuffer : 1; |
| 954 | u32 __iomem *gfx_hws_cpu_addr; |
| 955 | |
| 956 | unsigned int cpp; |
| 957 | int back_offset; |
| 958 | int front_offset; |
| 959 | int current_page; |
| 960 | int page_flipping; |
| 961 | |
| 962 | uint32_t counter; |
| 963 | }; |
| 964 | |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 965 | struct i915_ums_state { |
| 966 | /** |
| 967 | * Flag if the X Server, and thus DRM, is not currently in |
| 968 | * control of the device. |
| 969 | * |
| 970 | * This is set between LeaveVT and EnterVT. It needs to be |
| 971 | * replaced with a semaphore. It also needs to be |
| 972 | * transitioned away from for kernel modesetting. |
| 973 | */ |
| 974 | int mm_suspended; |
| 975 | }; |
| 976 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 977 | #define MAX_L3_SLICES 2 |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 978 | struct intel_l3_parity { |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 979 | u32 *remap_info[MAX_L3_SLICES]; |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 980 | struct work_struct error_work; |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 981 | int which_slice; |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 982 | }; |
| 983 | |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 984 | struct i915_gem_mm { |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 985 | /** Memory allocator for GTT stolen memory */ |
| 986 | struct drm_mm stolen; |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 987 | /** List of all objects in gtt_space. Used to restore gtt |
| 988 | * mappings on resume */ |
| 989 | struct list_head bound_list; |
| 990 | /** |
| 991 | * List of objects which are not bound to the GTT (thus |
| 992 | * are idle and not used by the GPU) but still have |
| 993 | * (presumably uncached) pages still attached. |
| 994 | */ |
| 995 | struct list_head unbound_list; |
| 996 | |
| 997 | /** Usable portion of the GTT for GEM */ |
| 998 | unsigned long stolen_base; /* limited to low memory (32-bit) */ |
| 999 | |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 1000 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
| 1001 | struct i915_hw_ppgtt *aliasing_ppgtt; |
| 1002 | |
| 1003 | struct shrinker inactive_shrinker; |
| 1004 | bool shrinker_no_lock_stealing; |
| 1005 | |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 1006 | /** LRU list of objects with fence regs on them. */ |
| 1007 | struct list_head fence_list; |
| 1008 | |
| 1009 | /** |
| 1010 | * We leave the user IRQ off as much as possible, |
| 1011 | * but this means that requests will finish and never |
| 1012 | * be retired once the system goes idle. Set a timer to |
| 1013 | * fire periodically while the ring is running. When it |
| 1014 | * fires, go retire requests. |
| 1015 | */ |
| 1016 | struct delayed_work retire_work; |
| 1017 | |
| 1018 | /** |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1019 | * When we detect an idle GPU, we want to turn on |
| 1020 | * powersaving features. So once we see that there |
| 1021 | * are no more requests outstanding and no more |
| 1022 | * arrive within a small period of time, we fire |
| 1023 | * off the idle_work. |
| 1024 | */ |
| 1025 | struct delayed_work idle_work; |
| 1026 | |
| 1027 | /** |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 1028 | * Are we in a non-interruptible section of code like |
| 1029 | * modesetting? |
| 1030 | */ |
| 1031 | bool interruptible; |
| 1032 | |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 1033 | /** Bit 6 swizzling required for X tiling */ |
| 1034 | uint32_t bit_6_swizzle_x; |
| 1035 | /** Bit 6 swizzling required for Y tiling */ |
| 1036 | uint32_t bit_6_swizzle_y; |
| 1037 | |
| 1038 | /* storage for physical objects */ |
| 1039 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; |
| 1040 | |
| 1041 | /* accounting, useful for userland debugging */ |
Daniel Vetter | c20e835 | 2013-07-24 22:40:23 +0200 | [diff] [blame] | 1042 | spinlock_t object_stat_lock; |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 1043 | size_t object_memory; |
| 1044 | u32 object_count; |
| 1045 | }; |
| 1046 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 1047 | struct drm_i915_error_state_buf { |
| 1048 | unsigned bytes; |
| 1049 | unsigned size; |
| 1050 | int err; |
| 1051 | u8 *buf; |
| 1052 | loff_t start; |
| 1053 | loff_t pos; |
| 1054 | }; |
| 1055 | |
Mika Kuoppala | fc16b48 | 2013-06-06 15:18:39 +0300 | [diff] [blame] | 1056 | struct i915_error_state_file_priv { |
| 1057 | struct drm_device *dev; |
| 1058 | struct drm_i915_error_state *error; |
| 1059 | }; |
| 1060 | |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 1061 | struct i915_gpu_error { |
| 1062 | /* For hangcheck timer */ |
| 1063 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ |
| 1064 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 1065 | /* Hang gpu twice in this window and your context gets banned */ |
| 1066 | #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) |
| 1067 | |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 1068 | struct timer_list hangcheck_timer; |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 1069 | |
| 1070 | /* For reset and error_state handling. */ |
| 1071 | spinlock_t lock; |
| 1072 | /* Protected by the above dev->gpu_error.lock. */ |
| 1073 | struct drm_i915_error_state *first_error; |
| 1074 | struct work_struct work; |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 1075 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1076 | |
| 1077 | unsigned long missed_irq_rings; |
| 1078 | |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1079 | /** |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1080 | * State variable and reset counter controlling the reset flow |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1081 | * |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1082 | * Upper bits are for the reset counter. This counter is used by the |
| 1083 | * wait_seqno code to race-free noticed that a reset event happened and |
| 1084 | * that it needs to restart the entire ioctl (since most likely the |
| 1085 | * seqno it waited for won't ever signal anytime soon). |
| 1086 | * |
| 1087 | * This is important for lock-free wait paths, where no contended lock |
| 1088 | * naturally enforces the correct ordering between the bail-out of the |
| 1089 | * waiter and the gpu reset work code. |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1090 | * |
| 1091 | * Lowest bit controls the reset state machine: Set means a reset is in |
| 1092 | * progress. This state will (presuming we don't have any bugs) decay |
| 1093 | * into either unset (successful reset) or the special WEDGED value (hw |
| 1094 | * terminally sour). All waiters on the reset_queue will be woken when |
| 1095 | * that happens. |
| 1096 | */ |
| 1097 | atomic_t reset_counter; |
| 1098 | |
| 1099 | /** |
| 1100 | * Special values/flags for reset_counter |
| 1101 | * |
| 1102 | * Note that the code relies on |
| 1103 | * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG |
| 1104 | * being true. |
| 1105 | */ |
| 1106 | #define I915_RESET_IN_PROGRESS_FLAG 1 |
| 1107 | #define I915_WEDGED 0xffffffff |
| 1108 | |
| 1109 | /** |
| 1110 | * Waitqueue to signal when the reset has completed. Used by clients |
| 1111 | * that wait for dev_priv->mm.wedged to settle. |
| 1112 | */ |
| 1113 | wait_queue_head_t reset_queue; |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 1114 | |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 1115 | /* For gpu hang simulation. */ |
| 1116 | unsigned int stop_rings; |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1117 | |
| 1118 | /* For missed irq/seqno simulation. */ |
| 1119 | unsigned int test_irq_rings; |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 1120 | }; |
| 1121 | |
Zhang Rui | b8efb17 | 2013-02-05 15:41:53 +0800 | [diff] [blame] | 1122 | enum modeset_restore { |
| 1123 | MODESET_ON_LID_OPEN, |
| 1124 | MODESET_DONE, |
| 1125 | MODESET_SUSPENDED, |
| 1126 | }; |
| 1127 | |
Paulo Zanoni | 6acab15 | 2013-09-12 17:06:24 -0300 | [diff] [blame] | 1128 | struct ddi_vbt_port_info { |
| 1129 | uint8_t hdmi_level_shift; |
Paulo Zanoni | 311a209 | 2013-09-12 17:12:18 -0300 | [diff] [blame] | 1130 | |
| 1131 | uint8_t supports_dvi:1; |
| 1132 | uint8_t supports_hdmi:1; |
| 1133 | uint8_t supports_dp:1; |
Paulo Zanoni | 6acab15 | 2013-09-12 17:06:24 -0300 | [diff] [blame] | 1134 | }; |
| 1135 | |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 1136 | struct intel_vbt_data { |
| 1137 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
| 1138 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ |
| 1139 | |
| 1140 | /* Feature bits */ |
| 1141 | unsigned int int_tv_support:1; |
| 1142 | unsigned int lvds_dither:1; |
| 1143 | unsigned int lvds_vbt:1; |
| 1144 | unsigned int int_crt_support:1; |
| 1145 | unsigned int lvds_use_ssc:1; |
| 1146 | unsigned int display_clock_mode:1; |
| 1147 | unsigned int fdi_rx_polarity_inverted:1; |
| 1148 | int lvds_ssc_freq; |
| 1149 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ |
| 1150 | |
| 1151 | /* eDP */ |
| 1152 | int edp_rate; |
| 1153 | int edp_lanes; |
| 1154 | int edp_preemphasis; |
| 1155 | int edp_vswing; |
| 1156 | bool edp_initialized; |
| 1157 | bool edp_support; |
| 1158 | int edp_bpp; |
| 1159 | struct edp_power_seq edp_pps; |
| 1160 | |
Shobhit Kumar | d17c544 | 2013-08-27 15:12:25 +0300 | [diff] [blame] | 1161 | /* MIPI DSI */ |
| 1162 | struct { |
| 1163 | u16 panel_id; |
| 1164 | } dsi; |
| 1165 | |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 1166 | int crt_ddc_pin; |
| 1167 | |
| 1168 | int child_dev_num; |
Paulo Zanoni | 768f69c | 2013-09-11 18:02:47 -0300 | [diff] [blame] | 1169 | union child_device_config *child_dev; |
Paulo Zanoni | 6acab15 | 2013-09-12 17:06:24 -0300 | [diff] [blame] | 1170 | |
| 1171 | struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 1172 | }; |
| 1173 | |
Ville Syrjälä | 77c122b | 2013-08-06 22:24:04 +0300 | [diff] [blame] | 1174 | enum intel_ddb_partitioning { |
| 1175 | INTEL_DDB_PART_1_2, |
| 1176 | INTEL_DDB_PART_5_6, /* IVB+ */ |
| 1177 | }; |
| 1178 | |
Ville Syrjälä | 1fd527c | 2013-08-06 22:24:05 +0300 | [diff] [blame] | 1179 | struct intel_wm_level { |
| 1180 | bool enable; |
| 1181 | uint32_t pri_val; |
| 1182 | uint32_t spr_val; |
| 1183 | uint32_t cur_val; |
| 1184 | uint32_t fbc_val; |
| 1185 | }; |
| 1186 | |
Ville Syrjälä | 609cede | 2013-10-09 19:18:03 +0300 | [diff] [blame] | 1187 | struct hsw_wm_values { |
| 1188 | uint32_t wm_pipe[3]; |
| 1189 | uint32_t wm_lp[3]; |
| 1190 | uint32_t wm_lp_spr[3]; |
| 1191 | uint32_t wm_linetime[3]; |
| 1192 | bool enable_fbc_wm; |
| 1193 | enum intel_ddb_partitioning partitioning; |
| 1194 | }; |
| 1195 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 1196 | /* |
| 1197 | * This struct tracks the state needed for the Package C8+ feature. |
| 1198 | * |
| 1199 | * Package states C8 and deeper are really deep PC states that can only be |
| 1200 | * reached when all the devices on the system allow it, so even if the graphics |
| 1201 | * device allows PC8+, it doesn't mean the system will actually get to these |
| 1202 | * states. |
| 1203 | * |
| 1204 | * Our driver only allows PC8+ when all the outputs are disabled, the power well |
| 1205 | * is disabled and the GPU is idle. When these conditions are met, we manually |
| 1206 | * do the other conditions: disable the interrupts, clocks and switch LCPLL |
| 1207 | * refclk to Fclk. |
| 1208 | * |
| 1209 | * When we really reach PC8 or deeper states (not just when we allow it) we lose |
| 1210 | * the state of some registers, so when we come back from PC8+ we need to |
| 1211 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't |
| 1212 | * need to take care of the registers kept by RC6. |
| 1213 | * |
| 1214 | * The interrupt disabling is part of the requirements. We can only leave the |
| 1215 | * PCH HPD interrupts enabled. If we're in PC8+ and we get another interrupt we |
| 1216 | * can lock the machine. |
| 1217 | * |
| 1218 | * Ideally every piece of our code that needs PC8+ disabled would call |
| 1219 | * hsw_disable_package_c8, which would increment disable_count and prevent the |
| 1220 | * system from reaching PC8+. But we don't have a symmetric way to do this for |
| 1221 | * everything, so we have the requirements_met and gpu_idle variables. When we |
| 1222 | * switch requirements_met or gpu_idle to true we decrease disable_count, and |
| 1223 | * increase it in the opposite case. The requirements_met variable is true when |
| 1224 | * all the CRTCs, encoders and the power well are disabled. The gpu_idle |
| 1225 | * variable is true when the GPU is idle. |
| 1226 | * |
| 1227 | * In addition to everything, we only actually enable PC8+ if disable_count |
| 1228 | * stays at zero for at least some seconds. This is implemented with the |
| 1229 | * enable_work variable. We do this so we don't enable/disable PC8 dozens of |
| 1230 | * consecutive times when all screens are disabled and some background app |
| 1231 | * queries the state of our connectors, or we have some application constantly |
| 1232 | * waking up to use the GPU. Only after the enable_work function actually |
| 1233 | * enables PC8+ the "enable" variable will become true, which means that it can |
| 1234 | * be false even if disable_count is 0. |
| 1235 | * |
| 1236 | * The irqs_disabled variable becomes true exactly after we disable the IRQs and |
| 1237 | * goes back to false exactly before we reenable the IRQs. We use this variable |
| 1238 | * to check if someone is trying to enable/disable IRQs while they're supposed |
| 1239 | * to be disabled. This shouldn't happen and we'll print some error messages in |
| 1240 | * case it happens, but if it actually happens we'll also update the variables |
| 1241 | * inside struct regsave so when we restore the IRQs they will contain the |
| 1242 | * latest expected values. |
| 1243 | * |
| 1244 | * For more, read "Display Sequences for Package C8" on our documentation. |
| 1245 | */ |
| 1246 | struct i915_package_c8 { |
| 1247 | bool requirements_met; |
| 1248 | bool gpu_idle; |
| 1249 | bool irqs_disabled; |
| 1250 | /* Only true after the delayed work task actually enables it. */ |
| 1251 | bool enabled; |
| 1252 | int disable_count; |
| 1253 | struct mutex lock; |
| 1254 | struct delayed_work enable_work; |
| 1255 | |
| 1256 | struct { |
| 1257 | uint32_t deimr; |
| 1258 | uint32_t sdeimr; |
| 1259 | uint32_t gtimr; |
| 1260 | uint32_t gtier; |
| 1261 | uint32_t gen6_pmimr; |
| 1262 | } regsave; |
| 1263 | }; |
| 1264 | |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 1265 | enum intel_pipe_crc_source { |
| 1266 | INTEL_PIPE_CRC_SOURCE_NONE, |
| 1267 | INTEL_PIPE_CRC_SOURCE_PLANE1, |
| 1268 | INTEL_PIPE_CRC_SOURCE_PLANE2, |
| 1269 | INTEL_PIPE_CRC_SOURCE_PF, |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 1270 | INTEL_PIPE_CRC_SOURCE_PIPE, |
Daniel Vetter | 3d099a0 | 2013-10-16 22:55:58 +0200 | [diff] [blame] | 1271 | /* TV/DP on pre-gen5/vlv can't use the pipe source. */ |
| 1272 | INTEL_PIPE_CRC_SOURCE_TV, |
| 1273 | INTEL_PIPE_CRC_SOURCE_DP_B, |
| 1274 | INTEL_PIPE_CRC_SOURCE_DP_C, |
| 1275 | INTEL_PIPE_CRC_SOURCE_DP_D, |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 1276 | INTEL_PIPE_CRC_SOURCE_AUTO, |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 1277 | INTEL_PIPE_CRC_SOURCE_MAX, |
| 1278 | }; |
| 1279 | |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1280 | struct intel_pipe_crc_entry { |
Damien Lespiau | ac2300d | 2013-10-15 18:55:30 +0100 | [diff] [blame] | 1281 | uint32_t frame; |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1282 | uint32_t crc[5]; |
| 1283 | }; |
| 1284 | |
Damien Lespiau | b2c88f5 | 2013-10-15 18:55:29 +0100 | [diff] [blame] | 1285 | #define INTEL_PIPE_CRC_ENTRIES_NR 128 |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1286 | struct intel_pipe_crc { |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1287 | spinlock_t lock; |
| 1288 | bool opened; /* exclusive access to the result file */ |
Damien Lespiau | e5f75ac | 2013-10-15 18:55:34 +0100 | [diff] [blame] | 1289 | struct intel_pipe_crc_entry *entries; |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 1290 | enum intel_pipe_crc_source source; |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1291 | int head, tail; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 1292 | wait_queue_head_t wq; |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1293 | }; |
| 1294 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1295 | typedef struct drm_i915_private { |
| 1296 | struct drm_device *dev; |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 1297 | struct kmem_cache *slab; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1298 | |
| 1299 | const struct intel_device_info *info; |
| 1300 | |
| 1301 | int relative_constants_mode; |
| 1302 | |
| 1303 | void __iomem *regs; |
| 1304 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1305 | struct intel_uncore uncore; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1306 | |
| 1307 | struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; |
| 1308 | |
Daniel Vetter | 28c70f1 | 2012-12-01 13:53:45 +0100 | [diff] [blame] | 1309 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1310 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
| 1311 | * controller on different i2c buses. */ |
| 1312 | struct mutex gmbus_mutex; |
| 1313 | |
| 1314 | /** |
| 1315 | * Base address of the gmbus and gpio block. |
| 1316 | */ |
| 1317 | uint32_t gpio_mmio_base; |
| 1318 | |
Daniel Vetter | 28c70f1 | 2012-12-01 13:53:45 +0100 | [diff] [blame] | 1319 | wait_queue_head_t gmbus_wait_queue; |
| 1320 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1321 | struct pci_dev *bridge_dev; |
| 1322 | struct intel_ring_buffer ring[I915_NUM_RINGS]; |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 1323 | uint32_t last_seqno, next_seqno; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1324 | |
| 1325 | drm_dma_handle_t *status_page_dmah; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1326 | struct resource mch_res; |
| 1327 | |
| 1328 | atomic_t irq_received; |
| 1329 | |
| 1330 | /* protects the irq masks */ |
| 1331 | spinlock_t irq_lock; |
| 1332 | |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 1333 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
| 1334 | struct pm_qos_request pm_qos; |
| 1335 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1336 | /* DPIO indirect register protection */ |
Daniel Vetter | 0915300 | 2012-12-12 14:06:44 +0100 | [diff] [blame] | 1337 | struct mutex dpio_lock; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1338 | |
| 1339 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1340 | union { |
| 1341 | u32 irq_mask; |
| 1342 | u32 de_irq_mask[I915_MAX_PIPES]; |
| 1343 | }; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1344 | u32 gt_irq_mask; |
Paulo Zanoni | 605cd25 | 2013-08-06 18:57:15 -0300 | [diff] [blame] | 1345 | u32 pm_irq_mask; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1346 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1347 | struct work_struct hotplug_work; |
Daniel Vetter | 52d7ece | 2012-12-01 21:03:22 +0100 | [diff] [blame] | 1348 | bool enable_hotplug_processing; |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1349 | struct { |
| 1350 | unsigned long hpd_last_jiffies; |
| 1351 | int hpd_cnt; |
| 1352 | enum { |
| 1353 | HPD_ENABLED = 0, |
| 1354 | HPD_DISABLED = 1, |
| 1355 | HPD_MARK_DISABLED = 2 |
| 1356 | } hpd_mark; |
| 1357 | } hpd_stats[HPD_NUM_PINS]; |
Egbert Eich | 142e239 | 2013-04-11 15:57:57 +0200 | [diff] [blame] | 1358 | u32 hpd_event_bits; |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 1359 | struct timer_list hotplug_reenable_timer; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1360 | |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 1361 | int num_plane; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1362 | |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 1363 | struct i915_fbc fbc; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1364 | struct intel_opregion opregion; |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 1365 | struct intel_vbt_data vbt; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1366 | |
| 1367 | /* overlay */ |
| 1368 | struct intel_overlay *overlay; |
Ville Syrjälä | 2c6602d | 2013-02-08 23:13:35 +0200 | [diff] [blame] | 1369 | unsigned int sprite_scaling_enabled; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1370 | |
Jani Nikula | 31ad8ec | 2013-04-02 15:48:09 +0300 | [diff] [blame] | 1371 | /* backlight */ |
| 1372 | struct { |
| 1373 | int level; |
| 1374 | bool enabled; |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 1375 | spinlock_t lock; /* bl registers and the above bl fields */ |
Jani Nikula | 31ad8ec | 2013-04-02 15:48:09 +0300 | [diff] [blame] | 1376 | struct backlight_device *device; |
| 1377 | } backlight; |
| 1378 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1379 | /* LVDS info */ |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1380 | bool no_aux_handshake; |
| 1381 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1382 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
| 1383 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ |
| 1384 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ |
| 1385 | |
| 1386 | unsigned int fsb_freq, mem_freq, is_ddr3; |
| 1387 | |
Daniel Vetter | 645416f | 2013-09-02 16:22:25 +0200 | [diff] [blame] | 1388 | /** |
| 1389 | * wq - Driver workqueue for GEM. |
| 1390 | * |
| 1391 | * NOTE: Work items scheduled here are not allowed to grab any modeset |
| 1392 | * locks, for otherwise the flushing done in the pageflip code will |
| 1393 | * result in deadlocks. |
| 1394 | */ |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1395 | struct workqueue_struct *wq; |
| 1396 | |
| 1397 | /* Display functions */ |
| 1398 | struct drm_i915_display_funcs display; |
| 1399 | |
| 1400 | /* PCH chipset type */ |
| 1401 | enum intel_pch pch_type; |
Paulo Zanoni | 17a303e | 2012-11-20 15:12:07 -0200 | [diff] [blame] | 1402 | unsigned short pch_id; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1403 | |
| 1404 | unsigned long quirks; |
| 1405 | |
Zhang Rui | b8efb17 | 2013-02-05 15:41:53 +0800 | [diff] [blame] | 1406 | enum modeset_restore modeset_restore; |
| 1407 | struct mutex modeset_restore_lock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1408 | |
Ben Widawsky | a7bbbd6 | 2013-07-16 16:50:07 -0700 | [diff] [blame] | 1409 | struct list_head vm_list; /* Global list of all address spaces */ |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1410 | struct i915_gtt gtt; /* VMA representing the global address space */ |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 1411 | |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 1412 | struct i915_gem_mm mm; |
Daniel Vetter | 8781342 | 2012-05-02 11:49:32 +0200 | [diff] [blame] | 1413 | |
Daniel Vetter | 8781342 | 2012-05-02 11:49:32 +0200 | [diff] [blame] | 1414 | /* Kernel Modesetting */ |
| 1415 | |
yakui_zhao | 9b9d172 | 2009-05-31 17:17:17 +0800 | [diff] [blame] | 1416 | struct sdvo_device_mapping sdvo_mappings[2]; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1417 | |
Jesse Barnes | 27f8227 | 2011-09-02 12:54:37 -0700 | [diff] [blame] | 1418 | struct drm_crtc *plane_to_crtc_mapping[3]; |
| 1419 | struct drm_crtc *pipe_to_crtc_mapping[3]; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1420 | wait_queue_head_t pending_flip_queue; |
| 1421 | |
Daniel Vetter | c459787 | 2013-10-21 21:04:07 +0200 | [diff] [blame] | 1422 | #ifdef CONFIG_DEBUG_FS |
| 1423 | struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; |
| 1424 | #endif |
| 1425 | |
Daniel Vetter | e72f9fb | 2013-06-05 13:34:06 +0200 | [diff] [blame] | 1426 | int num_shared_dpll; |
| 1427 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; |
Paulo Zanoni | 6441ab5 | 2012-10-05 12:05:58 -0300 | [diff] [blame] | 1428 | struct intel_ddi_plls ddi_plls; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1429 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1430 | /* Reclocking support */ |
| 1431 | bool render_reclock_avail; |
| 1432 | bool lvds_downclock_avail; |
Zhao Yakui | 18f9ed1 | 2009-11-20 03:24:16 +0000 | [diff] [blame] | 1433 | /* indicates the reduced downclock for LVDS*/ |
| 1434 | int lvds_downclock; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1435 | u16 orig_clock; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1436 | |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1437 | bool mchbar_need_disable; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1438 | |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 1439 | struct intel_l3_parity l3_parity; |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 1440 | |
Ben Widawsky | 5912450 | 2013-07-04 11:02:05 -0700 | [diff] [blame] | 1441 | /* Cannot be determined by PCIID. You must always read a register. */ |
| 1442 | size_t ellc_size; |
| 1443 | |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 1444 | /* gen6+ rps state */ |
Daniel Vetter | c85aa88 | 2012-11-02 19:55:03 +0100 | [diff] [blame] | 1445 | struct intel_gen6_power_mgmt rps; |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 1446 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 1447 | /* ilk-only ips/rps state. Everything in here is protected by the global |
| 1448 | * mchdev_lock in intel_pm.c */ |
Daniel Vetter | c85aa88 | 2012-11-02 19:55:03 +0100 | [diff] [blame] | 1449 | struct intel_ilk_power_mgmt ips; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1450 | |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 1451 | struct i915_power_domains power_domains; |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 1452 | |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 1453 | struct i915_psr psr; |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1454 | |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 1455 | struct i915_gpu_error gpu_error; |
Chris Wilson | ae681d9 | 2010-10-01 14:57:56 +0100 | [diff] [blame] | 1456 | |
Jesse Barnes | c9cddff | 2013-05-08 10:45:13 -0700 | [diff] [blame] | 1457 | struct drm_i915_gem_object *vlv_pctx; |
| 1458 | |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 1459 | #ifdef CONFIG_DRM_I915_FBDEV |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 1460 | /* list of fbdev register on this device */ |
| 1461 | struct intel_fbdev *fbdev; |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 1462 | #endif |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 1463 | |
Jesse Barnes | 073f34d | 2012-11-02 11:13:59 -0700 | [diff] [blame] | 1464 | /* |
| 1465 | * The console may be contended at resume, but we don't |
| 1466 | * want it to block on it. |
| 1467 | */ |
| 1468 | struct work_struct console_resume_work; |
| 1469 | |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 1470 | struct drm_property *broadcast_rgb_property; |
Chris Wilson | 3f43c48 | 2011-05-12 22:17:24 +0100 | [diff] [blame] | 1471 | struct drm_property *force_audio_property; |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1472 | |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 1473 | bool hw_contexts_disabled; |
| 1474 | uint32_t hw_context_size; |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 1475 | struct list_head context_list; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1476 | |
Damien Lespiau | 3e68320 | 2012-12-11 18:48:29 +0000 | [diff] [blame] | 1477 | u32 fdi_rx_config; |
Paulo Zanoni | 68d18ad | 2012-12-01 12:04:26 -0200 | [diff] [blame] | 1478 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1479 | struct i915_suspend_saved_registers regfile; |
Daniel Vetter | 231f42a | 2012-11-02 19:55:05 +0100 | [diff] [blame] | 1480 | |
Ville Syrjälä | 53615a5 | 2013-08-01 16:18:50 +0300 | [diff] [blame] | 1481 | struct { |
| 1482 | /* |
| 1483 | * Raw watermark latency values: |
| 1484 | * in 0.1us units for WM0, |
| 1485 | * in 0.5us units for WM1+. |
| 1486 | */ |
| 1487 | /* primary */ |
| 1488 | uint16_t pri_latency[5]; |
| 1489 | /* sprite */ |
| 1490 | uint16_t spr_latency[5]; |
| 1491 | /* cursor */ |
| 1492 | uint16_t cur_latency[5]; |
Ville Syrjälä | 609cede | 2013-10-09 19:18:03 +0300 | [diff] [blame] | 1493 | |
| 1494 | /* current hardware state */ |
| 1495 | struct hsw_wm_values hw; |
Ville Syrjälä | 53615a5 | 2013-08-01 16:18:50 +0300 | [diff] [blame] | 1496 | } wm; |
| 1497 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 1498 | struct i915_package_c8 pc8; |
| 1499 | |
Daniel Vetter | 231f42a | 2012-11-02 19:55:05 +0100 | [diff] [blame] | 1500 | /* Old dri1 support infrastructure, beware the dragons ya fools entering |
| 1501 | * here! */ |
| 1502 | struct i915_dri1_state dri1; |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 1503 | /* Old ums support infrastructure, same warning applies. */ |
| 1504 | struct i915_ums_state ums; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1505 | } drm_i915_private_t; |
| 1506 | |
Chris Wilson | 2c1792a | 2013-08-01 18:39:55 +0100 | [diff] [blame] | 1507 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) |
| 1508 | { |
| 1509 | return dev->dev_private; |
| 1510 | } |
| 1511 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 1512 | /* Iterate over initialised rings */ |
| 1513 | #define for_each_ring(ring__, dev_priv__, i__) \ |
| 1514 | for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ |
| 1515 | if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) |
| 1516 | |
Wu Fengguang | b1d7e4b | 2012-02-14 11:45:36 +0800 | [diff] [blame] | 1517 | enum hdmi_force_audio { |
| 1518 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ |
| 1519 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ |
| 1520 | HDMI_AUDIO_AUTO, /* trust EDID */ |
| 1521 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ |
| 1522 | }; |
| 1523 | |
Daniel Vetter | 190d6cd | 2013-07-04 13:06:28 +0200 | [diff] [blame] | 1524 | #define I915_GTT_OFFSET_NONE ((u32)-1) |
Chris Wilson | ed2f345 | 2012-11-15 11:32:19 +0000 | [diff] [blame] | 1525 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1526 | struct drm_i915_gem_object_ops { |
| 1527 | /* Interface between the GEM object and its backing storage. |
| 1528 | * get_pages() is called once prior to the use of the associated set |
| 1529 | * of pages before to binding them into the GTT, and put_pages() is |
| 1530 | * called after we no longer need them. As we expect there to be |
| 1531 | * associated cost with migrating pages between the backing storage |
| 1532 | * and making them available for the GPU (e.g. clflush), we may hold |
| 1533 | * onto the pages after they are no longer referenced by the GPU |
| 1534 | * in case they may be used again shortly (for example migrating the |
| 1535 | * pages to a different memory domain within the GTT). put_pages() |
| 1536 | * will therefore most likely be called when the object itself is |
| 1537 | * being released or under memory pressure (where we attempt to |
| 1538 | * reap pages for the shrinker). |
| 1539 | */ |
| 1540 | int (*get_pages)(struct drm_i915_gem_object *); |
| 1541 | void (*put_pages)(struct drm_i915_gem_object *); |
| 1542 | }; |
| 1543 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1544 | struct drm_i915_gem_object { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 1545 | struct drm_gem_object base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1546 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1547 | const struct drm_i915_gem_object_ops *ops; |
| 1548 | |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 1549 | /** List of VMAs backed by this object */ |
| 1550 | struct list_head vma_list; |
| 1551 | |
Chris Wilson | c1ad11f | 2012-11-15 11:32:21 +0000 | [diff] [blame] | 1552 | /** Stolen memory for this object, instead of being backed by shmem. */ |
| 1553 | struct drm_mm_node *stolen; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 1554 | struct list_head global_list; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1555 | |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1556 | struct list_head ring_list; |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 1557 | /** Used in execbuf to temporarily hold a ref */ |
| 1558 | struct list_head obj_exec_link; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1559 | |
| 1560 | /** |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 1561 | * This is set if the object is on the active lists (has pending |
| 1562 | * rendering and so a non-zero seqno), and is not set if it i s on |
| 1563 | * inactive (ready to be unbound) list. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1564 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1565 | unsigned int active:1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1566 | |
| 1567 | /** |
| 1568 | * This is set if the object has been written to since last bound |
| 1569 | * to the GTT |
| 1570 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1571 | unsigned int dirty:1; |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 1572 | |
| 1573 | /** |
| 1574 | * Fence register bits (if any) for this object. Will be set |
| 1575 | * as needed when mapped into the GTT. |
| 1576 | * Protected by dev->struct_mutex. |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 1577 | */ |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 1578 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 1579 | |
| 1580 | /** |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 1581 | * Advice: are the backing pages purgeable? |
| 1582 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1583 | unsigned int madv:2; |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 1584 | |
| 1585 | /** |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 1586 | * Current tiling mode for the object. |
| 1587 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1588 | unsigned int tiling_mode:2; |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 1589 | /** |
| 1590 | * Whether the tiling parameters for the currently associated fence |
| 1591 | * register have changed. Note that for the purposes of tracking |
| 1592 | * tiling changes we also treat the unfenced register, the register |
| 1593 | * slot that the object occupies whilst it executes a fenced |
| 1594 | * command (such as BLT on gen2/3), as a "fence". |
| 1595 | */ |
| 1596 | unsigned int fence_dirty:1; |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 1597 | |
| 1598 | /** How many users have pinned this object in GTT space. The following |
| 1599 | * users can each hold at most one reference: pwrite/pread, pin_ioctl |
| 1600 | * (via user_pin_count), execbuffer (objects are not allowed multiple |
| 1601 | * times for the same batchbuffer), and the framebuffer code. When |
| 1602 | * switching/pageflipping, the framebuffer code has at most two buffers |
| 1603 | * pinned per crtc. |
| 1604 | * |
| 1605 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 |
| 1606 | * bits with absolutely no headroom. So use 4 bits. */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1607 | unsigned int pin_count:4; |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 1608 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1609 | |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 1610 | /** |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 1611 | * Is the object at the current location in the gtt mappable and |
| 1612 | * fenceable? Used to avoid costly recalculations. |
| 1613 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1614 | unsigned int map_and_fenceable:1; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 1615 | |
| 1616 | /** |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 1617 | * Whether the current gtt mapping needs to be mappable (and isn't just |
| 1618 | * mappable by accident). Track pin and fault separate for a more |
| 1619 | * accurate mappable working set. |
| 1620 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1621 | unsigned int fault_mappable:1; |
| 1622 | unsigned int pin_mappable:1; |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 1623 | unsigned int pin_display:1; |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 1624 | |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1625 | /* |
| 1626 | * Is the GPU currently using a fence to access this buffer, |
| 1627 | */ |
| 1628 | unsigned int pending_fenced_gpu_access:1; |
| 1629 | unsigned int fenced_gpu_access:1; |
| 1630 | |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 1631 | unsigned int cache_level:3; |
Chris Wilson | 93dfb40 | 2011-03-29 16:59:50 -0700 | [diff] [blame] | 1632 | |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 1633 | unsigned int has_aliasing_ppgtt_mapping:1; |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 1634 | unsigned int has_global_gtt_mapping:1; |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1635 | unsigned int has_dma_mapping:1; |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 1636 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1637 | struct sg_table *pages; |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 1638 | int pages_pin_count; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1639 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1640 | /* prime dma-buf support */ |
Dave Airlie | 9a70cc2 | 2012-05-22 13:09:21 +0100 | [diff] [blame] | 1641 | void *dma_buf_vmapping; |
| 1642 | int vmapping_count; |
| 1643 | |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1644 | struct intel_ring_buffer *ring; |
| 1645 | |
Chris Wilson | 1c293ea | 2012-04-17 15:31:27 +0100 | [diff] [blame] | 1646 | /** Breadcrumb of last rendering to the buffer. */ |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 1647 | uint32_t last_read_seqno; |
| 1648 | uint32_t last_write_seqno; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1649 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
| 1650 | uint32_t last_fenced_seqno; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1651 | |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 1652 | /** Current tiling stride for the object, if it's tiled. */ |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1653 | uint32_t stride; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1654 | |
Daniel Vetter | 80075d4 | 2013-10-09 21:23:52 +0200 | [diff] [blame] | 1655 | /** References from framebuffers, locks out tiling changes. */ |
| 1656 | unsigned long framebuffer_references; |
| 1657 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1658 | /** Record of address bit 17 of each page at last unbind. */ |
Chris Wilson | d312ec2 | 2010-06-06 15:40:22 +0100 | [diff] [blame] | 1659 | unsigned long *bit_17; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1660 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1661 | /** User space pin count and filp owning the pin */ |
Daniel Vetter | aa5f802 | 2013-10-10 14:46:37 +0200 | [diff] [blame] | 1662 | unsigned long user_pin_count; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1663 | struct drm_file *pin_filp; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 1664 | |
| 1665 | /** for phy allocated objects */ |
| 1666 | struct drm_i915_gem_phys_object *phys_obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1667 | }; |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1668 | #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1669 | |
Daniel Vetter | 62b8b21 | 2010-04-09 19:05:08 +0000 | [diff] [blame] | 1670 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1671 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1672 | /** |
| 1673 | * Request queue structure. |
| 1674 | * |
| 1675 | * The request queue allows us to note sequence numbers that have been emitted |
| 1676 | * and may be associated with active buffers to be retired. |
| 1677 | * |
| 1678 | * By keeping this list, we can avoid having to do questionable |
| 1679 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate |
| 1680 | * an emission time with seqnos for tracking how far ahead of the GPU we are. |
| 1681 | */ |
| 1682 | struct drm_i915_gem_request { |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1683 | /** On Which ring this request was generated */ |
| 1684 | struct intel_ring_buffer *ring; |
| 1685 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1686 | /** GEM sequence number associated with this request. */ |
| 1687 | uint32_t seqno; |
| 1688 | |
Mika Kuoppala | 7d736f4 | 2013-06-12 15:01:39 +0300 | [diff] [blame] | 1689 | /** Position in the ringbuffer of the start of the request */ |
| 1690 | u32 head; |
| 1691 | |
| 1692 | /** Position in the ringbuffer of the end of the request */ |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1693 | u32 tail; |
| 1694 | |
Mika Kuoppala | 0e50e96 | 2013-05-02 16:48:08 +0300 | [diff] [blame] | 1695 | /** Context related to this request */ |
| 1696 | struct i915_hw_context *ctx; |
| 1697 | |
Mika Kuoppala | 7d736f4 | 2013-06-12 15:01:39 +0300 | [diff] [blame] | 1698 | /** Batch buffer related to this request if any */ |
| 1699 | struct drm_i915_gem_object *batch_obj; |
| 1700 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1701 | /** Time at which this request was emitted, in jiffies. */ |
| 1702 | unsigned long emitted_jiffies; |
| 1703 | |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1704 | /** global list entry for this request */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1705 | struct list_head list; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1706 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1707 | struct drm_i915_file_private *file_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1708 | /** file_priv list entry for this request */ |
| 1709 | struct list_head client_list; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1710 | }; |
| 1711 | |
| 1712 | struct drm_i915_file_private { |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1713 | struct drm_i915_private *dev_priv; |
| 1714 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1715 | struct { |
Luis R. Rodriguez | 99057c8 | 2012-11-29 12:45:06 -0800 | [diff] [blame] | 1716 | spinlock_t lock; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1717 | struct list_head request_list; |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1718 | struct delayed_work idle_work; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1719 | } mm; |
Ben Widawsky | 4052105 | 2012-06-04 14:42:43 -0700 | [diff] [blame] | 1720 | struct idr context_idr; |
Mika Kuoppala | e59ec13 | 2013-06-12 12:35:28 +0300 | [diff] [blame] | 1721 | |
| 1722 | struct i915_ctx_hang_stats hang_stats; |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1723 | atomic_t rps_wait_boost; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1724 | }; |
| 1725 | |
Chris Wilson | 2c1792a | 2013-08-01 18:39:55 +0100 | [diff] [blame] | 1726 | #define INTEL_INFO(dev) (to_i915(dev)->info) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1727 | |
Ville Syrjälä | ffbab09b | 2013-10-04 14:53:40 +0300 | [diff] [blame] | 1728 | #define IS_I830(dev) ((dev)->pdev->device == 0x3577) |
| 1729 | #define IS_845G(dev) ((dev)->pdev->device == 0x2562) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1730 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
Ville Syrjälä | ffbab09b | 2013-10-04 14:53:40 +0300 | [diff] [blame] | 1731 | #define IS_I865G(dev) ((dev)->pdev->device == 0x2572) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1732 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
Ville Syrjälä | ffbab09b | 2013-10-04 14:53:40 +0300 | [diff] [blame] | 1733 | #define IS_I915GM(dev) ((dev)->pdev->device == 0x2592) |
| 1734 | #define IS_I945G(dev) ((dev)->pdev->device == 0x2772) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1735 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
| 1736 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) |
| 1737 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) |
Ville Syrjälä | ffbab09b | 2013-10-04 14:53:40 +0300 | [diff] [blame] | 1738 | #define IS_GM45(dev) ((dev)->pdev->device == 0x2A42) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1739 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
Ville Syrjälä | ffbab09b | 2013-10-04 14:53:40 +0300 | [diff] [blame] | 1740 | #define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001) |
| 1741 | #define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1742 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
| 1743 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) |
Ville Syrjälä | ffbab09b | 2013-10-04 14:53:40 +0300 | [diff] [blame] | 1744 | #define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046) |
Jesse Barnes | 4b65177 | 2011-04-28 14:33:09 -0700 | [diff] [blame] | 1745 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
Ville Syrjälä | ffbab09b | 2013-10-04 14:53:40 +0300 | [diff] [blame] | 1746 | #define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \ |
| 1747 | (dev)->pdev->device == 0x0152 || \ |
| 1748 | (dev)->pdev->device == 0x015a) |
| 1749 | #define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \ |
| 1750 | (dev)->pdev->device == 0x0106 || \ |
| 1751 | (dev)->pdev->device == 0x010A) |
Jesse Barnes | 70a3eb7 | 2012-03-28 13:39:21 -0700 | [diff] [blame] | 1752 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
Eugeni Dodonov | 4cae9ae | 2012-03-29 12:32:18 -0300 | [diff] [blame] | 1753 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
Paulo Zanoni | 4e8058a | 2013-11-02 21:07:31 -0700 | [diff] [blame] | 1754 | #define IS_BROADWELL(dev) (INTEL_INFO(dev)->gen == 8) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1755 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
Paulo Zanoni | ed1c9e2 | 2013-08-12 14:34:08 -0300 | [diff] [blame] | 1756 | #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ |
Ville Syrjälä | ffbab09b | 2013-10-04 14:53:40 +0300 | [diff] [blame] | 1757 | ((dev)->pdev->device & 0xFF00) == 0x0C00) |
Ben Widawsky | 5dd8c4c | 2013-11-08 10:20:06 -0800 | [diff] [blame] | 1758 | #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ |
| 1759 | (((dev)->pdev->device & 0xf) == 0x2 || \ |
| 1760 | ((dev)->pdev->device & 0xf) == 0x6 || \ |
| 1761 | ((dev)->pdev->device & 0xf) == 0xe)) |
| 1762 | #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ |
Ville Syrjälä | ffbab09b | 2013-10-04 14:53:40 +0300 | [diff] [blame] | 1763 | ((dev)->pdev->device & 0xFF00) == 0x0A00) |
Ben Widawsky | 5dd8c4c | 2013-11-08 10:20:06 -0800 | [diff] [blame] | 1764 | #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
Rodrigo Vivi | 9435373 | 2013-08-28 16:45:46 -0300 | [diff] [blame] | 1765 | #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ |
Ville Syrjälä | ffbab09b | 2013-10-04 14:53:40 +0300 | [diff] [blame] | 1766 | ((dev)->pdev->device & 0x00F0) == 0x0020) |
Ben Widawsky | b833d68 | 2013-08-23 16:00:07 -0700 | [diff] [blame] | 1767 | #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1768 | |
Jesse Barnes | 8543669 | 2011-04-06 12:11:14 -0700 | [diff] [blame] | 1769 | /* |
| 1770 | * The genX designation typically refers to the render engine, so render |
| 1771 | * capability related checks should use IS_GEN, while display and other checks |
| 1772 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular |
| 1773 | * chips, etc.). |
| 1774 | */ |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1775 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
| 1776 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) |
| 1777 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) |
| 1778 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) |
| 1779 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) |
Jesse Barnes | 8543669 | 2011-04-06 12:11:14 -0700 | [diff] [blame] | 1780 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
Ben Widawsky | d298084 | 2013-11-02 21:06:59 -0700 | [diff] [blame] | 1781 | #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1782 | |
Ben Widawsky | 73ae478 | 2013-10-15 10:02:57 -0700 | [diff] [blame] | 1783 | #define RENDER_RING (1<<RCS) |
| 1784 | #define BSD_RING (1<<VCS) |
| 1785 | #define BLT_RING (1<<BCS) |
| 1786 | #define VEBOX_RING (1<<VECS) |
| 1787 | #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) |
| 1788 | #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) |
| 1789 | #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 1790 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 1791 | #define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1792 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
| 1793 | |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 1794 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) |
Jesse Barnes | 9355360 | 2012-06-15 11:55:23 -0700 | [diff] [blame] | 1795 | #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev)) |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1796 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1797 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1798 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
| 1799 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1800 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
| 1801 | #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) |
| 1802 | |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1803 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
| 1804 | * rows, which changed the alignment requirements and fence programming. |
| 1805 | */ |
| 1806 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ |
| 1807 | IS_I915GM(dev))) |
| 1808 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) |
| 1809 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) |
| 1810 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1811 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) |
| 1812 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1813 | |
| 1814 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) |
| 1815 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) |
| 1816 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1817 | |
Ben Widawsky | 2a114cc | 2013-11-02 21:07:47 -0700 | [diff] [blame] | 1818 | #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev)) |
Damien Lespiau | f5adf94 | 2013-06-24 18:29:34 +0100 | [diff] [blame] | 1819 | |
Damien Lespiau | dd93be5 | 2013-04-22 18:40:39 +0100 | [diff] [blame] | 1820 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) |
Paulo Zanoni | 6745a2c | 2013-11-02 21:07:34 -0700 | [diff] [blame] | 1821 | #define HAS_POWER_WELL(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Damien Lespiau | 30568c4 | 2013-04-22 18:40:41 +0100 | [diff] [blame] | 1822 | #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) |
Ben Widawsky | ed8546a | 2013-11-04 22:45:05 -0800 | [diff] [blame] | 1823 | #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Chris Wilson | 7c6c265 | 2013-11-18 18:32:37 -0800 | [diff] [blame] | 1824 | #define HAS_PC8(dev) (IS_HASWELL(dev)) /* XXX HSW:ULX */ |
Paulo Zanoni | affa935 | 2012-11-23 15:30:39 -0200 | [diff] [blame] | 1825 | |
Paulo Zanoni | 17a303e | 2012-11-20 15:12:07 -0200 | [diff] [blame] | 1826 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
| 1827 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 |
| 1828 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 |
| 1829 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 |
| 1830 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 |
| 1831 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 |
| 1832 | |
Chris Wilson | 2c1792a | 2013-08-01 18:39:55 +0100 | [diff] [blame] | 1833 | #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type) |
Eugeni Dodonov | eb877eb | 2012-03-29 12:32:20 -0300 | [diff] [blame] | 1834 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1835 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
| 1836 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) |
Ben Widawsky | 40c7ead | 2013-04-05 13:12:40 -0700 | [diff] [blame] | 1837 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
Paulo Zanoni | 45e6e3a | 2012-07-03 15:57:32 -0300 | [diff] [blame] | 1838 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1839 | |
Ben Widawsky | 040d2ba | 2013-09-19 11:01:40 -0700 | [diff] [blame] | 1840 | /* DPF == dynamic parity feature */ |
| 1841 | #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
| 1842 | #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) |
Ben Widawsky | e1ef7cc | 2012-07-24 20:47:31 -0700 | [diff] [blame] | 1843 | |
Ben Widawsky | c8735b0 | 2012-09-07 19:43:39 -0700 | [diff] [blame] | 1844 | #define GT_FREQUENCY_MULTIPLIER 50 |
| 1845 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1846 | #include "i915_trace.h" |
| 1847 | |
Rob Clark | baa7094 | 2013-08-02 13:27:49 -0400 | [diff] [blame] | 1848 | extern const struct drm_ioctl_desc i915_ioctls[]; |
Dave Airlie | b3a8363 | 2005-09-30 18:37:36 +1000 | [diff] [blame] | 1849 | extern int i915_max_ioctl; |
Ben Widawsky | a35d9d3 | 2011-07-13 14:38:17 -0700 | [diff] [blame] | 1850 | extern unsigned int i915_fbpercrtc __always_unused; |
| 1851 | extern int i915_panel_ignore_lid __read_mostly; |
| 1852 | extern unsigned int i915_powersave __read_mostly; |
Eugeni Dodonov | f45b555 | 2011-12-09 17:16:37 -0800 | [diff] [blame] | 1853 | extern int i915_semaphores __read_mostly; |
Ben Widawsky | a35d9d3 | 2011-07-13 14:38:17 -0700 | [diff] [blame] | 1854 | extern unsigned int i915_lvds_downclock __read_mostly; |
Takashi Iwai | 121d527 | 2012-03-20 13:07:06 +0100 | [diff] [blame] | 1855 | extern int i915_lvds_channel_mode __read_mostly; |
Keith Packard | 4415e63 | 2011-11-09 09:57:50 -0800 | [diff] [blame] | 1856 | extern int i915_panel_use_ssc __read_mostly; |
Ben Widawsky | a35d9d3 | 2011-07-13 14:38:17 -0700 | [diff] [blame] | 1857 | extern int i915_vbt_sdvo_panel_type __read_mostly; |
Keith Packard | c0f372b3 | 2011-11-16 22:24:52 -0800 | [diff] [blame] | 1858 | extern int i915_enable_rc6 __read_mostly; |
Keith Packard | 4415e63 | 2011-11-09 09:57:50 -0800 | [diff] [blame] | 1859 | extern int i915_enable_fbc __read_mostly; |
Ben Widawsky | a35d9d3 | 2011-07-13 14:38:17 -0700 | [diff] [blame] | 1860 | extern bool i915_enable_hangcheck __read_mostly; |
Daniel Vetter | 650dc07 | 2012-04-02 10:08:35 +0200 | [diff] [blame] | 1861 | extern int i915_enable_ppgtt __read_mostly; |
Rodrigo Vivi | 105b7c1 | 2013-07-11 18:45:02 -0300 | [diff] [blame] | 1862 | extern int i915_enable_psr __read_mostly; |
Rodrigo Vivi | 0a3af26 | 2012-10-15 17:16:23 -0300 | [diff] [blame] | 1863 | extern unsigned int i915_preliminary_hw_support __read_mostly; |
Paulo Zanoni | 2124b72 | 2013-03-22 14:07:23 -0300 | [diff] [blame] | 1864 | extern int i915_disable_power_well __read_mostly; |
Paulo Zanoni | 3c4ca58 | 2013-05-31 16:33:23 -0300 | [diff] [blame] | 1865 | extern int i915_enable_ips __read_mostly; |
Jesse Barnes | 2385bdf | 2013-06-26 01:38:15 +0300 | [diff] [blame] | 1866 | extern bool i915_fastboot __read_mostly; |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 1867 | extern int i915_enable_pc8 __read_mostly; |
Paulo Zanoni | 9005874 | 2013-08-19 13:18:11 -0300 | [diff] [blame] | 1868 | extern int i915_pc8_timeout __read_mostly; |
Xiong Zhang | 0b74b50 | 2013-07-19 13:51:24 +0800 | [diff] [blame] | 1869 | extern bool i915_prefault_disable __read_mostly; |
Dave Airlie | b3a8363 | 2005-09-30 18:37:36 +1000 | [diff] [blame] | 1870 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1871 | extern int i915_suspend(struct drm_device *dev, pm_message_t state); |
| 1872 | extern int i915_resume(struct drm_device *dev); |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1873 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
| 1874 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); |
| 1875 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1876 | /* i915_dma.c */ |
Daniel Vetter | d05c617 | 2012-04-26 23:28:09 +0200 | [diff] [blame] | 1877 | void i915_update_dri1_breadcrumb(struct drm_device *dev); |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1878 | extern void i915_kernel_lost_context(struct drm_device * dev); |
Dave Airlie | 22eae94 | 2005-11-10 22:16:34 +1100 | [diff] [blame] | 1879 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 1880 | extern int i915_driver_unload(struct drm_device *); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1881 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1882 | extern void i915_driver_lastclose(struct drm_device * dev); |
Eric Anholt | 6c340ea | 2007-08-25 20:23:09 +1000 | [diff] [blame] | 1883 | extern void i915_driver_preclose(struct drm_device *dev, |
| 1884 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1885 | extern void i915_driver_postclose(struct drm_device *dev, |
| 1886 | struct drm_file *file_priv); |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1887 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 1888 | #ifdef CONFIG_COMPAT |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 1889 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
| 1890 | unsigned long arg); |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 1891 | #endif |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1892 | extern int i915_emit_box(struct drm_device *dev, |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1893 | struct drm_clip_rect *box, |
| 1894 | int DR1, int DR4); |
Ben Widawsky | 8e96d9c | 2012-06-04 14:42:56 -0700 | [diff] [blame] | 1895 | extern int intel_gpu_reset(struct drm_device *dev); |
Daniel Vetter | d4b8bb2 | 2012-04-27 15:17:44 +0200 | [diff] [blame] | 1896 | extern int i915_reset(struct drm_device *dev); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1897 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
| 1898 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); |
| 1899 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); |
| 1900 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); |
| 1901 | |
Jesse Barnes | 073f34d | 2012-11-02 11:13:59 -0700 | [diff] [blame] | 1902 | extern void intel_console_resume(struct work_struct *work); |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 1903 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1904 | /* i915_irq.c */ |
Mika Kuoppala | 10cd45b | 2013-07-03 17:22:08 +0300 | [diff] [blame] | 1905 | void i915_queue_hangcheck(struct drm_device *dev); |
Chris Wilson | 527f9e9 | 2010-11-11 01:16:58 +0000 | [diff] [blame] | 1906 | void i915_handle_error(struct drm_device *dev, bool wedged); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1907 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 1908 | extern void intel_irq_init(struct drm_device *dev); |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 1909 | extern void intel_hpd_init(struct drm_device *dev); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1910 | |
| 1911 | extern void intel_uncore_sanitize(struct drm_device *dev); |
| 1912 | extern void intel_uncore_early_sanitize(struct drm_device *dev); |
| 1913 | extern void intel_uncore_init(struct drm_device *dev); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1914 | extern void intel_uncore_clear_errors(struct drm_device *dev); |
| 1915 | extern void intel_uncore_check_errors(struct drm_device *dev); |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 1916 | extern void intel_uncore_fini(struct drm_device *dev); |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 1917 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1918 | void |
Daniel Vetter | 3b6c42e | 2013-10-21 18:04:35 +0200 | [diff] [blame] | 1919 | i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1920 | |
| 1921 | void |
Daniel Vetter | 3b6c42e | 2013-10-21 18:04:35 +0200 | [diff] [blame] | 1922 | i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1923 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1924 | /* i915_gem.c */ |
| 1925 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, |
| 1926 | struct drm_file *file_priv); |
| 1927 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 1928 | struct drm_file *file_priv); |
| 1929 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
| 1930 | struct drm_file *file_priv); |
| 1931 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
| 1932 | struct drm_file *file_priv); |
| 1933 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
| 1934 | struct drm_file *file_priv); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1935 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 1936 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1937 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
| 1938 | struct drm_file *file_priv); |
| 1939 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
| 1940 | struct drm_file *file_priv); |
| 1941 | int i915_gem_execbuffer(struct drm_device *dev, void *data, |
| 1942 | struct drm_file *file_priv); |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 1943 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
| 1944 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1945 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
| 1946 | struct drm_file *file_priv); |
| 1947 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
| 1948 | struct drm_file *file_priv); |
| 1949 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
| 1950 | struct drm_file *file_priv); |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 1951 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
| 1952 | struct drm_file *file); |
| 1953 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
| 1954 | struct drm_file *file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1955 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 1956 | struct drm_file *file_priv); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1957 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 1958 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1959 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
| 1960 | struct drm_file *file_priv); |
| 1961 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
| 1962 | struct drm_file *file_priv); |
| 1963 | int i915_gem_set_tiling(struct drm_device *dev, void *data, |
| 1964 | struct drm_file *file_priv); |
| 1965 | int i915_gem_get_tiling(struct drm_device *dev, void *data, |
| 1966 | struct drm_file *file_priv); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 1967 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
| 1968 | struct drm_file *file_priv); |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 1969 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
| 1970 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1971 | void i915_gem_load(struct drm_device *dev); |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 1972 | void *i915_gem_object_alloc(struct drm_device *dev); |
| 1973 | void i915_gem_object_free(struct drm_i915_gem_object *obj); |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1974 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
| 1975 | const struct drm_i915_gem_object_ops *ops); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1976 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
| 1977 | size_t size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1978 | void i915_gem_free_object(struct drm_gem_object *obj); |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 1979 | void i915_gem_vma_destroy(struct i915_vma *vma); |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 1980 | |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 1981 | int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, |
Ben Widawsky | c37e220 | 2013-07-31 16:59:58 -0700 | [diff] [blame] | 1982 | struct i915_address_space *vm, |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 1983 | uint32_t alignment, |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 1984 | bool map_and_fenceable, |
| 1985 | bool nonblocking); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1986 | void i915_gem_object_unpin(struct drm_i915_gem_object *obj); |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 1987 | int __must_check i915_vma_unbind(struct i915_vma *vma); |
| 1988 | int __must_check i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj); |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1989 | int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1990 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1991 | void i915_gem_lastclose(struct drm_device *dev); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1992 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1993 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1994 | static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) |
| 1995 | { |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 1996 | struct sg_page_iter sg_iter; |
Chris Wilson | 1cf8378 | 2012-10-10 12:11:52 +0100 | [diff] [blame] | 1997 | |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 1998 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n) |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 1999 | return sg_page_iter_page(&sg_iter); |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 2000 | |
| 2001 | return NULL; |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2002 | } |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 2003 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
| 2004 | { |
| 2005 | BUG_ON(obj->pages == NULL); |
| 2006 | obj->pages_pin_count++; |
| 2007 | } |
| 2008 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) |
| 2009 | { |
| 2010 | BUG_ON(obj->pages_pin_count == 0); |
| 2011 | obj->pages_pin_count--; |
| 2012 | } |
| 2013 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 2014 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2015 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
| 2016 | struct intel_ring_buffer *to); |
Ben Widawsky | e2d05a8 | 2013-09-24 09:57:58 -0700 | [diff] [blame] | 2017 | void i915_vma_move_to_active(struct i915_vma *vma, |
| 2018 | struct intel_ring_buffer *ring); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 2019 | int i915_gem_dumb_create(struct drm_file *file_priv, |
| 2020 | struct drm_device *dev, |
| 2021 | struct drm_mode_create_dumb *args); |
| 2022 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, |
| 2023 | uint32_t handle, uint64_t *offset); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2024 | /** |
| 2025 | * Returns true if seq1 is later than seq2. |
| 2026 | */ |
| 2027 | static inline bool |
| 2028 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) |
| 2029 | { |
| 2030 | return (int32_t)(seq1 - seq2) >= 0; |
| 2031 | } |
| 2032 | |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 2033 | int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); |
| 2034 | int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); |
Chris Wilson | 06d9813 | 2012-04-17 15:31:24 +0100 | [diff] [blame] | 2035 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2036 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 2037 | |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 2038 | static inline bool |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2039 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) |
| 2040 | { |
| 2041 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 2042 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 2043 | dev_priv->fence_regs[obj->fence_reg].pin_count++; |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 2044 | return true; |
| 2045 | } else |
| 2046 | return false; |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2047 | } |
| 2048 | |
| 2049 | static inline void |
| 2050 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) |
| 2051 | { |
| 2052 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 2053 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | b8c3af7 | 2013-06-12 11:29:47 +0100 | [diff] [blame] | 2054 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0); |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2055 | dev_priv->fence_regs[obj->fence_reg].pin_count--; |
| 2056 | } |
| 2057 | } |
| 2058 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2059 | bool i915_gem_retire_requests(struct drm_device *dev); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2060 | void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 2061 | int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, |
Daniel Vetter | d6b2c79 | 2012-07-04 22:54:13 +0200 | [diff] [blame] | 2062 | bool interruptible); |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 2063 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) |
| 2064 | { |
| 2065 | return unlikely(atomic_read(&error->reset_counter) |
| 2066 | & I915_RESET_IN_PROGRESS_FLAG); |
| 2067 | } |
| 2068 | |
| 2069 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) |
| 2070 | { |
| 2071 | return atomic_read(&error->reset_counter) == I915_WEDGED; |
| 2072 | } |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2073 | |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 2074 | void i915_gem_reset(struct drm_device *dev); |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 2075 | bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2076 | int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 2077 | int __must_check i915_gem_init(struct drm_device *dev); |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 2078 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 2079 | int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice); |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 2080 | void i915_gem_init_swizzling(struct drm_device *dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2081 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 2082 | int __must_check i915_gpu_idle(struct drm_device *dev); |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 2083 | int __must_check i915_gem_suspend(struct drm_device *dev); |
Mika Kuoppala | 0025c07 | 2013-06-12 12:35:30 +0300 | [diff] [blame] | 2084 | int __i915_add_request(struct intel_ring_buffer *ring, |
| 2085 | struct drm_file *file, |
Mika Kuoppala | 7d736f4 | 2013-06-12 15:01:39 +0300 | [diff] [blame] | 2086 | struct drm_i915_gem_object *batch_obj, |
Mika Kuoppala | 0025c07 | 2013-06-12 12:35:30 +0300 | [diff] [blame] | 2087 | u32 *seqno); |
| 2088 | #define i915_add_request(ring, seqno) \ |
Dan Carpenter | 854c94a | 2013-06-18 10:29:58 +0300 | [diff] [blame] | 2089 | __i915_add_request(ring, NULL, NULL, seqno) |
Ben Widawsky | 199b2bc | 2012-05-24 15:03:11 -0700 | [diff] [blame] | 2090 | int __must_check i915_wait_seqno(struct intel_ring_buffer *ring, |
| 2091 | uint32_t seqno); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2092 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 2093 | int __must_check |
| 2094 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, |
| 2095 | bool write); |
| 2096 | int __must_check |
Chris Wilson | dabdfe0 | 2012-03-26 10:10:27 +0200 | [diff] [blame] | 2097 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
| 2098 | int __must_check |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 2099 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
| 2100 | u32 alignment, |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 2101 | struct intel_ring_buffer *pipelined); |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 2102 | void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 2103 | int i915_gem_attach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2104 | struct drm_i915_gem_object *obj, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 2105 | int id, |
| 2106 | int align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 2107 | void i915_gem_detach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2108 | struct drm_i915_gem_object *obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 2109 | void i915_gem_free_all_phys_object(struct drm_device *dev); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2110 | int i915_gem_open(struct drm_device *dev, struct drm_file *file); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2111 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2112 | |
Chris Wilson | 467cffb | 2011-03-07 10:42:03 +0000 | [diff] [blame] | 2113 | uint32_t |
Imre Deak | 0fa8779 | 2013-01-07 21:47:35 +0200 | [diff] [blame] | 2114 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); |
| 2115 | uint32_t |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 2116 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
| 2117 | int tiling_mode, bool fenced); |
Chris Wilson | 467cffb | 2011-03-07 10:42:03 +0000 | [diff] [blame] | 2118 | |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 2119 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
| 2120 | enum i915_cache_level cache_level); |
| 2121 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 2122 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
| 2123 | struct dma_buf *dma_buf); |
| 2124 | |
| 2125 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, |
| 2126 | struct drm_gem_object *gem_obj, int flags); |
| 2127 | |
Chris Wilson | 19b2dbd | 2013-06-12 10:15:12 +0100 | [diff] [blame] | 2128 | void i915_gem_restore_fences(struct drm_device *dev); |
| 2129 | |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 2130 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, |
| 2131 | struct i915_address_space *vm); |
| 2132 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); |
| 2133 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, |
| 2134 | struct i915_address_space *vm); |
| 2135 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, |
| 2136 | struct i915_address_space *vm); |
| 2137 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
| 2138 | struct i915_address_space *vm); |
Ben Widawsky | accfef2 | 2013-08-14 11:38:35 +0200 | [diff] [blame] | 2139 | struct i915_vma * |
| 2140 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, |
| 2141 | struct i915_address_space *vm); |
Ben Widawsky | 5c2abbe | 2013-09-24 09:57:57 -0700 | [diff] [blame] | 2142 | |
| 2143 | struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj); |
| 2144 | |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 2145 | /* Some GGTT VM helpers */ |
| 2146 | #define obj_to_ggtt(obj) \ |
| 2147 | (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base) |
| 2148 | static inline bool i915_is_ggtt(struct i915_address_space *vm) |
| 2149 | { |
| 2150 | struct i915_address_space *ggtt = |
| 2151 | &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base; |
| 2152 | return vm == ggtt; |
| 2153 | } |
| 2154 | |
| 2155 | static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) |
| 2156 | { |
| 2157 | return i915_gem_obj_bound(obj, obj_to_ggtt(obj)); |
| 2158 | } |
| 2159 | |
| 2160 | static inline unsigned long |
| 2161 | i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj) |
| 2162 | { |
| 2163 | return i915_gem_obj_offset(obj, obj_to_ggtt(obj)); |
| 2164 | } |
| 2165 | |
| 2166 | static inline unsigned long |
| 2167 | i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) |
| 2168 | { |
| 2169 | return i915_gem_obj_size(obj, obj_to_ggtt(obj)); |
| 2170 | } |
Ben Widawsky | c37e220 | 2013-07-31 16:59:58 -0700 | [diff] [blame] | 2171 | |
| 2172 | static inline int __must_check |
| 2173 | i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, |
| 2174 | uint32_t alignment, |
| 2175 | bool map_and_fenceable, |
| 2176 | bool nonblocking) |
| 2177 | { |
| 2178 | return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, |
| 2179 | map_and_fenceable, nonblocking); |
| 2180 | } |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 2181 | |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 2182 | /* i915_gem_context.c */ |
| 2183 | void i915_gem_context_init(struct drm_device *dev); |
| 2184 | void i915_gem_context_fini(struct drm_device *dev); |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 2185 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
Ben Widawsky | e055684 | 2012-06-04 14:42:46 -0700 | [diff] [blame] | 2186 | int i915_switch_context(struct intel_ring_buffer *ring, |
| 2187 | struct drm_file *file, int to_id); |
Mika Kuoppala | dce3271 | 2013-04-30 13:30:33 +0300 | [diff] [blame] | 2188 | void i915_gem_context_free(struct kref *ctx_ref); |
| 2189 | static inline void i915_gem_context_reference(struct i915_hw_context *ctx) |
| 2190 | { |
| 2191 | kref_get(&ctx->ref); |
| 2192 | } |
| 2193 | |
| 2194 | static inline void i915_gem_context_unreference(struct i915_hw_context *ctx) |
| 2195 | { |
| 2196 | kref_put(&ctx->ref, i915_gem_context_free); |
| 2197 | } |
| 2198 | |
Mika Kuoppala | c0bb617 | 2013-06-12 12:35:29 +0300 | [diff] [blame] | 2199 | struct i915_ctx_hang_stats * __must_check |
Chris Wilson | 11fa338 | 2013-07-03 17:22:06 +0300 | [diff] [blame] | 2200 | i915_gem_context_get_hang_stats(struct drm_device *dev, |
Mika Kuoppala | c0bb617 | 2013-06-12 12:35:29 +0300 | [diff] [blame] | 2201 | struct drm_file *file, |
| 2202 | u32 id); |
Ben Widawsky | 8462481 | 2012-06-04 14:42:54 -0700 | [diff] [blame] | 2203 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
| 2204 | struct drm_file *file); |
| 2205 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, |
| 2206 | struct drm_file *file); |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 2207 | |
Daniel Vetter | 76aaf22 | 2010-11-05 22:23:30 +0100 | [diff] [blame] | 2208 | /* i915_gem_gtt.c */ |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 2209 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2210 | void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, |
| 2211 | struct drm_i915_gem_object *obj, |
| 2212 | enum i915_cache_level cache_level); |
| 2213 | void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, |
| 2214 | struct drm_i915_gem_object *obj); |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 2215 | |
Ben Widawsky | 828c790 | 2013-10-16 09:21:30 -0700 | [diff] [blame] | 2216 | void i915_check_and_clear_faults(struct drm_device *dev); |
| 2217 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev); |
Daniel Vetter | 76aaf22 | 2010-11-05 22:23:30 +0100 | [diff] [blame] | 2218 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 2219 | int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); |
| 2220 | void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 2221 | enum i915_cache_level cache_level); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2222 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 2223 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); |
Ben Widawsky | d7e5008 | 2012-12-18 10:31:25 -0800 | [diff] [blame] | 2224 | void i915_gem_init_global_gtt(struct drm_device *dev); |
| 2225 | void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start, |
| 2226 | unsigned long mappable_end, unsigned long end); |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 2227 | int i915_gem_gtt_init(struct drm_device *dev); |
Ben Widawsky | d09105c | 2012-11-15 12:06:09 -0800 | [diff] [blame] | 2228 | static inline void i915_gem_chipset_flush(struct drm_device *dev) |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 2229 | { |
| 2230 | if (INTEL_INFO(dev)->gen < 6) |
| 2231 | intel_gtt_chipset_flush(); |
| 2232 | } |
| 2233 | |
Daniel Vetter | 76aaf22 | 2010-11-05 22:23:30 +0100 | [diff] [blame] | 2234 | |
Chris Wilson | b47eb4a | 2010-08-07 11:01:23 +0100 | [diff] [blame] | 2235 | /* i915_gem_evict.c */ |
Ben Widawsky | f6cd1f1 | 2013-07-31 17:00:11 -0700 | [diff] [blame] | 2236 | int __must_check i915_gem_evict_something(struct drm_device *dev, |
| 2237 | struct i915_address_space *vm, |
| 2238 | int min_size, |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 2239 | unsigned alignment, |
| 2240 | unsigned cache_level, |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 2241 | bool mappable, |
| 2242 | bool nonblock); |
Ben Widawsky | 68c8c17 | 2013-09-11 14:57:50 -0700 | [diff] [blame] | 2243 | int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2244 | int i915_gem_evict_everything(struct drm_device *dev); |
Chris Wilson | b47eb4a | 2010-08-07 11:01:23 +0100 | [diff] [blame] | 2245 | |
Chris Wilson | 9797fbf | 2012-04-24 15:47:39 +0100 | [diff] [blame] | 2246 | /* i915_gem_stolen.c */ |
| 2247 | int i915_gem_init_stolen(struct drm_device *dev); |
Chris Wilson | 11be49e | 2012-11-15 11:32:20 +0000 | [diff] [blame] | 2248 | int i915_gem_stolen_setup_compression(struct drm_device *dev, int size); |
| 2249 | void i915_gem_stolen_cleanup_compression(struct drm_device *dev); |
Chris Wilson | 9797fbf | 2012-04-24 15:47:39 +0100 | [diff] [blame] | 2250 | void i915_gem_cleanup_stolen(struct drm_device *dev); |
Chris Wilson | 0104fdb | 2012-11-15 11:32:26 +0000 | [diff] [blame] | 2251 | struct drm_i915_gem_object * |
| 2252 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); |
Chris Wilson | 866d12b | 2013-02-19 13:31:37 -0800 | [diff] [blame] | 2253 | struct drm_i915_gem_object * |
| 2254 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, |
| 2255 | u32 stolen_offset, |
| 2256 | u32 gtt_offset, |
| 2257 | u32 size); |
Chris Wilson | 0104fdb | 2012-11-15 11:32:26 +0000 | [diff] [blame] | 2258 | void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj); |
Chris Wilson | 9797fbf | 2012-04-24 15:47:39 +0100 | [diff] [blame] | 2259 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2260 | /* i915_gem_tiling.c */ |
Chris Wilson | 2c1792a | 2013-08-01 18:39:55 +0100 | [diff] [blame] | 2261 | static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
Chris Wilson | e9b73c6 | 2012-12-03 21:03:14 +0000 | [diff] [blame] | 2262 | { |
| 2263 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
| 2264 | |
| 2265 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && |
| 2266 | obj->tiling_mode != I915_TILING_NONE; |
| 2267 | } |
| 2268 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2269 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2270 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
| 2271 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2272 | |
| 2273 | /* i915_gem_debug.c */ |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 2274 | #if WATCH_LISTS |
| 2275 | int i915_verify_lists(struct drm_device *dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2276 | #else |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 2277 | #define i915_verify_lists(dev) 0 |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2278 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2279 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 2280 | /* i915_debugfs.c */ |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 2281 | int i915_debugfs_init(struct drm_minor *minor); |
| 2282 | void i915_debugfs_cleanup(struct drm_minor *minor); |
Daniel Vetter | f8c168f | 2013-10-16 11:49:58 +0200 | [diff] [blame] | 2283 | #ifdef CONFIG_DEBUG_FS |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2284 | void intel_display_crc_init(struct drm_device *dev); |
| 2285 | #else |
Daniel Vetter | f8c168f | 2013-10-16 11:49:58 +0200 | [diff] [blame] | 2286 | static inline void intel_display_crc_init(struct drm_device *dev) {} |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2287 | #endif |
Mika Kuoppala | 84734a0 | 2013-07-12 16:50:57 +0300 | [diff] [blame] | 2288 | |
| 2289 | /* i915_gpu_error.c */ |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 2290 | __printf(2, 3) |
| 2291 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); |
Mika Kuoppala | fc16b48 | 2013-06-06 15:18:39 +0300 | [diff] [blame] | 2292 | int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, |
| 2293 | const struct i915_error_state_file_priv *error); |
Mika Kuoppala | 4dc955f | 2013-06-06 15:18:41 +0300 | [diff] [blame] | 2294 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, |
| 2295 | size_t count, loff_t pos); |
| 2296 | static inline void i915_error_state_buf_release( |
| 2297 | struct drm_i915_error_state_buf *eb) |
| 2298 | { |
| 2299 | kfree(eb->buf); |
| 2300 | } |
Mika Kuoppala | 84734a0 | 2013-07-12 16:50:57 +0300 | [diff] [blame] | 2301 | void i915_capture_error_state(struct drm_device *dev); |
| 2302 | void i915_error_state_get(struct drm_device *dev, |
| 2303 | struct i915_error_state_file_priv *error_priv); |
| 2304 | void i915_error_state_put(struct i915_error_state_file_priv *error_priv); |
| 2305 | void i915_destroy_error_state(struct drm_device *dev); |
| 2306 | |
| 2307 | void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); |
| 2308 | const char *i915_cache_level_str(int type); |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 2309 | |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 2310 | /* i915_suspend.c */ |
| 2311 | extern int i915_save_state(struct drm_device *dev); |
| 2312 | extern int i915_restore_state(struct drm_device *dev); |
| 2313 | |
Daniel Vetter | d8157a3 | 2013-01-25 17:53:20 +0100 | [diff] [blame] | 2314 | /* i915_ums.c */ |
| 2315 | void i915_save_display_reg(struct drm_device *dev); |
| 2316 | void i915_restore_display_reg(struct drm_device *dev); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 2317 | |
Ben Widawsky | 0136db58 | 2012-04-10 21:17:01 -0700 | [diff] [blame] | 2318 | /* i915_sysfs.c */ |
| 2319 | void i915_setup_sysfs(struct drm_device *dev_priv); |
| 2320 | void i915_teardown_sysfs(struct drm_device *dev_priv); |
| 2321 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2322 | /* intel_i2c.c */ |
| 2323 | extern int intel_setup_gmbus(struct drm_device *dev); |
| 2324 | extern void intel_teardown_gmbus(struct drm_device *dev); |
Jan-Simon Möller | 8f375e1 | 2013-05-06 14:52:08 +0200 | [diff] [blame] | 2325 | static inline bool intel_gmbus_is_port_valid(unsigned port) |
Daniel Kurtz | 3bd7d90 | 2012-03-28 02:36:14 +0800 | [diff] [blame] | 2326 | { |
Daniel Kurtz | 2ed06c9 | 2012-03-28 02:36:15 +0800 | [diff] [blame] | 2327 | return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); |
Daniel Kurtz | 3bd7d90 | 2012-03-28 02:36:14 +0800 | [diff] [blame] | 2328 | } |
| 2329 | |
| 2330 | extern struct i2c_adapter *intel_gmbus_get_adapter( |
| 2331 | struct drm_i915_private *dev_priv, unsigned port); |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 2332 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
| 2333 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); |
Jan-Simon Möller | 8f375e1 | 2013-05-06 14:52:08 +0200 | [diff] [blame] | 2334 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
Chris Wilson | b8232e9 | 2010-09-28 16:41:32 +0100 | [diff] [blame] | 2335 | { |
| 2336 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; |
| 2337 | } |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2338 | extern void intel_i2c_reset(struct drm_device *dev); |
| 2339 | |
Chris Wilson | 3b61796 | 2010-08-24 09:02:58 +0100 | [diff] [blame] | 2340 | /* intel_opregion.c */ |
Jani Nikula | 9c4b0a6 | 2013-08-30 19:40:30 +0300 | [diff] [blame] | 2341 | struct intel_encoder; |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 2342 | extern int intel_opregion_setup(struct drm_device *dev); |
| 2343 | #ifdef CONFIG_ACPI |
| 2344 | extern void intel_opregion_init(struct drm_device *dev); |
| 2345 | extern void intel_opregion_fini(struct drm_device *dev); |
Chris Wilson | 3b61796 | 2010-08-24 09:02:58 +0100 | [diff] [blame] | 2346 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
Jani Nikula | 9c4b0a6 | 2013-08-30 19:40:30 +0300 | [diff] [blame] | 2347 | extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, |
| 2348 | bool enable); |
Jani Nikula | ecbc5cf | 2013-08-30 19:40:31 +0300 | [diff] [blame] | 2349 | extern int intel_opregion_notify_adapter(struct drm_device *dev, |
| 2350 | pci_power_t state); |
Len Brown | 65e082c | 2008-10-24 17:18:10 -0400 | [diff] [blame] | 2351 | #else |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 2352 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
| 2353 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } |
Chris Wilson | 3b61796 | 2010-08-24 09:02:58 +0100 | [diff] [blame] | 2354 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
Jani Nikula | 9c4b0a6 | 2013-08-30 19:40:30 +0300 | [diff] [blame] | 2355 | static inline int |
| 2356 | intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) |
| 2357 | { |
| 2358 | return 0; |
| 2359 | } |
Jani Nikula | ecbc5cf | 2013-08-30 19:40:31 +0300 | [diff] [blame] | 2360 | static inline int |
| 2361 | intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state) |
| 2362 | { |
| 2363 | return 0; |
| 2364 | } |
Len Brown | 65e082c | 2008-10-24 17:18:10 -0400 | [diff] [blame] | 2365 | #endif |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 2366 | |
Jesse Barnes | 723bfd7 | 2010-10-07 16:01:13 -0700 | [diff] [blame] | 2367 | /* intel_acpi.c */ |
| 2368 | #ifdef CONFIG_ACPI |
| 2369 | extern void intel_register_dsm_handler(void); |
| 2370 | extern void intel_unregister_dsm_handler(void); |
| 2371 | #else |
| 2372 | static inline void intel_register_dsm_handler(void) { return; } |
| 2373 | static inline void intel_unregister_dsm_handler(void) { return; } |
| 2374 | #endif /* CONFIG_ACPI */ |
| 2375 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2376 | /* modesetting */ |
Daniel Vetter | f817586 | 2012-04-10 15:50:11 +0200 | [diff] [blame] | 2377 | extern void intel_modeset_init_hw(struct drm_device *dev); |
Imre Deak | 7d708ee | 2013-04-17 14:04:50 +0300 | [diff] [blame] | 2378 | extern void intel_modeset_suspend_hw(struct drm_device *dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2379 | extern void intel_modeset_init(struct drm_device *dev); |
Chris Wilson | 2c7111d | 2011-03-29 10:40:27 +0100 | [diff] [blame] | 2380 | extern void intel_modeset_gem_init(struct drm_device *dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2381 | extern void intel_modeset_cleanup(struct drm_device *dev); |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 2382 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
Daniel Vetter | 45e2b5f | 2012-11-23 18:16:34 +0100 | [diff] [blame] | 2383 | extern void intel_modeset_setup_hw_state(struct drm_device *dev, |
| 2384 | bool force_restore); |
Daniel Vetter | 44cec74 | 2013-01-25 17:53:21 +0100 | [diff] [blame] | 2385 | extern void i915_redisable_vga(struct drm_device *dev); |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 2386 | extern bool intel_fbc_enabled(struct drm_device *dev); |
Chris Wilson | 43a9539 | 2011-07-08 12:22:36 +0100 | [diff] [blame] | 2387 | extern void intel_disable_fbc(struct drm_device *dev); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 2388 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 2389 | extern void intel_init_pch_refclk(struct drm_device *dev); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 2390 | extern void gen6_set_rps(struct drm_device *dev, u8 val); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 2391 | extern void valleyview_set_rps(struct drm_device *dev, u8 val); |
| 2392 | extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv); |
| 2393 | extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2394 | extern void intel_detect_pch(struct drm_device *dev); |
| 2395 | extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); |
Ben Widawsky | 0136db58 | 2012-04-10 21:17:01 -0700 | [diff] [blame] | 2396 | extern int intel_enable_rc6(const struct drm_device *dev); |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 2397 | |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2398 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
Ben Widawsky | c0c7bab | 2012-07-12 11:01:05 -0700 | [diff] [blame] | 2399 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
| 2400 | struct drm_file *file); |
Jesse Barnes | 575155a | 2012-03-28 13:39:37 -0700 | [diff] [blame] | 2401 | |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 2402 | /* overlay */ |
| 2403 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 2404 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, |
| 2405 | struct intel_overlay_error_state *error); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 2406 | |
| 2407 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 2408 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 2409 | struct drm_device *dev, |
| 2410 | struct intel_display_error_state *error); |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 2411 | |
Ben Widawsky | b7287d8 | 2011-04-25 11:22:22 -0700 | [diff] [blame] | 2412 | /* On SNB platform, before reading ring registers forcewake bit |
| 2413 | * must be set to prevent GT core from power down and stale values being |
| 2414 | * returned. |
| 2415 | */ |
Ben Widawsky | fcca792 | 2011-04-25 11:23:07 -0700 | [diff] [blame] | 2416 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); |
| 2417 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); |
Ben Widawsky | b7287d8 | 2011-04-25 11:22:22 -0700 | [diff] [blame] | 2418 | |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 2419 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); |
| 2420 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); |
Jani Nikula | 59de081 | 2013-05-22 15:36:16 +0300 | [diff] [blame] | 2421 | |
| 2422 | /* intel_sideband.c */ |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 2423 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr); |
| 2424 | void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val); |
| 2425 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); |
Jani Nikula | e9f882a | 2013-08-27 15:12:14 +0300 | [diff] [blame] | 2426 | u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); |
| 2427 | void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
| 2428 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); |
| 2429 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
| 2430 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); |
| 2431 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
| 2432 | u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg); |
| 2433 | void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 2434 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); |
| 2435 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); |
Jani Nikula | 59de081 | 2013-05-22 15:36:16 +0300 | [diff] [blame] | 2436 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
| 2437 | enum intel_sbi_destination destination); |
| 2438 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, |
| 2439 | enum intel_sbi_destination destination); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 2440 | |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 2441 | int vlv_gpu_freq(int ddr_freq, int val); |
| 2442 | int vlv_freq_opcode(int ddr_freq, int val); |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 2443 | |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 2444 | #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) |
| 2445 | #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) |
Keith Packard | 5f75377 | 2010-11-22 09:24:22 +0000 | [diff] [blame] | 2446 | |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 2447 | #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) |
| 2448 | #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) |
| 2449 | #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) |
| 2450 | #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) |
Keith Packard | 5f75377 | 2010-11-22 09:24:22 +0000 | [diff] [blame] | 2451 | |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 2452 | #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) |
| 2453 | #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) |
| 2454 | #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) |
| 2455 | #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) |
Keith Packard | 5f75377 | 2010-11-22 09:24:22 +0000 | [diff] [blame] | 2456 | |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 2457 | #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) |
| 2458 | #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 2459 | |
| 2460 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
| 2461 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) |
| 2462 | |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 2463 | /* "Broadcast RGB" property */ |
| 2464 | #define INTEL_BROADCAST_RGB_AUTO 0 |
| 2465 | #define INTEL_BROADCAST_RGB_FULL 1 |
| 2466 | #define INTEL_BROADCAST_RGB_LIMITED 2 |
Yuanhan Liu | ba4f01a | 2010-11-08 17:09:41 +0800 | [diff] [blame] | 2467 | |
Ville Syrjälä | 766aa1c | 2013-01-25 21:44:46 +0200 | [diff] [blame] | 2468 | static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) |
| 2469 | { |
| 2470 | if (HAS_PCH_SPLIT(dev)) |
| 2471 | return CPU_VGACNTRL; |
| 2472 | else if (IS_VALLEYVIEW(dev)) |
| 2473 | return VLV_VGACNTRL; |
| 2474 | else |
| 2475 | return VGACNTRL; |
| 2476 | } |
| 2477 | |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 2478 | static inline void __user *to_user_ptr(u64 address) |
| 2479 | { |
| 2480 | return (void __user *)(uintptr_t)address; |
| 2481 | } |
| 2482 | |
Imre Deak | df97729 | 2013-05-21 20:03:17 +0300 | [diff] [blame] | 2483 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
| 2484 | { |
| 2485 | unsigned long j = msecs_to_jiffies(m); |
| 2486 | |
| 2487 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); |
| 2488 | } |
| 2489 | |
| 2490 | static inline unsigned long |
| 2491 | timespec_to_jiffies_timeout(const struct timespec *value) |
| 2492 | { |
| 2493 | unsigned long j = timespec_to_jiffies(value); |
| 2494 | |
| 2495 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); |
| 2496 | } |
| 2497 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2498 | #endif |