Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 1 | /* |
| 2 | * |
| 3 | * Copyright 2008 (c) Intel Corporation |
| 4 | * Jesse Barnes <jbarnes@virtuousgeek.org> |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the |
| 8 | * "Software"), to deal in the Software without restriction, including |
| 9 | * without limitation the rights to use, copy, modify, merge, publish, |
| 10 | * distribute, sub license, and/or sell copies of the Software, and to |
| 11 | * permit persons to whom the Software is furnished to do so, subject to |
| 12 | * the following conditions: |
| 13 | * |
| 14 | * The above copyright notice and this permission notice (including the |
| 15 | * next paragraph) shall be included in all copies or substantial portions |
| 16 | * of the Software. |
| 17 | * |
| 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 19 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 20 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 21 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 22 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 23 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 24 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 25 | */ |
| 26 | |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 27 | #include <drm/drmP.h> |
| 28 | #include <drm/i915_drm.h> |
Eric Anholt | f0217c4 | 2009-12-01 11:56:30 -0800 | [diff] [blame] | 29 | #include "intel_drv.h" |
Eugeni Dodonov | 5e5b7fa | 2012-01-07 23:40:34 -0200 | [diff] [blame] | 30 | #include "i915_reg.h" |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 31 | |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 32 | static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg) |
| 33 | { |
| 34 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 35 | |
| 36 | I915_WRITE8(index_port, reg); |
| 37 | return I915_READ8(data_port); |
| 38 | } |
| 39 | |
| 40 | static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable) |
| 41 | { |
| 42 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 43 | |
| 44 | I915_READ8(st01); |
| 45 | I915_WRITE8(VGA_AR_INDEX, palette_enable | reg); |
| 46 | return I915_READ8(VGA_AR_DATA_READ); |
| 47 | } |
| 48 | |
| 49 | static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable) |
| 50 | { |
| 51 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 52 | |
| 53 | I915_READ8(st01); |
| 54 | I915_WRITE8(VGA_AR_INDEX, palette_enable | reg); |
| 55 | I915_WRITE8(VGA_AR_DATA_WRITE, val); |
| 56 | } |
| 57 | |
| 58 | static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val) |
| 59 | { |
| 60 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 61 | |
| 62 | I915_WRITE8(index_port, reg); |
| 63 | I915_WRITE8(data_port, val); |
| 64 | } |
| 65 | |
| 66 | static void i915_save_vga(struct drm_device *dev) |
| 67 | { |
| 68 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 69 | int i; |
| 70 | u16 cr_index, cr_data, st01; |
| 71 | |
Daniel Vetter | 44cec74 | 2013-01-25 17:53:21 +0100 | [diff] [blame] | 72 | /* VGA state */ |
| 73 | dev_priv->regfile.saveVGA0 = I915_READ(VGA0); |
| 74 | dev_priv->regfile.saveVGA1 = I915_READ(VGA1); |
| 75 | dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD); |
Ville Syrjälä | 766aa1c | 2013-01-25 21:44:46 +0200 | [diff] [blame] | 76 | dev_priv->regfile.saveVGACNTRL = I915_READ(i915_vgacntrl_reg(dev)); |
Daniel Vetter | 44cec74 | 2013-01-25 17:53:21 +0100 | [diff] [blame] | 77 | |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 78 | /* VGA color palette registers */ |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 79 | dev_priv->regfile.saveDACMASK = I915_READ8(VGA_DACMASK); |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 80 | |
| 81 | /* MSR bits */ |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 82 | dev_priv->regfile.saveMSR = I915_READ8(VGA_MSR_READ); |
| 83 | if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) { |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 84 | cr_index = VGA_CR_INDEX_CGA; |
| 85 | cr_data = VGA_CR_DATA_CGA; |
| 86 | st01 = VGA_ST01_CGA; |
| 87 | } else { |
| 88 | cr_index = VGA_CR_INDEX_MDA; |
| 89 | cr_data = VGA_CR_DATA_MDA; |
| 90 | st01 = VGA_ST01_MDA; |
| 91 | } |
| 92 | |
| 93 | /* CRT controller regs */ |
| 94 | i915_write_indexed(dev, cr_index, cr_data, 0x11, |
| 95 | i915_read_indexed(dev, cr_index, cr_data, 0x11) & |
| 96 | (~0x80)); |
| 97 | for (i = 0; i <= 0x24; i++) |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 98 | dev_priv->regfile.saveCR[i] = |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 99 | i915_read_indexed(dev, cr_index, cr_data, i); |
| 100 | /* Make sure we don't turn off CR group 0 writes */ |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 101 | dev_priv->regfile.saveCR[0x11] &= ~0x80; |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 102 | |
| 103 | /* Attribute controller registers */ |
| 104 | I915_READ8(st01); |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 105 | dev_priv->regfile.saveAR_INDEX = I915_READ8(VGA_AR_INDEX); |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 106 | for (i = 0; i <= 0x14; i++) |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 107 | dev_priv->regfile.saveAR[i] = i915_read_ar(dev, st01, i, 0); |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 108 | I915_READ8(st01); |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 109 | I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX); |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 110 | I915_READ8(st01); |
| 111 | |
| 112 | /* Graphics controller registers */ |
| 113 | for (i = 0; i < 9; i++) |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 114 | dev_priv->regfile.saveGR[i] = |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 115 | i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i); |
| 116 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 117 | dev_priv->regfile.saveGR[0x10] = |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 118 | i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10); |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 119 | dev_priv->regfile.saveGR[0x11] = |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 120 | i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11); |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 121 | dev_priv->regfile.saveGR[0x18] = |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 122 | i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18); |
| 123 | |
| 124 | /* Sequencer registers */ |
| 125 | for (i = 0; i < 8; i++) |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 126 | dev_priv->regfile.saveSR[i] = |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 127 | i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i); |
| 128 | } |
| 129 | |
| 130 | static void i915_restore_vga(struct drm_device *dev) |
| 131 | { |
| 132 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 133 | int i; |
| 134 | u16 cr_index, cr_data, st01; |
| 135 | |
Daniel Vetter | 44cec74 | 2013-01-25 17:53:21 +0100 | [diff] [blame] | 136 | /* VGA state */ |
Ville Syrjälä | 766aa1c | 2013-01-25 21:44:46 +0200 | [diff] [blame] | 137 | I915_WRITE(i915_vgacntrl_reg(dev), dev_priv->regfile.saveVGACNTRL); |
Daniel Vetter | 44cec74 | 2013-01-25 17:53:21 +0100 | [diff] [blame] | 138 | |
| 139 | I915_WRITE(VGA0, dev_priv->regfile.saveVGA0); |
| 140 | I915_WRITE(VGA1, dev_priv->regfile.saveVGA1); |
| 141 | I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD); |
| 142 | POSTING_READ(VGA_PD); |
| 143 | udelay(150); |
| 144 | |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 145 | /* MSR bits */ |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 146 | I915_WRITE8(VGA_MSR_WRITE, dev_priv->regfile.saveMSR); |
| 147 | if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) { |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 148 | cr_index = VGA_CR_INDEX_CGA; |
| 149 | cr_data = VGA_CR_DATA_CGA; |
| 150 | st01 = VGA_ST01_CGA; |
| 151 | } else { |
| 152 | cr_index = VGA_CR_INDEX_MDA; |
| 153 | cr_data = VGA_CR_DATA_MDA; |
| 154 | st01 = VGA_ST01_MDA; |
| 155 | } |
| 156 | |
| 157 | /* Sequencer registers, don't write SR07 */ |
| 158 | for (i = 0; i < 7; i++) |
| 159 | i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i, |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 160 | dev_priv->regfile.saveSR[i]); |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 161 | |
| 162 | /* CRT controller regs */ |
| 163 | /* Enable CR group 0 writes */ |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 164 | i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->regfile.saveCR[0x11]); |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 165 | for (i = 0; i <= 0x24; i++) |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 166 | i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->regfile.saveCR[i]); |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 167 | |
| 168 | /* Graphics controller regs */ |
| 169 | for (i = 0; i < 9; i++) |
| 170 | i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i, |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 171 | dev_priv->regfile.saveGR[i]); |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 172 | |
| 173 | i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10, |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 174 | dev_priv->regfile.saveGR[0x10]); |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 175 | i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11, |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 176 | dev_priv->regfile.saveGR[0x11]); |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 177 | i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18, |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 178 | dev_priv->regfile.saveGR[0x18]); |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 179 | |
| 180 | /* Attribute controller registers */ |
| 181 | I915_READ8(st01); /* switch back to index mode */ |
| 182 | for (i = 0; i <= 0x14; i++) |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 183 | i915_write_ar(dev, st01, i, dev_priv->regfile.saveAR[i], 0); |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 184 | I915_READ8(st01); /* switch back to index mode */ |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 185 | I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX | 0x20); |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 186 | I915_READ8(st01); |
| 187 | |
| 188 | /* VGA color palette registers */ |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 189 | I915_WRITE8(VGA_DACMASK, dev_priv->regfile.saveDACMASK); |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 190 | } |
| 191 | |
Keith Packard | d70bed1 | 2011-06-29 00:30:34 -0700 | [diff] [blame] | 192 | static void i915_save_display(struct drm_device *dev) |
Zhao Yakui | fccdaba | 2009-07-08 14:13:14 +0800 | [diff] [blame] | 193 | { |
| 194 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 195 | unsigned long flags; |
Zhao Yakui | fccdaba | 2009-07-08 14:13:14 +0800 | [diff] [blame] | 196 | |
| 197 | /* Display arbitration control */ |
Paulo Zanoni | 8de0add | 2013-01-18 18:29:03 -0200 | [diff] [blame] | 198 | if (INTEL_INFO(dev)->gen <= 4) |
| 199 | dev_priv->regfile.saveDSPARB = I915_READ(DSPARB); |
Zhao Yakui | fccdaba | 2009-07-08 14:13:14 +0800 | [diff] [blame] | 200 | |
| 201 | /* This is only meaningful in non-KMS mode */ |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 202 | /* Don't regfile.save them in KMS mode */ |
Daniel Vetter | 2e9723a | 2013-01-25 17:53:19 +0100 | [diff] [blame] | 203 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
Daniel Vetter | d8157a3 | 2013-01-25 17:53:20 +0100 | [diff] [blame] | 204 | i915_save_display_reg(dev); |
Ben Gamari | 1341d65 | 2009-09-14 17:48:42 -0400 | [diff] [blame] | 205 | |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 206 | spin_lock_irqsave(&dev_priv->backlight.lock, flags); |
| 207 | |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 208 | /* LVDS state */ |
Chris Wilson | 90eb77b | 2010-08-14 14:41:23 +0100 | [diff] [blame] | 209 | if (HAS_PCH_SPLIT(dev)) { |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 210 | dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL); |
| 211 | dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1); |
| 212 | dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2); |
| 213 | dev_priv->regfile.saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL); |
| 214 | dev_priv->regfile.saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2); |
Paulo Zanoni | 4deb88a | 2013-03-06 20:03:20 -0300 | [diff] [blame] | 215 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
| 216 | dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS); |
Jesse Barnes | 07bf139 | 2013-10-31 18:55:50 +0200 | [diff] [blame] | 217 | } else if (IS_VALLEYVIEW(dev)) { |
| 218 | dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL); |
| 219 | dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS); |
| 220 | |
| 221 | dev_priv->regfile.saveBLC_PWM_CTL = |
| 222 | I915_READ(VLV_BLC_PWM_CTL(PIPE_A)); |
| 223 | dev_priv->regfile.saveBLC_HIST_CTL = |
| 224 | I915_READ(VLV_BLC_HIST_CTL(PIPE_A)); |
| 225 | dev_priv->regfile.saveBLC_PWM_CTL2 = |
| 226 | I915_READ(VLV_BLC_PWM_CTL2(PIPE_A)); |
| 227 | dev_priv->regfile.saveBLC_PWM_CTL_B = |
| 228 | I915_READ(VLV_BLC_PWM_CTL(PIPE_B)); |
| 229 | dev_priv->regfile.saveBLC_HIST_CTL_B = |
| 230 | I915_READ(VLV_BLC_HIST_CTL(PIPE_B)); |
| 231 | dev_priv->regfile.saveBLC_PWM_CTL2_B = |
| 232 | I915_READ(VLV_BLC_PWM_CTL2(PIPE_B)); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 233 | } else { |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 234 | dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL); |
| 235 | dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS); |
| 236 | dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL); |
| 237 | dev_priv->regfile.saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 238 | if (INTEL_INFO(dev)->gen >= 4) |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 239 | dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 240 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 241 | dev_priv->regfile.saveLVDS = I915_READ(LVDS); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 242 | } |
| 243 | |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 244 | spin_unlock_irqrestore(&dev_priv->backlight.lock, flags); |
| 245 | |
Chris Wilson | 90eb77b | 2010-08-14 14:41:23 +0100 | [diff] [blame] | 246 | if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev)) |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 247 | dev_priv->regfile.savePFIT_CONTROL = I915_READ(PFIT_CONTROL); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 248 | |
Chris Wilson | 90eb77b | 2010-08-14 14:41:23 +0100 | [diff] [blame] | 249 | if (HAS_PCH_SPLIT(dev)) { |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 250 | dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS); |
| 251 | dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS); |
| 252 | dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 253 | } else { |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 254 | dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS); |
| 255 | dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS); |
| 256 | dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 257 | } |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 258 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 259 | /* Only regfile.save FBC state on the platform that supports FBC */ |
Zhao Yakui | a2c459e | 2010-03-19 17:05:10 +0800 | [diff] [blame] | 260 | if (I915_HAS_FBC(dev)) { |
Chris Wilson | 90eb77b | 2010-08-14 14:41:23 +0100 | [diff] [blame] | 261 | if (HAS_PCH_SPLIT(dev)) { |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 262 | dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE); |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 263 | } else if (IS_GM45(dev)) { |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 264 | dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE); |
Zhao Yakui | a2c459e | 2010-03-19 17:05:10 +0800 | [diff] [blame] | 265 | } else { |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 266 | dev_priv->regfile.saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE); |
| 267 | dev_priv->regfile.saveFBC_LL_BASE = I915_READ(FBC_LL_BASE); |
| 268 | dev_priv->regfile.saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2); |
| 269 | dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL); |
Zhao Yakui | a2c459e | 2010-03-19 17:05:10 +0800 | [diff] [blame] | 270 | } |
Jesse Barnes | 06027f9 | 2009-10-05 13:47:26 -0700 | [diff] [blame] | 271 | } |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 272 | |
Daniel Vetter | 44cec74 | 2013-01-25 17:53:21 +0100 | [diff] [blame] | 273 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 274 | i915_save_vga(dev); |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 275 | } |
| 276 | |
Keith Packard | d70bed1 | 2011-06-29 00:30:34 -0700 | [diff] [blame] | 277 | static void i915_restore_display(struct drm_device *dev) |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 278 | { |
| 279 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 2ec9066 | 2013-02-19 12:11:38 -0800 | [diff] [blame] | 280 | u32 mask = 0xffffffff; |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 281 | unsigned long flags; |
Peng Li | 461cba2 | 2008-11-18 12:39:02 +0800 | [diff] [blame] | 282 | |
Keith Packard | 881ee98 | 2008-11-02 23:08:44 -0800 | [diff] [blame] | 283 | /* Display arbitration */ |
Paulo Zanoni | 8de0add | 2013-01-18 18:29:03 -0200 | [diff] [blame] | 284 | if (INTEL_INFO(dev)->gen <= 4) |
| 285 | I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB); |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 286 | |
Daniel Vetter | 2e9723a | 2013-01-25 17:53:19 +0100 | [diff] [blame] | 287 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
Daniel Vetter | d8157a3 | 2013-01-25 17:53:20 +0100 | [diff] [blame] | 288 | i915_restore_display_reg(dev); |
Ben Gamari | 1341d65 | 2009-09-14 17:48:42 -0400 | [diff] [blame] | 289 | |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 290 | spin_lock_irqsave(&dev_priv->backlight.lock, flags); |
| 291 | |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 292 | /* LVDS state */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 293 | if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 294 | I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 295 | |
Jesse Barnes | 2ec9066 | 2013-02-19 12:11:38 -0800 | [diff] [blame] | 296 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 297 | mask = ~LVDS_PORT_EN; |
| 298 | |
Paulo Zanoni | 4deb88a | 2013-03-06 20:03:20 -0300 | [diff] [blame] | 299 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
Jesse Barnes | 2ec9066 | 2013-02-19 12:11:38 -0800 | [diff] [blame] | 300 | I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS & mask); |
Paulo Zanoni | 4deb88a | 2013-03-06 20:03:20 -0300 | [diff] [blame] | 301 | else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) |
Jesse Barnes | 2ec9066 | 2013-02-19 12:11:38 -0800 | [diff] [blame] | 302 | I915_WRITE(LVDS, dev_priv->regfile.saveLVDS & mask); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 303 | |
Chris Wilson | 90eb77b | 2010-08-14 14:41:23 +0100 | [diff] [blame] | 304 | if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev)) |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 305 | I915_WRITE(PFIT_CONTROL, dev_priv->regfile.savePFIT_CONTROL); |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 306 | |
Chris Wilson | 90eb77b | 2010-08-14 14:41:23 +0100 | [diff] [blame] | 307 | if (HAS_PCH_SPLIT(dev)) { |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 308 | I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->regfile.saveBLC_PWM_CTL); |
| 309 | I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2); |
Takashi Iwai | 6db65cb | 2012-06-21 15:30:41 +0200 | [diff] [blame] | 310 | /* NOTE: BLC_PWM_CPU_CTL must be written after BLC_PWM_CPU_CTL2; |
| 311 | * otherwise we get blank eDP screen after S3 on some machines |
| 312 | */ |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 313 | I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->regfile.saveBLC_CPU_PWM_CTL2); |
| 314 | I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->regfile.saveBLC_CPU_PWM_CTL); |
| 315 | I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS); |
| 316 | I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS); |
| 317 | I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR); |
| 318 | I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 319 | I915_WRITE(RSTDBYCTL, |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 320 | dev_priv->regfile.saveMCHBAR_RENDER_STANDBY); |
Jesse Barnes | 07bf139 | 2013-10-31 18:55:50 +0200 | [diff] [blame] | 321 | } else if (IS_VALLEYVIEW(dev)) { |
| 322 | I915_WRITE(VLV_BLC_PWM_CTL(PIPE_A), |
| 323 | dev_priv->regfile.saveBLC_PWM_CTL); |
| 324 | I915_WRITE(VLV_BLC_HIST_CTL(PIPE_A), |
| 325 | dev_priv->regfile.saveBLC_HIST_CTL); |
| 326 | I915_WRITE(VLV_BLC_PWM_CTL2(PIPE_A), |
| 327 | dev_priv->regfile.saveBLC_PWM_CTL2); |
| 328 | I915_WRITE(VLV_BLC_PWM_CTL(PIPE_B), |
| 329 | dev_priv->regfile.saveBLC_PWM_CTL); |
| 330 | I915_WRITE(VLV_BLC_HIST_CTL(PIPE_B), |
| 331 | dev_priv->regfile.saveBLC_HIST_CTL); |
| 332 | I915_WRITE(VLV_BLC_PWM_CTL2(PIPE_B), |
| 333 | dev_priv->regfile.saveBLC_PWM_CTL2); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 334 | } else { |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 335 | I915_WRITE(PFIT_PGM_RATIOS, dev_priv->regfile.savePFIT_PGM_RATIOS); |
| 336 | I915_WRITE(BLC_PWM_CTL, dev_priv->regfile.saveBLC_PWM_CTL); |
| 337 | I915_WRITE(BLC_HIST_CTL, dev_priv->regfile.saveBLC_HIST_CTL); |
| 338 | I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS); |
| 339 | I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS); |
| 340 | I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR); |
| 341 | I915_WRITE(PP_CONTROL, dev_priv->regfile.savePP_CONTROL); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 342 | } |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 343 | |
Jani Nikula | 8ba2d18 | 2013-04-12 15:18:37 +0300 | [diff] [blame] | 344 | spin_unlock_irqrestore(&dev_priv->backlight.lock, flags); |
| 345 | |
Zhao Yakui | a2c459e | 2010-03-19 17:05:10 +0800 | [diff] [blame] | 346 | /* only restore FBC info on the platform that supports FBC*/ |
Chris Wilson | 43a9539 | 2011-07-08 12:22:36 +0100 | [diff] [blame] | 347 | intel_disable_fbc(dev); |
Zhao Yakui | a2c459e | 2010-03-19 17:05:10 +0800 | [diff] [blame] | 348 | if (I915_HAS_FBC(dev)) { |
Chris Wilson | 90eb77b | 2010-08-14 14:41:23 +0100 | [diff] [blame] | 349 | if (HAS_PCH_SPLIT(dev)) { |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 350 | I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE); |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 351 | } else if (IS_GM45(dev)) { |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 352 | I915_WRITE(DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE); |
Zhao Yakui | a2c459e | 2010-03-19 17:05:10 +0800 | [diff] [blame] | 353 | } else { |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 354 | I915_WRITE(FBC_CFB_BASE, dev_priv->regfile.saveFBC_CFB_BASE); |
| 355 | I915_WRITE(FBC_LL_BASE, dev_priv->regfile.saveFBC_LL_BASE); |
| 356 | I915_WRITE(FBC_CONTROL2, dev_priv->regfile.saveFBC_CONTROL2); |
| 357 | I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL); |
Zhao Yakui | a2c459e | 2010-03-19 17:05:10 +0800 | [diff] [blame] | 358 | } |
Jesse Barnes | 06027f9 | 2009-10-05 13:47:26 -0700 | [diff] [blame] | 359 | } |
Daniel Vetter | a65e827 | 2013-01-25 17:53:22 +0100 | [diff] [blame] | 360 | |
Daniel Vetter | 44cec74 | 2013-01-25 17:53:21 +0100 | [diff] [blame] | 361 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 362 | i915_restore_vga(dev); |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 363 | else |
Daniel Vetter | 44cec74 | 2013-01-25 17:53:21 +0100 | [diff] [blame] | 364 | i915_redisable_vga(dev); |
Ben Gamari | 1341d65 | 2009-09-14 17:48:42 -0400 | [diff] [blame] | 365 | } |
| 366 | |
| 367 | int i915_save_state(struct drm_device *dev) |
| 368 | { |
| 369 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 370 | int i; |
| 371 | |
Paulo Zanoni | 8e8f8ae | 2013-09-12 13:58:17 -0300 | [diff] [blame] | 372 | if (INTEL_INFO(dev)->gen <= 4) |
| 373 | pci_read_config_byte(dev->pdev, LBB, |
| 374 | &dev_priv->regfile.saveLBB); |
Ben Gamari | 1341d65 | 2009-09-14 17:48:42 -0400 | [diff] [blame] | 375 | |
Keith Packard | d70bed1 | 2011-06-29 00:30:34 -0700 | [diff] [blame] | 376 | mutex_lock(&dev->struct_mutex); |
| 377 | |
Ben Gamari | 1341d65 | 2009-09-14 17:48:42 -0400 | [diff] [blame] | 378 | i915_save_display(dev); |
| 379 | |
Daniel Vetter | 905c27b | 2012-10-17 11:32:56 +0200 | [diff] [blame] | 380 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { |
| 381 | /* Interrupt state */ |
| 382 | if (HAS_PCH_SPLIT(dev)) { |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 383 | dev_priv->regfile.saveDEIER = I915_READ(DEIER); |
| 384 | dev_priv->regfile.saveDEIMR = I915_READ(DEIMR); |
| 385 | dev_priv->regfile.saveGTIER = I915_READ(GTIER); |
| 386 | dev_priv->regfile.saveGTIMR = I915_READ(GTIMR); |
| 387 | dev_priv->regfile.saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR); |
| 388 | dev_priv->regfile.saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR); |
| 389 | dev_priv->regfile.saveMCHBAR_RENDER_STANDBY = |
Daniel Vetter | 905c27b | 2012-10-17 11:32:56 +0200 | [diff] [blame] | 390 | I915_READ(RSTDBYCTL); |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 391 | dev_priv->regfile.savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG); |
Daniel Vetter | 905c27b | 2012-10-17 11:32:56 +0200 | [diff] [blame] | 392 | } else { |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 393 | dev_priv->regfile.saveIER = I915_READ(IER); |
| 394 | dev_priv->regfile.saveIMR = I915_READ(IMR); |
Daniel Vetter | 905c27b | 2012-10-17 11:32:56 +0200 | [diff] [blame] | 395 | } |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 396 | } |
Ben Gamari | 1341d65 | 2009-09-14 17:48:42 -0400 | [diff] [blame] | 397 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 398 | intel_disable_gt_powersave(dev); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 399 | |
Ben Gamari | 1341d65 | 2009-09-14 17:48:42 -0400 | [diff] [blame] | 400 | /* Cache mode state */ |
Jesse Barnes | e8cde23 | 2013-10-11 12:09:29 -0700 | [diff] [blame] | 401 | if (INTEL_INFO(dev)->gen < 7) |
| 402 | dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); |
Ben Gamari | 1341d65 | 2009-09-14 17:48:42 -0400 | [diff] [blame] | 403 | |
| 404 | /* Memory Arbitration state */ |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 405 | dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE); |
Ben Gamari | 1341d65 | 2009-09-14 17:48:42 -0400 | [diff] [blame] | 406 | |
| 407 | /* Scratch space */ |
| 408 | for (i = 0; i < 16; i++) { |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 409 | dev_priv->regfile.saveSWF0[i] = I915_READ(SWF00 + (i << 2)); |
| 410 | dev_priv->regfile.saveSWF1[i] = I915_READ(SWF10 + (i << 2)); |
Ben Gamari | 1341d65 | 2009-09-14 17:48:42 -0400 | [diff] [blame] | 411 | } |
| 412 | for (i = 0; i < 3; i++) |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 413 | dev_priv->regfile.saveSWF2[i] = I915_READ(SWF30 + (i << 2)); |
Ben Gamari | 1341d65 | 2009-09-14 17:48:42 -0400 | [diff] [blame] | 414 | |
Keith Packard | d70bed1 | 2011-06-29 00:30:34 -0700 | [diff] [blame] | 415 | mutex_unlock(&dev->struct_mutex); |
| 416 | |
Ben Gamari | 1341d65 | 2009-09-14 17:48:42 -0400 | [diff] [blame] | 417 | return 0; |
| 418 | } |
| 419 | |
| 420 | int i915_restore_state(struct drm_device *dev) |
| 421 | { |
| 422 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 423 | int i; |
| 424 | |
Paulo Zanoni | 8e8f8ae | 2013-09-12 13:58:17 -0300 | [diff] [blame] | 425 | if (INTEL_INFO(dev)->gen <= 4) |
| 426 | pci_write_config_byte(dev->pdev, LBB, |
| 427 | dev_priv->regfile.saveLBB); |
Ben Gamari | 1341d65 | 2009-09-14 17:48:42 -0400 | [diff] [blame] | 428 | |
Keith Packard | d70bed1 | 2011-06-29 00:30:34 -0700 | [diff] [blame] | 429 | mutex_lock(&dev->struct_mutex); |
| 430 | |
Chris Wilson | 19b2dbd | 2013-06-12 10:15:12 +0100 | [diff] [blame] | 431 | i915_gem_restore_fences(dev); |
Ben Gamari | 1341d65 | 2009-09-14 17:48:42 -0400 | [diff] [blame] | 432 | i915_restore_display(dev); |
| 433 | |
Daniel Vetter | 905c27b | 2012-10-17 11:32:56 +0200 | [diff] [blame] | 434 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { |
| 435 | /* Interrupt state */ |
| 436 | if (HAS_PCH_SPLIT(dev)) { |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 437 | I915_WRITE(DEIER, dev_priv->regfile.saveDEIER); |
| 438 | I915_WRITE(DEIMR, dev_priv->regfile.saveDEIMR); |
| 439 | I915_WRITE(GTIER, dev_priv->regfile.saveGTIER); |
| 440 | I915_WRITE(GTIMR, dev_priv->regfile.saveGTIMR); |
| 441 | I915_WRITE(_FDI_RXA_IMR, dev_priv->regfile.saveFDI_RXA_IMR); |
| 442 | I915_WRITE(_FDI_RXB_IMR, dev_priv->regfile.saveFDI_RXB_IMR); |
| 443 | I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->regfile.savePCH_PORT_HOTPLUG); |
Daniel Vetter | 905c27b | 2012-10-17 11:32:56 +0200 | [diff] [blame] | 444 | } else { |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 445 | I915_WRITE(IER, dev_priv->regfile.saveIER); |
| 446 | I915_WRITE(IMR, dev_priv->regfile.saveIMR); |
Daniel Vetter | 905c27b | 2012-10-17 11:32:56 +0200 | [diff] [blame] | 447 | } |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 448 | } |
Keith Packard | d70bed1 | 2011-06-29 00:30:34 -0700 | [diff] [blame] | 449 | |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 450 | /* Cache mode state */ |
Jesse Barnes | e8cde23 | 2013-10-11 12:09:29 -0700 | [diff] [blame] | 451 | if (INTEL_INFO(dev)->gen < 7) |
| 452 | I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | |
| 453 | 0xffff0000); |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 454 | |
| 455 | /* Memory arbitration state */ |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 456 | I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000); |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 457 | |
| 458 | for (i = 0; i < 16; i++) { |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 459 | I915_WRITE(SWF00 + (i << 2), dev_priv->regfile.saveSWF0[i]); |
| 460 | I915_WRITE(SWF10 + (i << 2), dev_priv->regfile.saveSWF1[i]); |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 461 | } |
| 462 | for (i = 0; i < 3; i++) |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 463 | I915_WRITE(SWF30 + (i << 2), dev_priv->regfile.saveSWF2[i]); |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 464 | |
Keith Packard | d70bed1 | 2011-06-29 00:30:34 -0700 | [diff] [blame] | 465 | mutex_unlock(&dev->struct_mutex); |
| 466 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 467 | intel_i2c_reset(dev); |
Eric Anholt | f0217c4 | 2009-12-01 11:56:30 -0800 | [diff] [blame] | 468 | |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 469 | return 0; |
| 470 | } |