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Joerg Roedelf6e2e6b2008-06-26 21:27:39 +02001/*
Joerg Roedel5d0d7152010-10-13 11:13:21 +02002 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
Joerg Roedelf6e2e6b2008-06-26 21:27:39 +02003 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/pci.h>
21#include <linux/acpi.h>
Joerg Roedelf6e2e6b2008-06-26 21:27:39 +020022#include <linux/list.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090023#include <linux/slab.h>
Rafael J. Wysockif3c6ea12011-03-23 22:15:54 +010024#include <linux/syscore_ops.h>
Joerg Roedela80dc3e2008-09-11 16:51:41 +020025#include <linux/interrupt.h>
26#include <linux/msi.h>
Joerg Roedel403f81d2011-06-14 16:44:25 +020027#include <linux/amd-iommu.h>
Joerg Roedelf6e2e6b2008-06-26 21:27:39 +020028#include <asm/pci-direct.h>
FUJITA Tomonori46a7fa22008-07-11 10:23:42 +090029#include <asm/iommu.h>
Joerg Roedel1d9b16d2008-11-27 18:39:15 +010030#include <asm/gart.h>
FUJITA Tomonoriea1b0d32009-11-10 19:46:15 +090031#include <asm/x86_init.h>
Konrad Rzeszutek Wilk22e6daf2010-08-26 13:58:03 -040032#include <asm/iommu_table.h>
Joerg Roedel403f81d2011-06-14 16:44:25 +020033
34#include "amd_iommu_proto.h"
35#include "amd_iommu_types.h"
36
Joerg Roedelf6e2e6b2008-06-26 21:27:39 +020037/*
38 * definitions for the ACPI scanning code
39 */
Joerg Roedelf6e2e6b2008-06-26 21:27:39 +020040#define IVRS_HEADER_LENGTH 48
Joerg Roedelf6e2e6b2008-06-26 21:27:39 +020041
42#define ACPI_IVHD_TYPE 0x10
43#define ACPI_IVMD_TYPE_ALL 0x20
44#define ACPI_IVMD_TYPE 0x21
45#define ACPI_IVMD_TYPE_RANGE 0x22
46
47#define IVHD_DEV_ALL 0x01
48#define IVHD_DEV_SELECT 0x02
49#define IVHD_DEV_SELECT_RANGE_START 0x03
50#define IVHD_DEV_RANGE_END 0x04
51#define IVHD_DEV_ALIAS 0x42
52#define IVHD_DEV_ALIAS_RANGE 0x43
53#define IVHD_DEV_EXT_SELECT 0x46
54#define IVHD_DEV_EXT_SELECT_RANGE 0x47
55
Joerg Roedel6da73422009-05-04 11:44:38 +020056#define IVHD_FLAG_HT_TUN_EN_MASK 0x01
57#define IVHD_FLAG_PASSPW_EN_MASK 0x02
58#define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
59#define IVHD_FLAG_ISOC_EN_MASK 0x08
Joerg Roedelf6e2e6b2008-06-26 21:27:39 +020060
61#define IVMD_FLAG_EXCL_RANGE 0x08
62#define IVMD_FLAG_UNITY_MAP 0x01
63
64#define ACPI_DEVFLAG_INITPASS 0x01
65#define ACPI_DEVFLAG_EXTINT 0x02
66#define ACPI_DEVFLAG_NMI 0x04
67#define ACPI_DEVFLAG_SYSMGT1 0x10
68#define ACPI_DEVFLAG_SYSMGT2 0x20
69#define ACPI_DEVFLAG_LINT0 0x40
70#define ACPI_DEVFLAG_LINT1 0x80
71#define ACPI_DEVFLAG_ATSDIS 0x10000000
72
Joerg Roedelb65233a2008-07-11 17:14:21 +020073/*
74 * ACPI table definitions
75 *
76 * These data structures are laid over the table to parse the important values
77 * out of it.
78 */
79
80/*
81 * structure describing one IOMMU in the ACPI table. Typically followed by one
82 * or more ivhd_entrys.
83 */
Joerg Roedelf6e2e6b2008-06-26 21:27:39 +020084struct ivhd_header {
85 u8 type;
86 u8 flags;
87 u16 length;
88 u16 devid;
89 u16 cap_ptr;
90 u64 mmio_phys;
91 u16 pci_seg;
92 u16 info;
93 u32 reserved;
94} __attribute__((packed));
95
Joerg Roedelb65233a2008-07-11 17:14:21 +020096/*
97 * A device entry describing which devices a specific IOMMU translates and
98 * which requestor ids they use.
99 */
Joerg Roedelf6e2e6b2008-06-26 21:27:39 +0200100struct ivhd_entry {
101 u8 type;
102 u16 devid;
103 u8 flags;
104 u32 ext;
105} __attribute__((packed));
106
Joerg Roedelb65233a2008-07-11 17:14:21 +0200107/*
108 * An AMD IOMMU memory definition structure. It defines things like exclusion
109 * ranges for devices and regions that should be unity mapped.
110 */
Joerg Roedelf6e2e6b2008-06-26 21:27:39 +0200111struct ivmd_header {
112 u8 type;
113 u8 flags;
114 u16 length;
115 u16 devid;
116 u16 aux;
117 u64 resv;
118 u64 range_start;
119 u64 range_length;
120} __attribute__((packed));
121
Joerg Roedelfefda112009-05-20 12:21:42 +0200122bool amd_iommu_dump;
123
Joerg Roedelc1cbebe2008-07-03 19:35:10 +0200124static int __initdata amd_iommu_detected;
Joerg Roedela5235722010-05-11 17:12:33 +0200125static bool __initdata amd_iommu_disabled;
Joerg Roedelc1cbebe2008-07-03 19:35:10 +0200126
Joerg Roedelb65233a2008-07-11 17:14:21 +0200127u16 amd_iommu_last_bdf; /* largest PCI device id we have
128 to handle */
Joerg Roedel2e228472008-07-11 17:14:31 +0200129LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
Joerg Roedelb65233a2008-07-11 17:14:21 +0200130 we find in ACPI */
FUJITA Tomonoriafa9fdc2008-09-20 01:23:30 +0900131bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
Joerg Roedel928abd22008-06-26 21:27:40 +0200132
Joerg Roedel2e228472008-07-11 17:14:31 +0200133LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
Joerg Roedelb65233a2008-07-11 17:14:21 +0200134 system */
135
Joerg Roedelbb527772009-11-20 14:31:51 +0100136/* Array to assign indices to IOMMUs*/
137struct amd_iommu *amd_iommus[MAX_IOMMUS];
138int amd_iommus_present;
139
Joerg Roedel318afd42009-11-23 18:32:38 +0100140/* IOMMUs have a non-present cache? */
141bool amd_iommu_np_cache __read_mostly;
Joerg Roedel60f723b2011-04-05 12:50:24 +0200142bool amd_iommu_iotlb_sup __read_mostly = true;
Joerg Roedel318afd42009-11-23 18:32:38 +0100143
Joerg Roedelb65233a2008-07-11 17:14:21 +0200144/*
Joerg Roedel3551a702010-03-01 13:52:19 +0100145 * The ACPI table parsing functions set this variable on an error
Joerg Roedel0f764802009-12-21 15:51:23 +0100146 */
Joerg Roedel3551a702010-03-01 13:52:19 +0100147static int __initdata amd_iommu_init_err;
Joerg Roedel0f764802009-12-21 15:51:23 +0100148
149/*
Joerg Roedelaeb26f52009-11-20 16:44:01 +0100150 * List of protection domains - used during resume
151 */
152LIST_HEAD(amd_iommu_pd_list);
153spinlock_t amd_iommu_pd_lock;
154
155/*
Joerg Roedelb65233a2008-07-11 17:14:21 +0200156 * Pointer to the device table which is shared by all AMD IOMMUs
157 * it is indexed by the PCI device id or the HT unit id and contains
158 * information about the domain the device belongs to as well as the
159 * page table root pointer.
160 */
Joerg Roedel928abd22008-06-26 21:27:40 +0200161struct dev_table_entry *amd_iommu_dev_table;
Joerg Roedelb65233a2008-07-11 17:14:21 +0200162
163/*
164 * The alias table is a driver specific data structure which contains the
165 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
166 * More than one device can share the same requestor id.
167 */
Joerg Roedel928abd22008-06-26 21:27:40 +0200168u16 *amd_iommu_alias_table;
Joerg Roedelb65233a2008-07-11 17:14:21 +0200169
170/*
171 * The rlookup table is used to find the IOMMU which is responsible
172 * for a specific device. It is also indexed by the PCI device id.
173 */
Joerg Roedel928abd22008-06-26 21:27:40 +0200174struct amd_iommu **amd_iommu_rlookup_table;
Joerg Roedelb65233a2008-07-11 17:14:21 +0200175
176/*
Joerg Roedelb65233a2008-07-11 17:14:21 +0200177 * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
178 * to know which ones are already in use.
179 */
Joerg Roedel928abd22008-06-26 21:27:40 +0200180unsigned long *amd_iommu_pd_alloc_bitmap;
181
Joerg Roedelb65233a2008-07-11 17:14:21 +0200182static u32 dev_table_size; /* size of the device table */
183static u32 alias_table_size; /* size of the alias table */
184static u32 rlookup_table_size; /* size if the rlookup table */
Joerg Roedel3e8064b2008-06-26 21:27:41 +0200185
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +0200186/*
187 * This function flushes all internal caches of
188 * the IOMMU used by this driver.
189 */
190extern void iommu_flush_all_caches(struct amd_iommu *iommu);
191
Joerg Roedel208ec8c2008-07-11 17:14:24 +0200192static inline void update_last_devid(u16 devid)
193{
194 if (devid > amd_iommu_last_bdf)
195 amd_iommu_last_bdf = devid;
196}
197
Joerg Roedelc5714842008-07-11 17:14:25 +0200198static inline unsigned long tbl_size(int entry_size)
199{
200 unsigned shift = PAGE_SHIFT +
Neil Turton421f9092009-05-14 14:00:35 +0100201 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
Joerg Roedelc5714842008-07-11 17:14:25 +0200202
203 return 1UL << shift;
204}
205
Matthew Garrett5bcd7572010-10-04 14:59:31 -0400206/* Access to l1 and l2 indexed register spaces */
207
208static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
209{
210 u32 val;
211
212 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
213 pci_read_config_dword(iommu->dev, 0xfc, &val);
214 return val;
215}
216
217static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
218{
219 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
220 pci_write_config_dword(iommu->dev, 0xfc, val);
221 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
222}
223
224static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
225{
226 u32 val;
227
228 pci_write_config_dword(iommu->dev, 0xf0, address);
229 pci_read_config_dword(iommu->dev, 0xf4, &val);
230 return val;
231}
232
233static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
234{
235 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
236 pci_write_config_dword(iommu->dev, 0xf4, val);
237}
238
Joerg Roedelb65233a2008-07-11 17:14:21 +0200239/****************************************************************************
240 *
241 * AMD IOMMU MMIO register space handling functions
242 *
243 * These functions are used to program the IOMMU device registers in
244 * MMIO space required for that driver.
245 *
246 ****************************************************************************/
247
248/*
249 * This function set the exclusion range in the IOMMU. DMA accesses to the
250 * exclusion range are passed through untranslated
251 */
Joerg Roedel05f92db2009-05-12 09:52:46 +0200252static void iommu_set_exclusion_range(struct amd_iommu *iommu)
Joerg Roedelb2026aa2008-06-26 21:27:44 +0200253{
254 u64 start = iommu->exclusion_start & PAGE_MASK;
255 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
256 u64 entry;
257
258 if (!iommu->exclusion_start)
259 return;
260
261 entry = start | MMIO_EXCL_ENABLE_MASK;
262 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
263 &entry, sizeof(entry));
264
265 entry = limit;
266 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
267 &entry, sizeof(entry));
268}
269
Joerg Roedelb65233a2008-07-11 17:14:21 +0200270/* Programs the physical address of the device table into the IOMMU hardware */
Joerg Roedelb2026aa2008-06-26 21:27:44 +0200271static void __init iommu_set_device_table(struct amd_iommu *iommu)
272{
Andreas Herrmannf6098912008-10-16 16:27:36 +0200273 u64 entry;
Joerg Roedelb2026aa2008-06-26 21:27:44 +0200274
275 BUG_ON(iommu->mmio_base == NULL);
276
277 entry = virt_to_phys(amd_iommu_dev_table);
278 entry |= (dev_table_size >> 12) - 1;
279 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
280 &entry, sizeof(entry));
281}
282
Joerg Roedelb65233a2008-07-11 17:14:21 +0200283/* Generic functions to enable/disable certain features of the IOMMU. */
Joerg Roedel05f92db2009-05-12 09:52:46 +0200284static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
Joerg Roedelb2026aa2008-06-26 21:27:44 +0200285{
286 u32 ctrl;
287
288 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
289 ctrl |= (1 << bit);
290 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
291}
292
Joerg Roedelca0207112009-10-28 18:02:26 +0100293static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
Joerg Roedelb2026aa2008-06-26 21:27:44 +0200294{
295 u32 ctrl;
296
Joerg Roedel199d0d52008-09-17 16:45:59 +0200297 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
Joerg Roedelb2026aa2008-06-26 21:27:44 +0200298 ctrl &= ~(1 << bit);
299 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
300}
301
Joerg Roedelb65233a2008-07-11 17:14:21 +0200302/* Function to enable the hardware */
Joerg Roedel05f92db2009-05-12 09:52:46 +0200303static void iommu_enable(struct amd_iommu *iommu)
Joerg Roedelb2026aa2008-06-26 21:27:44 +0200304{
Joerg Roedeld99ddec2011-04-11 11:03:18 +0200305 static const char * const feat_str[] = {
306 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
307 "IA", "GA", "HE", "PC", NULL
308 };
309 int i;
310
311 printk(KERN_INFO "AMD-Vi: Enabling IOMMU at %s cap 0x%hx",
Joerg Roedela4e267c2008-12-10 20:04:18 +0100312 dev_name(&iommu->dev->dev), iommu->cap_ptr);
Joerg Roedelb2026aa2008-06-26 21:27:44 +0200313
Joerg Roedeld99ddec2011-04-11 11:03:18 +0200314 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
315 printk(KERN_CONT " extended features: ");
316 for (i = 0; feat_str[i]; ++i)
317 if (iommu_feature(iommu, (1ULL << i)))
318 printk(KERN_CONT " %s", feat_str[i]);
319 }
320 printk(KERN_CONT "\n");
321
Joerg Roedelb2026aa2008-06-26 21:27:44 +0200322 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
Joerg Roedelb2026aa2008-06-26 21:27:44 +0200323}
324
Joerg Roedel92ac4322009-05-19 19:06:27 +0200325static void iommu_disable(struct amd_iommu *iommu)
Joerg Roedel126c52b2008-09-09 16:47:35 +0200326{
Chris Wrighta8c485b2009-06-15 15:53:45 +0200327 /* Disable command buffer */
328 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
329
330 /* Disable event logging and event interrupts */
331 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
332 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
333
334 /* Disable IOMMU hardware itself */
Joerg Roedel92ac4322009-05-19 19:06:27 +0200335 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
Joerg Roedel126c52b2008-09-09 16:47:35 +0200336}
337
Joerg Roedelb65233a2008-07-11 17:14:21 +0200338/*
339 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
340 * the system has one.
341 */
Joerg Roedel6c567472008-06-26 21:27:43 +0200342static u8 * __init iommu_map_mmio_space(u64 address)
343{
344 u8 *ret;
345
Joerg Roedele82752d2010-05-28 14:26:48 +0200346 if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) {
347 pr_err("AMD-Vi: Can not reserve memory region %llx for mmio\n",
348 address);
349 pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
Joerg Roedel6c567472008-06-26 21:27:43 +0200350 return NULL;
Joerg Roedele82752d2010-05-28 14:26:48 +0200351 }
Joerg Roedel6c567472008-06-26 21:27:43 +0200352
353 ret = ioremap_nocache(address, MMIO_REGION_LENGTH);
354 if (ret != NULL)
355 return ret;
356
357 release_mem_region(address, MMIO_REGION_LENGTH);
358
359 return NULL;
360}
361
362static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
363{
364 if (iommu->mmio_base)
365 iounmap(iommu->mmio_base);
366 release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
367}
368
Joerg Roedelb65233a2008-07-11 17:14:21 +0200369/****************************************************************************
370 *
371 * The functions below belong to the first pass of AMD IOMMU ACPI table
372 * parsing. In this pass we try to find out the highest device id this
373 * code has to handle. Upon this information the size of the shared data
374 * structures is determined later.
375 *
376 ****************************************************************************/
377
378/*
Joerg Roedelb514e552008-09-17 17:14:27 +0200379 * This function calculates the length of a given IVHD entry
380 */
381static inline int ivhd_entry_length(u8 *ivhd)
382{
383 return 0x04 << (*ivhd >> 6);
384}
385
386/*
Joerg Roedelb65233a2008-07-11 17:14:21 +0200387 * This function reads the last device id the IOMMU has to handle from the PCI
388 * capability header for this IOMMU
389 */
Joerg Roedel3e8064b2008-06-26 21:27:41 +0200390static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
391{
392 u32 cap;
393
394 cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
Joerg Roedeld591b0a2008-07-11 17:14:35 +0200395 update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
Joerg Roedel3e8064b2008-06-26 21:27:41 +0200396
397 return 0;
398}
399
Joerg Roedelb65233a2008-07-11 17:14:21 +0200400/*
401 * After reading the highest device id from the IOMMU PCI capability header
402 * this function looks if there is a higher device id defined in the ACPI table
403 */
Joerg Roedel3e8064b2008-06-26 21:27:41 +0200404static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
405{
406 u8 *p = (void *)h, *end = (void *)h;
407 struct ivhd_entry *dev;
408
409 p += sizeof(*h);
410 end += h->length;
411
412 find_last_devid_on_pci(PCI_BUS(h->devid),
413 PCI_SLOT(h->devid),
414 PCI_FUNC(h->devid),
415 h->cap_ptr);
416
417 while (p < end) {
418 dev = (struct ivhd_entry *)p;
419 switch (dev->type) {
420 case IVHD_DEV_SELECT:
421 case IVHD_DEV_RANGE_END:
422 case IVHD_DEV_ALIAS:
423 case IVHD_DEV_EXT_SELECT:
Joerg Roedelb65233a2008-07-11 17:14:21 +0200424 /* all the above subfield types refer to device ids */
Joerg Roedel208ec8c2008-07-11 17:14:24 +0200425 update_last_devid(dev->devid);
Joerg Roedel3e8064b2008-06-26 21:27:41 +0200426 break;
427 default:
428 break;
429 }
Joerg Roedelb514e552008-09-17 17:14:27 +0200430 p += ivhd_entry_length(p);
Joerg Roedel3e8064b2008-06-26 21:27:41 +0200431 }
432
433 WARN_ON(p != end);
434
435 return 0;
436}
437
Joerg Roedelb65233a2008-07-11 17:14:21 +0200438/*
439 * Iterate over all IVHD entries in the ACPI table and find the highest device
440 * id which we need to handle. This is the first of three functions which parse
441 * the ACPI table. So we check the checksum here.
442 */
Joerg Roedel3e8064b2008-06-26 21:27:41 +0200443static int __init find_last_devid_acpi(struct acpi_table_header *table)
444{
445 int i;
446 u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
447 struct ivhd_header *h;
448
449 /*
450 * Validate checksum here so we don't need to do it when
451 * we actually parse the table
452 */
453 for (i = 0; i < table->length; ++i)
454 checksum += p[i];
Joerg Roedel3551a702010-03-01 13:52:19 +0100455 if (checksum != 0) {
Joerg Roedel3e8064b2008-06-26 21:27:41 +0200456 /* ACPI table corrupt */
Joerg Roedel3551a702010-03-01 13:52:19 +0100457 amd_iommu_init_err = -ENODEV;
458 return 0;
459 }
Joerg Roedel3e8064b2008-06-26 21:27:41 +0200460
461 p += IVRS_HEADER_LENGTH;
462
463 end += table->length;
464 while (p < end) {
465 h = (struct ivhd_header *)p;
466 switch (h->type) {
467 case ACPI_IVHD_TYPE:
468 find_last_devid_from_ivhd(h);
469 break;
470 default:
471 break;
472 }
473 p += h->length;
474 }
475 WARN_ON(p != end);
476
477 return 0;
478}
479
Joerg Roedelb65233a2008-07-11 17:14:21 +0200480/****************************************************************************
481 *
482 * The following functions belong the the code path which parses the ACPI table
483 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
484 * data structures, initialize the device/alias/rlookup table and also
485 * basically initialize the hardware.
486 *
487 ****************************************************************************/
488
489/*
490 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
491 * write commands to that buffer later and the IOMMU will execute them
492 * asynchronously
493 */
Joerg Roedelb36ca912008-06-26 21:27:45 +0200494static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
495{
Joerg Roedeld0312b22008-07-11 17:14:29 +0200496 u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
Joerg Roedelb36ca912008-06-26 21:27:45 +0200497 get_order(CMD_BUFFER_SIZE));
Joerg Roedelb36ca912008-06-26 21:27:45 +0200498
499 if (cmd_buf == NULL)
500 return NULL;
501
Chris Wright549c90d2010-04-02 18:27:53 -0700502 iommu->cmd_buf_size = CMD_BUFFER_SIZE | CMD_BUFFER_UNINITIALIZED;
Joerg Roedelb36ca912008-06-26 21:27:45 +0200503
Joerg Roedel58492e12009-05-04 18:41:16 +0200504 return cmd_buf;
505}
506
507/*
Joerg Roedel93f1cc672009-09-03 14:50:20 +0200508 * This function resets the command buffer if the IOMMU stopped fetching
509 * commands from it.
510 */
511void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
512{
513 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
514
515 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
516 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
517
518 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
519}
520
521/*
Joerg Roedel58492e12009-05-04 18:41:16 +0200522 * This function writes the command buffer address to the hardware and
523 * enables it.
524 */
525static void iommu_enable_command_buffer(struct amd_iommu *iommu)
526{
527 u64 entry;
528
529 BUG_ON(iommu->cmd_buf == NULL);
530
531 entry = (u64)virt_to_phys(iommu->cmd_buf);
Joerg Roedelb36ca912008-06-26 21:27:45 +0200532 entry |= MMIO_CMD_SIZE_512;
Joerg Roedel58492e12009-05-04 18:41:16 +0200533
Joerg Roedelb36ca912008-06-26 21:27:45 +0200534 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
Joerg Roedel58492e12009-05-04 18:41:16 +0200535 &entry, sizeof(entry));
Joerg Roedelb36ca912008-06-26 21:27:45 +0200536
Joerg Roedel93f1cc672009-09-03 14:50:20 +0200537 amd_iommu_reset_cmd_buffer(iommu);
Chris Wright549c90d2010-04-02 18:27:53 -0700538 iommu->cmd_buf_size &= ~(CMD_BUFFER_UNINITIALIZED);
Joerg Roedelb36ca912008-06-26 21:27:45 +0200539}
540
541static void __init free_command_buffer(struct amd_iommu *iommu)
542{
Joerg Roedel23c17132008-09-17 17:18:17 +0200543 free_pages((unsigned long)iommu->cmd_buf,
Chris Wright549c90d2010-04-02 18:27:53 -0700544 get_order(iommu->cmd_buf_size & ~(CMD_BUFFER_UNINITIALIZED)));
Joerg Roedelb36ca912008-06-26 21:27:45 +0200545}
546
Joerg Roedel335503e2008-09-05 14:29:07 +0200547/* allocates the memory where the IOMMU will log its events to */
548static u8 * __init alloc_event_buffer(struct amd_iommu *iommu)
549{
Joerg Roedel335503e2008-09-05 14:29:07 +0200550 iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
551 get_order(EVT_BUFFER_SIZE));
552
553 if (iommu->evt_buf == NULL)
554 return NULL;
555
Joerg Roedel1bc6f832009-07-02 18:32:05 +0200556 iommu->evt_buf_size = EVT_BUFFER_SIZE;
557
Joerg Roedel58492e12009-05-04 18:41:16 +0200558 return iommu->evt_buf;
559}
560
561static void iommu_enable_event_buffer(struct amd_iommu *iommu)
562{
563 u64 entry;
564
565 BUG_ON(iommu->evt_buf == NULL);
566
Joerg Roedel335503e2008-09-05 14:29:07 +0200567 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
Joerg Roedel58492e12009-05-04 18:41:16 +0200568
Joerg Roedel335503e2008-09-05 14:29:07 +0200569 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
570 &entry, sizeof(entry));
571
Joerg Roedel090672072009-06-15 16:06:48 +0200572 /* set head and tail to zero manually */
573 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
574 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
575
Joerg Roedel58492e12009-05-04 18:41:16 +0200576 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
Joerg Roedel335503e2008-09-05 14:29:07 +0200577}
578
579static void __init free_event_buffer(struct amd_iommu *iommu)
580{
581 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
582}
583
Joerg Roedelb65233a2008-07-11 17:14:21 +0200584/* sets a specific bit in the device table entry. */
Joerg Roedel3566b772008-06-26 21:27:46 +0200585static void set_dev_entry_bit(u16 devid, u8 bit)
586{
587 int i = (bit >> 5) & 0x07;
588 int _bit = bit & 0x1f;
589
590 amd_iommu_dev_table[devid].data[i] |= (1 << _bit);
591}
592
Joerg Roedelc5cca142009-10-09 18:31:20 +0200593static int get_dev_entry_bit(u16 devid, u8 bit)
594{
595 int i = (bit >> 5) & 0x07;
596 int _bit = bit & 0x1f;
597
598 return (amd_iommu_dev_table[devid].data[i] & (1 << _bit)) >> _bit;
599}
600
601
602void amd_iommu_apply_erratum_63(u16 devid)
603{
604 int sysmgt;
605
606 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
607 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
608
609 if (sysmgt == 0x01)
610 set_dev_entry_bit(devid, DEV_ENTRY_IW);
611}
612
Joerg Roedel5ff47892008-07-14 20:11:18 +0200613/* Writes the specific IOMMU for a device into the rlookup table */
614static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
615{
616 amd_iommu_rlookup_table[devid] = iommu;
617}
618
Joerg Roedelb65233a2008-07-11 17:14:21 +0200619/*
620 * This function takes the device specific flags read from the ACPI
621 * table and sets up the device table entry with that information
622 */
Joerg Roedel5ff47892008-07-14 20:11:18 +0200623static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
624 u16 devid, u32 flags, u32 ext_flags)
Joerg Roedel3566b772008-06-26 21:27:46 +0200625{
626 if (flags & ACPI_DEVFLAG_INITPASS)
627 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
628 if (flags & ACPI_DEVFLAG_EXTINT)
629 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
630 if (flags & ACPI_DEVFLAG_NMI)
631 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
632 if (flags & ACPI_DEVFLAG_SYSMGT1)
633 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
634 if (flags & ACPI_DEVFLAG_SYSMGT2)
635 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
636 if (flags & ACPI_DEVFLAG_LINT0)
637 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
638 if (flags & ACPI_DEVFLAG_LINT1)
639 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
Joerg Roedel3566b772008-06-26 21:27:46 +0200640
Joerg Roedelc5cca142009-10-09 18:31:20 +0200641 amd_iommu_apply_erratum_63(devid);
642
Joerg Roedel5ff47892008-07-14 20:11:18 +0200643 set_iommu_for_device(iommu, devid);
Joerg Roedel3566b772008-06-26 21:27:46 +0200644}
645
Joerg Roedelb65233a2008-07-11 17:14:21 +0200646/*
647 * Reads the device exclusion range from ACPI and initialize IOMMU with
648 * it
649 */
Joerg Roedel3566b772008-06-26 21:27:46 +0200650static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
651{
652 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
653
654 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
655 return;
656
657 if (iommu) {
Joerg Roedelb65233a2008-07-11 17:14:21 +0200658 /*
659 * We only can configure exclusion ranges per IOMMU, not
660 * per device. But we can enable the exclusion range per
661 * device. This is done here
662 */
Joerg Roedel3566b772008-06-26 21:27:46 +0200663 set_dev_entry_bit(m->devid, DEV_ENTRY_EX);
664 iommu->exclusion_start = m->range_start;
665 iommu->exclusion_length = m->range_length;
666 }
667}
668
Joerg Roedelb65233a2008-07-11 17:14:21 +0200669/*
670 * This function reads some important data from the IOMMU PCI space and
671 * initializes the driver data structure with it. It reads the hardware
672 * capabilities and the first/last device entries
673 */
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200674static void __init init_iommu_from_pci(struct amd_iommu *iommu)
675{
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200676 int cap_ptr = iommu->cap_ptr;
Joerg Roedeld99ddec2011-04-11 11:03:18 +0200677 u32 range, misc, low, high;
Matthew Garrett5bcd7572010-10-04 14:59:31 -0400678 int i, j;
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200679
Joerg Roedel3eaf28a2008-09-08 15:55:10 +0200680 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
681 &iommu->cap);
682 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
683 &range);
Joerg Roedela80dc3e2008-09-11 16:51:41 +0200684 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
685 &misc);
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200686
Joerg Roedeld591b0a2008-07-11 17:14:35 +0200687 iommu->first_device = calc_devid(MMIO_GET_BUS(range),
688 MMIO_GET_FD(range));
689 iommu->last_device = calc_devid(MMIO_GET_BUS(range),
690 MMIO_GET_LD(range));
Joerg Roedela80dc3e2008-09-11 16:51:41 +0200691 iommu->evt_msi_num = MMIO_MSI_NUM(misc);
Joerg Roedel4c894f42010-09-23 15:15:19 +0200692
Joerg Roedel60f723b2011-04-05 12:50:24 +0200693 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
694 amd_iommu_iotlb_sup = false;
695
Joerg Roedeld99ddec2011-04-11 11:03:18 +0200696 /* read extended feature bits */
697 low = readl(iommu->mmio_base + MMIO_EXT_FEATURES);
698 high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4);
699
700 iommu->features = ((u64)high << 32) | low;
701
Matthew Garrett5bcd7572010-10-04 14:59:31 -0400702 if (!is_rd890_iommu(iommu->dev))
703 return;
704
705 /*
706 * Some rd890 systems may not be fully reconfigured by the BIOS, so
707 * it's necessary for us to store this information so it can be
708 * reprogrammed on resume
709 */
710
711 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
712 &iommu->stored_addr_lo);
713 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
714 &iommu->stored_addr_hi);
715
716 /* Low bit locks writes to configuration space */
717 iommu->stored_addr_lo &= ~1;
718
719 for (i = 0; i < 6; i++)
720 for (j = 0; j < 0x12; j++)
721 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
722
723 for (i = 0; i < 0x83; i++)
724 iommu->stored_l2[i] = iommu_read_l2(iommu, i);
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200725}
726
Joerg Roedelb65233a2008-07-11 17:14:21 +0200727/*
728 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
729 * initializes the hardware and our data structures with it.
730 */
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200731static void __init init_iommu_from_acpi(struct amd_iommu *iommu,
732 struct ivhd_header *h)
733{
734 u8 *p = (u8 *)h;
735 u8 *end = p, flags = 0;
Joerg Roedel0de66d52011-06-06 16:04:02 +0200736 u16 devid = 0, devid_start = 0, devid_to = 0;
737 u32 dev_i, ext_flags = 0;
Joerg Roedel58a3bee2008-07-11 17:14:30 +0200738 bool alias = false;
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200739 struct ivhd_entry *e;
740
741 /*
Joerg Roedele9bf5192010-09-20 14:33:07 +0200742 * First save the recommended feature enable bits from ACPI
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200743 */
Joerg Roedele9bf5192010-09-20 14:33:07 +0200744 iommu->acpi_flags = h->flags;
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200745
746 /*
747 * Done. Now parse the device entries
748 */
749 p += sizeof(struct ivhd_header);
750 end += h->length;
751
Joerg Roedel42a698f2009-05-20 15:41:28 +0200752
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200753 while (p < end) {
754 e = (struct ivhd_entry *)p;
755 switch (e->type) {
756 case IVHD_DEV_ALL:
Joerg Roedel42a698f2009-05-20 15:41:28 +0200757
758 DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x"
759 " last device %02x:%02x.%x flags: %02x\n",
760 PCI_BUS(iommu->first_device),
761 PCI_SLOT(iommu->first_device),
762 PCI_FUNC(iommu->first_device),
763 PCI_BUS(iommu->last_device),
764 PCI_SLOT(iommu->last_device),
765 PCI_FUNC(iommu->last_device),
766 e->flags);
767
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200768 for (dev_i = iommu->first_device;
769 dev_i <= iommu->last_device; ++dev_i)
Joerg Roedel5ff47892008-07-14 20:11:18 +0200770 set_dev_entry_from_acpi(iommu, dev_i,
771 e->flags, 0);
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200772 break;
773 case IVHD_DEV_SELECT:
Joerg Roedel42a698f2009-05-20 15:41:28 +0200774
775 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
776 "flags: %02x\n",
777 PCI_BUS(e->devid),
778 PCI_SLOT(e->devid),
779 PCI_FUNC(e->devid),
780 e->flags);
781
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200782 devid = e->devid;
Joerg Roedel5ff47892008-07-14 20:11:18 +0200783 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200784 break;
785 case IVHD_DEV_SELECT_RANGE_START:
Joerg Roedel42a698f2009-05-20 15:41:28 +0200786
787 DUMP_printk(" DEV_SELECT_RANGE_START\t "
788 "devid: %02x:%02x.%x flags: %02x\n",
789 PCI_BUS(e->devid),
790 PCI_SLOT(e->devid),
791 PCI_FUNC(e->devid),
792 e->flags);
793
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200794 devid_start = e->devid;
795 flags = e->flags;
796 ext_flags = 0;
Joerg Roedel58a3bee2008-07-11 17:14:30 +0200797 alias = false;
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200798 break;
799 case IVHD_DEV_ALIAS:
Joerg Roedel42a698f2009-05-20 15:41:28 +0200800
801 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
802 "flags: %02x devid_to: %02x:%02x.%x\n",
803 PCI_BUS(e->devid),
804 PCI_SLOT(e->devid),
805 PCI_FUNC(e->devid),
806 e->flags,
807 PCI_BUS(e->ext >> 8),
808 PCI_SLOT(e->ext >> 8),
809 PCI_FUNC(e->ext >> 8));
810
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200811 devid = e->devid;
812 devid_to = e->ext >> 8;
Joerg Roedel7a6a3a02009-07-02 12:23:23 +0200813 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
Neil Turton7455aab2009-05-14 14:08:11 +0100814 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200815 amd_iommu_alias_table[devid] = devid_to;
816 break;
817 case IVHD_DEV_ALIAS_RANGE:
Joerg Roedel42a698f2009-05-20 15:41:28 +0200818
819 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
820 "devid: %02x:%02x.%x flags: %02x "
821 "devid_to: %02x:%02x.%x\n",
822 PCI_BUS(e->devid),
823 PCI_SLOT(e->devid),
824 PCI_FUNC(e->devid),
825 e->flags,
826 PCI_BUS(e->ext >> 8),
827 PCI_SLOT(e->ext >> 8),
828 PCI_FUNC(e->ext >> 8));
829
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200830 devid_start = e->devid;
831 flags = e->flags;
832 devid_to = e->ext >> 8;
833 ext_flags = 0;
Joerg Roedel58a3bee2008-07-11 17:14:30 +0200834 alias = true;
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200835 break;
836 case IVHD_DEV_EXT_SELECT:
Joerg Roedel42a698f2009-05-20 15:41:28 +0200837
838 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
839 "flags: %02x ext: %08x\n",
840 PCI_BUS(e->devid),
841 PCI_SLOT(e->devid),
842 PCI_FUNC(e->devid),
843 e->flags, e->ext);
844
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200845 devid = e->devid;
Joerg Roedel5ff47892008-07-14 20:11:18 +0200846 set_dev_entry_from_acpi(iommu, devid, e->flags,
847 e->ext);
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200848 break;
849 case IVHD_DEV_EXT_SELECT_RANGE:
Joerg Roedel42a698f2009-05-20 15:41:28 +0200850
851 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
852 "%02x:%02x.%x flags: %02x ext: %08x\n",
853 PCI_BUS(e->devid),
854 PCI_SLOT(e->devid),
855 PCI_FUNC(e->devid),
856 e->flags, e->ext);
857
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200858 devid_start = e->devid;
859 flags = e->flags;
860 ext_flags = e->ext;
Joerg Roedel58a3bee2008-07-11 17:14:30 +0200861 alias = false;
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200862 break;
863 case IVHD_DEV_RANGE_END:
Joerg Roedel42a698f2009-05-20 15:41:28 +0200864
865 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
866 PCI_BUS(e->devid),
867 PCI_SLOT(e->devid),
868 PCI_FUNC(e->devid));
869
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200870 devid = e->devid;
871 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
Joerg Roedel7a6a3a02009-07-02 12:23:23 +0200872 if (alias) {
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200873 amd_iommu_alias_table[dev_i] = devid_to;
Joerg Roedel7a6a3a02009-07-02 12:23:23 +0200874 set_dev_entry_from_acpi(iommu,
875 devid_to, flags, ext_flags);
876 }
877 set_dev_entry_from_acpi(iommu, dev_i,
878 flags, ext_flags);
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200879 }
880 break;
881 default:
882 break;
883 }
884
Joerg Roedelb514e552008-09-17 17:14:27 +0200885 p += ivhd_entry_length(p);
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200886 }
887}
888
Joerg Roedelb65233a2008-07-11 17:14:21 +0200889/* Initializes the device->iommu mapping for the driver */
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200890static int __init init_iommu_devices(struct amd_iommu *iommu)
891{
Joerg Roedel0de66d52011-06-06 16:04:02 +0200892 u32 i;
Joerg Roedel5d0c8e42008-06-26 21:27:47 +0200893
894 for (i = iommu->first_device; i <= iommu->last_device; ++i)
895 set_iommu_for_device(iommu, i);
896
897 return 0;
898}
899
Joerg Roedele47d4022008-06-26 21:27:48 +0200900static void __init free_iommu_one(struct amd_iommu *iommu)
901{
902 free_command_buffer(iommu);
Joerg Roedel335503e2008-09-05 14:29:07 +0200903 free_event_buffer(iommu);
Joerg Roedele47d4022008-06-26 21:27:48 +0200904 iommu_unmap_mmio_space(iommu);
905}
906
907static void __init free_iommu_all(void)
908{
909 struct amd_iommu *iommu, *next;
910
Joerg Roedel3bd22172009-05-04 15:06:20 +0200911 for_each_iommu_safe(iommu, next) {
Joerg Roedele47d4022008-06-26 21:27:48 +0200912 list_del(&iommu->list);
913 free_iommu_one(iommu);
914 kfree(iommu);
915 }
916}
917
Joerg Roedelb65233a2008-07-11 17:14:21 +0200918/*
919 * This function clues the initialization function for one IOMMU
920 * together and also allocates the command buffer and programs the
921 * hardware. It does NOT enable the IOMMU. This is done afterwards.
922 */
Joerg Roedele47d4022008-06-26 21:27:48 +0200923static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
924{
925 spin_lock_init(&iommu->lock);
Joerg Roedelbb527772009-11-20 14:31:51 +0100926
927 /* Add IOMMU to internal data structures */
Joerg Roedele47d4022008-06-26 21:27:48 +0200928 list_add_tail(&iommu->list, &amd_iommu_list);
Joerg Roedelbb527772009-11-20 14:31:51 +0100929 iommu->index = amd_iommus_present++;
930
931 if (unlikely(iommu->index >= MAX_IOMMUS)) {
932 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
933 return -ENOSYS;
934 }
935
936 /* Index is fine - add IOMMU to the array */
937 amd_iommus[iommu->index] = iommu;
Joerg Roedele47d4022008-06-26 21:27:48 +0200938
939 /*
940 * Copy data from ACPI table entry to the iommu struct
941 */
Joerg Roedel3eaf28a2008-09-08 15:55:10 +0200942 iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff);
943 if (!iommu->dev)
944 return 1;
945
Joerg Roedele47d4022008-06-26 21:27:48 +0200946 iommu->cap_ptr = h->cap_ptr;
Joerg Roedelee893c22008-09-08 14:48:04 +0200947 iommu->pci_seg = h->pci_seg;
Joerg Roedele47d4022008-06-26 21:27:48 +0200948 iommu->mmio_phys = h->mmio_phys;
949 iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys);
950 if (!iommu->mmio_base)
951 return -ENOMEM;
952
Joerg Roedele47d4022008-06-26 21:27:48 +0200953 iommu->cmd_buf = alloc_command_buffer(iommu);
954 if (!iommu->cmd_buf)
955 return -ENOMEM;
956
Joerg Roedel335503e2008-09-05 14:29:07 +0200957 iommu->evt_buf = alloc_event_buffer(iommu);
958 if (!iommu->evt_buf)
959 return -ENOMEM;
960
Joerg Roedela80dc3e2008-09-11 16:51:41 +0200961 iommu->int_enabled = false;
962
Joerg Roedele47d4022008-06-26 21:27:48 +0200963 init_iommu_from_pci(iommu);
964 init_iommu_from_acpi(iommu, h);
965 init_iommu_devices(iommu);
966
Joerg Roedel318afd42009-11-23 18:32:38 +0100967 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
968 amd_iommu_np_cache = true;
969
Ingo Molnar8a667122008-10-12 15:24:53 +0200970 return pci_enable_device(iommu->dev);
Joerg Roedele47d4022008-06-26 21:27:48 +0200971}
972
Joerg Roedelb65233a2008-07-11 17:14:21 +0200973/*
974 * Iterates over all IOMMU entries in the ACPI table, allocates the
975 * IOMMU structure and initializes it with init_iommu_one()
976 */
Joerg Roedele47d4022008-06-26 21:27:48 +0200977static int __init init_iommu_all(struct acpi_table_header *table)
978{
979 u8 *p = (u8 *)table, *end = (u8 *)table;
980 struct ivhd_header *h;
981 struct amd_iommu *iommu;
982 int ret;
983
Joerg Roedele47d4022008-06-26 21:27:48 +0200984 end += table->length;
985 p += IVRS_HEADER_LENGTH;
986
987 while (p < end) {
988 h = (struct ivhd_header *)p;
989 switch (*p) {
990 case ACPI_IVHD_TYPE:
Joerg Roedel9c720412009-05-20 13:53:57 +0200991
Joerg Roedelae908c22009-09-01 16:52:16 +0200992 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
Joerg Roedel9c720412009-05-20 13:53:57 +0200993 "seg: %d flags: %01x info %04x\n",
994 PCI_BUS(h->devid), PCI_SLOT(h->devid),
995 PCI_FUNC(h->devid), h->cap_ptr,
996 h->pci_seg, h->flags, h->info);
997 DUMP_printk(" mmio-addr: %016llx\n",
998 h->mmio_phys);
999
Joerg Roedele47d4022008-06-26 21:27:48 +02001000 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
Joerg Roedel3551a702010-03-01 13:52:19 +01001001 if (iommu == NULL) {
1002 amd_iommu_init_err = -ENOMEM;
1003 return 0;
1004 }
1005
Joerg Roedele47d4022008-06-26 21:27:48 +02001006 ret = init_iommu_one(iommu, h);
Joerg Roedel3551a702010-03-01 13:52:19 +01001007 if (ret) {
1008 amd_iommu_init_err = ret;
1009 return 0;
1010 }
Joerg Roedele47d4022008-06-26 21:27:48 +02001011 break;
1012 default:
1013 break;
1014 }
1015 p += h->length;
1016
1017 }
1018 WARN_ON(p != end);
1019
1020 return 0;
1021}
1022
Joerg Roedelb65233a2008-07-11 17:14:21 +02001023/****************************************************************************
1024 *
Joerg Roedela80dc3e2008-09-11 16:51:41 +02001025 * The following functions initialize the MSI interrupts for all IOMMUs
1026 * in the system. Its a bit challenging because there could be multiple
1027 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1028 * pci_dev.
1029 *
1030 ****************************************************************************/
1031
Joerg Roedel9f800de2009-11-23 12:45:25 +01001032static int iommu_setup_msi(struct amd_iommu *iommu)
Joerg Roedela80dc3e2008-09-11 16:51:41 +02001033{
1034 int r;
Joerg Roedela80dc3e2008-09-11 16:51:41 +02001035
1036 if (pci_enable_msi(iommu->dev))
1037 return 1;
1038
Joerg Roedel72fe00f2011-05-10 10:50:42 +02001039 r = request_threaded_irq(iommu->dev->irq,
1040 amd_iommu_int_handler,
1041 amd_iommu_int_thread,
1042 0, "AMD-Vi",
1043 iommu->dev);
Joerg Roedela80dc3e2008-09-11 16:51:41 +02001044
1045 if (r) {
1046 pci_disable_msi(iommu->dev);
1047 return 1;
1048 }
1049
Joerg Roedelfab6afa2009-05-04 18:46:34 +02001050 iommu->int_enabled = true;
Joerg Roedel58492e12009-05-04 18:41:16 +02001051 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
1052
Joerg Roedela80dc3e2008-09-11 16:51:41 +02001053 return 0;
1054}
1055
Joerg Roedel05f92db2009-05-12 09:52:46 +02001056static int iommu_init_msi(struct amd_iommu *iommu)
Joerg Roedela80dc3e2008-09-11 16:51:41 +02001057{
1058 if (iommu->int_enabled)
1059 return 0;
1060
Joerg Roedeld91cecd2009-05-04 18:51:00 +02001061 if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI))
Joerg Roedela80dc3e2008-09-11 16:51:41 +02001062 return iommu_setup_msi(iommu);
1063
1064 return 1;
1065}
1066
1067/****************************************************************************
1068 *
Joerg Roedelb65233a2008-07-11 17:14:21 +02001069 * The next functions belong to the third pass of parsing the ACPI
1070 * table. In this last pass the memory mapping requirements are
1071 * gathered (like exclusion and unity mapping reanges).
1072 *
1073 ****************************************************************************/
1074
Joerg Roedelbe2a0222008-06-26 21:27:49 +02001075static void __init free_unity_maps(void)
1076{
1077 struct unity_map_entry *entry, *next;
1078
1079 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1080 list_del(&entry->list);
1081 kfree(entry);
1082 }
1083}
1084
Joerg Roedelb65233a2008-07-11 17:14:21 +02001085/* called when we find an exclusion range definition in ACPI */
Joerg Roedelbe2a0222008-06-26 21:27:49 +02001086static int __init init_exclusion_range(struct ivmd_header *m)
1087{
1088 int i;
1089
1090 switch (m->type) {
1091 case ACPI_IVMD_TYPE:
1092 set_device_exclusion_range(m->devid, m);
1093 break;
1094 case ACPI_IVMD_TYPE_ALL:
Joerg Roedel3a61ec32008-07-25 13:07:50 +02001095 for (i = 0; i <= amd_iommu_last_bdf; ++i)
Joerg Roedelbe2a0222008-06-26 21:27:49 +02001096 set_device_exclusion_range(i, m);
1097 break;
1098 case ACPI_IVMD_TYPE_RANGE:
1099 for (i = m->devid; i <= m->aux; ++i)
1100 set_device_exclusion_range(i, m);
1101 break;
1102 default:
1103 break;
1104 }
1105
1106 return 0;
1107}
1108
Joerg Roedelb65233a2008-07-11 17:14:21 +02001109/* called for unity map ACPI definition */
Joerg Roedelbe2a0222008-06-26 21:27:49 +02001110static int __init init_unity_map_range(struct ivmd_header *m)
1111{
1112 struct unity_map_entry *e = 0;
Joerg Roedel02acc432009-05-20 16:24:21 +02001113 char *s;
Joerg Roedelbe2a0222008-06-26 21:27:49 +02001114
1115 e = kzalloc(sizeof(*e), GFP_KERNEL);
1116 if (e == NULL)
1117 return -ENOMEM;
1118
1119 switch (m->type) {
1120 default:
Joerg Roedel0bc252f2009-05-22 12:48:05 +02001121 kfree(e);
1122 return 0;
Joerg Roedelbe2a0222008-06-26 21:27:49 +02001123 case ACPI_IVMD_TYPE:
Joerg Roedel02acc432009-05-20 16:24:21 +02001124 s = "IVMD_TYPEi\t\t\t";
Joerg Roedelbe2a0222008-06-26 21:27:49 +02001125 e->devid_start = e->devid_end = m->devid;
1126 break;
1127 case ACPI_IVMD_TYPE_ALL:
Joerg Roedel02acc432009-05-20 16:24:21 +02001128 s = "IVMD_TYPE_ALL\t\t";
Joerg Roedelbe2a0222008-06-26 21:27:49 +02001129 e->devid_start = 0;
1130 e->devid_end = amd_iommu_last_bdf;
1131 break;
1132 case ACPI_IVMD_TYPE_RANGE:
Joerg Roedel02acc432009-05-20 16:24:21 +02001133 s = "IVMD_TYPE_RANGE\t\t";
Joerg Roedelbe2a0222008-06-26 21:27:49 +02001134 e->devid_start = m->devid;
1135 e->devid_end = m->aux;
1136 break;
1137 }
1138 e->address_start = PAGE_ALIGN(m->range_start);
1139 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1140 e->prot = m->flags >> 1;
1141
Joerg Roedel02acc432009-05-20 16:24:21 +02001142 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1143 " range_start: %016llx range_end: %016llx flags: %x\n", s,
1144 PCI_BUS(e->devid_start), PCI_SLOT(e->devid_start),
1145 PCI_FUNC(e->devid_start), PCI_BUS(e->devid_end),
1146 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1147 e->address_start, e->address_end, m->flags);
1148
Joerg Roedelbe2a0222008-06-26 21:27:49 +02001149 list_add_tail(&e->list, &amd_iommu_unity_map);
1150
1151 return 0;
1152}
1153
Joerg Roedelb65233a2008-07-11 17:14:21 +02001154/* iterates over all memory definitions we find in the ACPI table */
Joerg Roedelbe2a0222008-06-26 21:27:49 +02001155static int __init init_memory_definitions(struct acpi_table_header *table)
1156{
1157 u8 *p = (u8 *)table, *end = (u8 *)table;
1158 struct ivmd_header *m;
1159
Joerg Roedelbe2a0222008-06-26 21:27:49 +02001160 end += table->length;
1161 p += IVRS_HEADER_LENGTH;
1162
1163 while (p < end) {
1164 m = (struct ivmd_header *)p;
1165 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1166 init_exclusion_range(m);
1167 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1168 init_unity_map_range(m);
1169
1170 p += m->length;
1171 }
1172
1173 return 0;
1174}
1175
Joerg Roedelb65233a2008-07-11 17:14:21 +02001176/*
Joerg Roedel9f5f5fb2008-08-14 19:55:16 +02001177 * Init the device table to not allow DMA access for devices and
1178 * suppress all page faults
1179 */
1180static void init_device_table(void)
1181{
Joerg Roedel0de66d52011-06-06 16:04:02 +02001182 u32 devid;
Joerg Roedel9f5f5fb2008-08-14 19:55:16 +02001183
1184 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1185 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1186 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
Joerg Roedel9f5f5fb2008-08-14 19:55:16 +02001187 }
1188}
1189
Joerg Roedele9bf5192010-09-20 14:33:07 +02001190static void iommu_init_flags(struct amd_iommu *iommu)
1191{
1192 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
1193 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
1194 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
1195
1196 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
1197 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
1198 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
1199
1200 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
1201 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
1202 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
1203
1204 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
1205 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
1206 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
1207
1208 /*
1209 * make IOMMU memory accesses cache coherent
1210 */
1211 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
1212}
1213
Matthew Garrett5bcd7572010-10-04 14:59:31 -04001214static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
Joerg Roedel4c894f42010-09-23 15:15:19 +02001215{
Matthew Garrett5bcd7572010-10-04 14:59:31 -04001216 int i, j;
1217 u32 ioc_feature_control;
1218 struct pci_dev *pdev = NULL;
1219
1220 /* RD890 BIOSes may not have completely reconfigured the iommu */
1221 if (!is_rd890_iommu(iommu->dev))
1222 return;
1223
1224 /*
1225 * First, we need to ensure that the iommu is enabled. This is
1226 * controlled by a register in the northbridge
1227 */
1228 pdev = pci_get_bus_and_slot(iommu->dev->bus->number, PCI_DEVFN(0, 0));
1229
1230 if (!pdev)
1231 return;
1232
1233 /* Select Northbridge indirect register 0x75 and enable writing */
1234 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
1235 pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
1236
1237 /* Enable the iommu */
1238 if (!(ioc_feature_control & 0x1))
1239 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
1240
1241 pci_dev_put(pdev);
1242
1243 /* Restore the iommu BAR */
1244 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1245 iommu->stored_addr_lo);
1246 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
1247 iommu->stored_addr_hi);
1248
1249 /* Restore the l1 indirect regs for each of the 6 l1s */
1250 for (i = 0; i < 6; i++)
1251 for (j = 0; j < 0x12; j++)
1252 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
1253
1254 /* Restore the l2 indirect regs */
1255 for (i = 0; i < 0x83; i++)
1256 iommu_write_l2(iommu, i, iommu->stored_l2[i]);
1257
1258 /* Lock PCI setup registers */
1259 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1260 iommu->stored_addr_lo | 1);
Joerg Roedel4c894f42010-09-23 15:15:19 +02001261}
1262
Joerg Roedel9f5f5fb2008-08-14 19:55:16 +02001263/*
Joerg Roedelb65233a2008-07-11 17:14:21 +02001264 * This function finally enables all IOMMUs found in the system after
1265 * they have been initialized
1266 */
Joerg Roedel05f92db2009-05-12 09:52:46 +02001267static void enable_iommus(void)
Joerg Roedel87361972008-06-26 21:28:07 +02001268{
1269 struct amd_iommu *iommu;
1270
Joerg Roedel3bd22172009-05-04 15:06:20 +02001271 for_each_iommu(iommu) {
Chris Wrighta8c485b2009-06-15 15:53:45 +02001272 iommu_disable(iommu);
Joerg Roedele9bf5192010-09-20 14:33:07 +02001273 iommu_init_flags(iommu);
Joerg Roedel58492e12009-05-04 18:41:16 +02001274 iommu_set_device_table(iommu);
1275 iommu_enable_command_buffer(iommu);
1276 iommu_enable_event_buffer(iommu);
Joerg Roedel87361972008-06-26 21:28:07 +02001277 iommu_set_exclusion_range(iommu);
Joerg Roedela80dc3e2008-09-11 16:51:41 +02001278 iommu_init_msi(iommu);
Joerg Roedel87361972008-06-26 21:28:07 +02001279 iommu_enable(iommu);
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001280 iommu_flush_all_caches(iommu);
Joerg Roedel87361972008-06-26 21:28:07 +02001281 }
1282}
1283
Joerg Roedel92ac4322009-05-19 19:06:27 +02001284static void disable_iommus(void)
1285{
1286 struct amd_iommu *iommu;
1287
1288 for_each_iommu(iommu)
1289 iommu_disable(iommu);
1290}
1291
Joerg Roedel7441e9c2008-06-30 20:18:02 +02001292/*
1293 * Suspend/Resume support
1294 * disable suspend until real resume implemented
1295 */
1296
Rafael J. Wysockif3c6ea12011-03-23 22:15:54 +01001297static void amd_iommu_resume(void)
Joerg Roedel7441e9c2008-06-30 20:18:02 +02001298{
Matthew Garrett5bcd7572010-10-04 14:59:31 -04001299 struct amd_iommu *iommu;
1300
1301 for_each_iommu(iommu)
1302 iommu_apply_resume_quirks(iommu);
1303
Joerg Roedel736501e2009-05-12 09:56:12 +02001304 /* re-load the hardware */
1305 enable_iommus();
1306
1307 /*
1308 * we have to flush after the IOMMUs are enabled because a
1309 * disabled IOMMU will never execute the commands we send
1310 */
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001311 for_each_iommu(iommu)
1312 iommu_flush_all_caches(iommu);
Joerg Roedel7441e9c2008-06-30 20:18:02 +02001313}
1314
Rafael J. Wysockif3c6ea12011-03-23 22:15:54 +01001315static int amd_iommu_suspend(void)
Joerg Roedel7441e9c2008-06-30 20:18:02 +02001316{
Joerg Roedel736501e2009-05-12 09:56:12 +02001317 /* disable IOMMUs to go out of the way for BIOS */
1318 disable_iommus();
1319
1320 return 0;
Joerg Roedel7441e9c2008-06-30 20:18:02 +02001321}
1322
Rafael J. Wysockif3c6ea12011-03-23 22:15:54 +01001323static struct syscore_ops amd_iommu_syscore_ops = {
Joerg Roedel7441e9c2008-06-30 20:18:02 +02001324 .suspend = amd_iommu_suspend,
1325 .resume = amd_iommu_resume,
1326};
1327
Joerg Roedelb65233a2008-07-11 17:14:21 +02001328/*
1329 * This is the core init function for AMD IOMMU hardware in the system.
1330 * This function is called from the generic x86 DMA layer initialization
1331 * code.
1332 *
1333 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1334 * three times:
1335 *
1336 * 1 pass) Find the highest PCI device id the driver has to handle.
1337 * Upon this information the size of the data structures is
1338 * determined that needs to be allocated.
1339 *
1340 * 2 pass) Initialize the data structures just allocated with the
1341 * information in the ACPI table about available AMD IOMMUs
1342 * in the system. It also maps the PCI devices in the
1343 * system to specific IOMMUs
1344 *
1345 * 3 pass) After the basic data structures are allocated and
1346 * initialized we update them with information about memory
1347 * remapping requirements parsed out of the ACPI table in
1348 * this last pass.
1349 *
1350 * After that the hardware is initialized and ready to go. In the last
1351 * step we do some Linux specific things like registering the driver in
1352 * the dma_ops interface and initializing the suspend/resume support
1353 * functions. Finally it prints some information about AMD IOMMUs and
1354 * the driver state and enables the hardware.
1355 */
FUJITA Tomonoriea1b0d32009-11-10 19:46:15 +09001356static int __init amd_iommu_init(void)
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001357{
1358 int i, ret = 0;
1359
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001360 /*
1361 * First parse ACPI tables to find the largest Bus/Dev/Func
1362 * we need to handle. Upon this information the shared data
1363 * structures for the IOMMUs in the system will be allocated
1364 */
1365 if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0)
1366 return -ENODEV;
1367
Joerg Roedel3551a702010-03-01 13:52:19 +01001368 ret = amd_iommu_init_err;
1369 if (ret)
1370 goto out;
1371
Joerg Roedelc5714842008-07-11 17:14:25 +02001372 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
1373 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
1374 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001375
1376 ret = -ENOMEM;
1377
1378 /* Device table - directly used by all IOMMUs */
Joerg Roedel5dc8bff2008-07-11 17:14:32 +02001379 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001380 get_order(dev_table_size));
1381 if (amd_iommu_dev_table == NULL)
1382 goto out;
1383
1384 /*
1385 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1386 * IOMMU see for that device
1387 */
1388 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
1389 get_order(alias_table_size));
1390 if (amd_iommu_alias_table == NULL)
1391 goto free;
1392
1393 /* IOMMU rlookup table - find the IOMMU for a specific device */
Joerg Roedel83fd5cc2008-12-16 19:17:11 +01001394 amd_iommu_rlookup_table = (void *)__get_free_pages(
1395 GFP_KERNEL | __GFP_ZERO,
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001396 get_order(rlookup_table_size));
1397 if (amd_iommu_rlookup_table == NULL)
1398 goto free;
1399
Joerg Roedel5dc8bff2008-07-11 17:14:32 +02001400 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
1401 GFP_KERNEL | __GFP_ZERO,
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001402 get_order(MAX_DOMAIN_ID/8));
1403 if (amd_iommu_pd_alloc_bitmap == NULL)
1404 goto free;
1405
Joerg Roedel9f5f5fb2008-08-14 19:55:16 +02001406 /* init the device table */
1407 init_device_table();
1408
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001409 /*
Joerg Roedel5dc8bff2008-07-11 17:14:32 +02001410 * let all alias entries point to itself
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001411 */
Joerg Roedel3a61ec32008-07-25 13:07:50 +02001412 for (i = 0; i <= amd_iommu_last_bdf; ++i)
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001413 amd_iommu_alias_table[i] = i;
1414
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001415 /*
1416 * never allocate domain 0 because its used as the non-allocated and
1417 * error value placeholder
1418 */
1419 amd_iommu_pd_alloc_bitmap[0] = 1;
1420
Joerg Roedelaeb26f52009-11-20 16:44:01 +01001421 spin_lock_init(&amd_iommu_pd_lock);
1422
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001423 /*
1424 * now the data structures are allocated and basically initialized
1425 * start the real acpi table scan
1426 */
1427 ret = -ENODEV;
1428 if (acpi_table_parse("IVRS", init_iommu_all) != 0)
1429 goto free;
1430
Joerg Roedel3551a702010-03-01 13:52:19 +01001431 if (amd_iommu_init_err) {
1432 ret = amd_iommu_init_err;
Joerg Roedel0f764802009-12-21 15:51:23 +01001433 goto free;
Joerg Roedel3551a702010-03-01 13:52:19 +01001434 }
Joerg Roedel0f764802009-12-21 15:51:23 +01001435
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001436 if (acpi_table_parse("IVRS", init_memory_definitions) != 0)
1437 goto free;
1438
Joerg Roedel3551a702010-03-01 13:52:19 +01001439 if (amd_iommu_init_err) {
1440 ret = amd_iommu_init_err;
1441 goto free;
1442 }
1443
Joerg Roedelb7cc9552009-12-10 11:03:39 +01001444 ret = amd_iommu_init_devices();
1445 if (ret)
1446 goto free;
1447
Chris Wright75f66532010-04-02 18:27:52 -07001448 enable_iommus();
1449
Joerg Roedel4751a952009-09-01 15:53:54 +02001450 if (iommu_pass_through)
1451 ret = amd_iommu_init_passthrough();
1452 else
1453 ret = amd_iommu_init_dma_ops();
Joerg Roedelf5325092010-01-22 17:44:35 +01001454
Joerg Roedel129d6ab2008-08-14 19:55:18 +02001455 if (ret)
Joerg Roedele82752d2010-05-28 14:26:48 +02001456 goto free_disable;
Joerg Roedel129d6ab2008-08-14 19:55:18 +02001457
Joerg Roedelf5325092010-01-22 17:44:35 +01001458 amd_iommu_init_api();
1459
Joerg Roedel8638c492009-12-10 11:12:25 +01001460 amd_iommu_init_notifier();
1461
Rafael J. Wysockif3c6ea12011-03-23 22:15:54 +01001462 register_syscore_ops(&amd_iommu_syscore_ops);
1463
Joerg Roedel4751a952009-09-01 15:53:54 +02001464 if (iommu_pass_through)
1465 goto out;
1466
FUJITA Tomonoriafa9fdc2008-09-20 01:23:30 +09001467 if (amd_iommu_unmap_flush)
Joerg Roedel4c6f40d2009-09-01 16:43:58 +02001468 printk(KERN_INFO "AMD-Vi: IO/TLB flush on unmap enabled\n");
Joerg Roedel1c655772008-09-04 18:40:05 +02001469 else
Joerg Roedel4c6f40d2009-09-01 16:43:58 +02001470 printk(KERN_INFO "AMD-Vi: Lazy IO/TLB flushing enabled\n");
Joerg Roedel1c655772008-09-04 18:40:05 +02001471
FUJITA Tomonori338bac52009-10-27 16:34:44 +09001472 x86_platform.iommu_shutdown = disable_iommus;
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001473out:
1474 return ret;
1475
Joerg Roedele82752d2010-05-28 14:26:48 +02001476free_disable:
Chris Wright75f66532010-04-02 18:27:52 -07001477 disable_iommus();
Joerg Roedelb7cc9552009-12-10 11:03:39 +01001478
Joerg Roedele82752d2010-05-28 14:26:48 +02001479free:
Joerg Roedelb7cc9552009-12-10 11:03:39 +01001480 amd_iommu_uninit_devices();
1481
Joerg Roedeld58befd2008-09-17 12:19:58 +02001482 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
1483 get_order(MAX_DOMAIN_ID/8));
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001484
Joerg Roedel9a836de2008-07-11 17:14:26 +02001485 free_pages((unsigned long)amd_iommu_rlookup_table,
1486 get_order(rlookup_table_size));
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001487
Joerg Roedel9a836de2008-07-11 17:14:26 +02001488 free_pages((unsigned long)amd_iommu_alias_table,
1489 get_order(alias_table_size));
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001490
Joerg Roedel9a836de2008-07-11 17:14:26 +02001491 free_pages((unsigned long)amd_iommu_dev_table,
1492 get_order(dev_table_size));
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001493
1494 free_iommu_all();
1495
1496 free_unity_maps();
1497
Joerg Roedeld7f07762010-05-31 15:05:20 +02001498#ifdef CONFIG_GART_IOMMU
1499 /*
1500 * We failed to initialize the AMD IOMMU - try fallback to GART
1501 * if possible.
1502 */
1503 gart_iommu_init();
1504
1505#endif
1506
Joerg Roedelfe74c9c2008-06-26 21:27:50 +02001507 goto out;
1508}
1509
Joerg Roedelb65233a2008-07-11 17:14:21 +02001510/****************************************************************************
1511 *
1512 * Early detect code. This code runs at IOMMU detection time in the DMA
1513 * layer. It just looks if there is an IVRS ACPI table to detect AMD
1514 * IOMMUs
1515 *
1516 ****************************************************************************/
Joerg Roedelae7877d2008-06-26 21:27:51 +02001517static int __init early_amd_iommu_detect(struct acpi_table_header *table)
1518{
1519 return 0;
1520}
1521
Konrad Rzeszutek Wilk480125b2010-08-26 13:57:57 -04001522int __init amd_iommu_detect(void)
Joerg Roedelae7877d2008-06-26 21:27:51 +02001523{
FUJITA Tomonori75f1cdf2009-11-10 19:46:20 +09001524 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
Konrad Rzeszutek Wilk480125b2010-08-26 13:57:57 -04001525 return -ENODEV;
Joerg Roedelae7877d2008-06-26 21:27:51 +02001526
Joerg Roedela5235722010-05-11 17:12:33 +02001527 if (amd_iommu_disabled)
Konrad Rzeszutek Wilk480125b2010-08-26 13:57:57 -04001528 return -ENODEV;
Joerg Roedela5235722010-05-11 17:12:33 +02001529
Joerg Roedelae7877d2008-06-26 21:27:51 +02001530 if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) {
1531 iommu_detected = 1;
Joerg Roedelc1cbebe2008-07-03 19:35:10 +02001532 amd_iommu_detected = 1;
FUJITA Tomonoriea1b0d32009-11-10 19:46:15 +09001533 x86_init.iommu.iommu_init = amd_iommu_init;
Linus Torvalds11bd04f2009-12-11 12:18:16 -08001534
Chris Wright5d990b62009-12-04 12:15:21 -08001535 /* Make sure ACS will be enabled */
1536 pci_request_acs();
Konrad Rzeszutek Wilk480125b2010-08-26 13:57:57 -04001537 return 1;
Joerg Roedelae7877d2008-06-26 21:27:51 +02001538 }
Konrad Rzeszutek Wilk480125b2010-08-26 13:57:57 -04001539 return -ENODEV;
Joerg Roedelae7877d2008-06-26 21:27:51 +02001540}
1541
Joerg Roedelb65233a2008-07-11 17:14:21 +02001542/****************************************************************************
1543 *
1544 * Parsing functions for the AMD IOMMU specific kernel command line
1545 * options.
1546 *
1547 ****************************************************************************/
1548
Joerg Roedelfefda112009-05-20 12:21:42 +02001549static int __init parse_amd_iommu_dump(char *str)
1550{
1551 amd_iommu_dump = true;
1552
1553 return 1;
1554}
1555
Joerg Roedel918ad6c2008-06-26 21:27:52 +02001556static int __init parse_amd_iommu_options(char *str)
1557{
1558 for (; *str; ++str) {
Joerg Roedel695b5672008-11-17 15:16:43 +01001559 if (strncmp(str, "fullflush", 9) == 0)
FUJITA Tomonoriafa9fdc2008-09-20 01:23:30 +09001560 amd_iommu_unmap_flush = true;
Joerg Roedela5235722010-05-11 17:12:33 +02001561 if (strncmp(str, "off", 3) == 0)
1562 amd_iommu_disabled = true;
Joerg Roedel918ad6c2008-06-26 21:27:52 +02001563 }
1564
1565 return 1;
1566}
1567
Joerg Roedelfefda112009-05-20 12:21:42 +02001568__setup("amd_iommu_dump", parse_amd_iommu_dump);
Joerg Roedel918ad6c2008-06-26 21:27:52 +02001569__setup("amd_iommu=", parse_amd_iommu_options);
Konrad Rzeszutek Wilk22e6daf2010-08-26 13:58:03 -04001570
1571IOMMU_INIT_FINISH(amd_iommu_detect,
1572 gart_iommu_hole_init,
1573 0,
1574 0);