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gerrit-public.fairphone.software / kernel / msm-4.9 / 14c95fc896e1d3929abde448fd86c07bdbae56d5 / . / drivers / pinctrl / sunxi / pinctrl-sun8i-a83t.c
blob: 90b973e159821c5889d95e58513bb04661bf8ff5 [file] [log] [blame]
Vishnu Patekar4730f332015-09-22 23:38:55 +0800[diff] [blame]1/*
2 * Allwinner a83t SoCs pinctrl driver.
3 *
4 * Copyright (C) 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
5 *
6 * Based on pinctrl-sun8i-a23.c, which is:
7 * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org>
8 * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#include <linux/module.h>
16#include <linux/platform_device.h>
17#include <linux/of.h>
18#include <linux/of_device.h>
19#include <linux/pinctrl/pinctrl.h>
20
21#include "pinctrl-sunxi.h"
22
23static const struct sunxi_desc_pin sun8i_a83t_pins[] = {
24 /* Hole */
25 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
26 SUNXI_FUNCTION(0x0, "gpio_in"),
27 SUNXI_FUNCTION(0x1, "gpio_out"),
28 SUNXI_FUNCTION(0x2, "uart2"), /* TX */
29 SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
30 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PB_EINT0 */
31 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
32 SUNXI_FUNCTION(0x0, "gpio_in"),
33 SUNXI_FUNCTION(0x1, "gpio_out"),
34 SUNXI_FUNCTION(0x2, "uart2"), /* RX */
35 SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
36 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PB_EINT1 */
37 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
38 SUNXI_FUNCTION(0x0, "gpio_in"),
39 SUNXI_FUNCTION(0x1, "gpio_out"),
40 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
41 SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
42 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PB_EINT2 */
43 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
44 SUNXI_FUNCTION(0x0, "gpio_in"),
45 SUNXI_FUNCTION(0x1, "gpio_out"),
46 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
47 SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
48 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PB_EINT3 */
49 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
50 SUNXI_FUNCTION(0x0, "gpio_in"),
51 SUNXI_FUNCTION(0x1, "gpio_out"),
52 SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */
53 SUNXI_FUNCTION(0x3, "tdm"), /* LRCK */
54 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PB_EINT4 */
55 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
56 SUNXI_FUNCTION(0x0, "gpio_in"),
57 SUNXI_FUNCTION(0x1, "gpio_out"),
58 SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
59 SUNXI_FUNCTION(0x3, "tdm"), /* BCLK */
60 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PB_EINT5 */
61 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
62 SUNXI_FUNCTION(0x0, "gpio_in"),
63 SUNXI_FUNCTION(0x1, "gpio_out"),
64 SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */
65 SUNXI_FUNCTION(0x3, "tdm"), /* DOUT */
66 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PB_EINT6 */
67 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
68 SUNXI_FUNCTION(0x0, "gpio_in"),
69 SUNXI_FUNCTION(0x1, "gpio_out"),
70 SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */
71 SUNXI_FUNCTION(0x3, "tdm"), /* DIN */
72 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PB_EINT7 */
73 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
74 SUNXI_FUNCTION(0x0, "gpio_in"),
75 SUNXI_FUNCTION(0x1, "gpio_out"),
76 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
77 SUNXI_FUNCTION(0x3, "tdm"), /* MCLK */
78 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PB_EINT8 */
79 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
80 SUNXI_FUNCTION(0x0, "gpio_in"),
81 SUNXI_FUNCTION(0x1, "gpio_out"),
82 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
83 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PB_EINT9 */
84 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
85 SUNXI_FUNCTION(0x0, "gpio_in"),
86 SUNXI_FUNCTION(0x1, "gpio_out"),
87 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
88 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PB_EINT10 */
89 /* Hole */
90 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
91 SUNXI_FUNCTION(0x0, "gpio_in"),
92 SUNXI_FUNCTION(0x1, "gpio_out"),
93 SUNXI_FUNCTION(0x2, "nand0"), /* WE */
94 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
95 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
96 SUNXI_FUNCTION(0x0, "gpio_in"),
97 SUNXI_FUNCTION(0x1, "gpio_out"),
98 SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
99 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
100 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
101 SUNXI_FUNCTION(0x0, "gpio_in"),
102 SUNXI_FUNCTION(0x1, "gpio_out"),
103 SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
104 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
105 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
106 SUNXI_FUNCTION(0x0, "gpio_in"),
107 SUNXI_FUNCTION(0x1, "gpio_out"),
108 SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */
109 SUNXI_FUNCTION(0x3, "spi0")), /* CS */
110 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
111 SUNXI_FUNCTION(0x0, "gpio_in"),
112 SUNXI_FUNCTION(0x1, "gpio_out"),
113 SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
114 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
115 SUNXI_FUNCTION(0x0, "gpio_in"),
116 SUNXI_FUNCTION(0x1, "gpio_out"),
117 SUNXI_FUNCTION(0x2, "nand0"), /* RE */
118 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
119 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
120 SUNXI_FUNCTION(0x0, "gpio_in"),
121 SUNXI_FUNCTION(0x1, "gpio_out"),
122 SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
123 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
124 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
125 SUNXI_FUNCTION(0x0, "gpio_in"),
126 SUNXI_FUNCTION(0x1, "gpio_out"),
127 SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */
128 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
129 SUNXI_FUNCTION(0x0, "gpio_in"),
130 SUNXI_FUNCTION(0x1, "gpio_out"),
131 SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
132 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
133 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
134 SUNXI_FUNCTION(0x0, "gpio_in"),
135 SUNXI_FUNCTION(0x1, "gpio_out"),
136 SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
137 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
138 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
139 SUNXI_FUNCTION(0x0, "gpio_in"),
140 SUNXI_FUNCTION(0x1, "gpio_out"),
141 SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
142 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
143 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
144 SUNXI_FUNCTION(0x0, "gpio_in"),
145 SUNXI_FUNCTION(0x1, "gpio_out"),
146 SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
147 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
148 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
149 SUNXI_FUNCTION(0x0, "gpio_in"),
150 SUNXI_FUNCTION(0x1, "gpio_out"),
151 SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
152 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
153 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
154 SUNXI_FUNCTION(0x0, "gpio_in"),
155 SUNXI_FUNCTION(0x1, "gpio_out"),
156 SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
157 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
158 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
159 SUNXI_FUNCTION(0x0, "gpio_in"),
160 SUNXI_FUNCTION(0x1, "gpio_out"),
161 SUNXI_FUNCTION(0x2, "nand"), /* DQ6 */
162 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
163 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
164 SUNXI_FUNCTION(0x0, "gpio_in"),
165 SUNXI_FUNCTION(0x1, "gpio_out"),
166 SUNXI_FUNCTION(0x2, "nand"), /* DQ7 */
167 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
168 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
169 SUNXI_FUNCTION(0x0, "gpio_in"),
170 SUNXI_FUNCTION(0x1, "gpio_out"),
171 SUNXI_FUNCTION(0x2, "nand"), /* DQS */
172 SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
173 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
174 SUNXI_FUNCTION(0x0, "gpio_in"),
175 SUNXI_FUNCTION(0x1, "gpio_out"),
176 SUNXI_FUNCTION(0x2, "nand")), /* CE2 */
177 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
178 SUNXI_FUNCTION(0x0, "gpio_in"),
179 SUNXI_FUNCTION(0x1, "gpio_out"),
180 SUNXI_FUNCTION(0x2, "nand")), /* CE3 */
181 /* Hole */
182 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
183 SUNXI_FUNCTION(0x0, "gpio_in"),
184 SUNXI_FUNCTION(0x1, "gpio_out"),
185 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
186 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD3 */
187 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
188 SUNXI_FUNCTION(0x0, "gpio_in"),
189 SUNXI_FUNCTION(0x1, "gpio_out"),
190 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
191 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD2 */
192 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
193 SUNXI_FUNCTION(0x0, "gpio_in"),
194 SUNXI_FUNCTION(0x1, "gpio_out"),
195 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
196 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD1 */
197 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
198 SUNXI_FUNCTION(0x0, "gpio_in"),
199 SUNXI_FUNCTION(0x1, "gpio_out"),
200 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
201 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD0 */
202 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
203 SUNXI_FUNCTION(0x0, "gpio_in"),
204 SUNXI_FUNCTION(0x1, "gpio_out"),
205 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
206 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXCK */
207 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
208 SUNXI_FUNCTION(0x0, "gpio_in"),
209 SUNXI_FUNCTION(0x1, "gpio_out"),
210 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
211 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXDV */
212 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
213 SUNXI_FUNCTION(0x0, "gpio_in"),
214 SUNXI_FUNCTION(0x1, "gpio_out"),
215 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
216 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXERR */
217 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
218 SUNXI_FUNCTION(0x0, "gpio_in"),
219 SUNXI_FUNCTION(0x1, "gpio_out"),
220 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
221 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII TXD3 */
222 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
223 SUNXI_FUNCTION(0x0, "gpio_in"),
224 SUNXI_FUNCTION(0x1, "gpio_out"),
225 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
226 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII TXD2 */
227 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
228 SUNXI_FUNCTION(0x0, "gpio_in"),
229 SUNXI_FUNCTION(0x1, "gpio_out"),
230 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
231 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII TXD1 */
232 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
233 SUNXI_FUNCTION(0x0, "gpio_in"),
234 SUNXI_FUNCTION(0x1, "gpio_out"),
235 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
236 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII TXD0 */
237 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
238 SUNXI_FUNCTION(0x0, "gpio_in"),
239 SUNXI_FUNCTION(0x1, "gpio_out"),
240 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
241 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII-NULL / MII-CRS */
242 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
243 SUNXI_FUNCTION(0x0, "gpio_in"),
244 SUNXI_FUNCTION(0x1, "gpio_out"),
245 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
246 SUNXI_FUNCTION(0x3, "lvds0"), /* VP0 */
247 SUNXI_FUNCTION(0x4, "gmac")), /* GTXCK / ETXCK */
248 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
249 SUNXI_FUNCTION(0x0, "gpio_in"),
250 SUNXI_FUNCTION(0x1, "gpio_out"),
251 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
252 SUNXI_FUNCTION(0x3, "lvds0"), /* VN0 */
253 SUNXI_FUNCTION(0x4, "gmac")), /* GTXCTL / ETXEL */
254 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
255 SUNXI_FUNCTION(0x0, "gpio_in"),
256 SUNXI_FUNCTION(0x1, "gpio_out"),
257 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
258 SUNXI_FUNCTION(0x3, "lvds0"), /* VP1 */
259 SUNXI_FUNCTION(0x4, "gmac")), /* GNULL / ETXERR */
260 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
261 SUNXI_FUNCTION(0x0, "gpio_in"),
262 SUNXI_FUNCTION(0x1, "gpio_out"),
263 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
264 SUNXI_FUNCTION(0x3, "lvds0"), /* VN1 */
265 SUNXI_FUNCTION(0x4, "gmac")), /* GCLKIN / ECOL */
266 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
267 SUNXI_FUNCTION(0x0, "gpio_in"),
268 SUNXI_FUNCTION(0x1, "gpio_out"),
269 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
270 SUNXI_FUNCTION(0x3, "lvds0"), /* VP2 */
271 SUNXI_FUNCTION(0x4, "gmac")), /* GMDC */
272 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
273 SUNXI_FUNCTION(0x0, "gpio_in"),
274 SUNXI_FUNCTION(0x1, "gpio_out"),
275 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
276 SUNXI_FUNCTION(0x3, "lvds0"), /* VN2 */
277 SUNXI_FUNCTION(0x4, "gmac")), /* GMDIO */
278 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
279 SUNXI_FUNCTION(0x0, "gpio_in"),
280 SUNXI_FUNCTION(0x1, "gpio_out"),
281 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
282 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
283 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
284 SUNXI_FUNCTION(0x0, "gpio_in"),
285 SUNXI_FUNCTION(0x1, "gpio_out"),
286 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
287 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
288 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
289 SUNXI_FUNCTION(0x0, "gpio_in"),
290 SUNXI_FUNCTION(0x1, "gpio_out"),
291 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
292 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
293 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
294 SUNXI_FUNCTION(0x0, "gpio_in"),
295 SUNXI_FUNCTION(0x1, "gpio_out"),
296 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
297 SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
298 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 28),
299 SUNXI_FUNCTION(0x0, "gpio_in"),
300 SUNXI_FUNCTION(0x1, "gpio_out"),
301 SUNXI_FUNCTION(0x2, "pwm")), /* PWM */
302 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 29),
303 SUNXI_FUNCTION(0x0, "gpio_in"),
304 SUNXI_FUNCTION(0x1, "gpio_out")),
305 /* Hole */
306 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
307 SUNXI_FUNCTION(0x0, "gpio_in"),
308 SUNXI_FUNCTION(0x1, "gpio_out"),
309 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
310 SUNXI_FUNCTION(0x4, "ccir")), /* CLK */
311 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
312 SUNXI_FUNCTION(0x0, "gpio_in"),
313 SUNXI_FUNCTION(0x1, "gpio_out"),
314 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
315 SUNXI_FUNCTION(0x4, "ccir")), /* DE */
316 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
317 SUNXI_FUNCTION(0x0, "gpio_in"),
318 SUNXI_FUNCTION(0x1, "gpio_out"),
319 SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
320 SUNXI_FUNCTION(0x4, "ccir")), /* HSYNC */
321 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
322 SUNXI_FUNCTION(0x0, "gpio_in"),
323 SUNXI_FUNCTION(0x1, "gpio_out"),
324 SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
325 SUNXI_FUNCTION(0x4, "ccir")), /* VSYNC */
326 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
327 SUNXI_FUNCTION(0x0, "gpio_in"),
328 SUNXI_FUNCTION(0x1, "gpio_out"),
329 SUNXI_FUNCTION(0x2, "csi")), /* D0 */
330 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
331 SUNXI_FUNCTION(0x0, "gpio_in"),
332 SUNXI_FUNCTION(0x1, "gpio_out"),
333 SUNXI_FUNCTION(0x2, "csi")), /* D1 */
334 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
335 SUNXI_FUNCTION(0x0, "gpio_in"),
336 SUNXI_FUNCTION(0x1, "gpio_out"),
337 SUNXI_FUNCTION(0x2, "csi"), /* D2 */
338 SUNXI_FUNCTION(0x4, "ccir")), /* D0 */
339 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
340 SUNXI_FUNCTION(0x0, "gpio_in"),
341 SUNXI_FUNCTION(0x1, "gpio_out"),
342 SUNXI_FUNCTION(0x2, "csi"), /* D3 */
343 SUNXI_FUNCTION(0x4, "ccir")), /* D1 */
344 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
345 SUNXI_FUNCTION(0x0, "gpio_in"),
346 SUNXI_FUNCTION(0x1, "gpio_out"),
347 SUNXI_FUNCTION(0x2, "csi"), /* D4 */
348 SUNXI_FUNCTION(0x4, "ccir")), /* D2 */
349 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
350 SUNXI_FUNCTION(0x0, "gpio_in"),
351 SUNXI_FUNCTION(0x1, "gpio_out"),
352 SUNXI_FUNCTION(0x2, "csi"), /* D5 */
353 SUNXI_FUNCTION(0x4, "ccir")), /* D3 */
354 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
355 SUNXI_FUNCTION(0x0, "gpio_in"),
356 SUNXI_FUNCTION(0x1, "gpio_out"),
357 SUNXI_FUNCTION(0x2, "csi"), /* D6 */
358 SUNXI_FUNCTION(0x3, "uart4"), /* TX */
359 SUNXI_FUNCTION(0x4, "ccir")), /* D4 */
360 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
361 SUNXI_FUNCTION(0x0, "gpio_in"),
362 SUNXI_FUNCTION(0x1, "gpio_out"),
363 SUNXI_FUNCTION(0x2, "csi"), /* D7 */
364 SUNXI_FUNCTION(0x3, "uart4"), /* RX */
365 SUNXI_FUNCTION(0x4, "ccir")), /* D5 */
366 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
367 SUNXI_FUNCTION(0x0, "gpio_in"),
368 SUNXI_FUNCTION(0x1, "gpio_out"),
369 SUNXI_FUNCTION(0x2, "csi"), /* D8 */
370 SUNXI_FUNCTION(0x3, "uart4"), /* RTS */
371 SUNXI_FUNCTION(0x4, "ccir")), /* D6 */
372 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
373 SUNXI_FUNCTION(0x0, "gpio_in"),
374 SUNXI_FUNCTION(0x1, "gpio_out"),
375 SUNXI_FUNCTION(0x2, "csi"), /* D9 */
376 SUNXI_FUNCTION(0x3, "uart4"), /* CTS */
377 SUNXI_FUNCTION(0x4, "ccir")), /* D7 */
378 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
379 SUNXI_FUNCTION(0x0, "gpio_in"),
380 SUNXI_FUNCTION(0x1, "gpio_out"),
381 SUNXI_FUNCTION(0x2, "csi"), /* SCK */
382 SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */
383 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
384 SUNXI_FUNCTION(0x0, "gpio_in"),
385 SUNXI_FUNCTION(0x1, "gpio_out"),
386 SUNXI_FUNCTION(0x2, "csi"), /* SDA */
387 SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */
388 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
389 SUNXI_FUNCTION(0x0, "gpio_in"),
390 SUNXI_FUNCTION(0x1, "gpio_out")),
391 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
392 SUNXI_FUNCTION(0x0, "gpio_in"),
393 SUNXI_FUNCTION(0x1, "gpio_out")),
394 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 18),
395 SUNXI_FUNCTION(0x0, "gpio_in"),
396 SUNXI_FUNCTION(0x1, "gpio_out"),
397 SUNXI_FUNCTION(0x3, "owa")), /* DOUT */
398 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 19),
399 SUNXI_FUNCTION(0x0, "gpio_in"),
400 SUNXI_FUNCTION(0x1, "gpio_out")),
401 /* Hole */
402 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
403 SUNXI_FUNCTION(0x0, "gpio_in"),
404 SUNXI_FUNCTION(0x1, "gpio_out"),
405 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
406 SUNXI_FUNCTION(0x3, "jtag")), /* MS1 */
407 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
408 SUNXI_FUNCTION(0x0, "gpio_in"),
409 SUNXI_FUNCTION(0x1, "gpio_out"),
410 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
411 SUNXI_FUNCTION(0x3, "jtag")), /* DI1 */
412 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
413 SUNXI_FUNCTION(0x0, "gpio_in"),
414 SUNXI_FUNCTION(0x1, "gpio_out"),
415 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
416 SUNXI_FUNCTION(0x3, "uart0")), /* TX */
417 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
418 SUNXI_FUNCTION(0x0, "gpio_in"),
419 SUNXI_FUNCTION(0x1, "gpio_out"),
420 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
421 SUNXI_FUNCTION(0x3, "jtag")), /* DO1 */
422 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
423 SUNXI_FUNCTION(0x0, "gpio_in"),
424 SUNXI_FUNCTION(0x1, "gpio_out"),
425 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
426 SUNXI_FUNCTION(0x3, "uart0")), /* RX */
427 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
428 SUNXI_FUNCTION(0x0, "gpio_in"),
429 SUNXI_FUNCTION(0x1, "gpio_out"),
430 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
431 SUNXI_FUNCTION(0x3, "jtag")), /* CK1 */
432 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
433 SUNXI_FUNCTION(0x0, "gpio_in"),
434 SUNXI_FUNCTION(0x1, "gpio_out")),
435 /* Hole */
436 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
437 SUNXI_FUNCTION(0x0, "gpio_in"),
438 SUNXI_FUNCTION(0x1, "gpio_out"),
439 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
440 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PG_EINT0 */
441 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
442 SUNXI_FUNCTION(0x0, "gpio_in"),
443 SUNXI_FUNCTION(0x1, "gpio_out"),
444 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
445 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PG_EINT1 */
446 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
447 SUNXI_FUNCTION(0x0, "gpio_in"),
448 SUNXI_FUNCTION(0x1, "gpio_out"),
449 SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
450 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PG_EINT2 */
451 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
452 SUNXI_FUNCTION(0x0, "gpio_in"),
453 SUNXI_FUNCTION(0x1, "gpio_out"),
454 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
455 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PG_EINT3 */
456 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
457 SUNXI_FUNCTION(0x0, "gpio_in"),
458 SUNXI_FUNCTION(0x1, "gpio_out"),
459 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
460 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PG_EINT4 */
461 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
462 SUNXI_FUNCTION(0x0, "gpio_in"),
463 SUNXI_FUNCTION(0x1, "gpio_out"),
464 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
465 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PG_EINT5 */
466 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
467 SUNXI_FUNCTION(0x0, "gpio_in"),
468 SUNXI_FUNCTION(0x1, "gpio_out"),
469 SUNXI_FUNCTION(0x2, "uart1"), /* TX */
470 SUNXI_FUNCTION(0x3, "spi1"), /* CS */
471 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PG_EINT6 */
472 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
473 SUNXI_FUNCTION(0x0, "gpio_in"),
474 SUNXI_FUNCTION(0x1, "gpio_out"),
475 SUNXI_FUNCTION(0x2, "uart1"), /* RX */
476 SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
477 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PG_EINT7 */
478 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
479 SUNXI_FUNCTION(0x0, "gpio_in"),
480 SUNXI_FUNCTION(0x1, "gpio_out"),
481 SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
482 SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
483 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* PG_EINT8 */
484 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
485 SUNXI_FUNCTION(0x0, "gpio_in"),
486 SUNXI_FUNCTION(0x1, "gpio_out"),
487 SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
488 SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
489 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* PG_EINT9 */
490 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
491 SUNXI_FUNCTION(0x0, "gpio_in"),
492 SUNXI_FUNCTION(0x1, "gpio_out"),
493 SUNXI_FUNCTION(0x2, "i2s1"), /* BCLK */
494 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
495 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* PG_EINT10 */
496 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
497 SUNXI_FUNCTION(0x0, "gpio_in"),
498 SUNXI_FUNCTION(0x1, "gpio_out"),
499 SUNXI_FUNCTION(0x2, "i2s1"), /* LRCK */
500 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
501 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* PG_EINT11 */
502 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
503 SUNXI_FUNCTION(0x0, "gpio_in"),
504 SUNXI_FUNCTION(0x1, "gpio_out"),
505 SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */
506 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
507 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* PG_EINT12 */
508 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
509 SUNXI_FUNCTION(0x0, "gpio_in"),
510 SUNXI_FUNCTION(0x1, "gpio_out"),
511 SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */
512 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
513 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* PG_EINT13 */
514 /* Hole */
515 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
516 SUNXI_FUNCTION(0x0, "gpio_in"),
517 SUNXI_FUNCTION(0x1, "gpio_out"),
518 SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
519 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PH_EINT0 */
520 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
521 SUNXI_FUNCTION(0x0, "gpio_in"),
522 SUNXI_FUNCTION(0x1, "gpio_out"),
523 SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
524 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PH_EINT1 */
525 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
526 SUNXI_FUNCTION(0x0, "gpio_in"),
527 SUNXI_FUNCTION(0x1, "gpio_out"),
528 SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
529 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PH_EINT2 */
530 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
531 SUNXI_FUNCTION(0x0, "gpio_in"),
532 SUNXI_FUNCTION(0x1, "gpio_out"),
533 SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */
534 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PH_EINT3 */
535 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
536 SUNXI_FUNCTION(0x0, "gpio_in"),
537 SUNXI_FUNCTION(0x1, "gpio_out"),
538 SUNXI_FUNCTION(0x2, "i2c2"), /* SCK */
539 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PH_EINT4 */
540 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
541 SUNXI_FUNCTION(0x0, "gpio_in"),
542 SUNXI_FUNCTION(0x1, "gpio_out"),
543 SUNXI_FUNCTION(0x2, "i2c2"), /* SDA */
544 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PH_EINT5 */
545 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
546 SUNXI_FUNCTION(0x0, "gpio_in"),
547 SUNXI_FUNCTION(0x1, "gpio_out"),
548 SUNXI_FUNCTION(0x2, "hdmi"), /* HSCL */
549 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PH_EINT6 */
550 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
551 SUNXI_FUNCTION(0x0, "gpio_in"),
552 SUNXI_FUNCTION(0x1, "gpio_out"),
553 SUNXI_FUNCTION(0x2, "hdmi"), /* HSDA */
554 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PH_EINT7 */
555 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
556 SUNXI_FUNCTION(0x0, "gpio_in"),
557 SUNXI_FUNCTION(0x1, "gpio_out"),
558 SUNXI_FUNCTION(0x2, "hdmi"), /* HCEC */
559 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PH_EINT8 */
560 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
561 SUNXI_FUNCTION(0x0, "gpio_in"),
562 SUNXI_FUNCTION(0x1, "gpio_out"),
563 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PH_EINT9 */
564 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
565 SUNXI_FUNCTION(0x0, "gpio_in"),
566 SUNXI_FUNCTION(0x1, "gpio_out"),
567 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PH_EINT10 */
568 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
569 SUNXI_FUNCTION(0x0, "gpio_in"),
570 SUNXI_FUNCTION(0x1, "gpio_out"),
571 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PH_EINT11 */
572};
573
574static const struct sunxi_pinctrl_desc sun8i_a83t_pinctrl_data = {
575 .pins = sun8i_a83t_pins,
576 .npins = ARRAY_SIZE(sun8i_a83t_pins),
577 .irq_banks = 3,
578};
579
580static int sun8i_a83t_pinctrl_probe(struct platform_device *pdev)
581{
582 return sunxi_pinctrl_init(pdev,
583 &sun8i_a83t_pinctrl_data);
584}
585
586static const struct of_device_id sun8i_a83t_pinctrl_match[] = {
587 { .compatible = "allwinner,sun8i-a83t-pinctrl", },
588 {}
589};
590MODULE_DEVICE_TABLE(of, sun8i_a83t_pinctrl_match);
591
592static struct platform_driver sun8i_a83t_pinctrl_driver = {
593 .probe = sun8i_a83t_pinctrl_probe,
594 .driver = {
595 .name = "sun8i-a83t-pinctrl",
596 .of_match_table = sun8i_a83t_pinctrl_match,
597 },
598};
599module_platform_driver(sun8i_a83t_pinctrl_driver);
600
601MODULE_AUTHOR("Vishnu Patekar <vishnupatekar0510@gmail.com>");
602MODULE_DESCRIPTION("Allwinner a83t pinctrl driver");
603MODULE_LICENSE("GPL");