Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-integrator/integrator_cp.c |
| 3 | * |
| 4 | * Copyright (C) 2003 Deep Blue Solutions Ltd |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License. |
| 9 | */ |
| 10 | #include <linux/types.h> |
| 11 | #include <linux/kernel.h> |
| 12 | #include <linux/init.h> |
| 13 | #include <linux/list.h> |
Russell King | d052d1b | 2005-10-29 19:07:23 +0100 | [diff] [blame] | 14 | #include <linux/platform_device.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15 | #include <linux/dma-mapping.h> |
| 16 | #include <linux/slab.h> |
| 17 | #include <linux/string.h> |
| 18 | #include <linux/sysdev.h> |
Russell King | a62c80e | 2006-01-07 13:52:45 +0000 | [diff] [blame] | 19 | #include <linux/amba/bus.h> |
| 20 | #include <linux/amba/kmi.h> |
| 21 | #include <linux/amba/clcd.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 22 | |
| 23 | #include <asm/hardware.h> |
| 24 | #include <asm/io.h> |
| 25 | #include <asm/irq.h> |
| 26 | #include <asm/setup.h> |
| 27 | #include <asm/mach-types.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | #include <asm/hardware/icst525.h> |
| 29 | |
| 30 | #include <asm/arch/cm.h> |
| 31 | #include <asm/arch/lm.h> |
| 32 | |
| 33 | #include <asm/mach/arch.h> |
| 34 | #include <asm/mach/flash.h> |
| 35 | #include <asm/mach/irq.h> |
| 36 | #include <asm/mach/mmc.h> |
| 37 | #include <asm/mach/map.h> |
| 38 | #include <asm/mach/time.h> |
| 39 | |
| 40 | #include "common.h" |
| 41 | #include "clock.h" |
| 42 | |
| 43 | #define INTCP_PA_MMC_BASE 0x1c000000 |
| 44 | #define INTCP_PA_AACI_BASE 0x1d000000 |
| 45 | |
| 46 | #define INTCP_PA_FLASH_BASE 0x24000000 |
| 47 | #define INTCP_FLASH_SIZE SZ_32M |
| 48 | |
| 49 | #define INTCP_PA_CLCD_BASE 0xc0000000 |
| 50 | |
| 51 | #define INTCP_VA_CIC_BASE 0xf1000040 |
| 52 | #define INTCP_VA_PIC_BASE 0xf1400000 |
| 53 | #define INTCP_VA_SIC_BASE 0xfca00000 |
| 54 | |
| 55 | #define INTCP_PA_ETH_BASE 0xc8000000 |
| 56 | #define INTCP_ETH_SIZE 0x10 |
| 57 | |
| 58 | #define INTCP_VA_CTRL_BASE 0xfcb00000 |
| 59 | #define INTCP_FLASHPROG 0x04 |
| 60 | #define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0) |
| 61 | #define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1) |
| 62 | |
| 63 | /* |
| 64 | * Logical Physical |
| 65 | * f1000000 10000000 Core module registers |
| 66 | * f1100000 11000000 System controller registers |
| 67 | * f1200000 12000000 EBI registers |
| 68 | * f1300000 13000000 Counter/Timer |
| 69 | * f1400000 14000000 Interrupt controller |
| 70 | * f1600000 16000000 UART 0 |
| 71 | * f1700000 17000000 UART 1 |
| 72 | * f1a00000 1a000000 Debug LEDs |
| 73 | * f1b00000 1b000000 GPIO |
| 74 | */ |
| 75 | |
| 76 | static struct map_desc intcp_io_desc[] __initdata = { |
Deepak Saxena | c8d2729 | 2005-10-28 15:19:10 +0100 | [diff] [blame] | 77 | { |
| 78 | .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE), |
| 79 | .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE), |
| 80 | .length = SZ_4K, |
| 81 | .type = MT_DEVICE |
| 82 | }, { |
| 83 | .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE), |
| 84 | .pfn = __phys_to_pfn(INTEGRATOR_SC_BASE), |
| 85 | .length = SZ_4K, |
| 86 | .type = MT_DEVICE |
| 87 | }, { |
| 88 | .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE), |
| 89 | .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE), |
| 90 | .length = SZ_4K, |
| 91 | .type = MT_DEVICE |
| 92 | }, { |
| 93 | .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE), |
| 94 | .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE), |
| 95 | .length = SZ_4K, |
| 96 | .type = MT_DEVICE |
| 97 | }, { |
| 98 | .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE), |
| 99 | .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE), |
| 100 | .length = SZ_4K, |
| 101 | .type = MT_DEVICE |
| 102 | }, { |
| 103 | .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE), |
| 104 | .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE), |
| 105 | .length = SZ_4K, |
| 106 | .type = MT_DEVICE |
| 107 | }, { |
| 108 | .virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE), |
| 109 | .pfn = __phys_to_pfn(INTEGRATOR_UART1_BASE), |
| 110 | .length = SZ_4K, |
| 111 | .type = MT_DEVICE |
| 112 | }, { |
| 113 | .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE), |
| 114 | .pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE), |
| 115 | .length = SZ_4K, |
| 116 | .type = MT_DEVICE |
| 117 | }, { |
| 118 | .virtual = IO_ADDRESS(INTEGRATOR_GPIO_BASE), |
| 119 | .pfn = __phys_to_pfn(INTEGRATOR_GPIO_BASE), |
| 120 | .length = SZ_4K, |
| 121 | .type = MT_DEVICE |
| 122 | }, { |
| 123 | .virtual = 0xfca00000, |
| 124 | .pfn = __phys_to_pfn(0xca000000), |
| 125 | .length = SZ_4K, |
| 126 | .type = MT_DEVICE |
| 127 | }, { |
| 128 | .virtual = 0xfcb00000, |
| 129 | .pfn = __phys_to_pfn(0xcb000000), |
| 130 | .length = SZ_4K, |
| 131 | .type = MT_DEVICE |
| 132 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 133 | }; |
| 134 | |
| 135 | static void __init intcp_map_io(void) |
| 136 | { |
| 137 | iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc)); |
| 138 | } |
| 139 | |
| 140 | #define cic_writel __raw_writel |
| 141 | #define cic_readl __raw_readl |
| 142 | #define pic_writel __raw_writel |
| 143 | #define pic_readl __raw_readl |
| 144 | #define sic_writel __raw_writel |
| 145 | #define sic_readl __raw_readl |
| 146 | |
| 147 | static void cic_mask_irq(unsigned int irq) |
| 148 | { |
| 149 | irq -= IRQ_CIC_START; |
| 150 | cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR); |
| 151 | } |
| 152 | |
| 153 | static void cic_unmask_irq(unsigned int irq) |
| 154 | { |
| 155 | irq -= IRQ_CIC_START; |
| 156 | cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_SET); |
| 157 | } |
| 158 | |
| 159 | static struct irqchip cic_chip = { |
| 160 | .ack = cic_mask_irq, |
| 161 | .mask = cic_mask_irq, |
| 162 | .unmask = cic_unmask_irq, |
| 163 | }; |
| 164 | |
| 165 | static void pic_mask_irq(unsigned int irq) |
| 166 | { |
| 167 | irq -= IRQ_PIC_START; |
| 168 | pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR); |
| 169 | } |
| 170 | |
| 171 | static void pic_unmask_irq(unsigned int irq) |
| 172 | { |
| 173 | irq -= IRQ_PIC_START; |
| 174 | pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_SET); |
| 175 | } |
| 176 | |
| 177 | static struct irqchip pic_chip = { |
| 178 | .ack = pic_mask_irq, |
| 179 | .mask = pic_mask_irq, |
| 180 | .unmask = pic_unmask_irq, |
| 181 | }; |
| 182 | |
| 183 | static void sic_mask_irq(unsigned int irq) |
| 184 | { |
| 185 | irq -= IRQ_SIC_START; |
| 186 | sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR); |
| 187 | } |
| 188 | |
| 189 | static void sic_unmask_irq(unsigned int irq) |
| 190 | { |
| 191 | irq -= IRQ_SIC_START; |
| 192 | sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_SET); |
| 193 | } |
| 194 | |
| 195 | static struct irqchip sic_chip = { |
| 196 | .ack = sic_mask_irq, |
| 197 | .mask = sic_mask_irq, |
| 198 | .unmask = sic_unmask_irq, |
| 199 | }; |
| 200 | |
| 201 | static void |
| 202 | sic_handle_irq(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs) |
| 203 | { |
| 204 | unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS); |
| 205 | |
| 206 | if (status == 0) { |
| 207 | do_bad_IRQ(irq, desc, regs); |
| 208 | return; |
| 209 | } |
| 210 | |
| 211 | do { |
| 212 | irq = ffs(status) - 1; |
| 213 | status &= ~(1 << irq); |
| 214 | |
| 215 | irq += IRQ_SIC_START; |
| 216 | |
| 217 | desc = irq_desc + irq; |
Russell King | 664399e | 2005-09-04 19:45:00 +0100 | [diff] [blame] | 218 | desc_handle_irq(irq, desc, regs); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 219 | } while (status); |
| 220 | } |
| 221 | |
| 222 | static void __init intcp_init_irq(void) |
| 223 | { |
| 224 | unsigned int i; |
| 225 | |
| 226 | /* |
| 227 | * Disable all interrupt sources |
| 228 | */ |
| 229 | pic_writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR); |
| 230 | pic_writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR); |
| 231 | |
| 232 | for (i = IRQ_PIC_START; i <= IRQ_PIC_END; i++) { |
| 233 | if (i == 11) |
| 234 | i = 22; |
| 235 | if (i == IRQ_CP_CPPLDINT) |
| 236 | i++; |
| 237 | if (i == 29) |
| 238 | break; |
| 239 | set_irq_chip(i, &pic_chip); |
| 240 | set_irq_handler(i, do_level_IRQ); |
| 241 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
| 242 | } |
| 243 | |
| 244 | cic_writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR); |
| 245 | cic_writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR); |
| 246 | |
| 247 | for (i = IRQ_CIC_START; i <= IRQ_CIC_END; i++) { |
| 248 | set_irq_chip(i, &cic_chip); |
| 249 | set_irq_handler(i, do_level_IRQ); |
| 250 | set_irq_flags(i, IRQF_VALID); |
| 251 | } |
| 252 | |
| 253 | sic_writel(0x00000fff, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR); |
| 254 | sic_writel(0x00000fff, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR); |
| 255 | |
| 256 | for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) { |
| 257 | set_irq_chip(i, &sic_chip); |
| 258 | set_irq_handler(i, do_level_IRQ); |
| 259 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
| 260 | } |
| 261 | |
| 262 | set_irq_handler(IRQ_CP_CPPLDINT, sic_handle_irq); |
| 263 | pic_unmask_irq(IRQ_CP_CPPLDINT); |
| 264 | } |
| 265 | |
| 266 | /* |
| 267 | * Clock handling |
| 268 | */ |
| 269 | #define CM_LOCK (IO_ADDRESS(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET) |
| 270 | #define CM_AUXOSC (IO_ADDRESS(INTEGRATOR_HDR_BASE)+0x1c) |
| 271 | |
| 272 | static const struct icst525_params cp_auxvco_params = { |
| 273 | .ref = 24000, |
| 274 | .vco_max = 320000, |
| 275 | .vd_min = 8, |
| 276 | .vd_max = 263, |
| 277 | .rd_min = 3, |
| 278 | .rd_max = 65, |
| 279 | }; |
| 280 | |
| 281 | static void cp_auxvco_set(struct clk *clk, struct icst525_vco vco) |
| 282 | { |
| 283 | u32 val; |
| 284 | |
| 285 | val = readl(CM_AUXOSC) & ~0x7ffff; |
| 286 | val |= vco.v | (vco.r << 9) | (vco.s << 16); |
| 287 | |
| 288 | writel(0xa05f, CM_LOCK); |
| 289 | writel(val, CM_AUXOSC); |
| 290 | writel(0, CM_LOCK); |
| 291 | } |
| 292 | |
| 293 | static struct clk cp_clcd_clk = { |
| 294 | .name = "CLCDCLK", |
| 295 | .params = &cp_auxvco_params, |
| 296 | .setvco = cp_auxvco_set, |
| 297 | }; |
| 298 | |
| 299 | static struct clk cp_mmci_clk = { |
| 300 | .name = "MCLK", |
| 301 | .rate = 14745600, |
| 302 | }; |
| 303 | |
| 304 | /* |
| 305 | * Flash handling. |
| 306 | */ |
| 307 | static int intcp_flash_init(void) |
| 308 | { |
| 309 | u32 val; |
| 310 | |
| 311 | val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG); |
| 312 | val |= CINTEGRATOR_FLASHPROG_FLWREN; |
| 313 | writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG); |
| 314 | |
| 315 | return 0; |
| 316 | } |
| 317 | |
| 318 | static void intcp_flash_exit(void) |
| 319 | { |
| 320 | u32 val; |
| 321 | |
| 322 | val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG); |
| 323 | val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN); |
| 324 | writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG); |
| 325 | } |
| 326 | |
| 327 | static void intcp_flash_set_vpp(int on) |
| 328 | { |
| 329 | u32 val; |
| 330 | |
| 331 | val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG); |
| 332 | if (on) |
| 333 | val |= CINTEGRATOR_FLASHPROG_FLVPPEN; |
| 334 | else |
| 335 | val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN; |
| 336 | writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG); |
| 337 | } |
| 338 | |
| 339 | static struct flash_platform_data intcp_flash_data = { |
| 340 | .map_name = "cfi_probe", |
| 341 | .width = 4, |
| 342 | .init = intcp_flash_init, |
| 343 | .exit = intcp_flash_exit, |
| 344 | .set_vpp = intcp_flash_set_vpp, |
| 345 | }; |
| 346 | |
| 347 | static struct resource intcp_flash_resource = { |
| 348 | .start = INTCP_PA_FLASH_BASE, |
| 349 | .end = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1, |
| 350 | .flags = IORESOURCE_MEM, |
| 351 | }; |
| 352 | |
| 353 | static struct platform_device intcp_flash_device = { |
| 354 | .name = "armflash", |
| 355 | .id = 0, |
| 356 | .dev = { |
| 357 | .platform_data = &intcp_flash_data, |
| 358 | }, |
| 359 | .num_resources = 1, |
| 360 | .resource = &intcp_flash_resource, |
| 361 | }; |
| 362 | |
| 363 | static struct resource smc91x_resources[] = { |
| 364 | [0] = { |
| 365 | .start = INTCP_PA_ETH_BASE, |
| 366 | .end = INTCP_PA_ETH_BASE + INTCP_ETH_SIZE - 1, |
| 367 | .flags = IORESOURCE_MEM, |
| 368 | }, |
| 369 | [1] = { |
| 370 | .start = IRQ_CP_ETHINT, |
| 371 | .end = IRQ_CP_ETHINT, |
| 372 | .flags = IORESOURCE_IRQ, |
| 373 | }, |
| 374 | }; |
| 375 | |
| 376 | static struct platform_device smc91x_device = { |
| 377 | .name = "smc91x", |
| 378 | .id = 0, |
| 379 | .num_resources = ARRAY_SIZE(smc91x_resources), |
| 380 | .resource = smc91x_resources, |
| 381 | }; |
| 382 | |
| 383 | static struct platform_device *intcp_devs[] __initdata = { |
| 384 | &intcp_flash_device, |
| 385 | &smc91x_device, |
| 386 | }; |
| 387 | |
| 388 | /* |
| 389 | * It seems that the card insertion interrupt remains active after |
| 390 | * we've acknowledged it. We therefore ignore the interrupt, and |
| 391 | * rely on reading it from the SIC. This also means that we must |
| 392 | * clear the latched interrupt. |
| 393 | */ |
| 394 | static unsigned int mmc_status(struct device *dev) |
| 395 | { |
| 396 | unsigned int status = readl(0xfca00004); |
| 397 | writel(8, 0xfcb00008); |
| 398 | |
| 399 | return status & 8; |
| 400 | } |
| 401 | |
| 402 | static struct mmc_platform_data mmc_data = { |
| 403 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, |
| 404 | .status = mmc_status, |
| 405 | }; |
| 406 | |
| 407 | static struct amba_device mmc_device = { |
| 408 | .dev = { |
| 409 | .bus_id = "mb:1c", |
| 410 | .platform_data = &mmc_data, |
| 411 | }, |
| 412 | .res = { |
| 413 | .start = INTCP_PA_MMC_BASE, |
| 414 | .end = INTCP_PA_MMC_BASE + SZ_4K - 1, |
| 415 | .flags = IORESOURCE_MEM, |
| 416 | }, |
| 417 | .irq = { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }, |
| 418 | .periphid = 0, |
| 419 | }; |
| 420 | |
| 421 | static struct amba_device aaci_device = { |
| 422 | .dev = { |
| 423 | .bus_id = "mb:1d", |
| 424 | }, |
| 425 | .res = { |
| 426 | .start = INTCP_PA_AACI_BASE, |
| 427 | .end = INTCP_PA_AACI_BASE + SZ_4K - 1, |
| 428 | .flags = IORESOURCE_MEM, |
| 429 | }, |
| 430 | .irq = { IRQ_CP_AACIINT, NO_IRQ }, |
| 431 | .periphid = 0, |
| 432 | }; |
| 433 | |
| 434 | |
| 435 | /* |
| 436 | * CLCD support |
| 437 | */ |
| 438 | static struct clcd_panel vga = { |
| 439 | .mode = { |
| 440 | .name = "VGA", |
| 441 | .refresh = 60, |
| 442 | .xres = 640, |
| 443 | .yres = 480, |
| 444 | .pixclock = 39721, |
| 445 | .left_margin = 40, |
| 446 | .right_margin = 24, |
| 447 | .upper_margin = 32, |
| 448 | .lower_margin = 11, |
| 449 | .hsync_len = 96, |
| 450 | .vsync_len = 2, |
| 451 | .sync = 0, |
| 452 | .vmode = FB_VMODE_NONINTERLACED, |
| 453 | }, |
| 454 | .width = -1, |
| 455 | .height = -1, |
| 456 | .tim2 = TIM2_BCD | TIM2_IPC, |
| 457 | .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1), |
| 458 | .bpp = 16, |
| 459 | .grayscale = 0, |
| 460 | }; |
| 461 | |
| 462 | /* |
| 463 | * Ensure VGA is selected. |
| 464 | */ |
| 465 | static void cp_clcd_enable(struct clcd_fb *fb) |
| 466 | { |
Russell King | 4774e22 | 2005-04-30 23:32:38 +0100 | [diff] [blame] | 467 | u32 val; |
| 468 | |
| 469 | if (fb->fb.var.bits_per_pixel <= 8) |
| 470 | val = CM_CTRL_LCDMUXSEL_VGA_8421BPP; |
| 471 | else if (fb->fb.var.bits_per_pixel <= 16) |
Catalin Marinas | 14e54cc | 2006-01-28 20:54:50 +0000 | [diff] [blame^] | 472 | val = CM_CTRL_LCDMUXSEL_VGA_16BPP |
| 473 | | CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1 |
| 474 | | CM_CTRL_STATIC1 | CM_CTRL_STATIC2; |
Russell King | 4774e22 | 2005-04-30 23:32:38 +0100 | [diff] [blame] | 475 | else |
| 476 | val = 0; /* no idea for this, don't trust the docs */ |
| 477 | |
| 478 | cm_control(CM_CTRL_LCDMUXSEL_MASK| |
| 479 | CM_CTRL_LCDEN0| |
| 480 | CM_CTRL_LCDEN1| |
| 481 | CM_CTRL_STATIC1| |
| 482 | CM_CTRL_STATIC2| |
| 483 | CM_CTRL_STATIC| |
| 484 | CM_CTRL_n24BITEN, val); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 485 | } |
| 486 | |
| 487 | static unsigned long framesize = SZ_1M; |
| 488 | |
| 489 | static int cp_clcd_setup(struct clcd_fb *fb) |
| 490 | { |
| 491 | dma_addr_t dma; |
| 492 | |
| 493 | fb->panel = &vga; |
| 494 | |
| 495 | fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize, |
| 496 | &dma, GFP_KERNEL); |
| 497 | if (!fb->fb.screen_base) { |
| 498 | printk(KERN_ERR "CLCD: unable to map framebuffer\n"); |
| 499 | return -ENOMEM; |
| 500 | } |
| 501 | |
| 502 | fb->fb.fix.smem_start = dma; |
| 503 | fb->fb.fix.smem_len = framesize; |
| 504 | |
| 505 | return 0; |
| 506 | } |
| 507 | |
| 508 | static int cp_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma) |
| 509 | { |
| 510 | return dma_mmap_writecombine(&fb->dev->dev, vma, |
| 511 | fb->fb.screen_base, |
| 512 | fb->fb.fix.smem_start, |
| 513 | fb->fb.fix.smem_len); |
| 514 | } |
| 515 | |
| 516 | static void cp_clcd_remove(struct clcd_fb *fb) |
| 517 | { |
| 518 | dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len, |
| 519 | fb->fb.screen_base, fb->fb.fix.smem_start); |
| 520 | } |
| 521 | |
| 522 | static struct clcd_board clcd_data = { |
| 523 | .name = "Integrator/CP", |
| 524 | .check = clcdfb_check, |
| 525 | .decode = clcdfb_decode, |
| 526 | .enable = cp_clcd_enable, |
| 527 | .setup = cp_clcd_setup, |
| 528 | .mmap = cp_clcd_mmap, |
| 529 | .remove = cp_clcd_remove, |
| 530 | }; |
| 531 | |
| 532 | static struct amba_device clcd_device = { |
| 533 | .dev = { |
| 534 | .bus_id = "mb:c0", |
| 535 | .coherent_dma_mask = ~0, |
| 536 | .platform_data = &clcd_data, |
| 537 | }, |
| 538 | .res = { |
| 539 | .start = INTCP_PA_CLCD_BASE, |
| 540 | .end = INTCP_PA_CLCD_BASE + SZ_4K - 1, |
| 541 | .flags = IORESOURCE_MEM, |
| 542 | }, |
| 543 | .dma_mask = ~0, |
| 544 | .irq = { IRQ_CP_CLCDCINT, NO_IRQ }, |
| 545 | .periphid = 0, |
| 546 | }; |
| 547 | |
| 548 | static struct amba_device *amba_devs[] __initdata = { |
| 549 | &mmc_device, |
| 550 | &aaci_device, |
| 551 | &clcd_device, |
| 552 | }; |
| 553 | |
| 554 | static void __init intcp_init(void) |
| 555 | { |
| 556 | int i; |
| 557 | |
| 558 | clk_register(&cp_clcd_clk); |
| 559 | clk_register(&cp_mmci_clk); |
| 560 | |
| 561 | platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs)); |
| 562 | |
| 563 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { |
| 564 | struct amba_device *d = amba_devs[i]; |
| 565 | amba_device_register(d, &iomem_resource); |
| 566 | } |
| 567 | } |
| 568 | |
| 569 | #define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable */ |
| 570 | |
| 571 | static void __init intcp_timer_init(void) |
| 572 | { |
| 573 | integrator_time_init(1000000 / HZ, TIMER_CTRL_IE); |
| 574 | } |
| 575 | |
| 576 | static struct sys_timer cp_timer = { |
| 577 | .init = intcp_timer_init, |
| 578 | .offset = integrator_gettimeoffset, |
| 579 | }; |
| 580 | |
| 581 | MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP") |
Russell King | e9dea0c | 2005-07-03 17:38:58 +0100 | [diff] [blame] | 582 | /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ |
Russell King | e9dea0c | 2005-07-03 17:38:58 +0100 | [diff] [blame] | 583 | .phys_io = 0x16000000, |
| 584 | .io_pg_offst = ((0xf1600000) >> 18) & 0xfffc, |
| 585 | .boot_params = 0x00000100, |
| 586 | .map_io = intcp_map_io, |
| 587 | .init_irq = intcp_init_irq, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 588 | .timer = &cp_timer, |
Russell King | e9dea0c | 2005-07-03 17:38:58 +0100 | [diff] [blame] | 589 | .init_machine = intcp_init, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 590 | MACHINE_END |