Beniamino Galvani | 6ac7309 | 2015-01-17 19:15:14 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Pin controller and GPIO driver for Amlogic Meson SoCs |
| 3 | * |
| 4 | * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * version 2 as published by the Free Software Foundation. |
| 9 | * |
| 10 | * You should have received a copy of the GNU General Public License |
| 11 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 12 | */ |
| 13 | |
| 14 | /* |
| 15 | * The available pins are organized in banks (A,B,C,D,E,X,Y,Z,AO, |
Carlo Caione | faa246d | 2015-03-19 22:34:11 +0100 | [diff] [blame] | 16 | * BOOT,CARD for meson6, X,Y,DV,H,Z,AO,BOOT,CARD for meson8 and |
| 17 | * X,Y,DV,H,AO,BOOT,CARD,DIF for meson8b) and each bank has a |
| 18 | * variable number of pins. |
Beniamino Galvani | 6ac7309 | 2015-01-17 19:15:14 +0100 | [diff] [blame] | 19 | * |
| 20 | * The AO bank is special because it belongs to the Always-On power |
| 21 | * domain which can't be powered off; the bank also uses a set of |
| 22 | * registers different from the other banks. |
| 23 | * |
| 24 | * For each of the two power domains (regular and always-on) there are |
| 25 | * 4 different register ranges that control the following properties |
| 26 | * of the pins: |
| 27 | * 1) pin muxing |
| 28 | * 2) pull enable/disable |
| 29 | * 3) pull up/down |
| 30 | * 4) GPIO direction, output value, input value |
| 31 | * |
| 32 | * In some cases the register ranges for pull enable and pull |
| 33 | * direction are the same and thus there are only 3 register ranges. |
| 34 | * |
| 35 | * Every pinmux group can be enabled by a specific bit in the first |
| 36 | * register range of the domain; when all groups for a given pin are |
| 37 | * disabled the pin acts as a GPIO. |
| 38 | * |
| 39 | * For the pull and GPIO configuration every bank uses a contiguous |
| 40 | * set of bits in the register sets described above; the same register |
| 41 | * can be shared by more banks with different offsets. |
| 42 | * |
| 43 | * In addition to this there are some registers shared between all |
| 44 | * banks that control the IRQ functionality. This feature is not |
| 45 | * supported at the moment by the driver. |
| 46 | */ |
| 47 | |
| 48 | #include <linux/device.h> |
| 49 | #include <linux/gpio.h> |
| 50 | #include <linux/init.h> |
| 51 | #include <linux/io.h> |
Beniamino Galvani | 6ac7309 | 2015-01-17 19:15:14 +0100 | [diff] [blame] | 52 | #include <linux/of.h> |
| 53 | #include <linux/of_address.h> |
| 54 | #include <linux/pinctrl/pinconf-generic.h> |
| 55 | #include <linux/pinctrl/pinconf.h> |
| 56 | #include <linux/pinctrl/pinctrl.h> |
| 57 | #include <linux/pinctrl/pinmux.h> |
| 58 | #include <linux/platform_device.h> |
| 59 | #include <linux/regmap.h> |
| 60 | #include <linux/seq_file.h> |
| 61 | |
| 62 | #include "../core.h" |
| 63 | #include "../pinctrl-utils.h" |
| 64 | #include "pinctrl-meson.h" |
| 65 | |
| 66 | /** |
| 67 | * meson_get_bank() - find the bank containing a given pin |
| 68 | * |
| 69 | * @domain: the domain containing the pin |
| 70 | * @pin: the pin number |
| 71 | * @bank: the found bank |
| 72 | * |
| 73 | * Return: 0 on success, a negative value on error |
| 74 | */ |
| 75 | static int meson_get_bank(struct meson_domain *domain, unsigned int pin, |
| 76 | struct meson_bank **bank) |
| 77 | { |
| 78 | int i; |
| 79 | |
| 80 | for (i = 0; i < domain->data->num_banks; i++) { |
| 81 | if (pin >= domain->data->banks[i].first && |
| 82 | pin <= domain->data->banks[i].last) { |
| 83 | *bank = &domain->data->banks[i]; |
| 84 | return 0; |
| 85 | } |
| 86 | } |
| 87 | |
| 88 | return -EINVAL; |
| 89 | } |
| 90 | |
| 91 | /** |
| 92 | * meson_get_domain_and_bank() - find domain and bank containing a given pin |
| 93 | * |
| 94 | * @pc: Meson pin controller device |
| 95 | * @pin: the pin number |
| 96 | * @domain: the found domain |
| 97 | * @bank: the found bank |
| 98 | * |
| 99 | * Return: 0 on success, a negative value on error |
| 100 | */ |
| 101 | static int meson_get_domain_and_bank(struct meson_pinctrl *pc, unsigned int pin, |
| 102 | struct meson_domain **domain, |
| 103 | struct meson_bank **bank) |
| 104 | { |
| 105 | struct meson_domain *d; |
Beniamino Galvani | 6ac7309 | 2015-01-17 19:15:14 +0100 | [diff] [blame] | 106 | |
Carlo Caione | 9dab186 | 2016-03-01 23:04:34 +0100 | [diff] [blame] | 107 | d = pc->domain; |
| 108 | |
| 109 | if (pin >= d->data->pin_base && |
| 110 | pin < d->data->pin_base + d->data->num_pins) { |
| 111 | *domain = d; |
| 112 | return meson_get_bank(d, pin, bank); |
Beniamino Galvani | 6ac7309 | 2015-01-17 19:15:14 +0100 | [diff] [blame] | 113 | } |
| 114 | |
| 115 | return -EINVAL; |
| 116 | } |
| 117 | |
| 118 | /** |
| 119 | * meson_calc_reg_and_bit() - calculate register and bit for a pin |
| 120 | * |
| 121 | * @bank: the bank containing the pin |
| 122 | * @pin: the pin number |
| 123 | * @reg_type: the type of register needed (pull-enable, pull, etc...) |
| 124 | * @reg: the computed register offset |
| 125 | * @bit: the computed bit |
| 126 | */ |
| 127 | static void meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin, |
| 128 | enum meson_reg_type reg_type, |
| 129 | unsigned int *reg, unsigned int *bit) |
| 130 | { |
| 131 | struct meson_reg_desc *desc = &bank->regs[reg_type]; |
| 132 | |
| 133 | *reg = desc->reg * 4; |
| 134 | *bit = desc->bit + pin - bank->first; |
| 135 | } |
| 136 | |
| 137 | static int meson_get_groups_count(struct pinctrl_dev *pcdev) |
| 138 | { |
| 139 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); |
| 140 | |
| 141 | return pc->data->num_groups; |
| 142 | } |
| 143 | |
| 144 | static const char *meson_get_group_name(struct pinctrl_dev *pcdev, |
| 145 | unsigned selector) |
| 146 | { |
| 147 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); |
| 148 | |
| 149 | return pc->data->groups[selector].name; |
| 150 | } |
| 151 | |
| 152 | static int meson_get_group_pins(struct pinctrl_dev *pcdev, unsigned selector, |
| 153 | const unsigned **pins, unsigned *num_pins) |
| 154 | { |
| 155 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); |
| 156 | |
| 157 | *pins = pc->data->groups[selector].pins; |
| 158 | *num_pins = pc->data->groups[selector].num_pins; |
| 159 | |
| 160 | return 0; |
| 161 | } |
| 162 | |
| 163 | static void meson_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s, |
| 164 | unsigned offset) |
| 165 | { |
| 166 | seq_printf(s, " %s", dev_name(pcdev->dev)); |
| 167 | } |
| 168 | |
| 169 | static const struct pinctrl_ops meson_pctrl_ops = { |
| 170 | .get_groups_count = meson_get_groups_count, |
| 171 | .get_group_name = meson_get_group_name, |
| 172 | .get_group_pins = meson_get_group_pins, |
| 173 | .dt_node_to_map = pinconf_generic_dt_node_to_map_all, |
Irina Tirdea | d32f7fd | 2016-03-31 14:44:42 +0300 | [diff] [blame] | 174 | .dt_free_map = pinctrl_utils_free_map, |
Beniamino Galvani | 6ac7309 | 2015-01-17 19:15:14 +0100 | [diff] [blame] | 175 | .pin_dbg_show = meson_pin_dbg_show, |
| 176 | }; |
| 177 | |
| 178 | /** |
| 179 | * meson_pmx_disable_other_groups() - disable other groups using a given pin |
| 180 | * |
| 181 | * @pc: meson pin controller device |
| 182 | * @pin: number of the pin |
| 183 | * @sel_group: index of the selected group, or -1 if none |
| 184 | * |
| 185 | * The function disables all pinmux groups using a pin except the |
| 186 | * selected one. If @sel_group is -1 all groups are disabled, leaving |
| 187 | * the pin in GPIO mode. |
| 188 | */ |
| 189 | static void meson_pmx_disable_other_groups(struct meson_pinctrl *pc, |
| 190 | unsigned int pin, int sel_group) |
| 191 | { |
| 192 | struct meson_pmx_group *group; |
| 193 | struct meson_domain *domain; |
| 194 | int i, j; |
| 195 | |
| 196 | for (i = 0; i < pc->data->num_groups; i++) { |
| 197 | group = &pc->data->groups[i]; |
| 198 | if (group->is_gpio || i == sel_group) |
| 199 | continue; |
| 200 | |
| 201 | for (j = 0; j < group->num_pins; j++) { |
| 202 | if (group->pins[j] == pin) { |
| 203 | /* We have found a group using the pin */ |
Carlo Caione | 9dab186 | 2016-03-01 23:04:34 +0100 | [diff] [blame] | 204 | domain = pc->domain; |
Beniamino Galvani | 6ac7309 | 2015-01-17 19:15:14 +0100 | [diff] [blame] | 205 | regmap_update_bits(domain->reg_mux, |
| 206 | group->reg * 4, |
| 207 | BIT(group->bit), 0); |
| 208 | } |
| 209 | } |
| 210 | } |
| 211 | } |
| 212 | |
| 213 | static int meson_pmx_set_mux(struct pinctrl_dev *pcdev, unsigned func_num, |
| 214 | unsigned group_num) |
| 215 | { |
| 216 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); |
| 217 | struct meson_pmx_func *func = &pc->data->funcs[func_num]; |
| 218 | struct meson_pmx_group *group = &pc->data->groups[group_num]; |
Carlo Caione | 9dab186 | 2016-03-01 23:04:34 +0100 | [diff] [blame] | 219 | struct meson_domain *domain = pc->domain; |
Beniamino Galvani | 6ac7309 | 2015-01-17 19:15:14 +0100 | [diff] [blame] | 220 | int i, ret = 0; |
| 221 | |
| 222 | dev_dbg(pc->dev, "enable function %s, group %s\n", func->name, |
| 223 | group->name); |
| 224 | |
| 225 | /* |
| 226 | * Disable groups using the same pin. |
| 227 | * The selected group is not disabled to avoid glitches. |
| 228 | */ |
| 229 | for (i = 0; i < group->num_pins; i++) |
| 230 | meson_pmx_disable_other_groups(pc, group->pins[i], group_num); |
| 231 | |
| 232 | /* Function 0 (GPIO) doesn't need any additional setting */ |
| 233 | if (func_num) |
| 234 | ret = regmap_update_bits(domain->reg_mux, group->reg * 4, |
| 235 | BIT(group->bit), BIT(group->bit)); |
| 236 | |
| 237 | return ret; |
| 238 | } |
| 239 | |
| 240 | static int meson_pmx_request_gpio(struct pinctrl_dev *pcdev, |
| 241 | struct pinctrl_gpio_range *range, |
| 242 | unsigned offset) |
| 243 | { |
| 244 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); |
| 245 | |
| 246 | meson_pmx_disable_other_groups(pc, range->pin_base + offset, -1); |
| 247 | |
| 248 | return 0; |
| 249 | } |
| 250 | |
| 251 | static int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev) |
| 252 | { |
| 253 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); |
| 254 | |
| 255 | return pc->data->num_funcs; |
| 256 | } |
| 257 | |
| 258 | static const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev, |
| 259 | unsigned selector) |
| 260 | { |
| 261 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); |
| 262 | |
| 263 | return pc->data->funcs[selector].name; |
| 264 | } |
| 265 | |
| 266 | static int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector, |
| 267 | const char * const **groups, |
| 268 | unsigned * const num_groups) |
| 269 | { |
| 270 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); |
| 271 | |
| 272 | *groups = pc->data->funcs[selector].groups; |
| 273 | *num_groups = pc->data->funcs[selector].num_groups; |
| 274 | |
| 275 | return 0; |
| 276 | } |
| 277 | |
| 278 | static const struct pinmux_ops meson_pmx_ops = { |
| 279 | .set_mux = meson_pmx_set_mux, |
| 280 | .get_functions_count = meson_pmx_get_funcs_count, |
| 281 | .get_function_name = meson_pmx_get_func_name, |
| 282 | .get_function_groups = meson_pmx_get_groups, |
| 283 | .gpio_request_enable = meson_pmx_request_gpio, |
| 284 | }; |
| 285 | |
| 286 | static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, |
| 287 | unsigned long *configs, unsigned num_configs) |
| 288 | { |
| 289 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); |
| 290 | struct meson_domain *domain; |
| 291 | struct meson_bank *bank; |
| 292 | enum pin_config_param param; |
| 293 | unsigned int reg, bit; |
| 294 | int i, ret; |
| 295 | u16 arg; |
| 296 | |
| 297 | ret = meson_get_domain_and_bank(pc, pin, &domain, &bank); |
| 298 | if (ret) |
| 299 | return ret; |
| 300 | |
| 301 | for (i = 0; i < num_configs; i++) { |
| 302 | param = pinconf_to_config_param(configs[i]); |
| 303 | arg = pinconf_to_config_argument(configs[i]); |
| 304 | |
| 305 | switch (param) { |
| 306 | case PIN_CONFIG_BIAS_DISABLE: |
| 307 | dev_dbg(pc->dev, "pin %u: disable bias\n", pin); |
| 308 | |
| 309 | meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); |
| 310 | ret = regmap_update_bits(domain->reg_pull, reg, |
| 311 | BIT(bit), 0); |
| 312 | if (ret) |
| 313 | return ret; |
| 314 | break; |
| 315 | case PIN_CONFIG_BIAS_PULL_UP: |
| 316 | dev_dbg(pc->dev, "pin %u: enable pull-up\n", pin); |
| 317 | |
| 318 | meson_calc_reg_and_bit(bank, pin, REG_PULLEN, |
| 319 | ®, &bit); |
| 320 | ret = regmap_update_bits(domain->reg_pullen, reg, |
| 321 | BIT(bit), BIT(bit)); |
| 322 | if (ret) |
| 323 | return ret; |
| 324 | |
| 325 | meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); |
| 326 | ret = regmap_update_bits(domain->reg_pull, reg, |
| 327 | BIT(bit), BIT(bit)); |
| 328 | if (ret) |
| 329 | return ret; |
| 330 | break; |
| 331 | case PIN_CONFIG_BIAS_PULL_DOWN: |
| 332 | dev_dbg(pc->dev, "pin %u: enable pull-down\n", pin); |
| 333 | |
| 334 | meson_calc_reg_and_bit(bank, pin, REG_PULLEN, |
| 335 | ®, &bit); |
| 336 | ret = regmap_update_bits(domain->reg_pullen, reg, |
| 337 | BIT(bit), BIT(bit)); |
| 338 | if (ret) |
| 339 | return ret; |
| 340 | |
| 341 | meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); |
| 342 | ret = regmap_update_bits(domain->reg_pull, reg, |
| 343 | BIT(bit), 0); |
| 344 | if (ret) |
| 345 | return ret; |
| 346 | break; |
| 347 | default: |
| 348 | return -ENOTSUPP; |
| 349 | } |
| 350 | } |
| 351 | |
| 352 | return 0; |
| 353 | } |
| 354 | |
| 355 | static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin) |
| 356 | { |
| 357 | struct meson_domain *domain; |
| 358 | struct meson_bank *bank; |
| 359 | unsigned int reg, bit, val; |
| 360 | int ret, conf; |
| 361 | |
| 362 | ret = meson_get_domain_and_bank(pc, pin, &domain, &bank); |
| 363 | if (ret) |
| 364 | return ret; |
| 365 | |
| 366 | meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); |
| 367 | |
| 368 | ret = regmap_read(domain->reg_pullen, reg, &val); |
| 369 | if (ret) |
| 370 | return ret; |
| 371 | |
| 372 | if (!(val & BIT(bit))) { |
| 373 | conf = PIN_CONFIG_BIAS_DISABLE; |
| 374 | } else { |
| 375 | meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); |
| 376 | |
| 377 | ret = regmap_read(domain->reg_pull, reg, &val); |
| 378 | if (ret) |
| 379 | return ret; |
| 380 | |
| 381 | if (val & BIT(bit)) |
| 382 | conf = PIN_CONFIG_BIAS_PULL_UP; |
| 383 | else |
| 384 | conf = PIN_CONFIG_BIAS_PULL_DOWN; |
| 385 | } |
| 386 | |
| 387 | return conf; |
| 388 | } |
| 389 | |
| 390 | static int meson_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin, |
| 391 | unsigned long *config) |
| 392 | { |
| 393 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); |
| 394 | enum pin_config_param param = pinconf_to_config_param(*config); |
| 395 | u16 arg; |
| 396 | |
| 397 | switch (param) { |
| 398 | case PIN_CONFIG_BIAS_DISABLE: |
| 399 | case PIN_CONFIG_BIAS_PULL_DOWN: |
| 400 | case PIN_CONFIG_BIAS_PULL_UP: |
| 401 | if (meson_pinconf_get_pull(pc, pin) == param) |
| 402 | arg = 1; |
| 403 | else |
| 404 | return -EINVAL; |
| 405 | break; |
| 406 | default: |
| 407 | return -ENOTSUPP; |
| 408 | } |
| 409 | |
| 410 | *config = pinconf_to_config_packed(param, arg); |
| 411 | dev_dbg(pc->dev, "pinconf for pin %u is %lu\n", pin, *config); |
| 412 | |
| 413 | return 0; |
| 414 | } |
| 415 | |
| 416 | static int meson_pinconf_group_set(struct pinctrl_dev *pcdev, |
| 417 | unsigned int num_group, |
| 418 | unsigned long *configs, unsigned num_configs) |
| 419 | { |
| 420 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); |
| 421 | struct meson_pmx_group *group = &pc->data->groups[num_group]; |
| 422 | int i; |
| 423 | |
| 424 | dev_dbg(pc->dev, "set pinconf for group %s\n", group->name); |
| 425 | |
| 426 | for (i = 0; i < group->num_pins; i++) { |
| 427 | meson_pinconf_set(pcdev, group->pins[i], configs, |
| 428 | num_configs); |
| 429 | } |
| 430 | |
| 431 | return 0; |
| 432 | } |
| 433 | |
| 434 | static int meson_pinconf_group_get(struct pinctrl_dev *pcdev, |
| 435 | unsigned int group, unsigned long *config) |
| 436 | { |
| 437 | return -ENOSYS; |
| 438 | } |
| 439 | |
| 440 | static const struct pinconf_ops meson_pinconf_ops = { |
| 441 | .pin_config_get = meson_pinconf_get, |
| 442 | .pin_config_set = meson_pinconf_set, |
| 443 | .pin_config_group_get = meson_pinconf_group_get, |
| 444 | .pin_config_group_set = meson_pinconf_group_set, |
| 445 | .is_generic = true, |
| 446 | }; |
| 447 | |
Beniamino Galvani | 6ac7309 | 2015-01-17 19:15:14 +0100 | [diff] [blame] | 448 | static int meson_gpio_request(struct gpio_chip *chip, unsigned gpio) |
| 449 | { |
| 450 | return pinctrl_request_gpio(chip->base + gpio); |
| 451 | } |
| 452 | |
| 453 | static void meson_gpio_free(struct gpio_chip *chip, unsigned gpio) |
| 454 | { |
Linus Walleij | 827c93d | 2015-12-08 08:26:34 +0100 | [diff] [blame] | 455 | struct meson_domain *domain = gpiochip_get_data(chip); |
Beniamino Galvani | 6ac7309 | 2015-01-17 19:15:14 +0100 | [diff] [blame] | 456 | |
| 457 | pinctrl_free_gpio(domain->data->pin_base + gpio); |
| 458 | } |
| 459 | |
| 460 | static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) |
| 461 | { |
Linus Walleij | 827c93d | 2015-12-08 08:26:34 +0100 | [diff] [blame] | 462 | struct meson_domain *domain = gpiochip_get_data(chip); |
Beniamino Galvani | 6ac7309 | 2015-01-17 19:15:14 +0100 | [diff] [blame] | 463 | unsigned int reg, bit, pin; |
| 464 | struct meson_bank *bank; |
| 465 | int ret; |
| 466 | |
| 467 | pin = domain->data->pin_base + gpio; |
| 468 | ret = meson_get_bank(domain, pin, &bank); |
| 469 | if (ret) |
| 470 | return ret; |
| 471 | |
| 472 | meson_calc_reg_and_bit(bank, pin, REG_DIR, ®, &bit); |
| 473 | |
| 474 | return regmap_update_bits(domain->reg_gpio, reg, BIT(bit), BIT(bit)); |
| 475 | } |
| 476 | |
| 477 | static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, |
| 478 | int value) |
| 479 | { |
Linus Walleij | 827c93d | 2015-12-08 08:26:34 +0100 | [diff] [blame] | 480 | struct meson_domain *domain = gpiochip_get_data(chip); |
Beniamino Galvani | 6ac7309 | 2015-01-17 19:15:14 +0100 | [diff] [blame] | 481 | unsigned int reg, bit, pin; |
| 482 | struct meson_bank *bank; |
| 483 | int ret; |
| 484 | |
| 485 | pin = domain->data->pin_base + gpio; |
| 486 | ret = meson_get_bank(domain, pin, &bank); |
| 487 | if (ret) |
| 488 | return ret; |
| 489 | |
| 490 | meson_calc_reg_and_bit(bank, pin, REG_DIR, ®, &bit); |
| 491 | ret = regmap_update_bits(domain->reg_gpio, reg, BIT(bit), 0); |
| 492 | if (ret) |
| 493 | return ret; |
| 494 | |
| 495 | meson_calc_reg_and_bit(bank, pin, REG_OUT, ®, &bit); |
| 496 | return regmap_update_bits(domain->reg_gpio, reg, BIT(bit), |
| 497 | value ? BIT(bit) : 0); |
| 498 | } |
| 499 | |
| 500 | static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value) |
| 501 | { |
Linus Walleij | 827c93d | 2015-12-08 08:26:34 +0100 | [diff] [blame] | 502 | struct meson_domain *domain = gpiochip_get_data(chip); |
Beniamino Galvani | 6ac7309 | 2015-01-17 19:15:14 +0100 | [diff] [blame] | 503 | unsigned int reg, bit, pin; |
| 504 | struct meson_bank *bank; |
| 505 | int ret; |
| 506 | |
| 507 | pin = domain->data->pin_base + gpio; |
| 508 | ret = meson_get_bank(domain, pin, &bank); |
| 509 | if (ret) |
| 510 | return; |
| 511 | |
| 512 | meson_calc_reg_and_bit(bank, pin, REG_OUT, ®, &bit); |
| 513 | regmap_update_bits(domain->reg_gpio, reg, BIT(bit), |
| 514 | value ? BIT(bit) : 0); |
| 515 | } |
| 516 | |
| 517 | static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio) |
| 518 | { |
Linus Walleij | 827c93d | 2015-12-08 08:26:34 +0100 | [diff] [blame] | 519 | struct meson_domain *domain = gpiochip_get_data(chip); |
Beniamino Galvani | 6ac7309 | 2015-01-17 19:15:14 +0100 | [diff] [blame] | 520 | unsigned int reg, bit, val, pin; |
| 521 | struct meson_bank *bank; |
| 522 | int ret; |
| 523 | |
| 524 | pin = domain->data->pin_base + gpio; |
| 525 | ret = meson_get_bank(domain, pin, &bank); |
| 526 | if (ret) |
| 527 | return ret; |
| 528 | |
| 529 | meson_calc_reg_and_bit(bank, pin, REG_IN, ®, &bit); |
| 530 | regmap_read(domain->reg_gpio, reg, &val); |
| 531 | |
| 532 | return !!(val & BIT(bit)); |
| 533 | } |
| 534 | |
| 535 | static const struct of_device_id meson_pinctrl_dt_match[] = { |
| 536 | { |
Carlo Caione | 9dab186 | 2016-03-01 23:04:34 +0100 | [diff] [blame] | 537 | .compatible = "amlogic,meson8-cbus-pinctrl", |
| 538 | .data = &meson8_cbus_pinctrl_data, |
Beniamino Galvani | 6ac7309 | 2015-01-17 19:15:14 +0100 | [diff] [blame] | 539 | }, |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 540 | { |
Carlo Caione | 9dab186 | 2016-03-01 23:04:34 +0100 | [diff] [blame] | 541 | .compatible = "amlogic,meson8b-cbus-pinctrl", |
| 542 | .data = &meson8b_cbus_pinctrl_data, |
| 543 | }, |
| 544 | { |
| 545 | .compatible = "amlogic,meson8-aobus-pinctrl", |
| 546 | .data = &meson8_aobus_pinctrl_data, |
| 547 | }, |
| 548 | { |
| 549 | .compatible = "amlogic,meson8b-aobus-pinctrl", |
| 550 | .data = &meson8b_aobus_pinctrl_data, |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 551 | }, |
Carlo Caione | 468c234 | 2016-05-02 10:02:15 +0200 | [diff] [blame] | 552 | { |
| 553 | .compatible = "amlogic,meson-gxbb-periphs-pinctrl", |
| 554 | .data = &meson_gxbb_periphs_pinctrl_data, |
| 555 | }, |
| 556 | { |
| 557 | .compatible = "amlogic,meson-gxbb-aobus-pinctrl", |
| 558 | .data = &meson_gxbb_aobus_pinctrl_data, |
| 559 | }, |
Beniamino Galvani | 6ac7309 | 2015-01-17 19:15:14 +0100 | [diff] [blame] | 560 | { }, |
| 561 | }; |
Beniamino Galvani | 6ac7309 | 2015-01-17 19:15:14 +0100 | [diff] [blame] | 562 | |
| 563 | static int meson_gpiolib_register(struct meson_pinctrl *pc) |
| 564 | { |
| 565 | struct meson_domain *domain; |
Carlo Caione | 9dab186 | 2016-03-01 23:04:34 +0100 | [diff] [blame] | 566 | int ret; |
Beniamino Galvani | 6ac7309 | 2015-01-17 19:15:14 +0100 | [diff] [blame] | 567 | |
Carlo Caione | 9dab186 | 2016-03-01 23:04:34 +0100 | [diff] [blame] | 568 | domain = pc->domain; |
Beniamino Galvani | 6ac7309 | 2015-01-17 19:15:14 +0100 | [diff] [blame] | 569 | |
Carlo Caione | 9dab186 | 2016-03-01 23:04:34 +0100 | [diff] [blame] | 570 | domain->chip.label = domain->data->name; |
| 571 | domain->chip.parent = pc->dev; |
| 572 | domain->chip.request = meson_gpio_request; |
| 573 | domain->chip.free = meson_gpio_free; |
| 574 | domain->chip.direction_input = meson_gpio_direction_input; |
| 575 | domain->chip.direction_output = meson_gpio_direction_output; |
| 576 | domain->chip.get = meson_gpio_get; |
| 577 | domain->chip.set = meson_gpio_set; |
| 578 | domain->chip.base = domain->data->pin_base; |
| 579 | domain->chip.ngpio = domain->data->num_pins; |
| 580 | domain->chip.can_sleep = false; |
| 581 | domain->chip.of_node = domain->of_node; |
| 582 | domain->chip.of_gpio_n_cells = 2; |
Beniamino Galvani | 6ac7309 | 2015-01-17 19:15:14 +0100 | [diff] [blame] | 583 | |
Carlo Caione | 9dab186 | 2016-03-01 23:04:34 +0100 | [diff] [blame] | 584 | ret = gpiochip_add_data(&domain->chip, domain); |
| 585 | if (ret) { |
| 586 | dev_err(pc->dev, "can't add gpio chip %s\n", |
| 587 | domain->data->name); |
| 588 | goto fail; |
| 589 | } |
Beniamino Galvani | 6ac7309 | 2015-01-17 19:15:14 +0100 | [diff] [blame] | 590 | |
Carlo Caione | 9dab186 | 2016-03-01 23:04:34 +0100 | [diff] [blame] | 591 | ret = gpiochip_add_pin_range(&domain->chip, dev_name(pc->dev), |
| 592 | 0, domain->data->pin_base, |
| 593 | domain->chip.ngpio); |
| 594 | if (ret) { |
| 595 | dev_err(pc->dev, "can't add pin range\n"); |
| 596 | goto fail; |
Beniamino Galvani | 6ac7309 | 2015-01-17 19:15:14 +0100 | [diff] [blame] | 597 | } |
| 598 | |
| 599 | return 0; |
| 600 | fail: |
Carlo Caione | 9dab186 | 2016-03-01 23:04:34 +0100 | [diff] [blame] | 601 | gpiochip_remove(&pc->domain->chip); |
Beniamino Galvani | 6ac7309 | 2015-01-17 19:15:14 +0100 | [diff] [blame] | 602 | |
| 603 | return ret; |
| 604 | } |
| 605 | |
Beniamino Galvani | 6ac7309 | 2015-01-17 19:15:14 +0100 | [diff] [blame] | 606 | static struct regmap_config meson_regmap_config = { |
| 607 | .reg_bits = 32, |
| 608 | .val_bits = 32, |
| 609 | .reg_stride = 4, |
| 610 | }; |
| 611 | |
| 612 | static struct regmap *meson_map_resource(struct meson_pinctrl *pc, |
| 613 | struct device_node *node, char *name) |
| 614 | { |
| 615 | struct resource res; |
| 616 | void __iomem *base; |
| 617 | int i; |
| 618 | |
| 619 | i = of_property_match_string(node, "reg-names", name); |
| 620 | if (of_address_to_resource(node, i, &res)) |
| 621 | return ERR_PTR(-ENOENT); |
| 622 | |
| 623 | base = devm_ioremap_resource(pc->dev, &res); |
| 624 | if (IS_ERR(base)) |
| 625 | return ERR_CAST(base); |
| 626 | |
| 627 | meson_regmap_config.max_register = resource_size(&res) - 4; |
| 628 | meson_regmap_config.name = devm_kasprintf(pc->dev, GFP_KERNEL, |
| 629 | "%s-%s", node->name, |
| 630 | name); |
| 631 | if (!meson_regmap_config.name) |
| 632 | return ERR_PTR(-ENOMEM); |
| 633 | |
| 634 | return devm_regmap_init_mmio(pc->dev, base, &meson_regmap_config); |
| 635 | } |
| 636 | |
| 637 | static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc, |
| 638 | struct device_node *node) |
| 639 | { |
| 640 | struct device_node *np; |
| 641 | struct meson_domain *domain; |
Carlo Caione | 9dab186 | 2016-03-01 23:04:34 +0100 | [diff] [blame] | 642 | int num_domains = 0; |
Beniamino Galvani | 6ac7309 | 2015-01-17 19:15:14 +0100 | [diff] [blame] | 643 | |
| 644 | for_each_child_of_node(node, np) { |
| 645 | if (!of_find_property(np, "gpio-controller", NULL)) |
| 646 | continue; |
| 647 | num_domains++; |
| 648 | } |
| 649 | |
Carlo Caione | 9dab186 | 2016-03-01 23:04:34 +0100 | [diff] [blame] | 650 | if (num_domains != 1) { |
Beniamino Galvani | 6ac7309 | 2015-01-17 19:15:14 +0100 | [diff] [blame] | 651 | dev_err(pc->dev, "wrong number of subnodes\n"); |
| 652 | return -EINVAL; |
| 653 | } |
| 654 | |
Carlo Caione | 9dab186 | 2016-03-01 23:04:34 +0100 | [diff] [blame] | 655 | pc->domain = devm_kzalloc(pc->dev, sizeof(struct meson_domain), GFP_KERNEL); |
| 656 | if (!pc->domain) |
Beniamino Galvani | 6ac7309 | 2015-01-17 19:15:14 +0100 | [diff] [blame] | 657 | return -ENOMEM; |
| 658 | |
Carlo Caione | 9dab186 | 2016-03-01 23:04:34 +0100 | [diff] [blame] | 659 | domain = pc->domain; |
| 660 | domain->data = pc->data->domain_data; |
| 661 | |
Beniamino Galvani | 6ac7309 | 2015-01-17 19:15:14 +0100 | [diff] [blame] | 662 | for_each_child_of_node(node, np) { |
| 663 | if (!of_find_property(np, "gpio-controller", NULL)) |
| 664 | continue; |
| 665 | |
Beniamino Galvani | 6ac7309 | 2015-01-17 19:15:14 +0100 | [diff] [blame] | 666 | domain->of_node = np; |
| 667 | |
| 668 | domain->reg_mux = meson_map_resource(pc, np, "mux"); |
| 669 | if (IS_ERR(domain->reg_mux)) { |
| 670 | dev_err(pc->dev, "mux registers not found\n"); |
| 671 | return PTR_ERR(domain->reg_mux); |
| 672 | } |
| 673 | |
| 674 | domain->reg_pull = meson_map_resource(pc, np, "pull"); |
| 675 | if (IS_ERR(domain->reg_pull)) { |
| 676 | dev_err(pc->dev, "pull registers not found\n"); |
| 677 | return PTR_ERR(domain->reg_pull); |
| 678 | } |
| 679 | |
| 680 | domain->reg_pullen = meson_map_resource(pc, np, "pull-enable"); |
| 681 | /* Use pull region if pull-enable one is not present */ |
| 682 | if (IS_ERR(domain->reg_pullen)) |
| 683 | domain->reg_pullen = domain->reg_pull; |
| 684 | |
| 685 | domain->reg_gpio = meson_map_resource(pc, np, "gpio"); |
| 686 | if (IS_ERR(domain->reg_gpio)) { |
| 687 | dev_err(pc->dev, "gpio registers not found\n"); |
| 688 | return PTR_ERR(domain->reg_gpio); |
| 689 | } |
| 690 | |
Carlo Caione | 9dab186 | 2016-03-01 23:04:34 +0100 | [diff] [blame] | 691 | break; |
Beniamino Galvani | 6ac7309 | 2015-01-17 19:15:14 +0100 | [diff] [blame] | 692 | } |
| 693 | |
| 694 | return 0; |
| 695 | } |
| 696 | |
| 697 | static int meson_pinctrl_probe(struct platform_device *pdev) |
| 698 | { |
| 699 | const struct of_device_id *match; |
| 700 | struct device *dev = &pdev->dev; |
| 701 | struct meson_pinctrl *pc; |
| 702 | int ret; |
| 703 | |
| 704 | pc = devm_kzalloc(dev, sizeof(struct meson_pinctrl), GFP_KERNEL); |
| 705 | if (!pc) |
| 706 | return -ENOMEM; |
| 707 | |
| 708 | pc->dev = dev; |
| 709 | match = of_match_node(meson_pinctrl_dt_match, pdev->dev.of_node); |
Carlo Caione | 9dab186 | 2016-03-01 23:04:34 +0100 | [diff] [blame] | 710 | pc->data = (struct meson_pinctrl_data *) match->data; |
Beniamino Galvani | 6ac7309 | 2015-01-17 19:15:14 +0100 | [diff] [blame] | 711 | |
| 712 | ret = meson_pinctrl_parse_dt(pc, pdev->dev.of_node); |
| 713 | if (ret) |
| 714 | return ret; |
| 715 | |
| 716 | pc->desc.name = "pinctrl-meson"; |
| 717 | pc->desc.owner = THIS_MODULE; |
| 718 | pc->desc.pctlops = &meson_pctrl_ops; |
| 719 | pc->desc.pmxops = &meson_pmx_ops; |
| 720 | pc->desc.confops = &meson_pinconf_ops; |
| 721 | pc->desc.pins = pc->data->pins; |
| 722 | pc->desc.npins = pc->data->num_pins; |
| 723 | |
Laxman Dewangan | e649f7e | 2016-02-24 14:44:07 +0530 | [diff] [blame] | 724 | pc->pcdev = devm_pinctrl_register(pc->dev, &pc->desc, pc); |
Masahiro Yamada | 323de9e | 2015-06-09 13:01:16 +0900 | [diff] [blame] | 725 | if (IS_ERR(pc->pcdev)) { |
Beniamino Galvani | 6ac7309 | 2015-01-17 19:15:14 +0100 | [diff] [blame] | 726 | dev_err(pc->dev, "can't register pinctrl device"); |
Masahiro Yamada | 323de9e | 2015-06-09 13:01:16 +0900 | [diff] [blame] | 727 | return PTR_ERR(pc->pcdev); |
Beniamino Galvani | 6ac7309 | 2015-01-17 19:15:14 +0100 | [diff] [blame] | 728 | } |
| 729 | |
| 730 | ret = meson_gpiolib_register(pc); |
| 731 | if (ret) { |
| 732 | pinctrl_unregister(pc->pcdev); |
| 733 | return ret; |
| 734 | } |
| 735 | |
| 736 | return 0; |
| 737 | } |
| 738 | |
| 739 | static struct platform_driver meson_pinctrl_driver = { |
| 740 | .probe = meson_pinctrl_probe, |
| 741 | .driver = { |
| 742 | .name = "meson-pinctrl", |
| 743 | .of_match_table = meson_pinctrl_dt_match, |
| 744 | }, |
| 745 | }; |
Paul Gortmaker | 2496eb3 | 2016-02-29 15:48:39 -0500 | [diff] [blame] | 746 | builtin_platform_driver(meson_pinctrl_driver); |