Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 Red Hat |
| 3 | * Author: Rob Clark <robdclark@gmail.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms of the GNU General Public License version 2 as published by |
| 7 | * the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 12 | * more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License along with |
| 15 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 16 | */ |
| 17 | |
| 18 | #ifndef __MSM_DRV_H__ |
| 19 | #define __MSM_DRV_H__ |
| 20 | |
| 21 | #include <linux/kernel.h> |
| 22 | #include <linux/clk.h> |
| 23 | #include <linux/cpufreq.h> |
| 24 | #include <linux/module.h> |
Rob Clark | 060530f | 2014-03-03 14:19:12 -0500 | [diff] [blame] | 25 | #include <linux/component.h> |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 26 | #include <linux/platform_device.h> |
| 27 | #include <linux/pm.h> |
| 28 | #include <linux/pm_runtime.h> |
| 29 | #include <linux/slab.h> |
| 30 | #include <linux/list.h> |
| 31 | #include <linux/iommu.h> |
| 32 | #include <linux/types.h> |
Archit Taneja | 3d6df06 | 2015-06-09 14:17:22 +0530 | [diff] [blame] | 33 | #include <linux/of_graph.h> |
Archit Taneja | e9fbdaf | 2015-11-18 12:15:14 +0530 | [diff] [blame] | 34 | #include <linux/of_device.h> |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 35 | #include <asm/sizes.h> |
| 36 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 37 | #include <drm/drmP.h> |
Rob Clark | cf3a7e4 | 2014-11-08 13:21:06 -0500 | [diff] [blame] | 38 | #include <drm/drm_atomic.h> |
| 39 | #include <drm/drm_atomic_helper.h> |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 40 | #include <drm/drm_crtc_helper.h> |
Rob Clark | cf3a7e4 | 2014-11-08 13:21:06 -0500 | [diff] [blame] | 41 | #include <drm/drm_plane_helper.h> |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 42 | #include <drm/drm_fb_helper.h> |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 43 | #include <drm/msm_drm.h> |
Daniel Vetter | d9fc941 | 2014-09-23 15:46:53 +0200 | [diff] [blame] | 44 | #include <drm/drm_gem.h> |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 45 | |
| 46 | struct msm_kms; |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 47 | struct msm_gpu; |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 48 | struct msm_mmu; |
Archit Taneja | 990a400 | 2016-05-07 23:11:25 +0530 | [diff] [blame] | 49 | struct msm_mdss; |
Rob Clark | a7d3c95 | 2014-05-30 14:47:38 -0400 | [diff] [blame] | 50 | struct msm_rd_state; |
Rob Clark | 70c70f0 | 2014-05-30 14:49:43 -0400 | [diff] [blame] | 51 | struct msm_perf_state; |
Rob Clark | a7d3c95 | 2014-05-30 14:47:38 -0400 | [diff] [blame] | 52 | struct msm_gem_submit; |
Rob Clark | ca762a8 | 2016-03-15 17:22:13 -0400 | [diff] [blame] | 53 | struct msm_fence_context; |
Rob Clark | fde5de6 | 2016-03-15 15:35:08 -0400 | [diff] [blame] | 54 | struct msm_fence_cb; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 55 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 56 | #define NUM_DOMAINS 2 /* one for KMS, then one per gpu core (?) */ |
| 57 | #define MAX_CRTCS 8 |
| 58 | #define MAX_PLANES 12 |
| 59 | #define MAX_ENCODERS 8 |
| 60 | #define MAX_BRIDGES 8 |
| 61 | #define MAX_CONNECTORS 8 |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 62 | |
| 63 | struct msm_file_private { |
| 64 | /* currently we don't do anything useful with this.. but when |
| 65 | * per-context address spaces are supported we'd keep track of |
| 66 | * the context's page-tables here. |
| 67 | */ |
| 68 | int dummy; |
| 69 | }; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 70 | |
jilai wang | 1298778 | 2015-06-25 17:37:42 -0400 | [diff] [blame] | 71 | enum msm_mdp_plane_property { |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 72 | /* blob properties, always put these first */ |
| 73 | PLANE_PROP_SCALER, |
| 74 | PLANE_PROP_CSC, |
| 75 | |
| 76 | /* # of blob properties */ |
| 77 | PLANE_PROP_BLOBCOUNT, |
| 78 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 79 | /* range properties */ |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 80 | PLANE_PROP_ZPOS = PLANE_PROP_BLOBCOUNT, |
jilai wang | 1298778 | 2015-06-25 17:37:42 -0400 | [diff] [blame] | 81 | PLANE_PROP_ALPHA, |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 82 | PLANE_PROP_COLOR_FILL, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 83 | PLANE_PROP_SYNC_FENCE, |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 84 | PLANE_PROP_SYNC_FENCE_TIMEOUT, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 85 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 86 | /* enum/bitmask properties */ |
| 87 | PLANE_PROP_ROTATION, |
| 88 | PLANE_PROP_BLEND_OP, |
| 89 | PLANE_PROP_SRC_CONFIG, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 90 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 91 | /* total # of properties */ |
| 92 | PLANE_PROP_COUNT |
jilai wang | 1298778 | 2015-06-25 17:37:42 -0400 | [diff] [blame] | 93 | }; |
| 94 | |
Hai Li | 78b1d47 | 2015-07-27 13:49:45 -0400 | [diff] [blame] | 95 | struct msm_vblank_ctrl { |
| 96 | struct work_struct work; |
| 97 | struct list_head event_list; |
| 98 | spinlock_t lock; |
| 99 | }; |
| 100 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 101 | struct msm_drm_private { |
| 102 | |
Rob Clark | 6820939 | 2016-05-17 16:19:32 -0400 | [diff] [blame] | 103 | struct drm_device *dev; |
| 104 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 105 | struct msm_kms *kms; |
| 106 | |
Rob Clark | 060530f | 2014-03-03 14:19:12 -0500 | [diff] [blame] | 107 | /* subordinate devices, if present: */ |
Rob Clark | 067fef3 | 2014-11-04 13:33:14 -0500 | [diff] [blame] | 108 | struct platform_device *gpu_pdev; |
| 109 | |
Archit Taneja | 990a400 | 2016-05-07 23:11:25 +0530 | [diff] [blame] | 110 | /* top level MDSS wrapper device (for MDP5 only) */ |
| 111 | struct msm_mdss *mdss; |
| 112 | |
Rob Clark | 067fef3 | 2014-11-04 13:33:14 -0500 | [diff] [blame] | 113 | /* possibly this should be in the kms component, but it is |
| 114 | * shared by both mdp4 and mdp5.. |
| 115 | */ |
| 116 | struct hdmi *hdmi; |
Rob Clark | 060530f | 2014-03-03 14:19:12 -0500 | [diff] [blame] | 117 | |
Hai Li | ab5b010 | 2015-01-07 18:47:44 -0500 | [diff] [blame] | 118 | /* eDP is for mdp5 only, but kms has not been created |
| 119 | * when edp_bind() and edp_init() are called. Here is the only |
| 120 | * place to keep the edp instance. |
| 121 | */ |
| 122 | struct msm_edp *edp; |
| 123 | |
Hai Li | a689554 | 2015-03-31 14:36:33 -0400 | [diff] [blame] | 124 | /* DSI is shared by mdp4 and mdp5 */ |
| 125 | struct msm_dsi *dsi[2]; |
| 126 | |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 127 | /* when we have more than one 'msm_gpu' these need to be an array: */ |
| 128 | struct msm_gpu *gpu; |
| 129 | struct msm_file_private *lastctx; |
| 130 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 131 | struct drm_fb_helper *fbdev; |
| 132 | |
Rob Clark | a7d3c95 | 2014-05-30 14:47:38 -0400 | [diff] [blame] | 133 | struct msm_rd_state *rd; |
Rob Clark | 70c70f0 | 2014-05-30 14:49:43 -0400 | [diff] [blame] | 134 | struct msm_perf_state *perf; |
Rob Clark | a7d3c95 | 2014-05-30 14:47:38 -0400 | [diff] [blame] | 135 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 136 | /* list of GEM objects: */ |
| 137 | struct list_head inactive_list; |
| 138 | |
| 139 | struct workqueue_struct *wq; |
Rob Clark | ba00c3f | 2016-03-16 18:18:17 -0400 | [diff] [blame] | 140 | struct workqueue_struct *atomic_wq; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 141 | |
Rob Clark | f86afec | 2014-11-25 12:41:18 -0500 | [diff] [blame] | 142 | /* crtcs pending async atomic updates: */ |
| 143 | uint32_t pending_crtcs; |
| 144 | wait_queue_head_t pending_crtcs_event; |
| 145 | |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 146 | /* registered MMUs: */ |
| 147 | unsigned int num_mmus; |
| 148 | struct msm_mmu *mmus[NUM_DOMAINS]; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 149 | |
Rob Clark | a862391 | 2013-10-08 12:57:48 -0400 | [diff] [blame] | 150 | unsigned int num_planes; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 151 | struct drm_plane *planes[MAX_PLANES]; |
Rob Clark | a862391 | 2013-10-08 12:57:48 -0400 | [diff] [blame] | 152 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 153 | unsigned int num_crtcs; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 154 | struct drm_crtc *crtcs[MAX_CRTCS]; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 155 | |
| 156 | unsigned int num_encoders; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 157 | struct drm_encoder *encoders[MAX_ENCODERS]; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 158 | |
Rob Clark | a3376e3 | 2013-08-30 13:02:15 -0400 | [diff] [blame] | 159 | unsigned int num_bridges; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 160 | struct drm_bridge *bridges[MAX_BRIDGES]; |
Rob Clark | a3376e3 | 2013-08-30 13:02:15 -0400 | [diff] [blame] | 161 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 162 | unsigned int num_connectors; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 163 | struct drm_connector *connectors[MAX_CONNECTORS]; |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 164 | |
jilai wang | 1298778 | 2015-06-25 17:37:42 -0400 | [diff] [blame] | 165 | /* Properties */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 166 | struct drm_property *plane_property[PLANE_PROP_COUNT]; |
jilai wang | 1298778 | 2015-06-25 17:37:42 -0400 | [diff] [blame] | 167 | |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 168 | /* VRAM carveout, used when no IOMMU: */ |
| 169 | struct { |
| 170 | unsigned long size; |
| 171 | dma_addr_t paddr; |
| 172 | /* NOTE: mm managed at the page level, size is in # of pages |
| 173 | * and position mm_node->start is in # of pages: |
| 174 | */ |
| 175 | struct drm_mm mm; |
| 176 | } vram; |
Hai Li | 78b1d47 | 2015-07-27 13:49:45 -0400 | [diff] [blame] | 177 | |
Rob Clark | e1e9db2 | 2016-05-27 11:16:28 -0400 | [diff] [blame] | 178 | struct notifier_block vmap_notifier; |
Rob Clark | 6820939 | 2016-05-17 16:19:32 -0400 | [diff] [blame] | 179 | struct shrinker shrinker; |
| 180 | |
Hai Li | 78b1d47 | 2015-07-27 13:49:45 -0400 | [diff] [blame] | 181 | struct msm_vblank_ctrl vblank_ctrl; |
Rob Clark | d78d383 | 2016-08-22 15:28:38 -0400 | [diff] [blame] | 182 | |
| 183 | /* task holding struct_mutex.. currently only used in submit path |
| 184 | * to detect and reject faults from copy_from_user() for submit |
| 185 | * ioctl. |
| 186 | */ |
| 187 | struct task_struct *struct_mutex_task; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 188 | }; |
| 189 | |
| 190 | struct msm_format { |
| 191 | uint32_t pixel_format; |
| 192 | }; |
| 193 | |
Daniel Vetter | b4274fb | 2014-11-26 17:02:18 +0100 | [diff] [blame] | 194 | int msm_atomic_check(struct drm_device *dev, |
| 195 | struct drm_atomic_state *state); |
Rob Clark | cf3a7e4 | 2014-11-08 13:21:06 -0500 | [diff] [blame] | 196 | int msm_atomic_commit(struct drm_device *dev, |
Maarten Lankhorst | a3ccfb9 | 2016-04-26 16:11:38 +0200 | [diff] [blame] | 197 | struct drm_atomic_state *state, bool nonblock); |
Rob Clark | cf3a7e4 | 2014-11-08 13:21:06 -0500 | [diff] [blame] | 198 | |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 199 | int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 200 | |
Rob Clark | 40e6815 | 2016-05-03 09:50:26 -0400 | [diff] [blame] | 201 | void msm_gem_submit_free(struct msm_gem_submit *submit); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 202 | int msm_ioctl_gem_submit(struct drm_device *dev, void *data, |
| 203 | struct drm_file *file); |
| 204 | |
Rob Clark | 6820939 | 2016-05-17 16:19:32 -0400 | [diff] [blame] | 205 | void msm_gem_shrinker_init(struct drm_device *dev); |
| 206 | void msm_gem_shrinker_cleanup(struct drm_device *dev); |
| 207 | |
Daniel Thompson | 77a147e | 2014-11-12 11:38:14 +0000 | [diff] [blame] | 208 | int msm_gem_mmap_obj(struct drm_gem_object *obj, |
| 209 | struct vm_area_struct *vma); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 210 | int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma); |
| 211 | int msm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
| 212 | uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj); |
| 213 | int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id, |
| 214 | uint32_t *iova); |
| 215 | int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint32_t *iova); |
Rob Clark | 2638d90 | 2014-11-08 09:13:37 -0500 | [diff] [blame] | 216 | uint32_t msm_gem_iova(struct drm_gem_object *obj, int id); |
Rob Clark | 05b8491 | 2013-09-28 11:28:35 -0400 | [diff] [blame] | 217 | struct page **msm_gem_get_pages(struct drm_gem_object *obj); |
| 218 | void msm_gem_put_pages(struct drm_gem_object *obj); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 219 | void msm_gem_put_iova(struct drm_gem_object *obj, int id); |
| 220 | int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev, |
| 221 | struct drm_mode_create_dumb *args); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 222 | int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev, |
| 223 | uint32_t handle, uint64_t *offset); |
Rob Clark | 05b8491 | 2013-09-28 11:28:35 -0400 | [diff] [blame] | 224 | struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj); |
| 225 | void *msm_gem_prime_vmap(struct drm_gem_object *obj); |
| 226 | void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); |
Daniel Thompson | 77a147e | 2014-11-12 11:38:14 +0000 | [diff] [blame] | 227 | int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); |
Rob Clark | 05b8491 | 2013-09-28 11:28:35 -0400 | [diff] [blame] | 228 | struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev, |
Maarten Lankhorst | b5e9c1a | 2014-01-09 11:03:14 +0100 | [diff] [blame] | 229 | struct dma_buf_attachment *attach, struct sg_table *sg); |
Rob Clark | 05b8491 | 2013-09-28 11:28:35 -0400 | [diff] [blame] | 230 | int msm_gem_prime_pin(struct drm_gem_object *obj); |
| 231 | void msm_gem_prime_unpin(struct drm_gem_object *obj); |
Rob Clark | 18f2304 | 2016-05-26 16:24:35 -0400 | [diff] [blame] | 232 | void *msm_gem_get_vaddr_locked(struct drm_gem_object *obj); |
| 233 | void *msm_gem_get_vaddr(struct drm_gem_object *obj); |
| 234 | void msm_gem_put_vaddr_locked(struct drm_gem_object *obj); |
| 235 | void msm_gem_put_vaddr(struct drm_gem_object *obj); |
Rob Clark | 4cd33c4 | 2016-05-17 15:44:49 -0400 | [diff] [blame] | 236 | int msm_gem_madvise(struct drm_gem_object *obj, unsigned madv); |
Rob Clark | 6820939 | 2016-05-17 16:19:32 -0400 | [diff] [blame] | 237 | void msm_gem_purge(struct drm_gem_object *obj); |
Rob Clark | e1e9db2 | 2016-05-27 11:16:28 -0400 | [diff] [blame] | 238 | void msm_gem_vunmap(struct drm_gem_object *obj); |
Rob Clark | b6295f9 | 2016-03-15 18:26:28 -0400 | [diff] [blame] | 239 | int msm_gem_sync_object(struct drm_gem_object *obj, |
| 240 | struct msm_fence_context *fctx, bool exclusive); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 241 | void msm_gem_move_to_active(struct drm_gem_object *obj, |
Rob Clark | b6295f9 | 2016-03-15 18:26:28 -0400 | [diff] [blame] | 242 | struct msm_gpu *gpu, bool exclusive, struct fence *fence); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 243 | void msm_gem_move_to_inactive(struct drm_gem_object *obj); |
Rob Clark | ba00c3f | 2016-03-16 18:18:17 -0400 | [diff] [blame] | 244 | int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 245 | int msm_gem_cpu_fini(struct drm_gem_object *obj); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 246 | void msm_gem_free_object(struct drm_gem_object *obj); |
| 247 | int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file, |
| 248 | uint32_t size, uint32_t flags, uint32_t *handle); |
| 249 | struct drm_gem_object *msm_gem_new(struct drm_device *dev, |
| 250 | uint32_t size, uint32_t flags); |
Rob Clark | 05b8491 | 2013-09-28 11:28:35 -0400 | [diff] [blame] | 251 | struct drm_gem_object *msm_gem_import(struct drm_device *dev, |
Rob Clark | 79f0e20 | 2016-03-16 12:40:35 -0400 | [diff] [blame] | 252 | struct dma_buf *dmabuf, struct sg_table *sgt); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 253 | |
Rob Clark | 2638d90 | 2014-11-08 09:13:37 -0500 | [diff] [blame] | 254 | int msm_framebuffer_prepare(struct drm_framebuffer *fb, int id); |
| 255 | void msm_framebuffer_cleanup(struct drm_framebuffer *fb, int id); |
| 256 | uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, int id, int plane); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 257 | struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); |
| 258 | const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); |
| 259 | struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev, |
Ville Syrjälä | 1eb8345 | 2015-11-11 19:11:29 +0200 | [diff] [blame] | 260 | const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 261 | struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, |
Ville Syrjälä | 1eb8345 | 2015-11-11 19:11:29 +0200 | [diff] [blame] | 262 | struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 263 | |
| 264 | struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev); |
Archit Taneja | 1aaa57f | 2016-02-25 11:19:45 +0530 | [diff] [blame] | 265 | void msm_fbdev_free(struct drm_device *dev); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 266 | |
Rob Clark | dada25b | 2013-12-01 12:12:54 -0500 | [diff] [blame] | 267 | struct hdmi; |
Arnd Bergmann | fcda50c | 2016-02-22 22:08:35 +0100 | [diff] [blame] | 268 | int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, |
Rob Clark | 067fef3 | 2014-11-04 13:33:14 -0500 | [diff] [blame] | 269 | struct drm_encoder *encoder); |
Arnd Bergmann | fcda50c | 2016-02-22 22:08:35 +0100 | [diff] [blame] | 270 | void __init msm_hdmi_register(void); |
| 271 | void __exit msm_hdmi_unregister(void); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 272 | |
Hai Li | 0045398 | 2014-12-12 14:41:17 -0500 | [diff] [blame] | 273 | struct msm_edp; |
| 274 | void __init msm_edp_register(void); |
| 275 | void __exit msm_edp_unregister(void); |
| 276 | int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev, |
| 277 | struct drm_encoder *encoder); |
| 278 | |
Hai Li | a689554 | 2015-03-31 14:36:33 -0400 | [diff] [blame] | 279 | struct msm_dsi; |
| 280 | enum msm_dsi_encoder_id { |
| 281 | MSM_DSI_VIDEO_ENCODER_ID = 0, |
| 282 | MSM_DSI_CMD_ENCODER_ID = 1, |
| 283 | MSM_DSI_ENCODER_NUM = 2 |
| 284 | }; |
| 285 | #ifdef CONFIG_DRM_MSM_DSI |
| 286 | void __init msm_dsi_register(void); |
| 287 | void __exit msm_dsi_unregister(void); |
| 288 | int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, |
| 289 | struct drm_encoder *encoders[MSM_DSI_ENCODER_NUM]); |
| 290 | #else |
| 291 | static inline void __init msm_dsi_register(void) |
| 292 | { |
| 293 | } |
| 294 | static inline void __exit msm_dsi_unregister(void) |
| 295 | { |
| 296 | } |
| 297 | static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, |
| 298 | struct drm_device *dev, |
| 299 | struct drm_encoder *encoders[MSM_DSI_ENCODER_NUM]) |
| 300 | { |
| 301 | return -EINVAL; |
| 302 | } |
| 303 | #endif |
| 304 | |
Archit Taneja | 1dd0a0b | 2016-05-30 16:36:50 +0530 | [diff] [blame] | 305 | void __init msm_mdp_register(void); |
| 306 | void __exit msm_mdp_unregister(void); |
| 307 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 308 | #ifdef CONFIG_DEBUG_FS |
| 309 | void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m); |
| 310 | void msm_gem_describe_objects(struct list_head *list, struct seq_file *m); |
| 311 | void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m); |
Rob Clark | a7d3c95 | 2014-05-30 14:47:38 -0400 | [diff] [blame] | 312 | int msm_debugfs_late_init(struct drm_device *dev); |
| 313 | int msm_rd_debugfs_init(struct drm_minor *minor); |
| 314 | void msm_rd_debugfs_cleanup(struct drm_minor *minor); |
| 315 | void msm_rd_dump_submit(struct msm_gem_submit *submit); |
Rob Clark | 70c70f0 | 2014-05-30 14:49:43 -0400 | [diff] [blame] | 316 | int msm_perf_debugfs_init(struct drm_minor *minor); |
| 317 | void msm_perf_debugfs_cleanup(struct drm_minor *minor); |
Rob Clark | a7d3c95 | 2014-05-30 14:47:38 -0400 | [diff] [blame] | 318 | #else |
| 319 | static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; } |
| 320 | static inline void msm_rd_dump_submit(struct msm_gem_submit *submit) {} |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 321 | #endif |
| 322 | |
| 323 | void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, |
| 324 | const char *dbgname); |
| 325 | void msm_writel(u32 data, void __iomem *addr); |
| 326 | u32 msm_readl(const void __iomem *addr); |
| 327 | |
| 328 | #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) |
| 329 | #define VERB(fmt, ...) if (0) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) |
| 330 | |
| 331 | static inline int align_pitch(int width, int bpp) |
| 332 | { |
| 333 | int bytespp = (bpp + 7) / 8; |
| 334 | /* adreno needs pitch aligned to 32 pixels: */ |
| 335 | return bytespp * ALIGN(width, 32); |
| 336 | } |
| 337 | |
| 338 | /* for the generated headers: */ |
| 339 | #define INVALID_IDX(idx) ({BUG(); 0;}) |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 340 | #define fui(x) ({BUG(); 0;}) |
| 341 | #define util_float_to_half(x) ({BUG(); 0;}) |
| 342 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 343 | |
| 344 | #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) |
| 345 | |
| 346 | /* for conditionally setting boolean flag(s): */ |
| 347 | #define COND(bool, val) ((bool) ? (val) : 0) |
| 348 | |
Rob Clark | 340ff41 | 2016-03-16 14:57:22 -0400 | [diff] [blame] | 349 | static inline unsigned long timeout_to_jiffies(const ktime_t *timeout) |
| 350 | { |
| 351 | ktime_t now = ktime_get(); |
| 352 | unsigned long remaining_jiffies; |
| 353 | |
| 354 | if (ktime_compare(*timeout, now) < 0) { |
| 355 | remaining_jiffies = 0; |
| 356 | } else { |
| 357 | ktime_t rem = ktime_sub(*timeout, now); |
| 358 | struct timespec ts = ktime_to_timespec(rem); |
| 359 | remaining_jiffies = timespec_to_jiffies(&ts); |
| 360 | } |
| 361 | |
| 362 | return remaining_jiffies; |
| 363 | } |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 364 | |
| 365 | #endif /* __MSM_DRV_H__ */ |